1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/debugfs.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/device.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/spi/spi.h> 18 #include <linux/err.h> 19 #include <linux/delay.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/of.h> 22 23 24 #include <linux/iio/backend.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 28 #include <linux/clk.h> 29 30 /* 31 * ADI High-Speed ADC common spi interface registers 32 * See Application-Note AN-877: 33 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 34 */ 35 36 #define AN877_ADC_REG_CHIP_PORT_CONF 0x00 37 #define AN877_ADC_REG_CHIP_ID 0x01 38 #define AN877_ADC_REG_CHIP_GRADE 0x02 39 #define AN877_ADC_REG_CHAN_INDEX 0x05 40 #define AN877_ADC_REG_TRANSFER 0xFF 41 #define AN877_ADC_REG_MODES 0x08 42 #define AN877_ADC_REG_TEST_IO 0x0D 43 #define AN877_ADC_REG_ADC_INPUT 0x0F 44 #define AN877_ADC_REG_OFFSET 0x10 45 #define AN877_ADC_REG_OUTPUT_MODE 0x14 46 #define AN877_ADC_REG_OUTPUT_ADJUST 0x15 47 #define AN877_ADC_REG_OUTPUT_PHASE 0x16 48 #define AN877_ADC_REG_OUTPUT_DELAY 0x17 49 #define AN877_ADC_REG_VREF 0x18 50 #define AN877_ADC_REG_ANALOG_INPUT 0x2C 51 52 /* AN877_ADC_REG_TEST_IO */ 53 #define AN877_ADC_TESTMODE_OFF 0x0 54 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 55 #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 56 #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 57 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 58 #define AN877_ADC_TESTMODE_PN23_SEQ 0x5 59 #define AN877_ADC_TESTMODE_PN9_SEQ 0x6 60 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 61 #define AN877_ADC_TESTMODE_USER 0x8 62 #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 63 #define AN877_ADC_TESTMODE_SYNC 0xA 64 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 65 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 66 #define AN877_ADC_TESTMODE_RAMP 0xF 67 68 /* AN877_ADC_REG_TRANSFER */ 69 #define AN877_ADC_TRANSFER_SYNC 0x1 70 71 /* AN877_ADC_REG_OUTPUT_MODE */ 72 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 73 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 74 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 75 76 /* AN877_ADC_REG_OUTPUT_PHASE */ 77 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 78 #define AN877_ADC_INVERT_DCO_CLK 0x80 79 80 /* AN877_ADC_REG_OUTPUT_DELAY */ 81 #define AN877_ADC_DCO_DELAY_ENABLE 0x80 82 83 /* 84 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 85 */ 86 87 #define CHIPID_AD9265 0x64 88 #define AD9265_DEF_OUTPUT_MODE 0x40 89 #define AD9265_REG_VREF_MASK 0xC0 90 91 /* 92 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 93 */ 94 95 #define CHIPID_AD9434 0x6A 96 #define AD9434_DEF_OUTPUT_MODE 0x00 97 #define AD9434_REG_VREF_MASK 0xC0 98 99 /* 100 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 101 */ 102 103 #define CHIPID_AD9467 0x50 104 #define AD9467_DEF_OUTPUT_MODE 0x08 105 #define AD9467_REG_VREF_MASK 0x0F 106 107 #define AD9647_MAX_TEST_POINTS 32 108 109 struct ad9467_chip_info { 110 const char *name; 111 unsigned int id; 112 const struct iio_chan_spec *channels; 113 unsigned int num_channels; 114 const unsigned int (*scale_table)[2]; 115 int num_scales; 116 unsigned long max_rate; 117 unsigned int default_output_mode; 118 unsigned int vref_mask; 119 unsigned int num_lanes; 120 /* data clock output */ 121 bool has_dco; 122 }; 123 124 struct ad9467_state { 125 const struct ad9467_chip_info *info; 126 struct iio_backend *back; 127 struct spi_device *spi; 128 struct clk *clk; 129 unsigned int output_mode; 130 unsigned int (*scales)[2]; 131 /* 132 * Times 2 because we may also invert the signal polarity and run the 133 * calibration again. For some reference on the test points (ad9265) see: 134 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad9265.pdf 135 * at page 38 for the dco output delay. On devices as ad9467, the 136 * calibration is done at the backend level. For the ADI axi-adc: 137 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 138 * at the io delay control section. 139 */ 140 DECLARE_BITMAP(calib_map, AD9647_MAX_TEST_POINTS * 2); 141 struct gpio_desc *pwrdown_gpio; 142 /* ensure consistent state obtained on multiple related accesses */ 143 struct mutex lock; 144 u8 buf[3] __aligned(IIO_DMA_MINALIGN); 145 }; 146 147 static int ad9467_spi_read(struct ad9467_state *st, unsigned int reg) 148 { 149 unsigned char tbuf[2], rbuf[1]; 150 int ret; 151 152 tbuf[0] = 0x80 | (reg >> 8); 153 tbuf[1] = reg & 0xFF; 154 155 ret = spi_write_then_read(st->spi, 156 tbuf, ARRAY_SIZE(tbuf), 157 rbuf, ARRAY_SIZE(rbuf)); 158 159 if (ret < 0) 160 return ret; 161 162 return rbuf[0]; 163 } 164 165 static int ad9467_spi_write(struct ad9467_state *st, unsigned int reg, 166 unsigned int val) 167 { 168 st->buf[0] = reg >> 8; 169 st->buf[1] = reg & 0xFF; 170 st->buf[2] = val; 171 172 return spi_write(st->spi, st->buf, ARRAY_SIZE(st->buf)); 173 } 174 175 static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg, 176 unsigned int writeval, unsigned int *readval) 177 { 178 struct ad9467_state *st = iio_priv(indio_dev); 179 int ret; 180 181 if (!readval) { 182 guard(mutex)(&st->lock); 183 ret = ad9467_spi_write(st, reg, writeval); 184 if (ret) 185 return ret; 186 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 187 AN877_ADC_TRANSFER_SYNC); 188 } 189 190 ret = ad9467_spi_read(st, reg); 191 if (ret < 0) 192 return ret; 193 *readval = ret; 194 195 return 0; 196 } 197 198 static const unsigned int ad9265_scale_table[][2] = { 199 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 200 }; 201 202 static const unsigned int ad9434_scale_table[][2] = { 203 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 204 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 205 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 206 {1200, 0x0B}, {1180, 0x0C}, 207 }; 208 209 static const unsigned int ad9467_scale_table[][2] = { 210 {2000, 0}, {2100, 6}, {2200, 7}, 211 {2300, 8}, {2400, 9}, {2500, 10}, 212 }; 213 214 static void __ad9467_get_scale(struct ad9467_state *st, int index, 215 unsigned int *val, unsigned int *val2) 216 { 217 const struct ad9467_chip_info *info = st->info; 218 const struct iio_chan_spec *chan = &info->channels[0]; 219 unsigned int tmp; 220 221 tmp = (info->scale_table[index][0] * 1000000ULL) >> 222 chan->scan_type.realbits; 223 *val = tmp / 1000000; 224 *val2 = tmp % 1000000; 225 } 226 227 #define AD9467_CHAN(_chan, _si, _bits, _sign) \ 228 { \ 229 .type = IIO_VOLTAGE, \ 230 .indexed = 1, \ 231 .channel = _chan, \ 232 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 233 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 234 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 235 .scan_index = _si, \ 236 .scan_type = { \ 237 .sign = _sign, \ 238 .realbits = _bits, \ 239 .storagebits = 16, \ 240 }, \ 241 } 242 243 static const struct iio_chan_spec ad9434_channels[] = { 244 AD9467_CHAN(0, 0, 12, 's'), 245 }; 246 247 static const struct iio_chan_spec ad9467_channels[] = { 248 AD9467_CHAN(0, 0, 16, 's'), 249 }; 250 251 static const struct ad9467_chip_info ad9467_chip_tbl = { 252 .name = "ad9467", 253 .id = CHIPID_AD9467, 254 .max_rate = 250000000UL, 255 .scale_table = ad9467_scale_table, 256 .num_scales = ARRAY_SIZE(ad9467_scale_table), 257 .channels = ad9467_channels, 258 .num_channels = ARRAY_SIZE(ad9467_channels), 259 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 260 .vref_mask = AD9467_REG_VREF_MASK, 261 .num_lanes = 8, 262 }; 263 264 static const struct ad9467_chip_info ad9434_chip_tbl = { 265 .name = "ad9434", 266 .id = CHIPID_AD9434, 267 .max_rate = 500000000UL, 268 .scale_table = ad9434_scale_table, 269 .num_scales = ARRAY_SIZE(ad9434_scale_table), 270 .channels = ad9434_channels, 271 .num_channels = ARRAY_SIZE(ad9434_channels), 272 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 273 .vref_mask = AD9434_REG_VREF_MASK, 274 .num_lanes = 6, 275 }; 276 277 static const struct ad9467_chip_info ad9265_chip_tbl = { 278 .name = "ad9265", 279 .id = CHIPID_AD9265, 280 .max_rate = 125000000UL, 281 .scale_table = ad9265_scale_table, 282 .num_scales = ARRAY_SIZE(ad9265_scale_table), 283 .channels = ad9467_channels, 284 .num_channels = ARRAY_SIZE(ad9467_channels), 285 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 286 .vref_mask = AD9265_REG_VREF_MASK, 287 .has_dco = true, 288 }; 289 290 static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2) 291 { 292 const struct ad9467_chip_info *info = st->info; 293 unsigned int i, vref_val; 294 int ret; 295 296 ret = ad9467_spi_read(st, AN877_ADC_REG_VREF); 297 if (ret < 0) 298 return ret; 299 300 vref_val = ret & info->vref_mask; 301 302 for (i = 0; i < info->num_scales; i++) { 303 if (vref_val == info->scale_table[i][1]) 304 break; 305 } 306 307 if (i == info->num_scales) 308 return -ERANGE; 309 310 __ad9467_get_scale(st, i, val, val2); 311 312 return IIO_VAL_INT_PLUS_MICRO; 313 } 314 315 static int ad9467_set_scale(struct ad9467_state *st, int val, int val2) 316 { 317 const struct ad9467_chip_info *info = st->info; 318 unsigned int scale_val[2]; 319 unsigned int i; 320 int ret; 321 322 if (val != 0) 323 return -EINVAL; 324 325 for (i = 0; i < info->num_scales; i++) { 326 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]); 327 if (scale_val[0] != val || scale_val[1] != val2) 328 continue; 329 330 guard(mutex)(&st->lock); 331 ret = ad9467_spi_write(st, AN877_ADC_REG_VREF, 332 info->scale_table[i][1]); 333 if (ret < 0) 334 return ret; 335 336 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 337 AN877_ADC_TRANSFER_SYNC); 338 } 339 340 return -EINVAL; 341 } 342 343 static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode) 344 { 345 int ret; 346 347 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_MODE, mode); 348 if (ret < 0) 349 return ret; 350 351 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 352 AN877_ADC_TRANSFER_SYNC); 353 } 354 355 static int ad9647_calibrate_prepare(struct ad9467_state *st) 356 { 357 struct iio_backend_data_fmt data = { 358 .enable = false, 359 }; 360 unsigned int c; 361 int ret; 362 363 ret = ad9467_spi_write(st, AN877_ADC_REG_TEST_IO, 364 AN877_ADC_TESTMODE_PN9_SEQ); 365 if (ret) 366 return ret; 367 368 ret = ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 369 AN877_ADC_TRANSFER_SYNC); 370 if (ret) 371 return ret; 372 373 ret = ad9467_outputmode_set(st, st->info->default_output_mode); 374 if (ret) 375 return ret; 376 377 for (c = 0; c < st->info->num_channels; c++) { 378 ret = iio_backend_data_format_set(st->back, c, &data); 379 if (ret) 380 return ret; 381 } 382 383 ret = iio_backend_test_pattern_set(st->back, 0, 384 IIO_BACKEND_ADI_PRBS_9A); 385 if (ret) 386 return ret; 387 388 return iio_backend_chan_enable(st->back, 0); 389 } 390 391 static int ad9647_calibrate_polarity_set(struct ad9467_state *st, 392 bool invert) 393 { 394 enum iio_backend_sample_trigger trigger; 395 396 if (st->info->has_dco) { 397 unsigned int phase = AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN; 398 399 if (invert) 400 phase |= AN877_ADC_INVERT_DCO_CLK; 401 402 return ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_PHASE, 403 phase); 404 } 405 406 if (invert) 407 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING; 408 else 409 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING; 410 411 return iio_backend_data_sample_trigger(st->back, trigger); 412 } 413 414 /* 415 * The idea is pretty simple. Find the max number of successful points in a row 416 * and get the one in the middle. 417 */ 418 static unsigned int ad9467_find_optimal_point(const unsigned long *calib_map, 419 unsigned int start, 420 unsigned int nbits, 421 unsigned int *val) 422 { 423 unsigned int bit = start, end, start_cnt, cnt = 0; 424 425 for_each_clear_bitrange_from(bit, end, calib_map, nbits + start) { 426 if (end - bit > cnt) { 427 cnt = end - bit; 428 start_cnt = bit; 429 } 430 } 431 432 if (cnt) 433 *val = start_cnt + cnt / 2; 434 435 return cnt; 436 } 437 438 static int ad9467_calibrate_apply(struct ad9467_state *st, unsigned int val) 439 { 440 unsigned int lane; 441 int ret; 442 443 if (st->info->has_dco) { 444 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_DELAY, 445 val); 446 if (ret) 447 return ret; 448 449 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 450 AN877_ADC_TRANSFER_SYNC); 451 } 452 453 for (lane = 0; lane < st->info->num_lanes; lane++) { 454 ret = iio_backend_iodelay_set(st->back, lane, val); 455 if (ret) 456 return ret; 457 } 458 459 return 0; 460 } 461 462 static int ad9647_calibrate_stop(struct ad9467_state *st) 463 { 464 struct iio_backend_data_fmt data = { 465 .sign_extend = true, 466 .enable = true, 467 }; 468 unsigned int c, mode; 469 int ret; 470 471 ret = iio_backend_chan_disable(st->back, 0); 472 if (ret) 473 return ret; 474 475 ret = iio_backend_test_pattern_set(st->back, 0, 476 IIO_BACKEND_NO_TEST_PATTERN); 477 if (ret) 478 return ret; 479 480 for (c = 0; c < st->info->num_channels; c++) { 481 ret = iio_backend_data_format_set(st->back, c, &data); 482 if (ret) 483 return ret; 484 } 485 486 mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 487 ret = ad9467_outputmode_set(st, mode); 488 if (ret) 489 return ret; 490 491 ret = ad9467_spi_write(st, AN877_ADC_REG_TEST_IO, 492 AN877_ADC_TESTMODE_OFF); 493 if (ret) 494 return ret; 495 496 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 497 AN877_ADC_TRANSFER_SYNC); 498 } 499 500 static int ad9467_calibrate(struct ad9467_state *st) 501 { 502 unsigned int point, val, inv_val, cnt, inv_cnt = 0; 503 /* 504 * Half of the bitmap is for the inverted signal. The number of test 505 * points is the same though... 506 */ 507 unsigned int test_points = AD9647_MAX_TEST_POINTS; 508 unsigned long sample_rate = clk_get_rate(st->clk); 509 struct device *dev = &st->spi->dev; 510 bool invert = false, stat; 511 int ret; 512 513 /* all points invalid */ 514 bitmap_fill(st->calib_map, BITS_PER_TYPE(st->calib_map)); 515 516 ret = ad9647_calibrate_prepare(st); 517 if (ret) 518 return ret; 519 retune: 520 ret = ad9647_calibrate_polarity_set(st, invert); 521 if (ret) 522 return ret; 523 524 for (point = 0; point < test_points; point++) { 525 ret = ad9467_calibrate_apply(st, point); 526 if (ret) 527 return ret; 528 529 ret = iio_backend_chan_status(st->back, 0, &stat); 530 if (ret) 531 return ret; 532 533 __assign_bit(point + invert * test_points, st->calib_map, stat); 534 } 535 536 if (!invert) { 537 cnt = ad9467_find_optimal_point(st->calib_map, 0, test_points, 538 &val); 539 /* 540 * We're happy if we find, at least, three good test points in 541 * a row. 542 */ 543 if (cnt < 3) { 544 invert = true; 545 goto retune; 546 } 547 } else { 548 inv_cnt = ad9467_find_optimal_point(st->calib_map, test_points, 549 test_points, &inv_val); 550 if (!inv_cnt && !cnt) 551 return -EIO; 552 } 553 554 if (inv_cnt < cnt) { 555 ret = ad9647_calibrate_polarity_set(st, false); 556 if (ret) 557 return ret; 558 } else { 559 /* 560 * polarity inverted is the last test to run. Hence, there's no 561 * need to re-do any configuration. We just need to "normalize" 562 * the selected value. 563 */ 564 val = inv_val - test_points; 565 } 566 567 if (st->info->has_dco) 568 dev_dbg(dev, "%sDCO 0x%X CLK %lu Hz\n", inv_cnt >= cnt ? "INVERT " : "", 569 val, sample_rate); 570 else 571 dev_dbg(dev, "%sIDELAY 0x%x\n", inv_cnt >= cnt ? "INVERT " : "", 572 val); 573 574 ret = ad9467_calibrate_apply(st, val); 575 if (ret) 576 return ret; 577 578 /* finally apply the optimal value */ 579 return ad9647_calibrate_stop(st); 580 } 581 582 static int ad9467_read_raw(struct iio_dev *indio_dev, 583 struct iio_chan_spec const *chan, 584 int *val, int *val2, long m) 585 { 586 struct ad9467_state *st = iio_priv(indio_dev); 587 588 switch (m) { 589 case IIO_CHAN_INFO_SCALE: 590 return ad9467_get_scale(st, val, val2); 591 case IIO_CHAN_INFO_SAMP_FREQ: 592 *val = clk_get_rate(st->clk); 593 594 return IIO_VAL_INT; 595 default: 596 return -EINVAL; 597 } 598 } 599 600 static int ad9467_write_raw(struct iio_dev *indio_dev, 601 struct iio_chan_spec const *chan, 602 int val, int val2, long mask) 603 { 604 struct ad9467_state *st = iio_priv(indio_dev); 605 const struct ad9467_chip_info *info = st->info; 606 unsigned long sample_rate; 607 long r_clk; 608 int ret; 609 610 switch (mask) { 611 case IIO_CHAN_INFO_SCALE: 612 return ad9467_set_scale(st, val, val2); 613 case IIO_CHAN_INFO_SAMP_FREQ: 614 r_clk = clk_round_rate(st->clk, val); 615 if (r_clk < 0 || r_clk > info->max_rate) { 616 dev_warn(&st->spi->dev, 617 "Error setting ADC sample rate %ld", r_clk); 618 return -EINVAL; 619 } 620 621 sample_rate = clk_get_rate(st->clk); 622 /* 623 * clk_set_rate() would also do this but since we would still 624 * need it for avoiding an unnecessary calibration, do it now. 625 */ 626 if (sample_rate == r_clk) 627 return 0; 628 629 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 630 ret = clk_set_rate(st->clk, r_clk); 631 if (ret) 632 return ret; 633 634 guard(mutex)(&st->lock); 635 ret = ad9467_calibrate(st); 636 } 637 return ret; 638 default: 639 return -EINVAL; 640 } 641 } 642 643 static int ad9467_read_avail(struct iio_dev *indio_dev, 644 struct iio_chan_spec const *chan, 645 const int **vals, int *type, int *length, 646 long mask) 647 { 648 struct ad9467_state *st = iio_priv(indio_dev); 649 const struct ad9467_chip_info *info = st->info; 650 651 switch (mask) { 652 case IIO_CHAN_INFO_SCALE: 653 *vals = (const int *)st->scales; 654 *type = IIO_VAL_INT_PLUS_MICRO; 655 /* Values are stored in a 2D matrix */ 656 *length = info->num_scales * 2; 657 return IIO_AVAIL_LIST; 658 default: 659 return -EINVAL; 660 } 661 } 662 663 static int ad9467_update_scan_mode(struct iio_dev *indio_dev, 664 const unsigned long *scan_mask) 665 { 666 struct ad9467_state *st = iio_priv(indio_dev); 667 unsigned int c; 668 int ret; 669 670 for (c = 0; c < st->info->num_channels; c++) { 671 if (test_bit(c, scan_mask)) 672 ret = iio_backend_chan_enable(st->back, c); 673 else 674 ret = iio_backend_chan_disable(st->back, c); 675 if (ret) 676 return ret; 677 } 678 679 return 0; 680 } 681 682 static const struct iio_info ad9467_info = { 683 .read_raw = ad9467_read_raw, 684 .write_raw = ad9467_write_raw, 685 .update_scan_mode = ad9467_update_scan_mode, 686 .debugfs_reg_access = ad9467_reg_access, 687 .read_avail = ad9467_read_avail, 688 }; 689 690 static int ad9467_scale_fill(struct ad9467_state *st) 691 { 692 const struct ad9467_chip_info *info = st->info; 693 unsigned int i, val1, val2; 694 695 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 696 sizeof(*st->scales), GFP_KERNEL); 697 if (!st->scales) 698 return -ENOMEM; 699 700 for (i = 0; i < info->num_scales; i++) { 701 __ad9467_get_scale(st, i, &val1, &val2); 702 st->scales[i][0] = val1; 703 st->scales[i][1] = val2; 704 } 705 706 return 0; 707 } 708 709 static int ad9467_reset(struct device *dev) 710 { 711 struct gpio_desc *gpio; 712 713 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 714 if (IS_ERR_OR_NULL(gpio)) 715 return PTR_ERR_OR_ZERO(gpio); 716 717 fsleep(1); 718 gpiod_set_value_cansleep(gpio, 0); 719 fsleep(10 * USEC_PER_MSEC); 720 721 return 0; 722 } 723 724 static int ad9467_iio_backend_get(struct ad9467_state *st) 725 { 726 struct device *dev = &st->spi->dev; 727 struct device_node *__back; 728 729 st->back = devm_iio_backend_get(dev, NULL); 730 if (!IS_ERR(st->back)) 731 return 0; 732 /* If not found, don't error out as we might have legacy DT property */ 733 if (PTR_ERR(st->back) != -ENOENT) 734 return PTR_ERR(st->back); 735 736 /* 737 * if we don't get the backend using the normal API's, use the legacy 738 * 'adi,adc-dev' property. So we get all nodes with that property, and 739 * look for the one pointing at us. Then we directly lookup that fwnode 740 * on the backend list of registered devices. This is done so we don't 741 * make io-backends mandatory which would break DT ABI. 742 */ 743 for_each_node_with_property(__back, "adi,adc-dev") { 744 struct device_node *__me; 745 746 __me = of_parse_phandle(__back, "adi,adc-dev", 0); 747 if (!__me) 748 continue; 749 750 if (!device_match_of_node(dev, __me)) { 751 of_node_put(__me); 752 continue; 753 } 754 755 of_node_put(__me); 756 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev, 757 of_fwnode_handle(__back)); 758 of_node_put(__back); 759 return PTR_ERR_OR_ZERO(st->back); 760 } 761 762 return -ENODEV; 763 } 764 765 static ssize_t ad9467_dump_calib_table(struct file *file, 766 char __user *userbuf, 767 size_t count, loff_t *ppos) 768 { 769 struct ad9467_state *st = file->private_data; 770 unsigned int bit, size = BITS_PER_TYPE(st->calib_map); 771 /* +2 for the newline and +1 for the string termination */ 772 unsigned char map[AD9647_MAX_TEST_POINTS * 2 + 3]; 773 ssize_t len = 0; 774 775 guard(mutex)(&st->lock); 776 if (*ppos) 777 goto out_read; 778 779 for (bit = 0; bit < size; bit++) { 780 if (bit == size / 2) 781 len += scnprintf(map + len, sizeof(map) - len, "\n"); 782 783 len += scnprintf(map + len, sizeof(map) - len, "%c", 784 test_bit(bit, st->calib_map) ? 'x' : 'o'); 785 } 786 787 len += scnprintf(map + len, sizeof(map) - len, "\n"); 788 out_read: 789 return simple_read_from_buffer(userbuf, count, ppos, map, len); 790 } 791 792 static const struct file_operations ad9467_calib_table_fops = { 793 .open = simple_open, 794 .read = ad9467_dump_calib_table, 795 .llseek = default_llseek, 796 .owner = THIS_MODULE, 797 }; 798 799 static void ad9467_debugfs_init(struct iio_dev *indio_dev) 800 { 801 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 802 struct ad9467_state *st = iio_priv(indio_dev); 803 804 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 805 return; 806 807 debugfs_create_file("calibration_table_dump", 0400, d, st, 808 &ad9467_calib_table_fops); 809 } 810 811 static int ad9467_probe(struct spi_device *spi) 812 { 813 struct iio_dev *indio_dev; 814 struct ad9467_state *st; 815 unsigned int id; 816 int ret; 817 818 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 819 if (!indio_dev) 820 return -ENOMEM; 821 822 st = iio_priv(indio_dev); 823 st->spi = spi; 824 825 st->info = spi_get_device_match_data(spi); 826 if (!st->info) 827 return -ENODEV; 828 829 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 830 if (IS_ERR(st->clk)) 831 return PTR_ERR(st->clk); 832 833 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 834 GPIOD_OUT_LOW); 835 if (IS_ERR(st->pwrdown_gpio)) 836 return PTR_ERR(st->pwrdown_gpio); 837 838 ret = ad9467_reset(&spi->dev); 839 if (ret) 840 return ret; 841 842 ret = ad9467_scale_fill(st); 843 if (ret) 844 return ret; 845 846 id = ad9467_spi_read(st, AN877_ADC_REG_CHIP_ID); 847 if (id != st->info->id) { 848 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 849 id, st->info->id); 850 return -ENODEV; 851 } 852 853 indio_dev->name = st->info->name; 854 indio_dev->channels = st->info->channels; 855 indio_dev->num_channels = st->info->num_channels; 856 indio_dev->info = &ad9467_info; 857 858 ret = ad9467_iio_backend_get(st); 859 if (ret) 860 return ret; 861 862 ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev); 863 if (ret) 864 return ret; 865 866 ret = devm_iio_backend_enable(&spi->dev, st->back); 867 if (ret) 868 return ret; 869 870 ret = ad9467_calibrate(st); 871 if (ret) 872 return ret; 873 874 ret = devm_iio_device_register(&spi->dev, indio_dev); 875 if (ret) 876 return ret; 877 878 ad9467_debugfs_init(indio_dev); 879 880 return 0; 881 } 882 883 static const struct of_device_id ad9467_of_match[] = { 884 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, }, 885 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, }, 886 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, }, 887 {} 888 }; 889 MODULE_DEVICE_TABLE(of, ad9467_of_match); 890 891 static const struct spi_device_id ad9467_ids[] = { 892 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl }, 893 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl }, 894 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl }, 895 {} 896 }; 897 MODULE_DEVICE_TABLE(spi, ad9467_ids); 898 899 static struct spi_driver ad9467_driver = { 900 .driver = { 901 .name = "ad9467", 902 .of_match_table = ad9467_of_match, 903 }, 904 .probe = ad9467_probe, 905 .id_table = ad9467_ids, 906 }; 907 module_spi_driver(ad9467_driver); 908 909 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 910 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 911 MODULE_LICENSE("GPL v2"); 912 MODULE_IMPORT_NS(IIO_BACKEND); 913