1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/of.h> 22 #include <linux/seq_file.h> 23 #include <linux/slab.h> 24 #include <linux/spi/spi.h> 25 #include <linux/units.h> 26 27 #include <linux/iio/backend.h> 28 #include <linux/iio/iio.h> 29 #include <linux/iio/sysfs.h> 30 31 /* 32 * ADI High-Speed ADC common spi interface registers 33 * See Application-Note AN-877: 34 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 35 */ 36 37 #define AN877_ADC_REG_CHIP_PORT_CONF 0x00 38 #define AN877_ADC_REG_CHIP_ID 0x01 39 #define AN877_ADC_REG_CHIP_GRADE 0x02 40 #define AN877_ADC_REG_CHAN_INDEX 0x05 41 #define AN877_ADC_REG_TRANSFER 0xFF 42 #define AN877_ADC_REG_MODES 0x08 43 #define AN877_ADC_REG_TEST_IO 0x0D 44 #define AN877_ADC_REG_ADC_INPUT 0x0F 45 #define AN877_ADC_REG_OFFSET 0x10 46 #define AN877_ADC_REG_OUTPUT_MODE 0x14 47 #define AN877_ADC_REG_OUTPUT_ADJUST 0x15 48 #define AN877_ADC_REG_OUTPUT_PHASE 0x16 49 #define AN877_ADC_REG_OUTPUT_DELAY 0x17 50 #define AN877_ADC_REG_VREF 0x18 51 #define AN877_ADC_REG_ANALOG_INPUT 0x2C 52 53 /* AN877_ADC_REG_TEST_IO */ 54 #define AN877_ADC_TESTMODE_OFF 0x0 55 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 56 #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 57 #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 58 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 59 #define AN877_ADC_TESTMODE_PN23_SEQ 0x5 60 #define AN877_ADC_TESTMODE_PN9_SEQ 0x6 61 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 62 #define AN877_ADC_TESTMODE_USER 0x8 63 #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 64 #define AN877_ADC_TESTMODE_SYNC 0xA 65 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 66 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 67 #define AN877_ADC_TESTMODE_RAMP 0xF 68 69 /* AN877_ADC_REG_TRANSFER */ 70 #define AN877_ADC_TRANSFER_SYNC 0x1 71 72 /* AN877_ADC_REG_OUTPUT_MODE */ 73 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 74 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 75 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 76 #define AN877_ADC_OUTPUT_MODE_MASK GENMASK(1, 0) 77 78 /* AN877_ADC_REG_OUTPUT_PHASE */ 79 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 80 #define AN877_ADC_INVERT_DCO_CLK 0x80 81 82 /* AN877_ADC_REG_OUTPUT_DELAY */ 83 #define AN877_ADC_DCO_DELAY_ENABLE 0x80 84 85 /* 86 * Analog Devices AD9211 10-Bit, 200/250/300 MSPS ADC 87 */ 88 89 #define CHIPID_AD9211 0x06 90 #define AD9211_DEF_OUTPUT_MODE 0x01 91 #define AD9211_REG_VREF_MASK GENMASK(4, 0) 92 93 /* 94 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 95 */ 96 97 #define CHIPID_AD9265 0x64 98 #define AD9265_DEF_OUTPUT_MODE 0x41 99 #define AD9265_REG_VREF_MASK 0xC0 100 101 /* 102 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 103 */ 104 105 #define CHIPID_AD9434 0x6A 106 #define AD9434_DEF_OUTPUT_MODE 0x01 107 #define AD9434_REG_VREF_MASK GENMASK(4, 0) 108 109 /* 110 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 111 */ 112 113 #define CHIPID_AD9467 0x50 114 #define AD9467_DEF_OUTPUT_MODE 0x09 115 #define AD9467_REG_VREF_MASK 0x0F 116 117 /* 118 * Analog Devices AD9643 14-Bit, 170/210/250 MSPS ADC 119 */ 120 121 #define CHIPID_AD9643 0x82 122 #define AD9643_DEF_OUTPUT_MODE 0x01 123 #define AD9643_REG_VREF_MASK 0x1F 124 125 /* 126 * Analog Devices AD9652 16-bit 310 MSPS ADC 127 */ 128 129 #define CHIPID_AD9652 0xC1 130 #define AD9652_DEF_OUTPUT_MODE 0x01 131 #define AD9652_REG_VREF_MASK 0xC0 132 133 /* 134 * Analog Devices AD9649 14-bit 20/40/65/80 MSPS ADC 135 */ 136 137 #define CHIPID_AD9649 0x6F 138 #define AD9649_DEF_OUTPUT_MODE 0x01 139 #define AD9649_TEST_POINTS 8 140 141 #define AD9647_MAX_TEST_POINTS 32 142 #define AD9467_CAN_INVERT(st) \ 143 (!(st)->info->has_dco || (st)->info->has_dco_invert) 144 145 struct ad9467_chip_info { 146 const char *name; 147 unsigned int id; 148 const struct iio_chan_spec *channels; 149 unsigned int num_channels; 150 const unsigned int (*scale_table)[2]; 151 int num_scales; 152 unsigned long test_mask; 153 unsigned int test_mask_len; 154 unsigned long max_rate; 155 unsigned int default_output_mode; 156 unsigned int vref_mask; 157 unsigned int num_lanes; 158 unsigned int dco_en; 159 unsigned int test_points; 160 const int *offset_range; 161 /* data clock output */ 162 bool has_dco; 163 bool has_dco_invert; 164 }; 165 166 struct ad9467_chan_test_mode { 167 struct ad9467_state *st; 168 unsigned int idx; 169 u8 mode; 170 }; 171 172 struct ad9467_state { 173 const struct ad9467_chip_info *info; 174 struct iio_backend *back; 175 struct spi_device *spi; 176 struct clk *clk; 177 /* used for debugfs */ 178 struct ad9467_chan_test_mode *chan_test; 179 unsigned int output_mode; 180 unsigned int (*scales)[2]; 181 /* 182 * Times 2 because we may also invert the signal polarity and run the 183 * calibration again. For some reference on the test points (ad9265) see: 184 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad9265.pdf 185 * at page 38 for the dco output delay. On devices as ad9467, the 186 * calibration is done at the backend level. For the ADI axi-adc: 187 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 188 * at the io delay control section. 189 */ 190 DECLARE_BITMAP(calib_map, AD9647_MAX_TEST_POINTS * 2); 191 /* number of bits of the map */ 192 unsigned int calib_map_size; 193 struct gpio_desc *pwrdown_gpio; 194 /* ensure consistent state obtained on multiple related accesses */ 195 struct mutex lock; 196 u8 buf[3] __aligned(IIO_DMA_MINALIGN); 197 }; 198 199 static int ad9467_spi_read(struct ad9467_state *st, unsigned int reg) 200 { 201 unsigned char tbuf[2], rbuf[1]; 202 int ret; 203 204 tbuf[0] = 0x80 | (reg >> 8); 205 tbuf[1] = reg & 0xFF; 206 207 ret = spi_write_then_read(st->spi, 208 tbuf, ARRAY_SIZE(tbuf), 209 rbuf, ARRAY_SIZE(rbuf)); 210 211 if (ret < 0) 212 return ret; 213 214 return rbuf[0]; 215 } 216 217 static int ad9467_spi_write(struct ad9467_state *st, unsigned int reg, 218 unsigned int val) 219 { 220 st->buf[0] = reg >> 8; 221 st->buf[1] = reg & 0xFF; 222 st->buf[2] = val; 223 224 return spi_write(st->spi, st->buf, ARRAY_SIZE(st->buf)); 225 } 226 227 static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg, 228 unsigned int writeval, unsigned int *readval) 229 { 230 struct ad9467_state *st = iio_priv(indio_dev); 231 int ret; 232 233 if (!readval) { 234 guard(mutex)(&st->lock); 235 ret = ad9467_spi_write(st, reg, writeval); 236 if (ret) 237 return ret; 238 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 239 AN877_ADC_TRANSFER_SYNC); 240 } 241 242 ret = ad9467_spi_read(st, reg); 243 if (ret < 0) 244 return ret; 245 *readval = ret; 246 247 return 0; 248 } 249 250 static const int ad9434_offset_range[] = { 251 -128, 1, 127, 252 }; 253 254 static const unsigned int ad9211_scale_table[][2] = { 255 {980, 0x10}, {1000, 0x11}, {1020, 0x12}, {1040, 0x13}, 256 {1060, 0x14}, {1080, 0x15}, {1100, 0x16}, {1120, 0x17}, 257 {1140, 0x18}, {1160, 0x19}, {1180, 0x1A}, {1190, 0x1B}, 258 {1200, 0x1C}, {1210, 0x1D}, {1220, 0x1E}, {1230, 0x1F}, 259 {1250, 0x0}, {1270, 0x1}, {1290, 0x2}, {1310, 0x3}, 260 {1330, 0x4}, {1350, 0x5}, {1370, 0x6}, {1390, 0x7}, 261 {1410, 0x8}, {1430, 0x9}, {1450, 0xA}, {1460, 0xB}, 262 {1470, 0xC}, {1480, 0xD}, {1490, 0xE}, {1500, 0xF}, 263 }; 264 265 static const unsigned int ad9265_scale_table[][2] = { 266 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 267 }; 268 269 static const unsigned int ad9434_scale_table[][2] = { 270 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 271 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 272 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 273 {1200, 0x0B}, {1180, 0x0C}, 274 }; 275 276 static const unsigned int ad9467_scale_table[][2] = { 277 {2000, 0}, {2100, 6}, {2200, 7}, 278 {2300, 8}, {2400, 9}, {2500, 10}, 279 }; 280 281 static const unsigned int ad9643_scale_table[][2] = { 282 {2087, 0x0F}, {2065, 0x0E}, {2042, 0x0D}, {2020, 0x0C}, {1997, 0x0B}, 283 {1975, 0x0A}, {1952, 0x09}, {1930, 0x08}, {1907, 0x07}, {1885, 0x06}, 284 {1862, 0x05}, {1840, 0x04}, {1817, 0x03}, {1795, 0x02}, {1772, 0x01}, 285 {1750, 0x00}, {1727, 0x1F}, {1704, 0x1E}, {1681, 0x1D}, {1658, 0x1C}, 286 {1635, 0x1B}, {1612, 0x1A}, {1589, 0x19}, {1567, 0x18}, {1544, 0x17}, 287 {1521, 0x16}, {1498, 0x15}, {1475, 0x14}, {1452, 0x13}, {1429, 0x12}, 288 {1406, 0x11}, {1383, 0x10}, 289 }; 290 291 static const unsigned int ad9649_scale_table[][2] = { 292 {2000, 0}, 293 }; 294 295 static const unsigned int ad9652_scale_table[][2] = { 296 {1250, 0}, {1125, 1}, {1200, 2}, {1250, 3}, {1000, 5}, 297 }; 298 299 static void __ad9467_get_scale(struct ad9467_state *st, int index, 300 unsigned int *val, unsigned int *val2) 301 { 302 const struct ad9467_chip_info *info = st->info; 303 const struct iio_chan_spec *chan = &info->channels[0]; 304 unsigned int tmp; 305 306 tmp = (info->scale_table[index][0] * 1000000ULL) >> 307 chan->scan_type.realbits; 308 *val = tmp / 1000000; 309 *val2 = tmp % 1000000; 310 } 311 312 #define AD9467_CHAN(_chan, avai_mask, _si, _bits, _sign) \ 313 { \ 314 .type = IIO_VOLTAGE, \ 315 .indexed = 1, \ 316 .channel = _chan, \ 317 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 318 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 319 .info_mask_shared_by_type_available = avai_mask, \ 320 .scan_index = _si, \ 321 .scan_type = { \ 322 .sign = _sign, \ 323 .realbits = _bits, \ 324 .storagebits = 16, \ 325 }, \ 326 } 327 328 static const struct iio_chan_spec ad9211_channels[] = { 329 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 10, 's'), 330 }; 331 332 static const struct iio_chan_spec ad9434_channels[] = { 333 { 334 .type = IIO_VOLTAGE, 335 .indexed = 1, 336 .channel = 0, 337 .info_mask_shared_by_type = 338 BIT(IIO_CHAN_INFO_SCALE) | 339 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 340 BIT(IIO_CHAN_INFO_CALIBBIAS), 341 .info_mask_shared_by_type_available = 342 BIT(IIO_CHAN_INFO_SCALE) | 343 BIT(IIO_CHAN_INFO_CALIBBIAS), 344 .scan_index = 0, 345 .scan_type = { 346 .sign = 's', 347 .realbits = 12, 348 .storagebits = 16, 349 }, 350 }, 351 }; 352 353 static const struct iio_chan_spec ad9467_channels[] = { 354 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'), 355 }; 356 357 static const struct iio_chan_spec ad9643_channels[] = { 358 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 14, 's'), 359 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 14, 's'), 360 }; 361 362 static const struct iio_chan_spec ad9649_channels[] = { 363 AD9467_CHAN(0, 0, 0, 14, 's'), 364 }; 365 366 static const struct iio_chan_spec ad9652_channels[] = { 367 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'), 368 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 16, 's'), 369 }; 370 371 static const char * const ad9467_test_modes[] = { 372 [AN877_ADC_TESTMODE_OFF] = "off", 373 [AN877_ADC_TESTMODE_MIDSCALE_SHORT] = "midscale_short", 374 [AN877_ADC_TESTMODE_POS_FULLSCALE] = "pos_fullscale", 375 [AN877_ADC_TESTMODE_NEG_FULLSCALE] = "neg_fullscale", 376 [AN877_ADC_TESTMODE_ALT_CHECKERBOARD] = "checkerboard", 377 [AN877_ADC_TESTMODE_PN23_SEQ] = "prbs23", 378 [AN877_ADC_TESTMODE_PN9_SEQ] = "prbs9", 379 [AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE] = "one_zero_toggle", 380 [AN877_ADC_TESTMODE_USER] = "user", 381 [AN877_ADC_TESTMODE_BIT_TOGGLE] = "bit_toggle", 382 [AN877_ADC_TESTMODE_SYNC] = "sync", 383 [AN877_ADC_TESTMODE_ONE_BIT_HIGH] = "one_bit_high", 384 [AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY] = "mixed_bit_frequency", 385 [AN877_ADC_TESTMODE_RAMP] = "ramp", 386 }; 387 388 static const struct ad9467_chip_info ad9467_chip_tbl = { 389 .name = "ad9467", 390 .id = CHIPID_AD9467, 391 .max_rate = 250000000UL, 392 .scale_table = ad9467_scale_table, 393 .num_scales = ARRAY_SIZE(ad9467_scale_table), 394 .channels = ad9467_channels, 395 .num_channels = ARRAY_SIZE(ad9467_channels), 396 .test_points = AD9647_MAX_TEST_POINTS, 397 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 398 AN877_ADC_TESTMODE_OFF), 399 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 400 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 401 .vref_mask = AD9467_REG_VREF_MASK, 402 .num_lanes = 8, 403 }; 404 405 static const struct ad9467_chip_info ad9434_chip_tbl = { 406 .name = "ad9434", 407 .id = CHIPID_AD9434, 408 .max_rate = 500000000UL, 409 .scale_table = ad9434_scale_table, 410 .num_scales = ARRAY_SIZE(ad9434_scale_table), 411 .channels = ad9434_channels, 412 .num_channels = ARRAY_SIZE(ad9434_channels), 413 .test_points = AD9647_MAX_TEST_POINTS, 414 .test_mask = GENMASK(AN877_ADC_TESTMODE_USER, AN877_ADC_TESTMODE_OFF), 415 .test_mask_len = AN877_ADC_TESTMODE_USER + 1, 416 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 417 .vref_mask = AD9434_REG_VREF_MASK, 418 .num_lanes = 6, 419 .offset_range = ad9434_offset_range, 420 }; 421 422 static const struct ad9467_chip_info ad9211_chip_tbl = { 423 .name = "ad9211", 424 .id = CHIPID_AD9211, 425 .max_rate = 300 * HZ_PER_MHZ, 426 .scale_table = ad9211_scale_table, 427 .num_scales = ARRAY_SIZE(ad9211_scale_table), 428 .channels = ad9211_channels, 429 .num_channels = ARRAY_SIZE(ad9211_channels), 430 .test_points = AD9647_MAX_TEST_POINTS, 431 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 432 AN877_ADC_TESTMODE_OFF), 433 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 434 .default_output_mode = AD9211_DEF_OUTPUT_MODE, 435 .vref_mask = AD9211_REG_VREF_MASK, 436 .has_dco = true, 437 }; 438 439 static const struct ad9467_chip_info ad9265_chip_tbl = { 440 .name = "ad9265", 441 .id = CHIPID_AD9265, 442 .max_rate = 125000000UL, 443 .scale_table = ad9265_scale_table, 444 .num_scales = ARRAY_SIZE(ad9265_scale_table), 445 .channels = ad9467_channels, 446 .num_channels = ARRAY_SIZE(ad9467_channels), 447 .test_points = AD9647_MAX_TEST_POINTS, 448 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 449 AN877_ADC_TESTMODE_OFF), 450 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 451 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 452 .vref_mask = AD9265_REG_VREF_MASK, 453 .has_dco = true, 454 .has_dco_invert = true, 455 }; 456 457 static const struct ad9467_chip_info ad9643_chip_tbl = { 458 .name = "ad9643", 459 .id = CHIPID_AD9643, 460 .max_rate = 250000000UL, 461 .scale_table = ad9643_scale_table, 462 .num_scales = ARRAY_SIZE(ad9643_scale_table), 463 .channels = ad9643_channels, 464 .num_channels = ARRAY_SIZE(ad9643_channels), 465 .test_points = AD9647_MAX_TEST_POINTS, 466 .test_mask = BIT(AN877_ADC_TESTMODE_RAMP) | 467 GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, AN877_ADC_TESTMODE_OFF), 468 .test_mask_len = AN877_ADC_TESTMODE_RAMP + 1, 469 .default_output_mode = AD9643_DEF_OUTPUT_MODE, 470 .vref_mask = AD9643_REG_VREF_MASK, 471 .has_dco = true, 472 .has_dco_invert = true, 473 .dco_en = AN877_ADC_DCO_DELAY_ENABLE, 474 }; 475 476 static const struct ad9467_chip_info ad9649_chip_tbl = { 477 .name = "ad9649", 478 .id = CHIPID_AD9649, 479 .max_rate = 80000000UL, 480 .scale_table = ad9649_scale_table, 481 .num_scales = ARRAY_SIZE(ad9649_scale_table), 482 .channels = ad9649_channels, 483 .num_channels = ARRAY_SIZE(ad9649_channels), 484 .test_points = AD9649_TEST_POINTS, 485 .test_mask = GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, 486 AN877_ADC_TESTMODE_OFF), 487 .test_mask_len = AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY + 1, 488 .default_output_mode = AD9649_DEF_OUTPUT_MODE, 489 .has_dco = true, 490 .has_dco_invert = true, 491 .dco_en = AN877_ADC_DCO_DELAY_ENABLE, 492 }; 493 494 static const struct ad9467_chip_info ad9652_chip_tbl = { 495 .name = "ad9652", 496 .id = CHIPID_AD9652, 497 .max_rate = 310000000UL, 498 .scale_table = ad9652_scale_table, 499 .num_scales = ARRAY_SIZE(ad9652_scale_table), 500 .channels = ad9652_channels, 501 .num_channels = ARRAY_SIZE(ad9652_channels), 502 .test_points = AD9647_MAX_TEST_POINTS, 503 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 504 AN877_ADC_TESTMODE_OFF), 505 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 506 .default_output_mode = AD9652_DEF_OUTPUT_MODE, 507 .vref_mask = AD9652_REG_VREF_MASK, 508 .has_dco = true, 509 }; 510 511 static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2) 512 { 513 const struct ad9467_chip_info *info = st->info; 514 unsigned int vref_val; 515 unsigned int i = 0; 516 int ret; 517 518 /* nothing to read if we only have one possible scale */ 519 if (info->num_scales == 1) 520 goto out_get_scale; 521 522 ret = ad9467_spi_read(st, AN877_ADC_REG_VREF); 523 if (ret < 0) 524 return ret; 525 526 vref_val = ret & info->vref_mask; 527 528 for (i = 0; i < info->num_scales; i++) { 529 if (vref_val == info->scale_table[i][1]) 530 break; 531 } 532 533 if (i == info->num_scales) 534 return -ERANGE; 535 536 out_get_scale: 537 __ad9467_get_scale(st, i, val, val2); 538 539 return IIO_VAL_INT_PLUS_MICRO; 540 } 541 542 static int ad9467_set_scale(struct ad9467_state *st, int val, int val2) 543 { 544 const struct ad9467_chip_info *info = st->info; 545 unsigned int scale_val[2]; 546 unsigned int i; 547 int ret; 548 549 if (val != 0) 550 return -EINVAL; 551 if (info->num_scales == 1) 552 return -EOPNOTSUPP; 553 554 for (i = 0; i < info->num_scales; i++) { 555 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]); 556 if (scale_val[0] != val || scale_val[1] != val2) 557 continue; 558 559 guard(mutex)(&st->lock); 560 ret = ad9467_spi_write(st, AN877_ADC_REG_VREF, 561 info->scale_table[i][1]); 562 if (ret < 0) 563 return ret; 564 565 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 566 AN877_ADC_TRANSFER_SYNC); 567 } 568 569 return -EINVAL; 570 } 571 572 static int ad9467_get_offset(struct ad9467_state *st, int *val) 573 { 574 int ret; 575 576 ret = ad9467_spi_read(st, AN877_ADC_REG_OFFSET); 577 if (ret < 0) 578 return ret; 579 *val = ret; 580 581 return IIO_VAL_INT; 582 } 583 584 static int ad9467_set_offset(struct ad9467_state *st, int val) 585 { 586 int ret; 587 588 if (val < st->info->offset_range[0] || val > st->info->offset_range[2]) 589 return -EINVAL; 590 591 ret = ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val); 592 if (ret < 0) 593 return ret; 594 595 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 596 AN877_ADC_TRANSFER_SYNC); 597 } 598 599 static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode) 600 { 601 int ret; 602 603 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_MODE, mode); 604 if (ret < 0) 605 return ret; 606 607 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 608 AN877_ADC_TRANSFER_SYNC); 609 } 610 611 static int ad9467_testmode_set(struct ad9467_state *st, unsigned int chan, 612 unsigned int test_mode) 613 { 614 int ret; 615 616 if (st->info->num_channels > 1) { 617 /* so that the test mode is only applied to one channel */ 618 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, BIT(chan)); 619 if (ret) 620 return ret; 621 } 622 623 ret = ad9467_spi_write(st, AN877_ADC_REG_TEST_IO, test_mode); 624 if (ret) 625 return ret; 626 627 if (st->info->num_channels > 1) { 628 /* go to default state where all channels get write commands */ 629 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, 630 GENMASK(st->info->num_channels - 1, 0)); 631 if (ret) 632 return ret; 633 } 634 635 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 636 AN877_ADC_TRANSFER_SYNC); 637 } 638 639 static int ad9467_backend_testmode_on(struct ad9467_state *st, 640 unsigned int chan, 641 enum iio_backend_test_pattern pattern) 642 { 643 struct iio_backend_data_fmt data = { 644 .enable = false, 645 }; 646 int ret; 647 648 ret = iio_backend_data_format_set(st->back, chan, &data); 649 if (ret) 650 return ret; 651 652 ret = iio_backend_test_pattern_set(st->back, chan, pattern); 653 if (ret) 654 return ret; 655 656 return iio_backend_chan_enable(st->back, chan); 657 } 658 659 static int ad9467_backend_testmode_off(struct ad9467_state *st, 660 unsigned int chan) 661 { 662 struct iio_backend_data_fmt data = { 663 .enable = true, 664 .sign_extend = true, 665 }; 666 int ret; 667 668 ret = iio_backend_chan_disable(st->back, chan); 669 if (ret) 670 return ret; 671 672 ret = iio_backend_test_pattern_set(st->back, chan, 673 IIO_BACKEND_NO_TEST_PATTERN); 674 if (ret) 675 return ret; 676 677 return iio_backend_data_format_set(st->back, chan, &data); 678 } 679 680 static int ad9647_calibrate_prepare(struct ad9467_state *st) 681 { 682 unsigned int cmode; 683 unsigned int c; 684 int ret; 685 686 cmode = st->info->default_output_mode; 687 FIELD_MODIFY(AN877_ADC_OUTPUT_MODE_MASK, &cmode, 688 AN877_ADC_OUTPUT_MODE_OFFSET_BINARY); 689 ret = ad9467_outputmode_set(st, cmode); 690 if (ret) 691 return ret; 692 693 for (c = 0; c < st->info->num_channels; c++) { 694 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_PN9_SEQ); 695 if (ret) 696 return ret; 697 698 ret = ad9467_backend_testmode_on(st, c, 699 IIO_BACKEND_ADI_PRBS_9A); 700 if (ret) 701 return ret; 702 } 703 704 return 0; 705 } 706 707 static int ad9647_calibrate_polarity_set(struct ad9467_state *st, 708 bool invert) 709 { 710 enum iio_backend_sample_trigger trigger; 711 712 if (st->info->has_dco) { 713 unsigned int phase = AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN; 714 715 if (invert) 716 phase |= AN877_ADC_INVERT_DCO_CLK; 717 718 return ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_PHASE, 719 phase); 720 } 721 722 if (invert) 723 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING; 724 else 725 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING; 726 727 return iio_backend_data_sample_trigger(st->back, trigger); 728 } 729 730 /* 731 * The idea is pretty simple. Find the max number of successful points in a row 732 * and get the one in the middle. 733 */ 734 static unsigned int ad9467_find_optimal_point(const unsigned long *calib_map, 735 unsigned int start, 736 unsigned int nbits, 737 unsigned int *val) 738 { 739 unsigned int bit = start, end, start_cnt, cnt = 0; 740 741 for_each_clear_bitrange_from(bit, end, calib_map, nbits + start) { 742 if (end - bit > cnt) { 743 cnt = end - bit; 744 start_cnt = bit; 745 } 746 } 747 748 if (cnt) 749 *val = start_cnt + cnt / 2; 750 751 return cnt; 752 } 753 754 static int ad9467_calibrate_apply(struct ad9467_state *st, unsigned int val) 755 { 756 unsigned int lane; 757 int ret; 758 759 if (st->info->has_dco) { 760 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_DELAY, 761 val | st->info->dco_en); 762 if (ret) 763 return ret; 764 765 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 766 AN877_ADC_TRANSFER_SYNC); 767 } 768 769 for (lane = 0; lane < st->info->num_lanes; lane++) { 770 ret = iio_backend_iodelay_set(st->back, lane, val); 771 if (ret) 772 return ret; 773 } 774 775 return 0; 776 } 777 778 static int ad9647_calibrate_stop(struct ad9467_state *st) 779 { 780 unsigned int c, mode; 781 int ret; 782 783 for (c = 0; c < st->info->num_channels; c++) { 784 ret = ad9467_backend_testmode_off(st, c); 785 if (ret) 786 return ret; 787 788 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_OFF); 789 if (ret) 790 return ret; 791 } 792 793 mode = st->info->default_output_mode; 794 return ad9467_outputmode_set(st, mode); 795 } 796 797 static int ad9467_calibrate(struct ad9467_state *st) 798 { 799 unsigned int point, val, inv_val, cnt, inv_cnt = 0, c; 800 /* 801 * Half of the bitmap is for the inverted signal. The number of test 802 * points is the same though... 803 */ 804 unsigned int test_points = st->info->test_points; 805 unsigned long sample_rate = clk_get_rate(st->clk); 806 struct device *dev = &st->spi->dev; 807 bool invert = false, stat; 808 int ret; 809 810 /* all points invalid */ 811 bitmap_fill(st->calib_map, st->calib_map_size); 812 813 ret = ad9647_calibrate_prepare(st); 814 if (ret) 815 return ret; 816 retune: 817 ret = ad9647_calibrate_polarity_set(st, invert); 818 if (ret) 819 return ret; 820 821 for (point = 0; point < st->info->test_points; point++) { 822 ret = ad9467_calibrate_apply(st, point); 823 if (ret) 824 return ret; 825 826 for (c = 0; c < st->info->num_channels; c++) { 827 ret = iio_backend_chan_status(st->back, c, &stat); 828 if (ret) 829 return ret; 830 831 /* 832 * A point is considered valid if all channels report no 833 * error. If one reports an error, then we consider the 834 * point as invalid and we can break the loop right away. 835 */ 836 if (stat) { 837 dev_dbg(dev, "Invalid point(%u, inv:%u) for CH:%u\n", 838 point, invert, c); 839 break; 840 } 841 842 if (c == st->info->num_channels - 1) 843 __clear_bit(point + invert * test_points, 844 st->calib_map); 845 } 846 } 847 848 if (!invert) { 849 cnt = ad9467_find_optimal_point(st->calib_map, 0, test_points, 850 &val); 851 /* 852 * We're happy if we find, at least, three good test points in 853 * a row. 854 */ 855 if (cnt < 3) { 856 if (AD9467_CAN_INVERT(st)) { 857 invert = true; 858 goto retune; 859 } 860 861 if (!cnt) 862 return -EIO; 863 } 864 } else { 865 inv_cnt = ad9467_find_optimal_point(st->calib_map, test_points, 866 test_points, &inv_val); 867 if (!inv_cnt && !cnt) 868 return -EIO; 869 } 870 871 if (inv_cnt < cnt) { 872 ret = ad9647_calibrate_polarity_set(st, false); 873 if (ret) 874 return ret; 875 } else { 876 /* 877 * polarity inverted is the last test to run. Hence, there's no 878 * need to re-do any configuration. We just need to "normalize" 879 * the selected value. 880 */ 881 val = inv_val - test_points; 882 } 883 884 if (st->info->has_dco) 885 dev_dbg(dev, "%sDCO 0x%X CLK %lu Hz\n", inv_cnt >= cnt ? "INVERT " : "", 886 val, sample_rate); 887 else 888 dev_dbg(dev, "%sIDELAY 0x%x\n", inv_cnt >= cnt ? "INVERT " : "", 889 val); 890 891 ret = ad9467_calibrate_apply(st, val); 892 if (ret) 893 return ret; 894 895 /* finally apply the optimal value */ 896 return ad9647_calibrate_stop(st); 897 } 898 899 static int ad9467_read_raw(struct iio_dev *indio_dev, 900 struct iio_chan_spec const *chan, 901 int *val, int *val2, long m) 902 { 903 struct ad9467_state *st = iio_priv(indio_dev); 904 905 switch (m) { 906 case IIO_CHAN_INFO_CALIBBIAS: 907 return ad9467_get_offset(st, val); 908 case IIO_CHAN_INFO_SCALE: 909 return ad9467_get_scale(st, val, val2); 910 case IIO_CHAN_INFO_SAMP_FREQ: 911 *val = clk_get_rate(st->clk); 912 913 return IIO_VAL_INT; 914 default: 915 return -EINVAL; 916 } 917 } 918 919 static int __ad9467_update_clock(struct ad9467_state *st, long r_clk) 920 { 921 int ret; 922 923 ret = clk_set_rate(st->clk, r_clk); 924 if (ret) 925 return ret; 926 927 guard(mutex)(&st->lock); 928 return ad9467_calibrate(st); 929 } 930 931 static int ad9467_write_raw(struct iio_dev *indio_dev, 932 struct iio_chan_spec const *chan, 933 int val, int val2, long mask) 934 { 935 struct ad9467_state *st = iio_priv(indio_dev); 936 const struct ad9467_chip_info *info = st->info; 937 unsigned long sample_rate; 938 long r_clk; 939 int ret; 940 941 switch (mask) { 942 case IIO_CHAN_INFO_CALIBBIAS: 943 return ad9467_set_offset(st, val); 944 case IIO_CHAN_INFO_SCALE: 945 return ad9467_set_scale(st, val, val2); 946 case IIO_CHAN_INFO_SAMP_FREQ: 947 r_clk = clk_round_rate(st->clk, val); 948 if (r_clk < 0 || r_clk > info->max_rate) { 949 dev_warn(&st->spi->dev, 950 "Error setting ADC sample rate %ld", r_clk); 951 return -EINVAL; 952 } 953 954 sample_rate = clk_get_rate(st->clk); 955 /* 956 * clk_set_rate() would also do this but since we would still 957 * need it for avoiding an unnecessary calibration, do it now. 958 */ 959 if (sample_rate == r_clk) 960 return 0; 961 962 if (!iio_device_claim_direct(indio_dev)) 963 return -EBUSY; 964 965 ret = __ad9467_update_clock(st, r_clk); 966 iio_device_release_direct(indio_dev); 967 return ret; 968 default: 969 return -EINVAL; 970 } 971 } 972 973 static int ad9467_read_avail(struct iio_dev *indio_dev, 974 struct iio_chan_spec const *chan, 975 const int **vals, int *type, int *length, 976 long mask) 977 { 978 struct ad9467_state *st = iio_priv(indio_dev); 979 const struct ad9467_chip_info *info = st->info; 980 981 switch (mask) { 982 case IIO_CHAN_INFO_CALIBBIAS: 983 *type = IIO_VAL_INT; 984 *vals = info->offset_range; 985 return IIO_AVAIL_RANGE; 986 case IIO_CHAN_INFO_SCALE: 987 *vals = (const int *)st->scales; 988 *type = IIO_VAL_INT_PLUS_MICRO; 989 /* Values are stored in a 2D matrix */ 990 *length = info->num_scales * 2; 991 return IIO_AVAIL_LIST; 992 default: 993 return -EINVAL; 994 } 995 } 996 997 static int ad9467_update_scan_mode(struct iio_dev *indio_dev, 998 const unsigned long *scan_mask) 999 { 1000 struct ad9467_state *st = iio_priv(indio_dev); 1001 unsigned int c; 1002 int ret; 1003 1004 for (c = 0; c < st->info->num_channels; c++) { 1005 if (test_bit(c, scan_mask)) 1006 ret = iio_backend_chan_enable(st->back, c); 1007 else 1008 ret = iio_backend_chan_disable(st->back, c); 1009 if (ret) 1010 return ret; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static const struct iio_info ad9467_info = { 1017 .read_raw = ad9467_read_raw, 1018 .write_raw = ad9467_write_raw, 1019 .update_scan_mode = ad9467_update_scan_mode, 1020 .debugfs_reg_access = ad9467_reg_access, 1021 .read_avail = ad9467_read_avail, 1022 }; 1023 1024 /* Same as above, but without .read_avail */ 1025 static const struct iio_info ad9467_info_no_read_avail = { 1026 .read_raw = ad9467_read_raw, 1027 .write_raw = ad9467_write_raw, 1028 .update_scan_mode = ad9467_update_scan_mode, 1029 .debugfs_reg_access = ad9467_reg_access, 1030 }; 1031 1032 static int ad9467_scale_fill(struct ad9467_state *st) 1033 { 1034 const struct ad9467_chip_info *info = st->info; 1035 unsigned int i, val1, val2; 1036 1037 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 1038 sizeof(*st->scales), GFP_KERNEL); 1039 if (!st->scales) 1040 return -ENOMEM; 1041 1042 for (i = 0; i < info->num_scales; i++) { 1043 __ad9467_get_scale(st, i, &val1, &val2); 1044 st->scales[i][0] = val1; 1045 st->scales[i][1] = val2; 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int ad9467_reset(struct device *dev) 1052 { 1053 struct gpio_desc *gpio; 1054 1055 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1056 if (IS_ERR_OR_NULL(gpio)) 1057 return PTR_ERR_OR_ZERO(gpio); 1058 1059 fsleep(1); 1060 gpiod_set_value_cansleep(gpio, 0); 1061 fsleep(10 * USEC_PER_MSEC); 1062 1063 return 0; 1064 } 1065 1066 static int ad9467_iio_backend_get(struct ad9467_state *st) 1067 { 1068 struct device *dev = &st->spi->dev; 1069 struct device_node *__back; 1070 1071 st->back = devm_iio_backend_get(dev, NULL); 1072 if (!IS_ERR(st->back)) 1073 return 0; 1074 /* If not found, don't error out as we might have legacy DT property */ 1075 if (PTR_ERR(st->back) != -ENOENT) 1076 return PTR_ERR(st->back); 1077 1078 /* 1079 * if we don't get the backend using the normal API's, use the legacy 1080 * 'adi,adc-dev' property. So we get all nodes with that property, and 1081 * look for the one pointing at us. Then we directly lookup that fwnode 1082 * on the backend list of registered devices. This is done so we don't 1083 * make io-backends mandatory which would break DT ABI. 1084 */ 1085 for_each_node_with_property(__back, "adi,adc-dev") { 1086 struct device_node *__me; 1087 1088 __me = of_parse_phandle(__back, "adi,adc-dev", 0); 1089 if (!__me) 1090 continue; 1091 1092 if (!device_match_of_node(dev, __me)) { 1093 of_node_put(__me); 1094 continue; 1095 } 1096 1097 of_node_put(__me); 1098 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev, 1099 of_fwnode_handle(__back)); 1100 of_node_put(__back); 1101 return PTR_ERR_OR_ZERO(st->back); 1102 } 1103 1104 return -ENODEV; 1105 } 1106 1107 static int ad9467_test_mode_available_show(struct seq_file *s, void *ignored) 1108 { 1109 struct ad9467_state *st = s->private; 1110 unsigned int bit; 1111 1112 for_each_set_bit(bit, &st->info->test_mask, st->info->test_mask_len) 1113 seq_printf(s, "%s\n", ad9467_test_modes[bit]); 1114 1115 return 0; 1116 } 1117 DEFINE_SHOW_ATTRIBUTE(ad9467_test_mode_available); 1118 1119 static ssize_t ad9467_chan_test_mode_read(struct file *file, 1120 char __user *userbuf, size_t count, 1121 loff_t *ppos) 1122 { 1123 struct ad9467_chan_test_mode *chan = file->private_data; 1124 struct ad9467_state *st = chan->st; 1125 char buf[128] = {0}; 1126 size_t len; 1127 int ret; 1128 1129 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1130 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1131 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test:\n\t", 1132 ad9467_test_modes[chan->mode]); 1133 1134 ret = iio_backend_debugfs_print_chan_status(st->back, chan->idx, 1135 buf + len, 1136 sizeof(buf) - len); 1137 if (ret < 0) 1138 return ret; 1139 len += ret; 1140 } else if (chan->mode == AN877_ADC_TESTMODE_OFF) { 1141 len = scnprintf(buf, sizeof(buf), "No test Running...\n"); 1142 } else { 1143 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test on CH:%u\n", 1144 ad9467_test_modes[chan->mode], chan->idx); 1145 } 1146 1147 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 1148 } 1149 1150 static ssize_t ad9467_chan_test_mode_write(struct file *file, 1151 const char __user *userbuf, 1152 size_t count, loff_t *ppos) 1153 { 1154 struct ad9467_chan_test_mode *chan = file->private_data; 1155 struct ad9467_state *st = chan->st; 1156 char test_mode[32] = {0}; 1157 unsigned int mode; 1158 int ret; 1159 1160 ret = simple_write_to_buffer(test_mode, sizeof(test_mode) - 1, ppos, 1161 userbuf, count); 1162 if (ret < 0) 1163 return ret; 1164 1165 for_each_set_bit(mode, &st->info->test_mask, st->info->test_mask_len) { 1166 if (sysfs_streq(test_mode, ad9467_test_modes[mode])) 1167 break; 1168 } 1169 1170 if (mode == st->info->test_mask_len) 1171 return -EINVAL; 1172 1173 guard(mutex)(&st->lock); 1174 1175 if (mode == AN877_ADC_TESTMODE_OFF) { 1176 unsigned int out_mode; 1177 1178 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1179 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1180 ret = ad9467_backend_testmode_off(st, chan->idx); 1181 if (ret) 1182 return ret; 1183 } 1184 1185 ret = ad9467_testmode_set(st, chan->idx, mode); 1186 if (ret) 1187 return ret; 1188 1189 out_mode = st->info->default_output_mode; 1190 ret = ad9467_outputmode_set(st, out_mode); 1191 if (ret) 1192 return ret; 1193 } else { 1194 unsigned int cmode; 1195 1196 cmode = st->info->default_output_mode; 1197 FIELD_MODIFY(AN877_ADC_OUTPUT_MODE_MASK, &cmode, 1198 AN877_ADC_OUTPUT_MODE_OFFSET_BINARY); 1199 ret = ad9467_outputmode_set(st, cmode); 1200 if (ret) 1201 return ret; 1202 1203 ret = ad9467_testmode_set(st, chan->idx, mode); 1204 if (ret) 1205 return ret; 1206 1207 /* some patterns have a backend matching monitoring block */ 1208 if (mode == AN877_ADC_TESTMODE_PN9_SEQ) { 1209 ret = ad9467_backend_testmode_on(st, chan->idx, 1210 IIO_BACKEND_ADI_PRBS_9A); 1211 if (ret) 1212 return ret; 1213 } else if (mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1214 ret = ad9467_backend_testmode_on(st, chan->idx, 1215 IIO_BACKEND_ADI_PRBS_23A); 1216 if (ret) 1217 return ret; 1218 } 1219 } 1220 1221 chan->mode = mode; 1222 1223 return count; 1224 } 1225 1226 static const struct file_operations ad9467_chan_test_mode_fops = { 1227 .open = simple_open, 1228 .read = ad9467_chan_test_mode_read, 1229 .write = ad9467_chan_test_mode_write, 1230 .llseek = default_llseek, 1231 .owner = THIS_MODULE, 1232 }; 1233 1234 static ssize_t ad9467_dump_calib_table(struct file *file, 1235 char __user *userbuf, 1236 size_t count, loff_t *ppos) 1237 { 1238 struct ad9467_state *st = file->private_data; 1239 unsigned int bit; 1240 /* +2 for the newline and +1 for the string termination */ 1241 unsigned char map[AD9647_MAX_TEST_POINTS * 2 + 3]; 1242 ssize_t len = 0; 1243 1244 guard(mutex)(&st->lock); 1245 if (*ppos) 1246 goto out_read; 1247 1248 for (bit = 0; bit < st->calib_map_size; bit++) { 1249 if (AD9467_CAN_INVERT(st) && bit == st->calib_map_size / 2) 1250 len += scnprintf(map + len, sizeof(map) - len, "\n"); 1251 1252 len += scnprintf(map + len, sizeof(map) - len, "%c", 1253 test_bit(bit, st->calib_map) ? 'x' : 'o'); 1254 } 1255 1256 len += scnprintf(map + len, sizeof(map) - len, "\n"); 1257 out_read: 1258 return simple_read_from_buffer(userbuf, count, ppos, map, len); 1259 } 1260 1261 static const struct file_operations ad9467_calib_table_fops = { 1262 .open = simple_open, 1263 .read = ad9467_dump_calib_table, 1264 .llseek = default_llseek, 1265 .owner = THIS_MODULE, 1266 }; 1267 1268 static void ad9467_debugfs_init(struct iio_dev *indio_dev) 1269 { 1270 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 1271 struct ad9467_state *st = iio_priv(indio_dev); 1272 char attr_name[32]; 1273 unsigned int chan; 1274 1275 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 1276 return; 1277 1278 st->chan_test = devm_kcalloc(&st->spi->dev, st->info->num_channels, 1279 sizeof(*st->chan_test), GFP_KERNEL); 1280 if (!st->chan_test) 1281 return; 1282 1283 debugfs_create_file("calibration_table_dump", 0400, d, st, 1284 &ad9467_calib_table_fops); 1285 1286 for (chan = 0; chan < st->info->num_channels; chan++) { 1287 snprintf(attr_name, sizeof(attr_name), "in_voltage%u_test_mode", 1288 chan); 1289 st->chan_test[chan].idx = chan; 1290 st->chan_test[chan].st = st; 1291 debugfs_create_file(attr_name, 0600, d, &st->chan_test[chan], 1292 &ad9467_chan_test_mode_fops); 1293 } 1294 1295 debugfs_create_file("in_voltage_test_mode_available", 0400, d, st, 1296 &ad9467_test_mode_available_fops); 1297 1298 iio_backend_debugfs_add(st->back, indio_dev); 1299 } 1300 1301 static int ad9467_probe(struct spi_device *spi) 1302 { 1303 struct iio_dev *indio_dev; 1304 struct ad9467_state *st; 1305 unsigned int id; 1306 int ret; 1307 1308 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1309 if (!indio_dev) 1310 return -ENOMEM; 1311 1312 st = iio_priv(indio_dev); 1313 st->spi = spi; 1314 1315 st->info = spi_get_device_match_data(spi); 1316 if (!st->info) 1317 return -ENODEV; 1318 1319 st->calib_map_size = st->info->test_points; 1320 if (AD9467_CAN_INVERT(st)) 1321 st->calib_map_size *= 2; 1322 1323 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 1324 if (IS_ERR(st->clk)) 1325 return PTR_ERR(st->clk); 1326 1327 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 1328 GPIOD_OUT_LOW); 1329 if (IS_ERR(st->pwrdown_gpio)) 1330 return PTR_ERR(st->pwrdown_gpio); 1331 1332 ret = ad9467_reset(&spi->dev); 1333 if (ret) 1334 return ret; 1335 1336 ret = ad9467_scale_fill(st); 1337 if (ret) 1338 return ret; 1339 1340 id = ad9467_spi_read(st, AN877_ADC_REG_CHIP_ID); 1341 if (id != st->info->id) { 1342 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 1343 id, st->info->id); 1344 return -ENODEV; 1345 } 1346 1347 if (st->info->num_scales > 1) 1348 indio_dev->info = &ad9467_info; 1349 else 1350 indio_dev->info = &ad9467_info_no_read_avail; 1351 indio_dev->name = st->info->name; 1352 indio_dev->channels = st->info->channels; 1353 indio_dev->num_channels = st->info->num_channels; 1354 1355 ret = ad9467_iio_backend_get(st); 1356 if (ret) 1357 return ret; 1358 1359 ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev); 1360 if (ret) 1361 return ret; 1362 1363 ret = devm_iio_backend_enable(&spi->dev, st->back); 1364 if (ret) 1365 return ret; 1366 1367 ret = ad9467_calibrate(st); 1368 if (ret) 1369 return ret; 1370 1371 ret = devm_iio_device_register(&spi->dev, indio_dev); 1372 if (ret) 1373 return ret; 1374 1375 ad9467_debugfs_init(indio_dev); 1376 1377 return 0; 1378 } 1379 1380 static const struct of_device_id ad9467_of_match[] = { 1381 { .compatible = "adi,ad9211", .data = &ad9211_chip_tbl, }, 1382 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, }, 1383 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, }, 1384 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, }, 1385 { .compatible = "adi,ad9643", .data = &ad9643_chip_tbl, }, 1386 { .compatible = "adi,ad9649", .data = &ad9649_chip_tbl, }, 1387 { .compatible = "adi,ad9652", .data = &ad9652_chip_tbl, }, 1388 { } 1389 }; 1390 MODULE_DEVICE_TABLE(of, ad9467_of_match); 1391 1392 static const struct spi_device_id ad9467_ids[] = { 1393 { "ad9211", (kernel_ulong_t)&ad9211_chip_tbl }, 1394 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl }, 1395 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl }, 1396 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl }, 1397 { "ad9643", (kernel_ulong_t)&ad9643_chip_tbl }, 1398 { "ad9649", (kernel_ulong_t)&ad9649_chip_tbl, }, 1399 { "ad9652", (kernel_ulong_t)&ad9652_chip_tbl, }, 1400 { } 1401 }; 1402 MODULE_DEVICE_TABLE(spi, ad9467_ids); 1403 1404 static struct spi_driver ad9467_driver = { 1405 .driver = { 1406 .name = "ad9467", 1407 .of_match_table = ad9467_of_match, 1408 }, 1409 .probe = ad9467_probe, 1410 .id_table = ad9467_ids, 1411 }; 1412 module_spi_driver(ad9467_driver); 1413 1414 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1415 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 1416 MODULE_LICENSE("GPL v2"); 1417 MODULE_IMPORT_NS("IIO_BACKEND"); 1418