xref: /linux/drivers/iio/adc/ad9467.c (revision 1a562c0d44974d3cf89c6cc5c34c708c08af420e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Analog Devices AD9467 SPI ADC driver
4  *
5  * Copyright 2012-2020 Analog Devices Inc.
6  */
7 #include <linux/cleanup.h>
8 #include <linux/module.h>
9 #include <linux/mutex.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/spi/spi.h>
14 #include <linux/err.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/of.h>
18 
19 
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 
23 #include <linux/clk.h>
24 
25 #include <linux/iio/adc/adi-axi-adc.h>
26 
27 /*
28  * ADI High-Speed ADC common spi interface registers
29  * See Application-Note AN-877:
30  *   https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
31  */
32 
33 #define AN877_ADC_REG_CHIP_PORT_CONF		0x00
34 #define AN877_ADC_REG_CHIP_ID			0x01
35 #define AN877_ADC_REG_CHIP_GRADE		0x02
36 #define AN877_ADC_REG_CHAN_INDEX		0x05
37 #define AN877_ADC_REG_TRANSFER			0xFF
38 #define AN877_ADC_REG_MODES			0x08
39 #define AN877_ADC_REG_TEST_IO			0x0D
40 #define AN877_ADC_REG_ADC_INPUT			0x0F
41 #define AN877_ADC_REG_OFFSET			0x10
42 #define AN877_ADC_REG_OUTPUT_MODE		0x14
43 #define AN877_ADC_REG_OUTPUT_ADJUST		0x15
44 #define AN877_ADC_REG_OUTPUT_PHASE		0x16
45 #define AN877_ADC_REG_OUTPUT_DELAY		0x17
46 #define AN877_ADC_REG_VREF			0x18
47 #define AN877_ADC_REG_ANALOG_INPUT		0x2C
48 
49 /* AN877_ADC_REG_TEST_IO */
50 #define AN877_ADC_TESTMODE_OFF			0x0
51 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT	0x1
52 #define AN877_ADC_TESTMODE_POS_FULLSCALE	0x2
53 #define AN877_ADC_TESTMODE_NEG_FULLSCALE	0x3
54 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD	0x4
55 #define AN877_ADC_TESTMODE_PN23_SEQ		0x5
56 #define AN877_ADC_TESTMODE_PN9_SEQ		0x6
57 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE	0x7
58 #define AN877_ADC_TESTMODE_USER			0x8
59 #define AN877_ADC_TESTMODE_BIT_TOGGLE		0x9
60 #define AN877_ADC_TESTMODE_SYNC			0xA
61 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH		0xB
62 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY	0xC
63 #define AN877_ADC_TESTMODE_RAMP			0xF
64 
65 /* AN877_ADC_REG_TRANSFER */
66 #define AN877_ADC_TRANSFER_SYNC			0x1
67 
68 /* AN877_ADC_REG_OUTPUT_MODE */
69 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY	0x0
70 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT	0x1
71 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE		0x2
72 
73 /* AN877_ADC_REG_OUTPUT_PHASE */
74 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN	0x20
75 #define AN877_ADC_INVERT_DCO_CLK		0x80
76 
77 /* AN877_ADC_REG_OUTPUT_DELAY */
78 #define AN877_ADC_DCO_DELAY_ENABLE		0x80
79 
80 /*
81  * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
82  */
83 
84 #define CHIPID_AD9265			0x64
85 #define AD9265_DEF_OUTPUT_MODE		0x40
86 #define AD9265_REG_VREF_MASK		0xC0
87 
88 /*
89  * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
90  */
91 
92 #define CHIPID_AD9434			0x6A
93 #define AD9434_DEF_OUTPUT_MODE		0x00
94 #define AD9434_REG_VREF_MASK		0xC0
95 
96 /*
97  * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
98  */
99 
100 #define CHIPID_AD9467			0x50
101 #define AD9467_DEF_OUTPUT_MODE		0x08
102 #define AD9467_REG_VREF_MASK		0x0F
103 
104 struct ad9467_chip_info {
105 	struct adi_axi_adc_chip_info	axi_adc_info;
106 	unsigned int			default_output_mode;
107 	unsigned int			vref_mask;
108 };
109 
110 #define to_ad9467_chip_info(_info)	\
111 	container_of(_info, struct ad9467_chip_info, axi_adc_info)
112 
113 struct ad9467_state {
114 	struct spi_device		*spi;
115 	struct clk			*clk;
116 	unsigned int			output_mode;
117 	unsigned int                    (*scales)[2];
118 
119 	struct gpio_desc		*pwrdown_gpio;
120 	/* ensure consistent state obtained on multiple related accesses */
121 	struct mutex			lock;
122 };
123 
124 static int ad9467_spi_read(struct spi_device *spi, unsigned int reg)
125 {
126 	unsigned char tbuf[2], rbuf[1];
127 	int ret;
128 
129 	tbuf[0] = 0x80 | (reg >> 8);
130 	tbuf[1] = reg & 0xFF;
131 
132 	ret = spi_write_then_read(spi,
133 				  tbuf, ARRAY_SIZE(tbuf),
134 				  rbuf, ARRAY_SIZE(rbuf));
135 
136 	if (ret < 0)
137 		return ret;
138 
139 	return rbuf[0];
140 }
141 
142 static int ad9467_spi_write(struct spi_device *spi, unsigned int reg,
143 			    unsigned int val)
144 {
145 	unsigned char buf[3];
146 
147 	buf[0] = reg >> 8;
148 	buf[1] = reg & 0xFF;
149 	buf[2] = val;
150 
151 	return spi_write(spi, buf, ARRAY_SIZE(buf));
152 }
153 
154 static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg,
155 			     unsigned int writeval, unsigned int *readval)
156 {
157 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
158 	struct spi_device *spi = st->spi;
159 	int ret;
160 
161 	if (!readval) {
162 		guard(mutex)(&st->lock);
163 		ret = ad9467_spi_write(spi, reg, writeval);
164 		if (ret)
165 			return ret;
166 		return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
167 					AN877_ADC_TRANSFER_SYNC);
168 	}
169 
170 	ret = ad9467_spi_read(spi, reg);
171 	if (ret < 0)
172 		return ret;
173 	*readval = ret;
174 
175 	return 0;
176 }
177 
178 static const unsigned int ad9265_scale_table[][2] = {
179 	{1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
180 };
181 
182 static const unsigned int ad9434_scale_table[][2] = {
183 	{1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00},
184 	{1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05},
185 	{1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A},
186 	{1200, 0x0B}, {1180, 0x0C},
187 };
188 
189 static const unsigned int ad9467_scale_table[][2] = {
190 	{2000, 0}, {2100, 6}, {2200, 7},
191 	{2300, 8}, {2400, 9}, {2500, 10},
192 };
193 
194 static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index,
195 			       unsigned int *val, unsigned int *val2)
196 {
197 	const struct adi_axi_adc_chip_info *info = conv->chip_info;
198 	const struct iio_chan_spec *chan = &info->channels[0];
199 	unsigned int tmp;
200 
201 	tmp = (info->scale_table[index][0] * 1000000ULL) >>
202 			chan->scan_type.realbits;
203 	*val = tmp / 1000000;
204 	*val2 = tmp % 1000000;
205 }
206 
207 #define AD9467_CHAN(_chan, _si, _bits, _sign)				\
208 {									\
209 	.type = IIO_VOLTAGE,						\
210 	.indexed = 1,							\
211 	.channel = _chan,						\
212 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |		\
213 		BIT(IIO_CHAN_INFO_SAMP_FREQ),				\
214 	.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
215 	.scan_index = _si,						\
216 	.scan_type = {							\
217 		.sign = _sign,						\
218 		.realbits = _bits,					\
219 		.storagebits = 16,					\
220 	},								\
221 }
222 
223 static const struct iio_chan_spec ad9434_channels[] = {
224 	AD9467_CHAN(0, 0, 12, 'S'),
225 };
226 
227 static const struct iio_chan_spec ad9467_channels[] = {
228 	AD9467_CHAN(0, 0, 16, 'S'),
229 };
230 
231 static const struct ad9467_chip_info ad9467_chip_tbl = {
232 	.axi_adc_info = {
233 		.name = "ad9467",
234 		.id = CHIPID_AD9467,
235 		.max_rate = 250000000UL,
236 		.scale_table = ad9467_scale_table,
237 		.num_scales = ARRAY_SIZE(ad9467_scale_table),
238 		.channels = ad9467_channels,
239 		.num_channels = ARRAY_SIZE(ad9467_channels),
240 	},
241 	.default_output_mode = AD9467_DEF_OUTPUT_MODE,
242 	.vref_mask = AD9467_REG_VREF_MASK,
243 };
244 
245 static const struct ad9467_chip_info ad9434_chip_tbl = {
246 	.axi_adc_info = {
247 		.name = "ad9434",
248 		.id = CHIPID_AD9434,
249 		.max_rate = 500000000UL,
250 		.scale_table = ad9434_scale_table,
251 		.num_scales = ARRAY_SIZE(ad9434_scale_table),
252 		.channels = ad9434_channels,
253 		.num_channels = ARRAY_SIZE(ad9434_channels),
254 	},
255 	.default_output_mode = AD9434_DEF_OUTPUT_MODE,
256 	.vref_mask = AD9434_REG_VREF_MASK,
257 };
258 
259 static const struct ad9467_chip_info ad9265_chip_tbl = {
260 	.axi_adc_info = {
261 		.name = "ad9265",
262 		.id = CHIPID_AD9265,
263 		.max_rate = 125000000UL,
264 		.scale_table = ad9265_scale_table,
265 		.num_scales = ARRAY_SIZE(ad9265_scale_table),
266 		.channels = ad9467_channels,
267 		.num_channels = ARRAY_SIZE(ad9467_channels),
268 	},
269 	.default_output_mode = AD9265_DEF_OUTPUT_MODE,
270 	.vref_mask = AD9265_REG_VREF_MASK,
271 };
272 
273 static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)
274 {
275 	const struct adi_axi_adc_chip_info *info = conv->chip_info;
276 	const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info);
277 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
278 	unsigned int i, vref_val;
279 	int ret;
280 
281 	ret = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF);
282 	if (ret < 0)
283 		return ret;
284 
285 	vref_val = ret & info1->vref_mask;
286 
287 	for (i = 0; i < info->num_scales; i++) {
288 		if (vref_val == info->scale_table[i][1])
289 			break;
290 	}
291 
292 	if (i == info->num_scales)
293 		return -ERANGE;
294 
295 	__ad9467_get_scale(conv, i, val, val2);
296 
297 	return IIO_VAL_INT_PLUS_MICRO;
298 }
299 
300 static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)
301 {
302 	const struct adi_axi_adc_chip_info *info = conv->chip_info;
303 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
304 	unsigned int scale_val[2];
305 	unsigned int i;
306 	int ret;
307 
308 	if (val != 0)
309 		return -EINVAL;
310 
311 	for (i = 0; i < info->num_scales; i++) {
312 		__ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]);
313 		if (scale_val[0] != val || scale_val[1] != val2)
314 			continue;
315 
316 		guard(mutex)(&st->lock);
317 		ret = ad9467_spi_write(st->spi, AN877_ADC_REG_VREF,
318 				       info->scale_table[i][1]);
319 		if (ret < 0)
320 			return ret;
321 
322 		return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER,
323 					AN877_ADC_TRANSFER_SYNC);
324 	}
325 
326 	return -EINVAL;
327 }
328 
329 static int ad9467_read_raw(struct adi_axi_adc_conv *conv,
330 			   struct iio_chan_spec const *chan,
331 			   int *val, int *val2, long m)
332 {
333 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
334 
335 	switch (m) {
336 	case IIO_CHAN_INFO_SCALE:
337 		return ad9467_get_scale(conv, val, val2);
338 	case IIO_CHAN_INFO_SAMP_FREQ:
339 		*val = clk_get_rate(st->clk);
340 
341 		return IIO_VAL_INT;
342 	default:
343 		return -EINVAL;
344 	}
345 }
346 
347 static int ad9467_write_raw(struct adi_axi_adc_conv *conv,
348 			    struct iio_chan_spec const *chan,
349 			    int val, int val2, long mask)
350 {
351 	const struct adi_axi_adc_chip_info *info = conv->chip_info;
352 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
353 	long r_clk;
354 
355 	switch (mask) {
356 	case IIO_CHAN_INFO_SCALE:
357 		return ad9467_set_scale(conv, val, val2);
358 	case IIO_CHAN_INFO_SAMP_FREQ:
359 		r_clk = clk_round_rate(st->clk, val);
360 		if (r_clk < 0 || r_clk > info->max_rate) {
361 			dev_warn(&st->spi->dev,
362 				 "Error setting ADC sample rate %ld", r_clk);
363 			return -EINVAL;
364 		}
365 
366 		return clk_set_rate(st->clk, r_clk);
367 	default:
368 		return -EINVAL;
369 	}
370 }
371 
372 static int ad9467_read_avail(struct adi_axi_adc_conv *conv,
373 			     struct iio_chan_spec const *chan,
374 			     const int **vals, int *type, int *length,
375 			     long mask)
376 {
377 	const struct adi_axi_adc_chip_info *info = conv->chip_info;
378 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
379 
380 	switch (mask) {
381 	case IIO_CHAN_INFO_SCALE:
382 		*vals = (const int *)st->scales;
383 		*type = IIO_VAL_INT_PLUS_MICRO;
384 		/* Values are stored in a 2D matrix */
385 		*length = info->num_scales * 2;
386 		return IIO_AVAIL_LIST;
387 	default:
388 		return -EINVAL;
389 	}
390 }
391 
392 static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)
393 {
394 	int ret;
395 
396 	ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode);
397 	if (ret < 0)
398 		return ret;
399 
400 	return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
401 				AN877_ADC_TRANSFER_SYNC);
402 }
403 
404 static int ad9467_scale_fill(struct adi_axi_adc_conv *conv)
405 {
406 	const struct adi_axi_adc_chip_info *info = conv->chip_info;
407 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
408 	unsigned int i, val1, val2;
409 
410 	st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales,
411 					sizeof(*st->scales), GFP_KERNEL);
412 	if (!st->scales)
413 		return -ENOMEM;
414 
415 	for (i = 0; i < info->num_scales; i++) {
416 		__ad9467_get_scale(conv, i, &val1, &val2);
417 		st->scales[i][0] = val1;
418 		st->scales[i][1] = val2;
419 	}
420 
421 	return 0;
422 }
423 
424 static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)
425 {
426 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
427 
428 	return ad9467_outputmode_set(st->spi, st->output_mode);
429 }
430 
431 static int ad9467_reset(struct device *dev)
432 {
433 	struct gpio_desc *gpio;
434 
435 	gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
436 	if (IS_ERR_OR_NULL(gpio))
437 		return PTR_ERR_OR_ZERO(gpio);
438 
439 	fsleep(1);
440 	gpiod_set_value_cansleep(gpio, 0);
441 	fsleep(10 * USEC_PER_MSEC);
442 
443 	return 0;
444 }
445 
446 static int ad9467_probe(struct spi_device *spi)
447 {
448 	const struct ad9467_chip_info *info;
449 	struct adi_axi_adc_conv *conv;
450 	struct ad9467_state *st;
451 	unsigned int id;
452 	int ret;
453 
454 	info = spi_get_device_match_data(spi);
455 	if (!info)
456 		return -ENODEV;
457 
458 	conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st));
459 	if (IS_ERR(conv))
460 		return PTR_ERR(conv);
461 
462 	st = adi_axi_adc_conv_priv(conv);
463 	st->spi = spi;
464 
465 	st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk");
466 	if (IS_ERR(st->clk))
467 		return PTR_ERR(st->clk);
468 
469 	st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
470 						   GPIOD_OUT_LOW);
471 	if (IS_ERR(st->pwrdown_gpio))
472 		return PTR_ERR(st->pwrdown_gpio);
473 
474 	ret = ad9467_reset(&spi->dev);
475 	if (ret)
476 		return ret;
477 
478 	conv->chip_info = &info->axi_adc_info;
479 
480 	ret = ad9467_scale_fill(conv);
481 	if (ret)
482 		return ret;
483 
484 	id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID);
485 	if (id != conv->chip_info->id) {
486 		dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",
487 			id, conv->chip_info->id);
488 		return -ENODEV;
489 	}
490 
491 	conv->reg_access = ad9467_reg_access;
492 	conv->write_raw = ad9467_write_raw;
493 	conv->read_raw = ad9467_read_raw;
494 	conv->read_avail = ad9467_read_avail;
495 	conv->preenable_setup = ad9467_preenable_setup;
496 
497 	st->output_mode = info->default_output_mode |
498 			  AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
499 
500 	return 0;
501 }
502 
503 static const struct of_device_id ad9467_of_match[] = {
504 	{ .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, },
505 	{ .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, },
506 	{ .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, },
507 	{}
508 };
509 MODULE_DEVICE_TABLE(of, ad9467_of_match);
510 
511 static const struct spi_device_id ad9467_ids[] = {
512 	{ "ad9265", (kernel_ulong_t)&ad9265_chip_tbl },
513 	{ "ad9434", (kernel_ulong_t)&ad9434_chip_tbl },
514 	{ "ad9467", (kernel_ulong_t)&ad9467_chip_tbl },
515 	{}
516 };
517 MODULE_DEVICE_TABLE(spi, ad9467_ids);
518 
519 static struct spi_driver ad9467_driver = {
520 	.driver = {
521 		.name = "ad9467",
522 		.of_match_table = ad9467_of_match,
523 	},
524 	.probe = ad9467_probe,
525 	.id_table = ad9467_ids,
526 };
527 module_spi_driver(ad9467_driver);
528 
529 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
530 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
531 MODULE_LICENSE("GPL v2");
532 MODULE_IMPORT_NS(IIO_ADI_AXI);
533