1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD7944/85/86 PulSAR ADC family driver. 4 * 5 * Copyright 2024 Analog Devices, Inc. 6 * Copyright 2024 BayLibre, SAS 7 */ 8 9 #include <linux/align.h> 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/module.h> 17 #include <linux/property.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spi/spi.h> 20 #include <linux/string_helpers.h> 21 22 #include <linux/iio/iio.h> 23 #include <linux/iio/sysfs.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 27 #define AD7944_INTERNAL_REF_MV 4096 28 29 struct ad7944_timing_spec { 30 /* Normal mode max conversion time (t_{CONV}). */ 31 unsigned int conv_ns; 32 /* TURBO mode max conversion time (t_{CONV}). */ 33 unsigned int turbo_conv_ns; 34 }; 35 36 enum ad7944_spi_mode { 37 /* datasheet calls this "4-wire mode" */ 38 AD7944_SPI_MODE_DEFAULT, 39 /* datasheet calls this "3-wire mode" (not related to SPI_3WIRE!) */ 40 AD7944_SPI_MODE_SINGLE, 41 /* datasheet calls this "chain mode" */ 42 AD7944_SPI_MODE_CHAIN, 43 }; 44 45 /* maps adi,spi-mode property value to enum */ 46 static const char * const ad7944_spi_modes[] = { 47 [AD7944_SPI_MODE_DEFAULT] = "", 48 [AD7944_SPI_MODE_SINGLE] = "single", 49 [AD7944_SPI_MODE_CHAIN] = "chain", 50 }; 51 52 struct ad7944_adc { 53 struct spi_device *spi; 54 enum ad7944_spi_mode spi_mode; 55 struct spi_transfer xfers[3]; 56 struct spi_message msg; 57 void *chain_mode_buf; 58 /* Chip-specific timing specifications. */ 59 const struct ad7944_timing_spec *timing_spec; 60 /* GPIO connected to CNV pin. */ 61 struct gpio_desc *cnv; 62 /* Optional GPIO to enable turbo mode. */ 63 struct gpio_desc *turbo; 64 /* Indicates TURBO is hard-wired to be always enabled. */ 65 bool always_turbo; 66 /* Reference voltage (millivolts). */ 67 unsigned int ref_mv; 68 69 /* 70 * DMA (thus cache coherency maintenance) requires the 71 * transfer buffers to live in their own cache lines. 72 */ 73 struct { 74 union { 75 u16 u16; 76 u32 u32; 77 } raw; 78 u64 timestamp __aligned(8); 79 } sample __aligned(IIO_DMA_MINALIGN); 80 }; 81 82 /* quite time before CNV rising edge */ 83 #define T_QUIET_NS 20 84 85 static const struct ad7944_timing_spec ad7944_timing_spec = { 86 .conv_ns = 420, 87 .turbo_conv_ns = 320, 88 }; 89 90 static const struct ad7944_timing_spec ad7986_timing_spec = { 91 .conv_ns = 500, 92 .turbo_conv_ns = 400, 93 }; 94 95 struct ad7944_chip_info { 96 const char *name; 97 const struct ad7944_timing_spec *timing_spec; 98 const struct iio_chan_spec channels[2]; 99 }; 100 101 /* 102 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a specific chip 103 * @_name: The name of the chip 104 * @_ts: The timing specification for the chip 105 * @_bits: The number of bits in the conversion result 106 * @_diff: Whether the chip is true differential or not 107 */ 108 #define AD7944_DEFINE_CHIP_INFO(_name, _ts, _bits, _diff) \ 109 static const struct ad7944_chip_info _name##_chip_info = { \ 110 .name = #_name, \ 111 .timing_spec = &_ts##_timing_spec, \ 112 .channels = { \ 113 { \ 114 .type = IIO_VOLTAGE, \ 115 .indexed = 1, \ 116 .differential = _diff, \ 117 .channel = 0, \ 118 .channel2 = _diff ? 1 : 0, \ 119 .scan_index = 0, \ 120 .scan_type.sign = _diff ? 's' : 'u', \ 121 .scan_type.realbits = _bits, \ 122 .scan_type.storagebits = _bits > 16 ? 32 : 16, \ 123 .scan_type.endianness = IIO_CPU, \ 124 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 125 | BIT(IIO_CHAN_INFO_SCALE), \ 126 }, \ 127 IIO_CHAN_SOFT_TIMESTAMP(1), \ 128 }, \ 129 } 130 131 /* pseudo-differential with ground sense */ 132 AD7944_DEFINE_CHIP_INFO(ad7944, ad7944, 14, 0); 133 AD7944_DEFINE_CHIP_INFO(ad7985, ad7944, 16, 0); 134 /* fully differential */ 135 AD7944_DEFINE_CHIP_INFO(ad7986, ad7986, 18, 1); 136 137 static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 138 const struct iio_chan_spec *chan) 139 { 140 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns 141 : adc->timing_spec->conv_ns; 142 struct spi_transfer *xfers = adc->xfers; 143 144 /* 145 * NB: can get better performance from some SPI controllers if we use 146 * the same bits_per_word in every transfer. 147 */ 148 xfers[0].bits_per_word = chan->scan_type.realbits; 149 /* 150 * CS is tied to CNV and we need a low to high transition to start the 151 * conversion, so place CNV low for t_QUIET to prepare for this. 152 */ 153 xfers[0].delay.value = T_QUIET_NS; 154 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 155 156 /* 157 * CS has to be high for full conversion time to avoid triggering the 158 * busy indication. 159 */ 160 xfers[1].cs_off = 1; 161 xfers[1].delay.value = t_conv_ns; 162 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS; 163 xfers[1].bits_per_word = chan->scan_type.realbits; 164 165 /* Then we can read the data during the acquisition phase */ 166 xfers[2].rx_buf = &adc->sample.raw; 167 xfers[2].len = BITS_TO_BYTES(chan->scan_type.storagebits); 168 xfers[2].bits_per_word = chan->scan_type.realbits; 169 170 spi_message_init_with_transfers(&adc->msg, xfers, 3); 171 172 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); 173 } 174 175 static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 176 const struct iio_chan_spec *chan) 177 { 178 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns 179 : adc->timing_spec->conv_ns; 180 struct spi_transfer *xfers = adc->xfers; 181 182 /* 183 * NB: can get better performance from some SPI controllers if we use 184 * the same bits_per_word in every transfer. 185 */ 186 xfers[0].bits_per_word = chan->scan_type.realbits; 187 /* 188 * CS has to be high for full conversion time to avoid triggering the 189 * busy indication. 190 */ 191 xfers[0].cs_off = 1; 192 xfers[0].delay.value = t_conv_ns; 193 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 194 195 xfers[1].rx_buf = &adc->sample.raw; 196 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits); 197 xfers[1].bits_per_word = chan->scan_type.realbits; 198 199 spi_message_init_with_transfers(&adc->msg, xfers, 2); 200 201 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); 202 } 203 204 static int ad7944_chain_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 205 const struct iio_chan_spec *chan, 206 u32 n_chain_dev) 207 { 208 struct spi_transfer *xfers = adc->xfers; 209 210 /* 211 * NB: SCLK has to be low before we toggle CS to avoid triggering the 212 * busy indication. 213 */ 214 if (adc->spi->mode & SPI_CPOL) 215 return dev_err_probe(dev, -EINVAL, 216 "chain mode requires ~SPI_CPOL\n"); 217 218 /* 219 * We only support CNV connected to CS in chain mode and we need CNV 220 * to be high during the transfer to trigger the conversion. 221 */ 222 if (!(adc->spi->mode & SPI_CS_HIGH)) 223 return dev_err_probe(dev, -EINVAL, 224 "chain mode requires SPI_CS_HIGH\n"); 225 226 /* CNV has to be high for full conversion time before reading data. */ 227 xfers[0].delay.value = adc->timing_spec->conv_ns; 228 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 229 230 xfers[1].rx_buf = adc->chain_mode_buf; 231 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits) * n_chain_dev; 232 xfers[1].bits_per_word = chan->scan_type.realbits; 233 234 spi_message_init_with_transfers(&adc->msg, xfers, 2); 235 236 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); 237 } 238 239 /** 240 * ad7944_convert_and_acquire - Perform a single conversion and acquisition 241 * @adc: The ADC device structure 242 * Return: 0 on success, a negative error code on failure 243 * 244 * Perform a conversion and acquisition of a single sample using the 245 * pre-optimized adc->msg. 246 * 247 * Upon successful return adc->sample.raw will contain the conversion result 248 * (or adc->chain_mode_buf if the device is using chain mode). 249 */ 250 static int ad7944_convert_and_acquire(struct ad7944_adc *adc) 251 { 252 int ret; 253 254 /* 255 * In 4-wire mode, the CNV line is held high for the entire conversion 256 * and acquisition process. In other modes adc->cnv is NULL and is 257 * ignored (CS is wired to CNV in those cases). 258 */ 259 gpiod_set_value_cansleep(adc->cnv, 1); 260 ret = spi_sync(adc->spi, &adc->msg); 261 gpiod_set_value_cansleep(adc->cnv, 0); 262 263 return ret; 264 } 265 266 static int ad7944_single_conversion(struct ad7944_adc *adc, 267 const struct iio_chan_spec *chan, 268 int *val) 269 { 270 int ret; 271 272 ret = ad7944_convert_and_acquire(adc); 273 if (ret) 274 return ret; 275 276 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) { 277 if (chan->scan_type.storagebits > 16) 278 *val = ((u32 *)adc->chain_mode_buf)[chan->scan_index]; 279 else 280 *val = ((u16 *)adc->chain_mode_buf)[chan->scan_index]; 281 } else { 282 if (chan->scan_type.storagebits > 16) 283 *val = adc->sample.raw.u32; 284 else 285 *val = adc->sample.raw.u16; 286 } 287 288 if (chan->scan_type.sign == 's') 289 *val = sign_extend32(*val, chan->scan_type.realbits - 1); 290 291 return IIO_VAL_INT; 292 } 293 294 static int ad7944_read_raw(struct iio_dev *indio_dev, 295 const struct iio_chan_spec *chan, 296 int *val, int *val2, long info) 297 { 298 struct ad7944_adc *adc = iio_priv(indio_dev); 299 int ret; 300 301 switch (info) { 302 case IIO_CHAN_INFO_RAW: 303 ret = iio_device_claim_direct_mode(indio_dev); 304 if (ret) 305 return ret; 306 307 ret = ad7944_single_conversion(adc, chan, val); 308 iio_device_release_direct_mode(indio_dev); 309 return ret; 310 311 case IIO_CHAN_INFO_SCALE: 312 switch (chan->type) { 313 case IIO_VOLTAGE: 314 *val = adc->ref_mv; 315 316 if (chan->scan_type.sign == 's') 317 *val2 = chan->scan_type.realbits - 1; 318 else 319 *val2 = chan->scan_type.realbits; 320 321 return IIO_VAL_FRACTIONAL_LOG2; 322 default: 323 return -EINVAL; 324 } 325 326 default: 327 return -EINVAL; 328 } 329 } 330 331 static const struct iio_info ad7944_iio_info = { 332 .read_raw = &ad7944_read_raw, 333 }; 334 335 static irqreturn_t ad7944_trigger_handler(int irq, void *p) 336 { 337 struct iio_poll_func *pf = p; 338 struct iio_dev *indio_dev = pf->indio_dev; 339 struct ad7944_adc *adc = iio_priv(indio_dev); 340 int ret; 341 342 ret = ad7944_convert_and_acquire(adc); 343 if (ret) 344 goto out; 345 346 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) 347 iio_push_to_buffers_with_timestamp(indio_dev, adc->chain_mode_buf, 348 pf->timestamp); 349 else 350 iio_push_to_buffers_with_timestamp(indio_dev, &adc->sample.raw, 351 pf->timestamp); 352 353 out: 354 iio_trigger_notify_done(indio_dev->trig); 355 356 return IRQ_HANDLED; 357 } 358 359 /** 360 * ad7944_chain_mode_alloc - allocate and initialize channel specs and buffers 361 * for daisy-chained devices 362 * @dev: The device for devm_ functions 363 * @chan_template: The channel template for the devices (array of 2 channels 364 * voltage and timestamp) 365 * @n_chain_dev: The number of devices in the chain 366 * @chain_chan: Pointer to receive the allocated channel specs 367 * @chain_mode_buf: Pointer to receive the allocated rx buffer 368 * @chain_scan_masks: Pointer to receive the allocated scan masks 369 * Return: 0 on success, a negative error code on failure 370 */ 371 static int ad7944_chain_mode_alloc(struct device *dev, 372 const struct iio_chan_spec *chan_template, 373 u32 n_chain_dev, 374 struct iio_chan_spec **chain_chan, 375 void **chain_mode_buf, 376 unsigned long **chain_scan_masks) 377 { 378 struct iio_chan_spec *chan; 379 size_t chain_mode_buf_size; 380 unsigned long *scan_masks; 381 void *buf; 382 int i; 383 384 /* 1 channel for each device in chain plus 1 for soft timestamp */ 385 386 chan = devm_kcalloc(dev, n_chain_dev + 1, sizeof(*chan), GFP_KERNEL); 387 if (!chan) 388 return -ENOMEM; 389 390 for (i = 0; i < n_chain_dev; i++) { 391 chan[i] = chan_template[0]; 392 393 if (chan_template[0].differential) { 394 chan[i].channel = 2 * i; 395 chan[i].channel2 = 2 * i + 1; 396 } else { 397 chan[i].channel = i; 398 } 399 400 chan[i].scan_index = i; 401 } 402 403 /* soft timestamp */ 404 chan[i] = chan_template[1]; 405 chan[i].scan_index = i; 406 407 *chain_chan = chan; 408 409 /* 1 word for each voltage channel + aligned u64 for timestamp */ 410 411 chain_mode_buf_size = ALIGN(n_chain_dev * 412 BITS_TO_BYTES(chan[0].scan_type.storagebits), sizeof(u64)) 413 + sizeof(u64); 414 buf = devm_kzalloc(dev, chain_mode_buf_size, GFP_KERNEL); 415 if (!buf) 416 return -ENOMEM; 417 418 *chain_mode_buf = buf; 419 420 /* 421 * Have to limit n_chain_dev due to current implementation of 422 * available_scan_masks. 423 */ 424 if (n_chain_dev > BITS_PER_LONG) 425 return dev_err_probe(dev, -EINVAL, 426 "chain is limited to 32 devices\n"); 427 428 scan_masks = devm_kcalloc(dev, 2, sizeof(*scan_masks), GFP_KERNEL); 429 if (!scan_masks) 430 return -ENOMEM; 431 432 /* 433 * Scan mask is needed since we always have to read all devices in the 434 * chain in one SPI transfer. 435 */ 436 scan_masks[0] = GENMASK(n_chain_dev - 1, 0); 437 438 *chain_scan_masks = scan_masks; 439 440 return 0; 441 } 442 443 static const char * const ad7944_power_supplies[] = { 444 "avdd", "dvdd", "bvdd", "vio" 445 }; 446 447 static int ad7944_probe(struct spi_device *spi) 448 { 449 const struct ad7944_chip_info *chip_info; 450 struct device *dev = &spi->dev; 451 struct iio_dev *indio_dev; 452 struct ad7944_adc *adc; 453 bool have_refin; 454 struct iio_chan_spec *chain_chan; 455 unsigned long *chain_scan_masks; 456 u32 n_chain_dev; 457 int ret, ref_mv; 458 459 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 460 if (!indio_dev) 461 return -ENOMEM; 462 463 adc = iio_priv(indio_dev); 464 adc->spi = spi; 465 466 chip_info = spi_get_device_match_data(spi); 467 if (!chip_info) 468 return dev_err_probe(dev, -EINVAL, "no chip info\n"); 469 470 adc->timing_spec = chip_info->timing_spec; 471 472 ret = device_property_match_property_string(dev, "adi,spi-mode", 473 ad7944_spi_modes, 474 ARRAY_SIZE(ad7944_spi_modes)); 475 /* absence of adi,spi-mode property means default mode */ 476 if (ret == -EINVAL) 477 adc->spi_mode = AD7944_SPI_MODE_DEFAULT; 478 else if (ret < 0) 479 return dev_err_probe(dev, ret, 480 "getting adi,spi-mode property failed\n"); 481 else 482 adc->spi_mode = ret; 483 484 /* 485 * Some chips use unusual word sizes, so check now instead of waiting 486 * for the first xfer. 487 */ 488 if (!spi_is_bpw_supported(spi, chip_info->channels[0].scan_type.realbits)) 489 return dev_err_probe(dev, -EINVAL, 490 "SPI host does not support %d bits per word\n", 491 chip_info->channels[0].scan_type.realbits); 492 493 ret = devm_regulator_bulk_get_enable(dev, 494 ARRAY_SIZE(ad7944_power_supplies), 495 ad7944_power_supplies); 496 if (ret) 497 return dev_err_probe(dev, ret, 498 "failed to get and enable supplies\n"); 499 500 /* 501 * Sort out what is being used for the reference voltage. Options are: 502 * - internal reference: neither REF or REFIN is connected 503 * - internal reference with external buffer: REF not connected, REFIN 504 * is connected 505 * - external reference: REF is connected, REFIN is not connected 506 */ 507 508 ret = devm_regulator_get_enable_read_voltage(dev, "ref"); 509 if (ret < 0 && ret != -ENODEV) 510 return dev_err_probe(dev, ret, "failed to get REF voltage\n"); 511 512 ref_mv = ret == -ENODEV ? 0 : ret / 1000; 513 514 ret = devm_regulator_get_enable_optional(dev, "refin"); 515 if (ret < 0 && ret != -ENODEV) 516 return dev_err_probe(dev, ret, "failed to get REFIN voltage\n"); 517 518 have_refin = ret != -ENODEV; 519 520 if (have_refin && ref_mv) 521 return dev_err_probe(dev, -EINVAL, 522 "cannot have both refin and ref supplies\n"); 523 524 adc->ref_mv = ref_mv ?: AD7944_INTERNAL_REF_MV; 525 526 adc->cnv = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW); 527 if (IS_ERR(adc->cnv)) 528 return dev_err_probe(dev, PTR_ERR(adc->cnv), 529 "failed to get CNV GPIO\n"); 530 531 if (!adc->cnv && adc->spi_mode == AD7944_SPI_MODE_DEFAULT) 532 return dev_err_probe(&spi->dev, -EINVAL, "CNV GPIO is required\n"); 533 if (adc->cnv && adc->spi_mode != AD7944_SPI_MODE_DEFAULT) 534 return dev_err_probe(&spi->dev, -EINVAL, 535 "CNV GPIO in single and chain mode is not currently supported\n"); 536 537 adc->turbo = devm_gpiod_get_optional(dev, "turbo", GPIOD_OUT_LOW); 538 if (IS_ERR(adc->turbo)) 539 return dev_err_probe(dev, PTR_ERR(adc->turbo), 540 "failed to get TURBO GPIO\n"); 541 542 adc->always_turbo = device_property_present(dev, "adi,always-turbo"); 543 544 if (adc->turbo && adc->always_turbo) 545 return dev_err_probe(dev, -EINVAL, 546 "cannot have both turbo-gpios and adi,always-turbo\n"); 547 548 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN && adc->always_turbo) 549 return dev_err_probe(dev, -EINVAL, 550 "cannot have both chain mode and always turbo\n"); 551 552 switch (adc->spi_mode) { 553 case AD7944_SPI_MODE_DEFAULT: 554 ret = ad7944_4wire_mode_init_msg(dev, adc, &chip_info->channels[0]); 555 if (ret) 556 return ret; 557 558 break; 559 case AD7944_SPI_MODE_SINGLE: 560 ret = ad7944_3wire_cs_mode_init_msg(dev, adc, &chip_info->channels[0]); 561 if (ret) 562 return ret; 563 564 break; 565 case AD7944_SPI_MODE_CHAIN: 566 ret = device_property_read_u32(dev, "#daisy-chained-devices", 567 &n_chain_dev); 568 if (ret) 569 return dev_err_probe(dev, ret, 570 "failed to get #daisy-chained-devices\n"); 571 572 ret = ad7944_chain_mode_alloc(dev, chip_info->channels, 573 n_chain_dev, &chain_chan, 574 &adc->chain_mode_buf, 575 &chain_scan_masks); 576 if (ret) 577 return ret; 578 579 ret = ad7944_chain_mode_init_msg(dev, adc, &chain_chan[0], 580 n_chain_dev); 581 if (ret) 582 return ret; 583 584 break; 585 } 586 587 indio_dev->name = chip_info->name; 588 indio_dev->modes = INDIO_DIRECT_MODE; 589 indio_dev->info = &ad7944_iio_info; 590 591 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) { 592 indio_dev->available_scan_masks = chain_scan_masks; 593 indio_dev->channels = chain_chan; 594 indio_dev->num_channels = n_chain_dev + 1; 595 } else { 596 indio_dev->channels = chip_info->channels; 597 indio_dev->num_channels = ARRAY_SIZE(chip_info->channels); 598 } 599 600 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 601 iio_pollfunc_store_time, 602 ad7944_trigger_handler, NULL); 603 if (ret) 604 return ret; 605 606 return devm_iio_device_register(dev, indio_dev); 607 } 608 609 static const struct of_device_id ad7944_of_match[] = { 610 { .compatible = "adi,ad7944", .data = &ad7944_chip_info }, 611 { .compatible = "adi,ad7985", .data = &ad7985_chip_info }, 612 { .compatible = "adi,ad7986", .data = &ad7986_chip_info }, 613 { } 614 }; 615 MODULE_DEVICE_TABLE(of, ad7944_of_match); 616 617 static const struct spi_device_id ad7944_spi_id[] = { 618 { "ad7944", (kernel_ulong_t)&ad7944_chip_info }, 619 { "ad7985", (kernel_ulong_t)&ad7985_chip_info }, 620 { "ad7986", (kernel_ulong_t)&ad7986_chip_info }, 621 { } 622 623 }; 624 MODULE_DEVICE_TABLE(spi, ad7944_spi_id); 625 626 static struct spi_driver ad7944_driver = { 627 .driver = { 628 .name = "ad7944", 629 .of_match_table = ad7944_of_match, 630 }, 631 .probe = ad7944_probe, 632 .id_table = ad7944_spi_id, 633 }; 634 module_spi_driver(ad7944_driver); 635 636 MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>"); 637 MODULE_DESCRIPTION("Analog Devices AD7944 PulSAR ADC family driver"); 638 MODULE_LICENSE("GPL"); 639