1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD7944/85/86 PulSAR ADC family driver. 4 * 5 * Copyright 2024 Analog Devices, Inc. 6 * Copyright 2024 BayLibre, SAS 7 */ 8 9 #include <linux/align.h> 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/module.h> 17 #include <linux/property.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spi/offload/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/string_helpers.h> 22 #include <linux/units.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/sysfs.h> 26 #include <linux/iio/buffer-dmaengine.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 30 #define AD7944_INTERNAL_REF_MV 4096 31 32 struct ad7944_timing_spec { 33 /* Normal mode max conversion time (t_{CONV}). */ 34 unsigned int conv_ns; 35 /* TURBO mode max conversion time (t_{CONV}). */ 36 unsigned int turbo_conv_ns; 37 }; 38 39 enum ad7944_spi_mode { 40 /* datasheet calls this "4-wire mode" */ 41 AD7944_SPI_MODE_DEFAULT, 42 /* datasheet calls this "3-wire mode" (not related to SPI_3WIRE!) */ 43 AD7944_SPI_MODE_SINGLE, 44 /* datasheet calls this "chain mode" */ 45 AD7944_SPI_MODE_CHAIN, 46 }; 47 48 /* maps adi,spi-mode property value to enum */ 49 static const char * const ad7944_spi_modes[] = { 50 [AD7944_SPI_MODE_DEFAULT] = "", 51 [AD7944_SPI_MODE_SINGLE] = "single", 52 [AD7944_SPI_MODE_CHAIN] = "chain", 53 }; 54 55 struct ad7944_adc { 56 struct spi_device *spi; 57 enum ad7944_spi_mode spi_mode; 58 struct spi_transfer xfers[3]; 59 struct spi_message msg; 60 struct spi_transfer offload_xfers[2]; 61 struct spi_message offload_msg; 62 struct spi_offload *offload; 63 struct spi_offload_trigger *offload_trigger; 64 unsigned long offload_trigger_hz; 65 int sample_freq_range[3]; 66 void *chain_mode_buf; 67 /* Chip-specific timing specifications. */ 68 const struct ad7944_timing_spec *timing_spec; 69 /* GPIO connected to CNV pin. */ 70 struct gpio_desc *cnv; 71 /* Optional GPIO to enable turbo mode. */ 72 struct gpio_desc *turbo; 73 /* Indicates TURBO is hard-wired to be always enabled. */ 74 bool always_turbo; 75 /* Reference voltage (millivolts). */ 76 unsigned int ref_mv; 77 78 /* 79 * DMA (thus cache coherency maintenance) requires the 80 * transfer buffers to live in their own cache lines. 81 */ 82 struct { 83 union { 84 u16 u16; 85 u32 u32; 86 } raw; 87 aligned_s64 timestamp; 88 } sample __aligned(IIO_DMA_MINALIGN); 89 }; 90 91 /* quite time before CNV rising edge */ 92 #define AD7944_T_QUIET_NS 20 93 /* minimum CNV high time to trigger conversion */ 94 #define AD7944_T_CNVH_NS 10 95 96 static const struct ad7944_timing_spec ad7944_timing_spec = { 97 .conv_ns = 420, 98 .turbo_conv_ns = 320, 99 }; 100 101 static const struct ad7944_timing_spec ad7986_timing_spec = { 102 .conv_ns = 500, 103 .turbo_conv_ns = 400, 104 }; 105 106 struct ad7944_chip_info { 107 const char *name; 108 const struct ad7944_timing_spec *timing_spec; 109 u32 max_sample_rate_hz; 110 const struct iio_chan_spec channels[2]; 111 const struct iio_chan_spec offload_channels[1]; 112 }; 113 114 /* get number of bytes for SPI xfer */ 115 #define AD7944_SPI_BYTES(scan_type) ((scan_type).realbits > 16 ? 4 : 2) 116 117 /* 118 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a specific chip 119 * @_name: The name of the chip 120 * @_ts: The timing specification for the chip 121 * @_max: The maximum sample rate in Hz 122 * @_bits: The number of bits in the conversion result 123 * @_diff: Whether the chip is true differential or not 124 */ 125 #define AD7944_DEFINE_CHIP_INFO(_name, _ts, _max, _bits, _diff) \ 126 static const struct ad7944_chip_info _name##_chip_info = { \ 127 .name = #_name, \ 128 .timing_spec = &_ts##_timing_spec, \ 129 .max_sample_rate_hz = _max, \ 130 .channels = { \ 131 { \ 132 .type = IIO_VOLTAGE, \ 133 .indexed = 1, \ 134 .differential = _diff, \ 135 .channel = 0, \ 136 .channel2 = _diff ? 1 : 0, \ 137 .scan_index = 0, \ 138 .scan_type.sign = _diff ? 's' : 'u', \ 139 .scan_type.realbits = _bits, \ 140 .scan_type.storagebits = _bits > 16 ? 32 : 16, \ 141 .scan_type.endianness = IIO_CPU, \ 142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 143 | BIT(IIO_CHAN_INFO_SCALE), \ 144 }, \ 145 IIO_CHAN_SOFT_TIMESTAMP(1), \ 146 }, \ 147 .offload_channels = { \ 148 { \ 149 .type = IIO_VOLTAGE, \ 150 .indexed = 1, \ 151 .differential = _diff, \ 152 .channel = 0, \ 153 .channel2 = _diff ? 1 : 0, \ 154 .scan_index = 0, \ 155 .scan_type.sign = _diff ? 's' : 'u', \ 156 .scan_type.realbits = _bits, \ 157 .scan_type.storagebits = 32, \ 158 .scan_type.endianness = IIO_CPU, \ 159 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 160 | BIT(IIO_CHAN_INFO_SCALE) \ 161 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 162 .info_mask_separate_available = \ 163 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 164 }, \ 165 }, \ 166 } 167 168 /* 169 * Notes on the offload channels: 170 * - There is no soft timestamp since everything is done in hardware. 171 * - There is a sampling frequency attribute added. This controls the SPI 172 * offload trigger. 173 * - The storagebits value depends on the SPI offload provider. Currently there 174 * is only one supported provider, namely the ADI PULSAR ADC HDL project, 175 * which always uses 32-bit words for data values, even for <= 16-bit ADCs. 176 * So the value is just hardcoded to 32 for now. 177 */ 178 179 /* pseudo-differential with ground sense */ 180 AD7944_DEFINE_CHIP_INFO(ad7944, ad7944, 2.5 * MEGA, 14, 0); 181 AD7944_DEFINE_CHIP_INFO(ad7985, ad7944, 2.5 * MEGA, 16, 0); 182 /* fully differential */ 183 AD7944_DEFINE_CHIP_INFO(ad7986, ad7986, 2 * MEGA, 18, 1); 184 185 static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 186 const struct iio_chan_spec *chan) 187 { 188 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns 189 : adc->timing_spec->conv_ns; 190 struct spi_transfer *xfers = adc->xfers; 191 192 /* 193 * NB: can get better performance from some SPI controllers if we use 194 * the same bits_per_word in every transfer. 195 */ 196 xfers[0].bits_per_word = chan->scan_type.realbits; 197 /* 198 * CS is tied to CNV and we need a low to high transition to start the 199 * conversion, so place CNV low for t_QUIET to prepare for this. 200 */ 201 xfers[0].delay.value = AD7944_T_QUIET_NS; 202 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 203 204 /* 205 * CS has to be high for full conversion time to avoid triggering the 206 * busy indication. 207 */ 208 xfers[1].cs_off = 1; 209 xfers[1].delay.value = t_conv_ns; 210 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS; 211 xfers[1].bits_per_word = chan->scan_type.realbits; 212 213 /* Then we can read the data during the acquisition phase */ 214 xfers[2].rx_buf = &adc->sample.raw; 215 xfers[2].len = AD7944_SPI_BYTES(chan->scan_type); 216 xfers[2].bits_per_word = chan->scan_type.realbits; 217 218 spi_message_init_with_transfers(&adc->msg, xfers, 3); 219 220 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); 221 } 222 223 static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 224 const struct iio_chan_spec *chan) 225 { 226 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns 227 : adc->timing_spec->conv_ns; 228 struct spi_transfer *xfers = adc->xfers; 229 230 /* 231 * NB: can get better performance from some SPI controllers if we use 232 * the same bits_per_word in every transfer. 233 */ 234 xfers[0].bits_per_word = chan->scan_type.realbits; 235 /* 236 * CS has to be high for full conversion time to avoid triggering the 237 * busy indication. 238 */ 239 xfers[0].cs_off = 1; 240 xfers[0].delay.value = t_conv_ns; 241 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 242 243 xfers[1].rx_buf = &adc->sample.raw; 244 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type); 245 xfers[1].bits_per_word = chan->scan_type.realbits; 246 247 spi_message_init_with_transfers(&adc->msg, xfers, 2); 248 249 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); 250 } 251 252 static int ad7944_chain_mode_init_msg(struct device *dev, struct ad7944_adc *adc, 253 const struct iio_chan_spec *chan, 254 u32 n_chain_dev) 255 { 256 struct spi_transfer *xfers = adc->xfers; 257 258 /* 259 * NB: SCLK has to be low before we toggle CS to avoid triggering the 260 * busy indication. 261 */ 262 if (adc->spi->mode & SPI_CPOL) 263 return dev_err_probe(dev, -EINVAL, 264 "chain mode requires ~SPI_CPOL\n"); 265 266 /* 267 * We only support CNV connected to CS in chain mode and we need CNV 268 * to be high during the transfer to trigger the conversion. 269 */ 270 if (!(adc->spi->mode & SPI_CS_HIGH)) 271 return dev_err_probe(dev, -EINVAL, 272 "chain mode requires SPI_CS_HIGH\n"); 273 274 /* CNV has to be high for full conversion time before reading data. */ 275 xfers[0].delay.value = adc->timing_spec->conv_ns; 276 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 277 278 xfers[1].rx_buf = adc->chain_mode_buf; 279 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type) * n_chain_dev; 280 xfers[1].bits_per_word = chan->scan_type.realbits; 281 282 spi_message_init_with_transfers(&adc->msg, xfers, 2); 283 284 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); 285 } 286 287 /* 288 * Unlike ad7944_3wire_cs_mode_init_msg(), this creates a message that reads 289 * during the conversion phase instead of the acquisition phase when reading 290 * a sample from the ADC. This is needed to be able to read at the maximum 291 * sample rate. It requires the SPI controller to have offload support and a 292 * high enough SCLK rate to read the sample during the conversion phase. 293 */ 294 static int ad7944_3wire_cs_mode_init_offload_msg(struct device *dev, 295 struct ad7944_adc *adc, 296 const struct iio_chan_spec *chan) 297 { 298 struct spi_transfer *xfers = adc->offload_xfers; 299 int ret; 300 301 /* 302 * CS is tied to CNV and we need a low to high transition to start the 303 * conversion, so place CNV low for t_QUIET to prepare for this. 304 */ 305 xfers[0].delay.value = AD7944_T_QUIET_NS; 306 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 307 /* CNV has to be high for a minimum time to trigger conversion. */ 308 xfers[0].cs_change = 1; 309 xfers[0].cs_change_delay.value = AD7944_T_CNVH_NS; 310 xfers[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 311 312 /* Then we can read the previous sample during the conversion phase */ 313 xfers[1].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 314 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type); 315 xfers[1].bits_per_word = chan->scan_type.realbits; 316 317 spi_message_init_with_transfers(&adc->offload_msg, xfers, 318 ARRAY_SIZE(adc->offload_xfers)); 319 320 adc->offload_msg.offload = adc->offload; 321 322 ret = devm_spi_optimize_message(dev, adc->spi, &adc->offload_msg); 323 if (ret) 324 return dev_err_probe(dev, ret, "failed to prepare offload msg\n"); 325 326 return 0; 327 } 328 329 /** 330 * ad7944_convert_and_acquire - Perform a single conversion and acquisition 331 * @adc: The ADC device structure 332 * Return: 0 on success, a negative error code on failure 333 * 334 * Perform a conversion and acquisition of a single sample using the 335 * pre-optimized adc->msg. 336 * 337 * Upon successful return adc->sample.raw will contain the conversion result 338 * (or adc->chain_mode_buf if the device is using chain mode). 339 */ 340 static int ad7944_convert_and_acquire(struct ad7944_adc *adc) 341 { 342 int ret; 343 344 /* 345 * In 4-wire mode, the CNV line is held high for the entire conversion 346 * and acquisition process. In other modes adc->cnv is NULL and is 347 * ignored (CS is wired to CNV in those cases). 348 */ 349 gpiod_set_value_cansleep(adc->cnv, 1); 350 ret = spi_sync(adc->spi, &adc->msg); 351 gpiod_set_value_cansleep(adc->cnv, 0); 352 353 return ret; 354 } 355 356 static int ad7944_single_conversion(struct ad7944_adc *adc, 357 const struct iio_chan_spec *chan, 358 int *val) 359 { 360 int ret; 361 362 ret = ad7944_convert_and_acquire(adc); 363 if (ret) 364 return ret; 365 366 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) { 367 if (chan->scan_type.realbits > 16) 368 *val = ((u32 *)adc->chain_mode_buf)[chan->scan_index]; 369 else 370 *val = ((u16 *)adc->chain_mode_buf)[chan->scan_index]; 371 } else { 372 if (chan->scan_type.realbits > 16) 373 *val = adc->sample.raw.u32; 374 else 375 *val = adc->sample.raw.u16; 376 } 377 378 if (chan->scan_type.sign == 's') 379 *val = sign_extend32(*val, chan->scan_type.realbits - 1); 380 381 return IIO_VAL_INT; 382 } 383 384 static int ad7944_read_avail(struct iio_dev *indio_dev, 385 struct iio_chan_spec const *chan, 386 const int **vals, int *type, int *length, 387 long mask) 388 { 389 struct ad7944_adc *adc = iio_priv(indio_dev); 390 391 switch (mask) { 392 case IIO_CHAN_INFO_SAMP_FREQ: 393 *vals = adc->sample_freq_range; 394 *type = IIO_VAL_INT; 395 return IIO_AVAIL_RANGE; 396 default: 397 return -EINVAL; 398 } 399 } 400 401 static int ad7944_read_raw(struct iio_dev *indio_dev, 402 const struct iio_chan_spec *chan, 403 int *val, int *val2, long info) 404 { 405 struct ad7944_adc *adc = iio_priv(indio_dev); 406 int ret; 407 408 switch (info) { 409 case IIO_CHAN_INFO_RAW: 410 if (!iio_device_claim_direct(indio_dev)) 411 return -EBUSY; 412 413 ret = ad7944_single_conversion(adc, chan, val); 414 iio_device_release_direct(indio_dev); 415 return ret; 416 417 case IIO_CHAN_INFO_SCALE: 418 switch (chan->type) { 419 case IIO_VOLTAGE: 420 *val = adc->ref_mv; 421 422 if (chan->scan_type.sign == 's') 423 *val2 = chan->scan_type.realbits - 1; 424 else 425 *val2 = chan->scan_type.realbits; 426 427 return IIO_VAL_FRACTIONAL_LOG2; 428 default: 429 return -EINVAL; 430 } 431 432 case IIO_CHAN_INFO_SAMP_FREQ: 433 *val = adc->offload_trigger_hz; 434 return IIO_VAL_INT; 435 436 default: 437 return -EINVAL; 438 } 439 } 440 441 static int ad7944_set_sample_freq(struct ad7944_adc *adc, int val) 442 { 443 struct spi_offload_trigger_config config = { 444 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 445 .periodic = { 446 .frequency_hz = val, 447 }, 448 }; 449 int ret; 450 451 ret = spi_offload_trigger_validate(adc->offload_trigger, &config); 452 if (ret) 453 return ret; 454 455 adc->offload_trigger_hz = config.periodic.frequency_hz; 456 457 return 0; 458 } 459 460 static int ad7944_write_raw(struct iio_dev *indio_dev, 461 const struct iio_chan_spec *chan, 462 int val, int val2, long info) 463 { 464 struct ad7944_adc *adc = iio_priv(indio_dev); 465 466 switch (info) { 467 case IIO_CHAN_INFO_SAMP_FREQ: 468 if (val < 1 || val > adc->sample_freq_range[2]) 469 return -EINVAL; 470 471 return ad7944_set_sample_freq(adc, val); 472 default: 473 return -EINVAL; 474 } 475 } 476 477 static int ad7944_write_raw_get_fmt(struct iio_dev *indio_dev, 478 const struct iio_chan_spec *chan, 479 long mask) 480 { 481 switch (mask) { 482 case IIO_CHAN_INFO_SAMP_FREQ: 483 return IIO_VAL_INT; 484 default: 485 return IIO_VAL_INT_PLUS_MICRO; 486 } 487 } 488 489 static const struct iio_info ad7944_iio_info = { 490 .read_avail = &ad7944_read_avail, 491 .read_raw = &ad7944_read_raw, 492 .write_raw = &ad7944_write_raw, 493 .write_raw_get_fmt = &ad7944_write_raw_get_fmt, 494 }; 495 496 static int ad7944_offload_buffer_postenable(struct iio_dev *indio_dev) 497 { 498 struct ad7944_adc *adc = iio_priv(indio_dev); 499 struct spi_offload_trigger_config config = { 500 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 501 .periodic = { 502 .frequency_hz = adc->offload_trigger_hz, 503 }, 504 }; 505 int ret; 506 507 gpiod_set_value_cansleep(adc->turbo, 1); 508 509 ret = spi_offload_trigger_enable(adc->offload, adc->offload_trigger, 510 &config); 511 if (ret) 512 gpiod_set_value_cansleep(adc->turbo, 0); 513 514 return ret; 515 } 516 517 static int ad7944_offload_buffer_predisable(struct iio_dev *indio_dev) 518 { 519 struct ad7944_adc *adc = iio_priv(indio_dev); 520 521 spi_offload_trigger_disable(adc->offload, adc->offload_trigger); 522 gpiod_set_value_cansleep(adc->turbo, 0); 523 524 return 0; 525 } 526 527 static const struct iio_buffer_setup_ops ad7944_offload_buffer_setup_ops = { 528 .postenable = &ad7944_offload_buffer_postenable, 529 .predisable = &ad7944_offload_buffer_predisable, 530 }; 531 532 static irqreturn_t ad7944_trigger_handler(int irq, void *p) 533 { 534 struct iio_poll_func *pf = p; 535 struct iio_dev *indio_dev = pf->indio_dev; 536 struct ad7944_adc *adc = iio_priv(indio_dev); 537 int ret; 538 539 ret = ad7944_convert_and_acquire(adc); 540 if (ret) 541 goto out; 542 543 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) 544 iio_push_to_buffers_with_timestamp(indio_dev, adc->chain_mode_buf, 545 pf->timestamp); 546 else 547 iio_push_to_buffers_with_timestamp(indio_dev, &adc->sample.raw, 548 pf->timestamp); 549 550 out: 551 iio_trigger_notify_done(indio_dev->trig); 552 553 return IRQ_HANDLED; 554 } 555 556 /** 557 * ad7944_chain_mode_alloc - allocate and initialize channel specs and buffers 558 * for daisy-chained devices 559 * @dev: The device for devm_ functions 560 * @chan_template: The channel template for the devices (array of 2 channels 561 * voltage and timestamp) 562 * @n_chain_dev: The number of devices in the chain 563 * @chain_chan: Pointer to receive the allocated channel specs 564 * @chain_mode_buf: Pointer to receive the allocated rx buffer 565 * @chain_scan_masks: Pointer to receive the allocated scan masks 566 * Return: 0 on success, a negative error code on failure 567 */ 568 static int ad7944_chain_mode_alloc(struct device *dev, 569 const struct iio_chan_spec *chan_template, 570 u32 n_chain_dev, 571 struct iio_chan_spec **chain_chan, 572 void **chain_mode_buf, 573 unsigned long **chain_scan_masks) 574 { 575 struct iio_chan_spec *chan; 576 size_t chain_mode_buf_size; 577 unsigned long *scan_masks; 578 void *buf; 579 int i; 580 581 /* 1 channel for each device in chain plus 1 for soft timestamp */ 582 583 chan = devm_kcalloc(dev, n_chain_dev + 1, sizeof(*chan), GFP_KERNEL); 584 if (!chan) 585 return -ENOMEM; 586 587 for (i = 0; i < n_chain_dev; i++) { 588 chan[i] = chan_template[0]; 589 590 if (chan_template[0].differential) { 591 chan[i].channel = 2 * i; 592 chan[i].channel2 = 2 * i + 1; 593 } else { 594 chan[i].channel = i; 595 } 596 597 chan[i].scan_index = i; 598 } 599 600 /* soft timestamp */ 601 chan[i] = chan_template[1]; 602 chan[i].scan_index = i; 603 604 *chain_chan = chan; 605 606 /* 1 word for each voltage channel + aligned u64 for timestamp */ 607 608 chain_mode_buf_size = ALIGN(n_chain_dev * 609 AD7944_SPI_BYTES(chan[0].scan_type), sizeof(u64)) + sizeof(u64); 610 buf = devm_kzalloc(dev, chain_mode_buf_size, GFP_KERNEL); 611 if (!buf) 612 return -ENOMEM; 613 614 *chain_mode_buf = buf; 615 616 /* 617 * Have to limit n_chain_dev due to current implementation of 618 * available_scan_masks. 619 */ 620 if (n_chain_dev > BITS_PER_LONG) 621 return dev_err_probe(dev, -EINVAL, 622 "chain is limited to 32 devices\n"); 623 624 scan_masks = devm_kcalloc(dev, 2, sizeof(*scan_masks), GFP_KERNEL); 625 if (!scan_masks) 626 return -ENOMEM; 627 628 /* 629 * Scan mask is needed since we always have to read all devices in the 630 * chain in one SPI transfer. 631 */ 632 scan_masks[0] = GENMASK(n_chain_dev - 1, 0); 633 634 *chain_scan_masks = scan_masks; 635 636 return 0; 637 } 638 639 static const char * const ad7944_power_supplies[] = { 640 "avdd", "dvdd", "bvdd", "vio" 641 }; 642 643 static const struct spi_offload_config ad7944_offload_config = { 644 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 645 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 646 }; 647 648 static int ad7944_probe(struct spi_device *spi) 649 { 650 const struct ad7944_chip_info *chip_info; 651 struct device *dev = &spi->dev; 652 struct iio_dev *indio_dev; 653 struct ad7944_adc *adc; 654 bool have_refin; 655 struct iio_chan_spec *chain_chan; 656 unsigned long *chain_scan_masks; 657 u32 n_chain_dev; 658 int ret, ref_mv; 659 660 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 661 if (!indio_dev) 662 return -ENOMEM; 663 664 adc = iio_priv(indio_dev); 665 adc->spi = spi; 666 667 chip_info = spi_get_device_match_data(spi); 668 if (!chip_info) 669 return dev_err_probe(dev, -EINVAL, "no chip info\n"); 670 671 adc->timing_spec = chip_info->timing_spec; 672 673 adc->sample_freq_range[0] = 1; /* min */ 674 adc->sample_freq_range[1] = 1; /* step */ 675 adc->sample_freq_range[2] = chip_info->max_sample_rate_hz; /* max */ 676 677 ret = device_property_match_property_string(dev, "adi,spi-mode", 678 ad7944_spi_modes, 679 ARRAY_SIZE(ad7944_spi_modes)); 680 /* absence of adi,spi-mode property means default mode */ 681 if (ret == -EINVAL) 682 adc->spi_mode = AD7944_SPI_MODE_DEFAULT; 683 else if (ret < 0) 684 return dev_err_probe(dev, ret, 685 "getting adi,spi-mode property failed\n"); 686 else 687 adc->spi_mode = ret; 688 689 /* 690 * Some chips use unusual word sizes, so check now instead of waiting 691 * for the first xfer. 692 */ 693 if (!spi_is_bpw_supported(spi, chip_info->channels[0].scan_type.realbits)) 694 return dev_err_probe(dev, -EINVAL, 695 "SPI host does not support %d bits per word\n", 696 chip_info->channels[0].scan_type.realbits); 697 698 ret = devm_regulator_bulk_get_enable(dev, 699 ARRAY_SIZE(ad7944_power_supplies), 700 ad7944_power_supplies); 701 if (ret) 702 return dev_err_probe(dev, ret, 703 "failed to get and enable supplies\n"); 704 705 /* 706 * Sort out what is being used for the reference voltage. Options are: 707 * - internal reference: neither REF or REFIN is connected 708 * - internal reference with external buffer: REF not connected, REFIN 709 * is connected 710 * - external reference: REF is connected, REFIN is not connected 711 */ 712 713 ret = devm_regulator_get_enable_read_voltage(dev, "ref"); 714 if (ret < 0 && ret != -ENODEV) 715 return dev_err_probe(dev, ret, "failed to get REF voltage\n"); 716 717 ref_mv = ret == -ENODEV ? 0 : ret / 1000; 718 719 ret = devm_regulator_get_enable_optional(dev, "refin"); 720 if (ret < 0 && ret != -ENODEV) 721 return dev_err_probe(dev, ret, "failed to get REFIN voltage\n"); 722 723 have_refin = ret != -ENODEV; 724 725 if (have_refin && ref_mv) 726 return dev_err_probe(dev, -EINVAL, 727 "cannot have both refin and ref supplies\n"); 728 729 adc->ref_mv = ref_mv ?: AD7944_INTERNAL_REF_MV; 730 731 adc->cnv = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW); 732 if (IS_ERR(adc->cnv)) 733 return dev_err_probe(dev, PTR_ERR(adc->cnv), 734 "failed to get CNV GPIO\n"); 735 736 if (!adc->cnv && adc->spi_mode == AD7944_SPI_MODE_DEFAULT) 737 return dev_err_probe(&spi->dev, -EINVAL, "CNV GPIO is required\n"); 738 if (adc->cnv && adc->spi_mode != AD7944_SPI_MODE_DEFAULT) 739 return dev_err_probe(&spi->dev, -EINVAL, 740 "CNV GPIO in single and chain mode is not currently supported\n"); 741 742 adc->turbo = devm_gpiod_get_optional(dev, "turbo", GPIOD_OUT_LOW); 743 if (IS_ERR(adc->turbo)) 744 return dev_err_probe(dev, PTR_ERR(adc->turbo), 745 "failed to get TURBO GPIO\n"); 746 747 adc->always_turbo = device_property_present(dev, "adi,always-turbo"); 748 749 if (adc->turbo && adc->always_turbo) 750 return dev_err_probe(dev, -EINVAL, 751 "cannot have both turbo-gpios and adi,always-turbo\n"); 752 753 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN && adc->always_turbo) 754 return dev_err_probe(dev, -EINVAL, 755 "cannot have both chain mode and always turbo\n"); 756 757 switch (adc->spi_mode) { 758 case AD7944_SPI_MODE_DEFAULT: 759 ret = ad7944_4wire_mode_init_msg(dev, adc, &chip_info->channels[0]); 760 if (ret) 761 return ret; 762 763 break; 764 case AD7944_SPI_MODE_SINGLE: 765 ret = ad7944_3wire_cs_mode_init_msg(dev, adc, &chip_info->channels[0]); 766 if (ret) 767 return ret; 768 769 break; 770 case AD7944_SPI_MODE_CHAIN: 771 ret = device_property_read_u32(dev, "#daisy-chained-devices", 772 &n_chain_dev); 773 if (ret) 774 return dev_err_probe(dev, ret, 775 "failed to get #daisy-chained-devices\n"); 776 777 ret = ad7944_chain_mode_alloc(dev, chip_info->channels, 778 n_chain_dev, &chain_chan, 779 &adc->chain_mode_buf, 780 &chain_scan_masks); 781 if (ret) 782 return ret; 783 784 ret = ad7944_chain_mode_init_msg(dev, adc, &chain_chan[0], 785 n_chain_dev); 786 if (ret) 787 return ret; 788 789 break; 790 } 791 792 indio_dev->name = chip_info->name; 793 indio_dev->modes = INDIO_DIRECT_MODE; 794 indio_dev->info = &ad7944_iio_info; 795 796 adc->offload = devm_spi_offload_get(dev, spi, &ad7944_offload_config); 797 ret = PTR_ERR_OR_ZERO(adc->offload); 798 if (ret && ret != -ENODEV) 799 return dev_err_probe(dev, ret, "failed to get offload\n"); 800 801 /* Fall back to low speed usage when no SPI offload available. */ 802 if (ret == -ENODEV) { 803 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) { 804 indio_dev->available_scan_masks = chain_scan_masks; 805 indio_dev->channels = chain_chan; 806 indio_dev->num_channels = n_chain_dev + 1; 807 } else { 808 indio_dev->channels = chip_info->channels; 809 indio_dev->num_channels = ARRAY_SIZE(chip_info->channels); 810 } 811 812 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 813 iio_pollfunc_store_time, 814 ad7944_trigger_handler, 815 NULL); 816 if (ret) 817 return ret; 818 } else { 819 struct dma_chan *rx_dma; 820 821 if (adc->spi_mode != AD7944_SPI_MODE_SINGLE) 822 return dev_err_probe(dev, -EINVAL, 823 "offload only supported in single mode\n"); 824 825 indio_dev->setup_ops = &ad7944_offload_buffer_setup_ops; 826 indio_dev->channels = chip_info->offload_channels; 827 indio_dev->num_channels = ARRAY_SIZE(chip_info->offload_channels); 828 829 adc->offload_trigger = devm_spi_offload_trigger_get(dev, 830 adc->offload, SPI_OFFLOAD_TRIGGER_PERIODIC); 831 if (IS_ERR(adc->offload_trigger)) 832 return dev_err_probe(dev, PTR_ERR(adc->offload_trigger), 833 "failed to get offload trigger\n"); 834 835 ret = ad7944_set_sample_freq(adc, 2 * MEGA); 836 if (ret) 837 return dev_err_probe(dev, ret, 838 "failed to init sample rate\n"); 839 840 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, 841 adc->offload); 842 if (IS_ERR(rx_dma)) 843 return dev_err_probe(dev, PTR_ERR(rx_dma), 844 "failed to get offload RX DMA\n"); 845 846 /* 847 * REVISIT: ideally, we would confirm that the offload RX DMA 848 * buffer layout is the same as what is hard-coded in 849 * offload_channels. Right now, the only supported offload 850 * is the pulsar_adc project which always uses 32-bit word 851 * size for data values, regardless of the SPI bits per word. 852 */ 853 854 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, 855 indio_dev, rx_dma, IIO_BUFFER_DIRECTION_IN); 856 if (ret) 857 return ret; 858 859 ret = ad7944_3wire_cs_mode_init_offload_msg(dev, adc, 860 &chip_info->offload_channels[0]); 861 if (ret) 862 return ret; 863 } 864 865 return devm_iio_device_register(dev, indio_dev); 866 } 867 868 static const struct of_device_id ad7944_of_match[] = { 869 { .compatible = "adi,ad7944", .data = &ad7944_chip_info }, 870 { .compatible = "adi,ad7985", .data = &ad7985_chip_info }, 871 { .compatible = "adi,ad7986", .data = &ad7986_chip_info }, 872 { } 873 }; 874 MODULE_DEVICE_TABLE(of, ad7944_of_match); 875 876 static const struct spi_device_id ad7944_spi_id[] = { 877 { "ad7944", (kernel_ulong_t)&ad7944_chip_info }, 878 { "ad7985", (kernel_ulong_t)&ad7985_chip_info }, 879 { "ad7986", (kernel_ulong_t)&ad7986_chip_info }, 880 { } 881 882 }; 883 MODULE_DEVICE_TABLE(spi, ad7944_spi_id); 884 885 static struct spi_driver ad7944_driver = { 886 .driver = { 887 .name = "ad7944", 888 .of_match_table = ad7944_of_match, 889 }, 890 .probe = ad7944_probe, 891 .id_table = ad7944_spi_id, 892 }; 893 module_spi_driver(ad7944_driver); 894 895 MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>"); 896 MODULE_DESCRIPTION("Analog Devices AD7944 PulSAR ADC family driver"); 897 MODULE_LICENSE("GPL"); 898 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 899