1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7770, AD7771, AD7779 ADC 4 * 5 * Copyright 2023-2024 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/clk.h> 11 #include <linux/crc8.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/math.h> 18 #include <linux/module.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/string.h> 22 #include <linux/types.h> 23 #include <linux/unaligned.h> 24 #include <linux/units.h> 25 26 #include <linux/iio/iio.h> 27 #include <linux/iio/backend.h> 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/sysfs.h> 30 #include <linux/iio/trigger.h> 31 #include <linux/iio/triggered_buffer.h> 32 #include <linux/iio/trigger_consumer.h> 33 34 #define AD7779_SPI_READ_CMD BIT(7) 35 36 #define AD7779_DISABLE_SD BIT(7) 37 38 #define AD7779_REG_CH_DISABLE 0x08 39 #define AD7779_REG_CH_SYNC_OFFSET(ch) (0x09 + (ch)) 40 #define AD7779_REG_CH_CONFIG(ch) (0x00 + (ch)) 41 #define AD7779_REG_GENERAL_USER_CONFIG_1 0x11 42 #define AD7779_REG_GENERAL_USER_CONFIG_2 0x12 43 #define AD7779_REG_GENERAL_USER_CONFIG_3 0x13 44 #define AD7779_REG_DOUT_FORMAT 0x14 45 #define AD7779_REG_ADC_MUX_CONFIG 0x15 46 #define AD7779_REG_GPIO_CONFIG 0x17 47 #define AD7779_REG_BUFFER_CONFIG_1 0x19 48 #define AD7779_REG_GLOBAL_MUX_CONFIG 0x16 49 #define AD7779_REG_BUFFER_CONFIG_2 0x1A 50 #define AD7779_REG_GPIO_DATA 0x18 51 #define AD7779_REG_CH_OFFSET_UPPER_BYTE(ch) (0x1C + (ch) * 6) 52 #define AD7779_REG_CH_OFFSET_LOWER_BYTE(ch) (0x1E + (ch) * 6) 53 #define AD7779_REG_CH_GAIN_UPPER_BYTE(ch) (0x1F + (ch) * 6) 54 #define AD7779_REG_CH_OFFSET_MID_BYTE(ch) (0x1D + (ch) * 6) 55 #define AD7779_REG_CH_GAIN_MID_BYTE(ch) (0x20 + (ch) * 6) 56 #define AD7779_REG_CH_ERR_REG(ch) (0x4C + (ch)) 57 #define AD7779_REG_CH0_1_SAT_ERR 0x54 58 #define AD7779_REG_CH_GAIN_LOWER_BYTE(ch) (0x21 + (ch) * 6) 59 #define AD7779_REG_CH2_3_SAT_ERR 0x55 60 #define AD7779_REG_CH4_5_SAT_ERR 0x56 61 #define AD7779_REG_CH6_7_SAT_ERR 0x57 62 #define AD7779_REG_CHX_ERR_REG_EN 0x58 63 #define AD7779_REG_GEN_ERR_REG_1 0x59 64 #define AD7779_REG_GEN_ERR_REG_1_EN 0x5A 65 #define AD7779_REG_GEN_ERR_REG_2 0x5B 66 #define AD7779_REG_GEN_ERR_REG_2_EN 0x5C 67 #define AD7779_REG_STATUS_REG_1 0x5D 68 #define AD7779_REG_STATUS_REG_2 0x5E 69 #define AD7779_REG_STATUS_REG_3 0x5F 70 #define AD7779_REG_SRC_N_MSB 0x60 71 #define AD7779_REG_SRC_N_LSB 0x61 72 #define AD7779_REG_SRC_IF_MSB 0x62 73 #define AD7779_REG_SRC_IF_LSB 0x63 74 #define AD7779_REG_SRC_UPDATE 0x64 75 76 #define AD7779_FILTER_MSK BIT(6) 77 #define AD7779_MOD_POWERMODE_MSK BIT(6) 78 #define AD7779_MOD_PDB_REFOUT_MSK BIT(4) 79 #define AD7779_MOD_SPI_EN_MSK BIT(4) 80 #define AD7779_USRMOD_INIT_MSK GENMASK(6, 4) 81 82 /* AD7779_REG_DOUT_FORMAT */ 83 #define AD7779_DOUT_FORMAT_MSK GENMASK(7, 6) 84 #define AD7779_DOUT_HEADER_FORMAT BIT(5) 85 #define AD7779_DCLK_CLK_DIV_MSK GENMASK(3, 1) 86 87 #define AD7779_REFMUX_CTRL_MSK GENMASK(7, 6) 88 #define AD7779_SPI_CRC_EN_MSK BIT(0) 89 90 #define AD7779_MAXCLK_LOWPOWER (4096 * HZ_PER_KHZ) 91 #define AD7779_NUM_CHANNELS 8 92 #define AD7779_RESET_BUF_SIZE 8 93 #define AD7779_CHAN_DATA_SIZE 4 94 95 #define AD7779_LOWPOWER_DIV 512 96 #define AD7779_HIGHPOWER_DIV 2048 97 98 #define AD7779_SINC3_MAXFREQ (16 * HZ_PER_KHZ) 99 #define AD7779_SINC5_MAXFREQ (128 * HZ_PER_KHZ) 100 101 #define AD7779_DEFAULT_SAMPLING_FREQ (8 * HZ_PER_KHZ) 102 #define AD7779_DEFAULT_SAMPLING_2LINE (4 * HZ_PER_KHZ) 103 #define AD7779_DEFAULT_SAMPLING_1LINE (2 * HZ_PER_KHZ) 104 105 #define AD7779_SPIMODE_MAX_SAMP_FREQ (16 * HZ_PER_KHZ) 106 107 #define GAIN_REL 0x555555 108 #define AD7779_FREQ_MSB_MSK GENMASK(15, 8) 109 #define AD7779_FREQ_LSB_MSK GENMASK(7, 0) 110 #define AD7779_UPPER GENMASK(23, 16) 111 #define AD7779_MID GENMASK(15, 8) 112 #define AD7779_LOWER GENMASK(7, 0) 113 114 #define AD7779_REG_MSK GENMASK(6, 0) 115 116 #define AD7779_CRC8_POLY 0x07 117 DECLARE_CRC8_TABLE(ad7779_crc8_table); 118 119 enum ad7779_filter { 120 AD7779_SINC3, 121 AD7779_SINC5, 122 }; 123 124 enum ad7779_variant { 125 ad7770, 126 ad7771, 127 ad7779, 128 }; 129 130 enum ad7779_power_mode { 131 AD7779_LOW_POWER, 132 AD7779_HIGH_POWER, 133 }; 134 135 struct ad7779_chip_info { 136 const char *name; 137 struct iio_chan_spec const *channels; 138 }; 139 140 struct ad7779_state { 141 struct spi_device *spi; 142 const struct ad7779_chip_info *chip_info; 143 struct clk *mclk; 144 struct iio_trigger *trig; 145 struct completion completion; 146 unsigned int sampling_freq; 147 enum ad7779_filter filter_enabled; 148 struct iio_backend *back; 149 /* 150 * DMA (thus cache coherency maintenance) requires the 151 * transfer buffers to live in their own cache lines. 152 */ 153 struct { 154 u32 chans[8]; 155 aligned_s64 timestamp; 156 } data __aligned(IIO_DMA_MINALIGN); 157 u32 spidata_tx[8]; 158 u8 reg_rx_buf[3]; 159 u8 reg_tx_buf[3]; 160 u8 reset_buf[8]; 161 }; 162 163 static const char * const ad7779_filter_type[] = { 164 [AD7779_SINC3] = "sinc3", 165 [AD7779_SINC5] = "sinc5", 166 }; 167 168 static const char * const ad7779_power_supplies[] = { 169 "avdd1", "avdd2", "avdd4", 170 }; 171 172 static int ad7779_spi_read(struct ad7779_state *st, u8 reg, u8 *rbuf) 173 { 174 int ret; 175 u8 crc_buf[2]; 176 u8 exp_crc; 177 struct spi_transfer t = { 178 .tx_buf = st->reg_tx_buf, 179 .rx_buf = st->reg_rx_buf, 180 }; 181 182 st->reg_tx_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg); 183 st->reg_tx_buf[1] = 0; 184 185 if (reg == AD7779_REG_GEN_ERR_REG_1_EN) { 186 t.len = 2; 187 } else { 188 t.len = 3; 189 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf, 190 t.len - 1, 0); 191 } 192 193 ret = spi_sync_transfer(st->spi, &t, 1); 194 if (ret) 195 return ret; 196 197 crc_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg); 198 crc_buf[1] = st->reg_rx_buf[1]; 199 exp_crc = crc8(ad7779_crc8_table, crc_buf, ARRAY_SIZE(crc_buf), 0); 200 if (reg != AD7779_REG_GEN_ERR_REG_1_EN && exp_crc != st->reg_rx_buf[2]) { 201 dev_err(&st->spi->dev, "Bad CRC %x, expected %x", 202 st->reg_rx_buf[2], exp_crc); 203 return -EINVAL; 204 } 205 *rbuf = st->reg_rx_buf[1]; 206 207 return 0; 208 } 209 210 static int ad7779_spi_write(struct ad7779_state *st, u8 reg, u8 val) 211 { 212 u8 length = 3; 213 214 st->reg_tx_buf[0] = FIELD_GET(AD7779_REG_MSK, reg); 215 st->reg_tx_buf[1] = val; 216 if (reg == AD7779_REG_GEN_ERR_REG_1_EN) 217 length = 2; 218 else 219 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf, 220 length - 1, 0); 221 222 return spi_write(st->spi, st->reg_tx_buf, length); 223 } 224 225 static int ad7779_spi_write_mask(struct ad7779_state *st, u8 reg, u8 mask, 226 u8 val) 227 { 228 int ret; 229 u8 regval, data; 230 231 ret = ad7779_spi_read(st, reg, &data); 232 if (ret) 233 return ret; 234 235 regval = (data & ~mask) | (val & mask); 236 237 if (regval == data) 238 return 0; 239 240 return ad7779_spi_write(st, reg, regval); 241 } 242 243 static int ad7779_reg_access(struct iio_dev *indio_dev, 244 unsigned int reg, 245 unsigned int writeval, 246 unsigned int *readval) 247 { 248 struct ad7779_state *st = iio_priv(indio_dev); 249 u8 rval; 250 int ret; 251 252 if (readval) { 253 ret = ad7779_spi_read(st, reg, &rval); 254 *readval = rval; 255 return ret; 256 } 257 258 return ad7779_spi_write(st, reg, writeval); 259 } 260 261 static int ad7779_set_sampling_frequency(struct ad7779_state *st, 262 unsigned int sampling_freq) 263 { 264 int ret; 265 unsigned int dec; 266 unsigned int frac; 267 unsigned int div; 268 unsigned int decimal; 269 unsigned int freq_khz; 270 271 if (st->filter_enabled == AD7779_SINC3 && 272 sampling_freq > AD7779_SINC3_MAXFREQ) 273 return -EINVAL; 274 275 if (st->filter_enabled == AD7779_SINC5 && 276 sampling_freq > AD7779_SINC5_MAXFREQ) 277 return -EINVAL; 278 279 if (sampling_freq > AD7779_SPIMODE_MAX_SAMP_FREQ) 280 return -EINVAL; 281 282 div = AD7779_HIGHPOWER_DIV; 283 284 freq_khz = sampling_freq / HZ_PER_KHZ; 285 dec = div / freq_khz; 286 frac = div % freq_khz; 287 288 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, 289 FIELD_GET(AD7779_FREQ_MSB_MSK, dec)); 290 if (ret) 291 return ret; 292 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, 293 FIELD_GET(AD7779_FREQ_LSB_MSK, dec)); 294 if (ret) 295 return ret; 296 297 if (frac) { 298 /* 299 * In order to obtain the first three decimals of the decimation 300 * the initial number is multiplied with 10^3 prior to the 301 * division, then the original division result is subtracted and 302 * the number is divided by 10^3. 303 */ 304 decimal = ((mult_frac(div, KILO, freq_khz) - dec * KILO) << 16) 305 / KILO; 306 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, 307 FIELD_GET(AD7779_FREQ_MSB_MSK, decimal)); 308 if (ret) 309 return ret; 310 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, 311 FIELD_GET(AD7779_FREQ_LSB_MSK, decimal)); 312 if (ret) 313 return ret; 314 } else { 315 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, 316 FIELD_GET(AD7779_FREQ_MSB_MSK, 0x0)); 317 if (ret) 318 return ret; 319 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, 320 FIELD_GET(AD7779_FREQ_LSB_MSK, 0x0)); 321 if (ret) 322 return ret; 323 } 324 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, BIT(0)); 325 if (ret) 326 return ret; 327 328 /* SRC update settling time */ 329 fsleep(15); 330 331 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, 0x0); 332 if (ret) 333 return ret; 334 335 /* SRC update settling time */ 336 fsleep(15); 337 338 st->sampling_freq = sampling_freq; 339 340 return 0; 341 } 342 343 static int ad7779_get_filter(struct iio_dev *indio_dev, 344 struct iio_chan_spec const *chan) 345 { 346 struct ad7779_state *st = iio_priv(indio_dev); 347 u8 temp; 348 int ret; 349 350 ret = ad7779_spi_read(st, AD7779_REG_GENERAL_USER_CONFIG_2, &temp); 351 if (ret) 352 return ret; 353 354 return FIELD_GET(AD7779_FILTER_MSK, temp); 355 } 356 357 static int ad7779_set_filter(struct iio_dev *indio_dev, 358 struct iio_chan_spec const *chan, 359 unsigned int mode) 360 { 361 struct ad7779_state *st = iio_priv(indio_dev); 362 int ret; 363 364 ret = ad7779_spi_write_mask(st, 365 AD7779_REG_GENERAL_USER_CONFIG_2, 366 AD7779_FILTER_MSK, 367 FIELD_PREP(AD7779_FILTER_MSK, mode)); 368 if (ret) 369 return ret; 370 371 ret = ad7779_set_sampling_frequency(st, st->sampling_freq); 372 if (ret) 373 return ret; 374 375 st->filter_enabled = mode; 376 377 return 0; 378 } 379 380 static int ad7779_get_calibscale(struct ad7779_state *st, int channel) 381 { 382 int ret; 383 u8 calibscale[3]; 384 385 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel), 386 &calibscale[0]); 387 if (ret) 388 return ret; 389 390 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_MID_BYTE(channel), 391 &calibscale[1]); 392 if (ret) 393 return ret; 394 395 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel), 396 &calibscale[2]); 397 if (ret) 398 return ret; 399 400 return get_unaligned_be24(calibscale); 401 } 402 403 static int ad7779_set_calibscale(struct ad7779_state *st, int channel, int val) 404 { 405 int ret; 406 unsigned int gain; 407 u8 gain_bytes[3]; 408 409 /* 410 * The gain value is relative to 0x555555, which represents a gain of 1 411 */ 412 gain = DIV_ROUND_CLOSEST_ULL((u64)val * 5592405LL, MEGA); 413 put_unaligned_be24(gain, gain_bytes); 414 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel), 415 gain_bytes[0]); 416 if (ret) 417 return ret; 418 419 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_MID_BYTE(channel), 420 gain_bytes[1]); 421 if (ret) 422 return ret; 423 424 return ad7779_spi_write(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel), 425 gain_bytes[2]); 426 } 427 428 static int ad7779_get_calibbias(struct ad7779_state *st, int channel) 429 { 430 int ret; 431 u8 calibbias[3]; 432 433 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel), 434 &calibbias[0]); 435 if (ret) 436 return ret; 437 438 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel), 439 &calibbias[1]); 440 if (ret) 441 return ret; 442 443 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel), 444 &calibbias[2]); 445 if (ret) 446 return ret; 447 448 return get_unaligned_be24(calibbias); 449 } 450 451 static int ad7779_set_calibbias(struct ad7779_state *st, int channel, int val) 452 { 453 int ret; 454 u8 calibbias[3]; 455 456 put_unaligned_be24(val, calibbias); 457 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel), 458 calibbias[0]); 459 if (ret) 460 return ret; 461 462 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel), 463 calibbias[1]); 464 if (ret) 465 return ret; 466 467 return ad7779_spi_write(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel), 468 calibbias[2]); 469 } 470 471 static int __ad7779_read_raw(struct iio_dev *indio_dev, 472 struct iio_chan_spec const *chan, int *val, 473 int *val2, long mask) 474 { 475 struct ad7779_state *st = iio_priv(indio_dev); 476 int ret; 477 478 switch (mask) { 479 case IIO_CHAN_INFO_CALIBSCALE: 480 ret = ad7779_get_calibscale(st, chan->channel); 481 if (ret < 0) 482 return ret; 483 *val = ret; 484 *val2 = GAIN_REL; 485 return IIO_VAL_FRACTIONAL; 486 case IIO_CHAN_INFO_CALIBBIAS: 487 ret = ad7779_get_calibbias(st, chan->channel); 488 if (ret < 0) 489 return ret; 490 *val = ret; 491 return IIO_VAL_INT; 492 case IIO_CHAN_INFO_SAMP_FREQ: 493 *val = st->sampling_freq; 494 if (*val < 0) 495 return -EINVAL; 496 return IIO_VAL_INT; 497 default: 498 return -EINVAL; 499 } 500 } 501 502 static int ad7779_read_raw(struct iio_dev *indio_dev, 503 struct iio_chan_spec const *chan, int *val, 504 int *val2, long mask) 505 { 506 int ret; 507 508 if (!iio_device_claim_direct(indio_dev)) 509 return -EBUSY; 510 511 ret = __ad7779_read_raw(indio_dev, chan, val, val2, mask); 512 iio_device_release_direct(indio_dev); 513 return ret; 514 } 515 516 static int __ad7779_write_raw(struct iio_dev *indio_dev, 517 struct iio_chan_spec const *chan, 518 int val, int val2, 519 long mask) 520 { 521 struct ad7779_state *st = iio_priv(indio_dev); 522 523 switch (mask) { 524 case IIO_CHAN_INFO_CALIBSCALE: 525 return ad7779_set_calibscale(st, chan->channel, val2); 526 case IIO_CHAN_INFO_CALIBBIAS: 527 return ad7779_set_calibbias(st, chan->channel, val); 528 case IIO_CHAN_INFO_SAMP_FREQ: 529 return ad7779_set_sampling_frequency(st, val); 530 default: 531 return -EINVAL; 532 } 533 } 534 535 static int ad7779_write_raw(struct iio_dev *indio_dev, 536 struct iio_chan_spec const *chan, int val, int val2, 537 long mask) 538 { 539 int ret; 540 541 if (!iio_device_claim_direct(indio_dev)) 542 return -EBUSY; 543 544 ret = __ad7779_write_raw(indio_dev, chan, val, val2, mask); 545 iio_device_release_direct(indio_dev); 546 return ret; 547 } 548 549 static int ad7779_buffer_preenable(struct iio_dev *indio_dev) 550 { 551 int ret; 552 struct ad7779_state *st = iio_priv(indio_dev); 553 554 ret = ad7779_spi_write_mask(st, 555 AD7779_REG_GENERAL_USER_CONFIG_3, 556 AD7779_MOD_SPI_EN_MSK, 557 FIELD_PREP(AD7779_MOD_SPI_EN_MSK, 1)); 558 if (ret) 559 return ret; 560 561 /* 562 * DRDY output cannot be disabled at device level therefore we mask 563 * the irq at host end. 564 */ 565 enable_irq(st->spi->irq); 566 567 return 0; 568 } 569 570 static int ad7779_buffer_postdisable(struct iio_dev *indio_dev) 571 { 572 struct ad7779_state *st = iio_priv(indio_dev); 573 574 disable_irq(st->spi->irq); 575 576 return ad7779_spi_write(st, AD7779_REG_GENERAL_USER_CONFIG_3, 577 AD7779_DISABLE_SD); 578 } 579 580 static irqreturn_t ad7779_trigger_handler(int irq, void *p) 581 { 582 struct iio_poll_func *pf = p; 583 struct iio_dev *indio_dev = pf->indio_dev; 584 struct ad7779_state *st = iio_priv(indio_dev); 585 int ret; 586 struct spi_transfer t = { 587 .rx_buf = st->data.chans, 588 .tx_buf = st->spidata_tx, 589 .len = AD7779_NUM_CHANNELS * AD7779_CHAN_DATA_SIZE, 590 }; 591 592 st->spidata_tx[0] = AD7779_SPI_READ_CMD; 593 ret = spi_sync_transfer(st->spi, &t, 1); 594 if (ret) { 595 dev_err(&st->spi->dev, "SPI transfer error in IRQ handler"); 596 goto exit_handler; 597 } 598 599 iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data), 600 pf->timestamp); 601 602 exit_handler: 603 iio_trigger_notify_done(indio_dev->trig); 604 return IRQ_HANDLED; 605 } 606 607 static int ad7779_reset(struct iio_dev *indio_dev, struct gpio_desc *reset_gpio) 608 { 609 struct ad7779_state *st = iio_priv(indio_dev); 610 int ret; 611 struct spi_transfer t = { 612 .tx_buf = st->reset_buf, 613 .len = 8, 614 }; 615 616 if (reset_gpio) { 617 gpiod_set_value(reset_gpio, 1); 618 /* Delay for reset to occur is 225 microseconds */ 619 fsleep(230); 620 ret = 0; 621 } else { 622 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); 623 ret = spi_sync_transfer(st->spi, &t, 1); 624 if (ret) 625 return ret; 626 } 627 628 /* Delay for reset to occur is 225 microseconds */ 629 fsleep(230); 630 631 return ret; 632 } 633 634 static int ad7779_update_scan_mode(struct iio_dev *indio_dev, 635 const unsigned long *scan_mask) 636 { 637 struct ad7779_state *st = iio_priv(indio_dev); 638 unsigned int c; 639 int ret; 640 641 for (c = 0; c < AD7779_NUM_CHANNELS; c++) { 642 if (test_bit(c, scan_mask)) 643 ret = iio_backend_chan_enable(st->back, c); 644 else 645 ret = iio_backend_chan_disable(st->back, c); 646 if (ret) 647 return ret; 648 } 649 650 return 0; 651 } 652 653 static const struct iio_info ad7779_info = { 654 .read_raw = ad7779_read_raw, 655 .write_raw = ad7779_write_raw, 656 .debugfs_reg_access = &ad7779_reg_access, 657 }; 658 659 static const struct iio_info ad7779_info_data = { 660 .read_raw = ad7779_read_raw, 661 .write_raw = ad7779_write_raw, 662 .debugfs_reg_access = &ad7779_reg_access, 663 .update_scan_mode = &ad7779_update_scan_mode, 664 }; 665 666 static const struct iio_enum ad7779_filter_enum = { 667 .items = ad7779_filter_type, 668 .num_items = ARRAY_SIZE(ad7779_filter_type), 669 .get = ad7779_get_filter, 670 .set = ad7779_set_filter, 671 }; 672 673 static const struct iio_chan_spec_ext_info ad7779_ext_filter[] = { 674 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7779_filter_enum), 675 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, 676 &ad7779_filter_enum), 677 { } 678 }; 679 680 #define AD777x_CHAN_S(index, _ext_info) \ 681 { \ 682 .type = IIO_VOLTAGE, \ 683 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 684 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 685 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 686 .address = (index), \ 687 .indexed = 1, \ 688 .channel = (index), \ 689 .scan_index = (index), \ 690 .ext_info = (_ext_info), \ 691 .scan_type = { \ 692 .sign = 's', \ 693 .realbits = 24, \ 694 .storagebits = 32, \ 695 .endianness = IIO_BE, \ 696 }, \ 697 } 698 699 #define AD777x_CHAN_NO_FILTER_S(index) \ 700 AD777x_CHAN_S(index, NULL) 701 702 #define AD777x_CHAN_FILTER_S(index) \ 703 AD777x_CHAN_S(index, ad7779_ext_filter) 704 static const struct iio_chan_spec ad7779_channels[] = { 705 AD777x_CHAN_NO_FILTER_S(0), 706 AD777x_CHAN_NO_FILTER_S(1), 707 AD777x_CHAN_NO_FILTER_S(2), 708 AD777x_CHAN_NO_FILTER_S(3), 709 AD777x_CHAN_NO_FILTER_S(4), 710 AD777x_CHAN_NO_FILTER_S(5), 711 AD777x_CHAN_NO_FILTER_S(6), 712 AD777x_CHAN_NO_FILTER_S(7), 713 IIO_CHAN_SOFT_TIMESTAMP(8), 714 }; 715 716 static const struct iio_chan_spec ad7779_channels_filter[] = { 717 AD777x_CHAN_FILTER_S(0), 718 AD777x_CHAN_FILTER_S(1), 719 AD777x_CHAN_FILTER_S(2), 720 AD777x_CHAN_FILTER_S(3), 721 AD777x_CHAN_FILTER_S(4), 722 AD777x_CHAN_FILTER_S(5), 723 AD777x_CHAN_FILTER_S(6), 724 AD777x_CHAN_FILTER_S(7), 725 IIO_CHAN_SOFT_TIMESTAMP(8), 726 }; 727 728 static const struct iio_buffer_setup_ops ad7779_buffer_setup_ops = { 729 .preenable = ad7779_buffer_preenable, 730 .postdisable = ad7779_buffer_postdisable, 731 }; 732 733 static const struct iio_trigger_ops ad7779_trigger_ops = { 734 .validate_device = iio_trigger_validate_own_device, 735 }; 736 737 static int ad7779_conf(struct ad7779_state *st, struct gpio_desc *start_gpio) 738 { 739 int ret; 740 741 ret = ad7779_spi_write_mask(st, AD7779_REG_GEN_ERR_REG_1_EN, 742 AD7779_SPI_CRC_EN_MSK, 743 FIELD_PREP(AD7779_SPI_CRC_EN_MSK, 1)); 744 if (ret) 745 return ret; 746 747 ret = ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, 748 AD7779_USRMOD_INIT_MSK, 749 FIELD_PREP(AD7779_USRMOD_INIT_MSK, 5)); 750 if (ret) 751 return ret; 752 753 ret = ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, 754 AD7779_DCLK_CLK_DIV_MSK, 755 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 1)); 756 if (ret) 757 return ret; 758 759 ret = ad7779_spi_write_mask(st, AD7779_REG_ADC_MUX_CONFIG, 760 AD7779_REFMUX_CTRL_MSK, 761 FIELD_PREP(AD7779_REFMUX_CTRL_MSK, 1)); 762 if (ret) 763 return ret; 764 765 ret = ad7779_set_sampling_frequency(st, AD7779_DEFAULT_SAMPLING_FREQ); 766 if (ret) 767 return ret; 768 769 gpiod_set_value(start_gpio, 0); 770 /* Start setup time */ 771 fsleep(15); 772 gpiod_set_value(start_gpio, 1); 773 /* Start setup time */ 774 fsleep(15); 775 gpiod_set_value(start_gpio, 0); 776 /* Start setup time */ 777 fsleep(15); 778 779 return 0; 780 } 781 782 static int ad7779_set_data_lines(struct iio_dev *indio_dev, u32 num_lanes) 783 { 784 struct ad7779_state *st = iio_priv(indio_dev); 785 int ret; 786 787 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) 788 return -EINVAL; 789 790 ret = ad7779_set_sampling_frequency(st, num_lanes * AD7779_DEFAULT_SAMPLING_1LINE); 791 if (ret) 792 return ret; 793 794 ret = iio_backend_num_lanes_set(st->back, num_lanes); 795 if (ret) 796 return ret; 797 798 return ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, 799 AD7779_DOUT_FORMAT_MSK, 800 FIELD_PREP(AD7779_DOUT_FORMAT_MSK, 2 - ilog2(num_lanes))); 801 } 802 803 static int ad7779_setup_channels(struct iio_dev *indio_dev, const struct ad7779_state *st) 804 { 805 struct iio_chan_spec *channels; 806 struct device *dev = &st->spi->dev; 807 808 channels = devm_kmemdup_array(dev, st->chip_info->channels, 809 ARRAY_SIZE(ad7779_channels), 810 sizeof(*channels), GFP_KERNEL); 811 if (!channels) 812 return -ENOMEM; 813 814 for (unsigned int i = 0; i < ARRAY_SIZE(ad7779_channels); i++) 815 channels[i].scan_type.endianness = IIO_CPU; 816 817 indio_dev->channels = channels; 818 indio_dev->num_channels = ARRAY_SIZE(ad7779_channels); 819 820 return 0; 821 } 822 823 static int ad7779_setup_without_backend(struct ad7779_state *st, struct iio_dev *indio_dev) 824 { 825 int ret; 826 struct device *dev = &st->spi->dev; 827 828 indio_dev->info = &ad7779_info; 829 indio_dev->channels = st->chip_info->channels; 830 indio_dev->num_channels = ARRAY_SIZE(ad7779_channels); 831 832 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 833 iio_device_id(indio_dev)); 834 if (!st->trig) 835 return -ENOMEM; 836 837 st->trig->ops = &ad7779_trigger_ops; 838 839 iio_trigger_set_drvdata(st->trig, st); 840 841 ret = devm_request_irq(dev, st->spi->irq, iio_trigger_generic_data_rdy_poll, 842 IRQF_NO_THREAD | IRQF_NO_AUTOEN, indio_dev->name, 843 st->trig); 844 if (ret) 845 return dev_err_probe(dev, ret, "request IRQ %d failed\n", 846 st->spi->irq); 847 848 ret = devm_iio_trigger_register(dev, st->trig); 849 if (ret) 850 return ret; 851 852 indio_dev->trig = iio_trigger_get(st->trig); 853 854 init_completion(&st->completion); 855 856 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 857 &iio_pollfunc_store_time, 858 &ad7779_trigger_handler, 859 &ad7779_buffer_setup_ops); 860 if (ret) 861 return ret; 862 863 return ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, 864 AD7779_DCLK_CLK_DIV_MSK, 865 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 7)); 866 } 867 868 static int ad7779_setup_backend(struct ad7779_state *st, struct iio_dev *indio_dev) 869 { 870 struct device *dev = &st->spi->dev; 871 int ret; 872 u32 num_lanes; 873 874 indio_dev->info = &ad7779_info_data; 875 876 ret = ad7779_setup_channels(indio_dev, st); 877 if (ret) 878 return ret; 879 880 st->back = devm_iio_backend_get(dev, NULL); 881 if (IS_ERR(st->back)) 882 return dev_err_probe(dev, PTR_ERR(st->back), 883 "failed to get iio backend"); 884 885 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 886 if (ret) 887 return ret; 888 889 ret = devm_iio_backend_enable(dev, st->back); 890 if (ret) 891 return ret; 892 893 num_lanes = 4; 894 ret = device_property_read_u32(dev, "adi,num-lanes", &num_lanes); 895 if (ret && ret != -EINVAL) 896 return ret; 897 898 return ad7779_set_data_lines(indio_dev, num_lanes); 899 } 900 901 static int ad7779_probe(struct spi_device *spi) 902 { 903 struct iio_dev *indio_dev; 904 struct ad7779_state *st; 905 struct gpio_desc *reset_gpio, *start_gpio; 906 struct device *dev = &spi->dev; 907 int ret = -EINVAL; 908 909 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 910 if (!indio_dev) 911 return -ENOMEM; 912 913 st = iio_priv(indio_dev); 914 915 ret = devm_regulator_bulk_get_enable(dev, 916 ARRAY_SIZE(ad7779_power_supplies), 917 ad7779_power_supplies); 918 if (ret) 919 return dev_err_probe(dev, ret, 920 "failed to get and enable supplies\n"); 921 922 st->mclk = devm_clk_get_enabled(dev, "mclk"); 923 if (IS_ERR(st->mclk)) 924 return PTR_ERR(st->mclk); 925 926 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 927 if (IS_ERR(reset_gpio)) 928 return PTR_ERR(reset_gpio); 929 930 start_gpio = devm_gpiod_get(dev, "start", GPIOD_OUT_HIGH); 931 if (IS_ERR(start_gpio)) 932 return PTR_ERR(start_gpio); 933 934 crc8_populate_msb(ad7779_crc8_table, AD7779_CRC8_POLY); 935 st->spi = spi; 936 937 st->chip_info = spi_get_device_match_data(spi); 938 if (!st->chip_info) 939 return -ENODEV; 940 941 ret = ad7779_reset(indio_dev, reset_gpio); 942 if (ret) 943 return ret; 944 945 ret = ad7779_conf(st, start_gpio); 946 if (ret) 947 return ret; 948 949 indio_dev->name = st->chip_info->name; 950 indio_dev->modes = INDIO_DIRECT_MODE; 951 952 if (device_property_present(dev, "io-backends")) 953 ret = ad7779_setup_backend(st, indio_dev); 954 else 955 ret = ad7779_setup_without_backend(st, indio_dev); 956 if (ret) 957 return ret; 958 959 return devm_iio_device_register(dev, indio_dev); 960 } 961 962 static int ad7779_suspend(struct device *dev) 963 { 964 struct iio_dev *indio_dev = dev_get_drvdata(dev); 965 struct ad7779_state *st = iio_priv(indio_dev); 966 967 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, 968 AD7779_MOD_POWERMODE_MSK, 969 FIELD_PREP(AD7779_MOD_POWERMODE_MSK, 970 AD7779_LOW_POWER)); 971 } 972 973 static int ad7779_resume(struct device *dev) 974 { 975 struct iio_dev *indio_dev = dev_get_drvdata(dev); 976 struct ad7779_state *st = iio_priv(indio_dev); 977 978 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, 979 AD7779_MOD_POWERMODE_MSK, 980 FIELD_PREP(AD7779_MOD_POWERMODE_MSK, 981 AD7779_HIGH_POWER)); 982 } 983 984 static DEFINE_SIMPLE_DEV_PM_OPS(ad7779_pm_ops, ad7779_suspend, ad7779_resume); 985 986 static const struct ad7779_chip_info ad7770_chip_info = { 987 .name = "ad7770", 988 .channels = ad7779_channels, 989 }; 990 991 static const struct ad7779_chip_info ad7771_chip_info = { 992 .name = "ad7771", 993 .channels = ad7779_channels_filter, 994 }; 995 996 static const struct ad7779_chip_info ad7779_chip_info = { 997 .name = "ad7779", 998 .channels = ad7779_channels, 999 }; 1000 1001 static const struct spi_device_id ad7779_id[] = { 1002 { 1003 .name = "ad7770", 1004 .driver_data = (kernel_ulong_t)&ad7770_chip_info, 1005 }, 1006 { 1007 .name = "ad7771", 1008 .driver_data = (kernel_ulong_t)&ad7771_chip_info, 1009 }, 1010 { 1011 .name = "ad7779", 1012 .driver_data = (kernel_ulong_t)&ad7779_chip_info, 1013 }, 1014 { } 1015 }; 1016 MODULE_DEVICE_TABLE(spi, ad7779_id); 1017 1018 static const struct of_device_id ad7779_of_table[] = { 1019 { 1020 .compatible = "adi,ad7770", 1021 .data = &ad7770_chip_info, 1022 }, 1023 { 1024 .compatible = "adi,ad7771", 1025 .data = &ad7771_chip_info, 1026 }, 1027 { 1028 .compatible = "adi,ad7779", 1029 .data = &ad7779_chip_info, 1030 }, 1031 { } 1032 }; 1033 MODULE_DEVICE_TABLE(of, ad7779_of_table); 1034 1035 static struct spi_driver ad7779_driver = { 1036 .driver = { 1037 .name = "ad7779", 1038 .pm = pm_sleep_ptr(&ad7779_pm_ops), 1039 .of_match_table = ad7779_of_table, 1040 }, 1041 .probe = ad7779_probe, 1042 .id_table = ad7779_id, 1043 }; 1044 module_spi_driver(ad7779_driver); 1045 1046 MODULE_AUTHOR("Ramona Alexandra Nechita <ramona.nechita@analog.com>"); 1047 MODULE_DESCRIPTION("Analog Devices AD7779 ADC"); 1048 MODULE_LICENSE("GPL"); 1049 MODULE_IMPORT_NS("IIO_BACKEND"); 1050