1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7770, AD7771, AD7779 ADC 4 * 5 * Copyright 2023-2024 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/clk.h> 11 #include <linux/crc8.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/math.h> 18 #include <linux/module.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/string.h> 22 #include <linux/types.h> 23 #include <linux/unaligned.h> 24 #include <linux/units.h> 25 26 #include <linux/iio/iio.h> 27 #include <linux/iio/backend.h> 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/sysfs.h> 30 #include <linux/iio/trigger.h> 31 #include <linux/iio/triggered_buffer.h> 32 #include <linux/iio/trigger_consumer.h> 33 34 #define AD7779_SPI_READ_CMD BIT(7) 35 36 #define AD7779_DISABLE_SD BIT(7) 37 38 #define AD7779_REG_CH_DISABLE 0x08 39 #define AD7779_REG_CH_SYNC_OFFSET(ch) (0x09 + (ch)) 40 #define AD7779_REG_CH_CONFIG(ch) (0x00 + (ch)) 41 #define AD7779_REG_GENERAL_USER_CONFIG_1 0x11 42 #define AD7779_REG_GENERAL_USER_CONFIG_2 0x12 43 #define AD7779_REG_GENERAL_USER_CONFIG_3 0x13 44 #define AD7779_REG_DOUT_FORMAT 0x14 45 #define AD7779_REG_ADC_MUX_CONFIG 0x15 46 #define AD7779_REG_GPIO_CONFIG 0x17 47 #define AD7779_REG_BUFFER_CONFIG_1 0x19 48 #define AD7779_REG_GLOBAL_MUX_CONFIG 0x16 49 #define AD7779_REG_BUFFER_CONFIG_2 0x1A 50 #define AD7779_REG_GPIO_DATA 0x18 51 #define AD7779_REG_CH_OFFSET_UPPER_BYTE(ch) (0x1C + (ch) * 6) 52 #define AD7779_REG_CH_OFFSET_LOWER_BYTE(ch) (0x1E + (ch) * 6) 53 #define AD7779_REG_CH_GAIN_UPPER_BYTE(ch) (0x1F + (ch) * 6) 54 #define AD7779_REG_CH_OFFSET_MID_BYTE(ch) (0x1D + (ch) * 6) 55 #define AD7779_REG_CH_GAIN_MID_BYTE(ch) (0x20 + (ch) * 6) 56 #define AD7779_REG_CH_ERR_REG(ch) (0x4C + (ch)) 57 #define AD7779_REG_CH0_1_SAT_ERR 0x54 58 #define AD7779_REG_CH_GAIN_LOWER_BYTE(ch) (0x21 + (ch) * 6) 59 #define AD7779_REG_CH2_3_SAT_ERR 0x55 60 #define AD7779_REG_CH4_5_SAT_ERR 0x56 61 #define AD7779_REG_CH6_7_SAT_ERR 0x57 62 #define AD7779_REG_CHX_ERR_REG_EN 0x58 63 #define AD7779_REG_GEN_ERR_REG_1 0x59 64 #define AD7779_REG_GEN_ERR_REG_1_EN 0x5A 65 #define AD7779_REG_GEN_ERR_REG_2 0x5B 66 #define AD7779_REG_GEN_ERR_REG_2_EN 0x5C 67 #define AD7779_REG_STATUS_REG_1 0x5D 68 #define AD7779_REG_STATUS_REG_2 0x5E 69 #define AD7779_REG_STATUS_REG_3 0x5F 70 #define AD7779_REG_SRC_N_MSB 0x60 71 #define AD7779_REG_SRC_N_LSB 0x61 72 #define AD7779_REG_SRC_IF_MSB 0x62 73 #define AD7779_REG_SRC_IF_LSB 0x63 74 #define AD7779_REG_SRC_UPDATE 0x64 75 76 #define AD7779_FILTER_MSK BIT(6) 77 #define AD7779_MOD_POWERMODE_MSK BIT(6) 78 #define AD7779_MOD_PDB_REFOUT_MSK BIT(4) 79 #define AD7779_MOD_SPI_EN_MSK BIT(4) 80 #define AD7779_USRMOD_INIT_MSK GENMASK(6, 4) 81 82 /* AD7779_REG_DOUT_FORMAT */ 83 #define AD7779_DOUT_FORMAT_MSK GENMASK(7, 6) 84 #define AD7779_DOUT_HEADER_FORMAT BIT(5) 85 #define AD7779_DCLK_CLK_DIV_MSK GENMASK(3, 1) 86 87 #define AD7779_REFMUX_CTRL_MSK GENMASK(7, 6) 88 #define AD7779_SPI_CRC_EN_MSK BIT(0) 89 90 #define AD7779_MAXCLK_LOWPOWER (4096 * HZ_PER_KHZ) 91 #define AD7779_NUM_CHANNELS 8 92 #define AD7779_RESET_BUF_SIZE 8 93 #define AD7779_CHAN_DATA_SIZE 4 94 95 #define AD7779_LOWPOWER_DIV 512 96 #define AD7779_HIGHPOWER_DIV 2048 97 98 #define AD7779_SINC3_MAXFREQ (16 * HZ_PER_KHZ) 99 #define AD7779_SINC5_MAXFREQ (128 * HZ_PER_KHZ) 100 101 #define AD7779_DEFAULT_SAMPLING_FREQ (8 * HZ_PER_KHZ) 102 #define AD7779_DEFAULT_SAMPLING_2LINE (4 * HZ_PER_KHZ) 103 #define AD7779_DEFAULT_SAMPLING_1LINE (2 * HZ_PER_KHZ) 104 105 #define AD7779_SPIMODE_MAX_SAMP_FREQ (16 * HZ_PER_KHZ) 106 107 #define GAIN_REL 0x555555 108 #define AD7779_FREQ_MSB_MSK GENMASK(15, 8) 109 #define AD7779_FREQ_LSB_MSK GENMASK(7, 0) 110 #define AD7779_UPPER GENMASK(23, 16) 111 #define AD7779_MID GENMASK(15, 8) 112 #define AD7779_LOWER GENMASK(7, 0) 113 114 #define AD7779_REG_MSK GENMASK(6, 0) 115 116 #define AD7779_CRC8_POLY 0x07 117 DECLARE_CRC8_TABLE(ad7779_crc8_table); 118 119 enum ad7779_filter { 120 AD7779_SINC3, 121 AD7779_SINC5, 122 }; 123 124 enum ad7779_variant { 125 ad7770, 126 ad7771, 127 ad7779, 128 }; 129 130 enum ad7779_power_mode { 131 AD7779_LOW_POWER, 132 AD7779_HIGH_POWER, 133 }; 134 135 struct ad7779_chip_info { 136 const char *name; 137 struct iio_chan_spec const *channels; 138 }; 139 140 struct ad7779_state { 141 struct spi_device *spi; 142 const struct ad7779_chip_info *chip_info; 143 struct clk *mclk; 144 struct iio_trigger *trig; 145 unsigned int sampling_freq; 146 enum ad7779_filter filter_enabled; 147 struct iio_backend *back; 148 /* 149 * DMA (thus cache coherency maintenance) requires the 150 * transfer buffers to live in their own cache lines. 151 */ 152 struct { 153 u32 chans[8]; 154 aligned_s64 timestamp; 155 } data __aligned(IIO_DMA_MINALIGN); 156 u32 spidata_tx[8]; 157 u8 reg_rx_buf[3]; 158 u8 reg_tx_buf[3]; 159 u8 reset_buf[8]; 160 }; 161 162 static const char * const ad7779_filter_type[] = { 163 [AD7779_SINC3] = "sinc3", 164 [AD7779_SINC5] = "sinc5", 165 }; 166 167 static const char * const ad7779_power_supplies[] = { 168 "avdd1", "avdd2", "avdd4", 169 }; 170 171 static int ad7779_spi_read(struct ad7779_state *st, u8 reg, u8 *rbuf) 172 { 173 int ret; 174 u8 crc_buf[2]; 175 u8 exp_crc; 176 struct spi_transfer t = { 177 .tx_buf = st->reg_tx_buf, 178 .rx_buf = st->reg_rx_buf, 179 }; 180 181 st->reg_tx_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg); 182 st->reg_tx_buf[1] = 0; 183 184 if (reg == AD7779_REG_GEN_ERR_REG_1_EN) { 185 t.len = 2; 186 } else { 187 t.len = 3; 188 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf, 189 t.len - 1, 0); 190 } 191 192 ret = spi_sync_transfer(st->spi, &t, 1); 193 if (ret) 194 return ret; 195 196 crc_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg); 197 crc_buf[1] = st->reg_rx_buf[1]; 198 exp_crc = crc8(ad7779_crc8_table, crc_buf, ARRAY_SIZE(crc_buf), 0); 199 if (reg != AD7779_REG_GEN_ERR_REG_1_EN && exp_crc != st->reg_rx_buf[2]) { 200 dev_err(&st->spi->dev, "Bad CRC %x, expected %x", 201 st->reg_rx_buf[2], exp_crc); 202 return -EINVAL; 203 } 204 *rbuf = st->reg_rx_buf[1]; 205 206 return 0; 207 } 208 209 static int ad7779_spi_write(struct ad7779_state *st, u8 reg, u8 val) 210 { 211 u8 length = 3; 212 213 st->reg_tx_buf[0] = FIELD_GET(AD7779_REG_MSK, reg); 214 st->reg_tx_buf[1] = val; 215 if (reg == AD7779_REG_GEN_ERR_REG_1_EN) 216 length = 2; 217 else 218 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf, 219 length - 1, 0); 220 221 return spi_write(st->spi, st->reg_tx_buf, length); 222 } 223 224 static int ad7779_spi_write_mask(struct ad7779_state *st, u8 reg, u8 mask, 225 u8 val) 226 { 227 int ret; 228 u8 regval, data; 229 230 ret = ad7779_spi_read(st, reg, &data); 231 if (ret) 232 return ret; 233 234 regval = (data & ~mask) | (val & mask); 235 236 if (regval == data) 237 return 0; 238 239 return ad7779_spi_write(st, reg, regval); 240 } 241 242 static int ad7779_reg_access(struct iio_dev *indio_dev, 243 unsigned int reg, 244 unsigned int writeval, 245 unsigned int *readval) 246 { 247 struct ad7779_state *st = iio_priv(indio_dev); 248 u8 rval; 249 int ret; 250 251 if (readval) { 252 ret = ad7779_spi_read(st, reg, &rval); 253 *readval = rval; 254 return ret; 255 } 256 257 return ad7779_spi_write(st, reg, writeval); 258 } 259 260 static int ad7779_set_sampling_frequency(struct ad7779_state *st, 261 unsigned int sampling_freq) 262 { 263 int ret; 264 unsigned int dec; 265 unsigned int frac; 266 unsigned int div; 267 unsigned int decimal; 268 unsigned int freq_khz; 269 270 if (st->filter_enabled == AD7779_SINC3 && 271 sampling_freq > AD7779_SINC3_MAXFREQ) 272 return -EINVAL; 273 274 if (st->filter_enabled == AD7779_SINC5 && 275 sampling_freq > AD7779_SINC5_MAXFREQ) 276 return -EINVAL; 277 278 if (sampling_freq > AD7779_SPIMODE_MAX_SAMP_FREQ) 279 return -EINVAL; 280 281 div = AD7779_HIGHPOWER_DIV; 282 283 freq_khz = sampling_freq / HZ_PER_KHZ; 284 dec = div / freq_khz; 285 frac = div % freq_khz; 286 287 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, 288 FIELD_GET(AD7779_FREQ_MSB_MSK, dec)); 289 if (ret) 290 return ret; 291 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, 292 FIELD_GET(AD7779_FREQ_LSB_MSK, dec)); 293 if (ret) 294 return ret; 295 296 if (frac) { 297 /* 298 * In order to obtain the first three decimals of the decimation 299 * the initial number is multiplied with 10^3 prior to the 300 * division, then the original division result is subtracted and 301 * the number is divided by 10^3. 302 */ 303 decimal = ((mult_frac(div, KILO, freq_khz) - dec * KILO) << 16) 304 / KILO; 305 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, 306 FIELD_GET(AD7779_FREQ_MSB_MSK, decimal)); 307 if (ret) 308 return ret; 309 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, 310 FIELD_GET(AD7779_FREQ_LSB_MSK, decimal)); 311 if (ret) 312 return ret; 313 } else { 314 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, 315 FIELD_GET(AD7779_FREQ_MSB_MSK, 0x0)); 316 if (ret) 317 return ret; 318 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, 319 FIELD_GET(AD7779_FREQ_LSB_MSK, 0x0)); 320 if (ret) 321 return ret; 322 } 323 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, BIT(0)); 324 if (ret) 325 return ret; 326 327 /* SRC update settling time */ 328 fsleep(15); 329 330 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, 0x0); 331 if (ret) 332 return ret; 333 334 /* SRC update settling time */ 335 fsleep(15); 336 337 st->sampling_freq = sampling_freq; 338 339 return 0; 340 } 341 342 static int ad7779_get_filter(struct iio_dev *indio_dev, 343 struct iio_chan_spec const *chan) 344 { 345 struct ad7779_state *st = iio_priv(indio_dev); 346 u8 temp; 347 int ret; 348 349 ret = ad7779_spi_read(st, AD7779_REG_GENERAL_USER_CONFIG_2, &temp); 350 if (ret) 351 return ret; 352 353 return FIELD_GET(AD7779_FILTER_MSK, temp); 354 } 355 356 static int ad7779_set_filter(struct iio_dev *indio_dev, 357 struct iio_chan_spec const *chan, 358 unsigned int mode) 359 { 360 struct ad7779_state *st = iio_priv(indio_dev); 361 int ret; 362 363 ret = ad7779_spi_write_mask(st, 364 AD7779_REG_GENERAL_USER_CONFIG_2, 365 AD7779_FILTER_MSK, 366 FIELD_PREP(AD7779_FILTER_MSK, mode)); 367 if (ret) 368 return ret; 369 370 ret = ad7779_set_sampling_frequency(st, st->sampling_freq); 371 if (ret) 372 return ret; 373 374 st->filter_enabled = mode; 375 376 return 0; 377 } 378 379 static int ad7779_get_calibscale(struct ad7779_state *st, int channel) 380 { 381 int ret; 382 u8 calibscale[3]; 383 384 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel), 385 &calibscale[0]); 386 if (ret) 387 return ret; 388 389 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_MID_BYTE(channel), 390 &calibscale[1]); 391 if (ret) 392 return ret; 393 394 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel), 395 &calibscale[2]); 396 if (ret) 397 return ret; 398 399 return get_unaligned_be24(calibscale); 400 } 401 402 static int ad7779_set_calibscale(struct ad7779_state *st, int channel, int val) 403 { 404 int ret; 405 unsigned int gain; 406 u8 gain_bytes[3]; 407 408 /* 409 * The gain value is relative to 0x555555, which represents a gain of 1 410 */ 411 gain = DIV_ROUND_CLOSEST_ULL((u64)val * 5592405LL, MEGA); 412 put_unaligned_be24(gain, gain_bytes); 413 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel), 414 gain_bytes[0]); 415 if (ret) 416 return ret; 417 418 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_MID_BYTE(channel), 419 gain_bytes[1]); 420 if (ret) 421 return ret; 422 423 return ad7779_spi_write(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel), 424 gain_bytes[2]); 425 } 426 427 static int ad7779_get_calibbias(struct ad7779_state *st, int channel) 428 { 429 int ret; 430 u8 calibbias[3]; 431 432 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel), 433 &calibbias[0]); 434 if (ret) 435 return ret; 436 437 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel), 438 &calibbias[1]); 439 if (ret) 440 return ret; 441 442 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel), 443 &calibbias[2]); 444 if (ret) 445 return ret; 446 447 return get_unaligned_be24(calibbias); 448 } 449 450 static int ad7779_set_calibbias(struct ad7779_state *st, int channel, int val) 451 { 452 int ret; 453 u8 calibbias[3]; 454 455 put_unaligned_be24(val, calibbias); 456 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel), 457 calibbias[0]); 458 if (ret) 459 return ret; 460 461 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel), 462 calibbias[1]); 463 if (ret) 464 return ret; 465 466 return ad7779_spi_write(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel), 467 calibbias[2]); 468 } 469 470 static int __ad7779_read_raw(struct iio_dev *indio_dev, 471 struct iio_chan_spec const *chan, int *val, 472 int *val2, long mask) 473 { 474 struct ad7779_state *st = iio_priv(indio_dev); 475 int ret; 476 477 switch (mask) { 478 case IIO_CHAN_INFO_CALIBSCALE: 479 ret = ad7779_get_calibscale(st, chan->channel); 480 if (ret < 0) 481 return ret; 482 *val = ret; 483 *val2 = GAIN_REL; 484 return IIO_VAL_FRACTIONAL; 485 case IIO_CHAN_INFO_CALIBBIAS: 486 ret = ad7779_get_calibbias(st, chan->channel); 487 if (ret < 0) 488 return ret; 489 *val = ret; 490 return IIO_VAL_INT; 491 case IIO_CHAN_INFO_SAMP_FREQ: 492 *val = st->sampling_freq; 493 if (*val < 0) 494 return -EINVAL; 495 return IIO_VAL_INT; 496 default: 497 return -EINVAL; 498 } 499 } 500 501 static int ad7779_read_raw(struct iio_dev *indio_dev, 502 struct iio_chan_spec const *chan, int *val, 503 int *val2, long mask) 504 { 505 int ret; 506 507 if (!iio_device_claim_direct(indio_dev)) 508 return -EBUSY; 509 510 ret = __ad7779_read_raw(indio_dev, chan, val, val2, mask); 511 iio_device_release_direct(indio_dev); 512 return ret; 513 } 514 515 static int __ad7779_write_raw(struct iio_dev *indio_dev, 516 struct iio_chan_spec const *chan, 517 int val, int val2, 518 long mask) 519 { 520 struct ad7779_state *st = iio_priv(indio_dev); 521 522 switch (mask) { 523 case IIO_CHAN_INFO_CALIBSCALE: 524 return ad7779_set_calibscale(st, chan->channel, val2); 525 case IIO_CHAN_INFO_CALIBBIAS: 526 return ad7779_set_calibbias(st, chan->channel, val); 527 case IIO_CHAN_INFO_SAMP_FREQ: 528 return ad7779_set_sampling_frequency(st, val); 529 default: 530 return -EINVAL; 531 } 532 } 533 534 static int ad7779_write_raw(struct iio_dev *indio_dev, 535 struct iio_chan_spec const *chan, int val, int val2, 536 long mask) 537 { 538 int ret; 539 540 if (!iio_device_claim_direct(indio_dev)) 541 return -EBUSY; 542 543 ret = __ad7779_write_raw(indio_dev, chan, val, val2, mask); 544 iio_device_release_direct(indio_dev); 545 return ret; 546 } 547 548 static int ad7779_buffer_preenable(struct iio_dev *indio_dev) 549 { 550 int ret; 551 struct ad7779_state *st = iio_priv(indio_dev); 552 553 ret = ad7779_spi_write_mask(st, 554 AD7779_REG_GENERAL_USER_CONFIG_3, 555 AD7779_MOD_SPI_EN_MSK, 556 FIELD_PREP(AD7779_MOD_SPI_EN_MSK, 1)); 557 if (ret) 558 return ret; 559 560 /* 561 * DRDY output cannot be disabled at device level therefore we mask 562 * the irq at host end. 563 */ 564 enable_irq(st->spi->irq); 565 566 return 0; 567 } 568 569 static int ad7779_buffer_postdisable(struct iio_dev *indio_dev) 570 { 571 struct ad7779_state *st = iio_priv(indio_dev); 572 573 disable_irq(st->spi->irq); 574 575 return ad7779_spi_write(st, AD7779_REG_GENERAL_USER_CONFIG_3, 576 AD7779_DISABLE_SD); 577 } 578 579 static irqreturn_t ad7779_trigger_handler(int irq, void *p) 580 { 581 struct iio_poll_func *pf = p; 582 struct iio_dev *indio_dev = pf->indio_dev; 583 struct ad7779_state *st = iio_priv(indio_dev); 584 int ret; 585 struct spi_transfer t = { 586 .rx_buf = st->data.chans, 587 .tx_buf = st->spidata_tx, 588 .len = AD7779_NUM_CHANNELS * AD7779_CHAN_DATA_SIZE, 589 }; 590 591 st->spidata_tx[0] = AD7779_SPI_READ_CMD; 592 ret = spi_sync_transfer(st->spi, &t, 1); 593 if (ret) { 594 dev_err(&st->spi->dev, "SPI transfer error in IRQ handler"); 595 goto exit_handler; 596 } 597 598 iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data), 599 pf->timestamp); 600 601 exit_handler: 602 iio_trigger_notify_done(indio_dev->trig); 603 return IRQ_HANDLED; 604 } 605 606 static int ad7779_reset(struct iio_dev *indio_dev, struct gpio_desc *reset_gpio) 607 { 608 struct ad7779_state *st = iio_priv(indio_dev); 609 int ret; 610 struct spi_transfer t = { 611 .tx_buf = st->reset_buf, 612 .len = 8, 613 }; 614 615 if (reset_gpio) { 616 gpiod_set_value(reset_gpio, 1); 617 /* Delay for reset to occur is 225 microseconds */ 618 fsleep(230); 619 ret = 0; 620 } else { 621 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); 622 ret = spi_sync_transfer(st->spi, &t, 1); 623 if (ret) 624 return ret; 625 } 626 627 /* Delay for reset to occur is 225 microseconds */ 628 fsleep(230); 629 630 return ret; 631 } 632 633 static int ad7779_update_scan_mode(struct iio_dev *indio_dev, 634 const unsigned long *scan_mask) 635 { 636 struct ad7779_state *st = iio_priv(indio_dev); 637 unsigned int c; 638 int ret; 639 640 for (c = 0; c < AD7779_NUM_CHANNELS; c++) { 641 if (test_bit(c, scan_mask)) 642 ret = iio_backend_chan_enable(st->back, c); 643 else 644 ret = iio_backend_chan_disable(st->back, c); 645 if (ret) 646 return ret; 647 } 648 649 return 0; 650 } 651 652 static const struct iio_info ad7779_info = { 653 .read_raw = ad7779_read_raw, 654 .write_raw = ad7779_write_raw, 655 .debugfs_reg_access = &ad7779_reg_access, 656 }; 657 658 static const struct iio_info ad7779_info_data = { 659 .read_raw = ad7779_read_raw, 660 .write_raw = ad7779_write_raw, 661 .debugfs_reg_access = &ad7779_reg_access, 662 .update_scan_mode = &ad7779_update_scan_mode, 663 }; 664 665 static const struct iio_enum ad7779_filter_enum = { 666 .items = ad7779_filter_type, 667 .num_items = ARRAY_SIZE(ad7779_filter_type), 668 .get = ad7779_get_filter, 669 .set = ad7779_set_filter, 670 }; 671 672 static const struct iio_chan_spec_ext_info ad7779_ext_filter[] = { 673 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7779_filter_enum), 674 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, 675 &ad7779_filter_enum), 676 { } 677 }; 678 679 #define AD777x_CHAN_S(index, _ext_info) \ 680 { \ 681 .type = IIO_VOLTAGE, \ 682 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 683 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 684 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 685 .address = (index), \ 686 .indexed = 1, \ 687 .channel = (index), \ 688 .scan_index = (index), \ 689 .ext_info = (_ext_info), \ 690 .scan_type = { \ 691 .sign = 's', \ 692 .realbits = 24, \ 693 .storagebits = 32, \ 694 .endianness = IIO_BE, \ 695 }, \ 696 } 697 698 #define AD777x_CHAN_NO_FILTER_S(index) \ 699 AD777x_CHAN_S(index, NULL) 700 701 #define AD777x_CHAN_FILTER_S(index) \ 702 AD777x_CHAN_S(index, ad7779_ext_filter) 703 static const struct iio_chan_spec ad7779_channels[] = { 704 AD777x_CHAN_NO_FILTER_S(0), 705 AD777x_CHAN_NO_FILTER_S(1), 706 AD777x_CHAN_NO_FILTER_S(2), 707 AD777x_CHAN_NO_FILTER_S(3), 708 AD777x_CHAN_NO_FILTER_S(4), 709 AD777x_CHAN_NO_FILTER_S(5), 710 AD777x_CHAN_NO_FILTER_S(6), 711 AD777x_CHAN_NO_FILTER_S(7), 712 IIO_CHAN_SOFT_TIMESTAMP(8), 713 }; 714 715 static const struct iio_chan_spec ad7779_channels_filter[] = { 716 AD777x_CHAN_FILTER_S(0), 717 AD777x_CHAN_FILTER_S(1), 718 AD777x_CHAN_FILTER_S(2), 719 AD777x_CHAN_FILTER_S(3), 720 AD777x_CHAN_FILTER_S(4), 721 AD777x_CHAN_FILTER_S(5), 722 AD777x_CHAN_FILTER_S(6), 723 AD777x_CHAN_FILTER_S(7), 724 IIO_CHAN_SOFT_TIMESTAMP(8), 725 }; 726 727 static const struct iio_buffer_setup_ops ad7779_buffer_setup_ops = { 728 .preenable = ad7779_buffer_preenable, 729 .postdisable = ad7779_buffer_postdisable, 730 }; 731 732 static const struct iio_trigger_ops ad7779_trigger_ops = { 733 .validate_device = iio_trigger_validate_own_device, 734 }; 735 736 static int ad7779_conf(struct ad7779_state *st, struct gpio_desc *start_gpio) 737 { 738 int ret; 739 740 ret = ad7779_spi_write_mask(st, AD7779_REG_GEN_ERR_REG_1_EN, 741 AD7779_SPI_CRC_EN_MSK, 742 FIELD_PREP(AD7779_SPI_CRC_EN_MSK, 1)); 743 if (ret) 744 return ret; 745 746 ret = ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, 747 AD7779_USRMOD_INIT_MSK, 748 FIELD_PREP(AD7779_USRMOD_INIT_MSK, 5)); 749 if (ret) 750 return ret; 751 752 ret = ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, 753 AD7779_DCLK_CLK_DIV_MSK, 754 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 1)); 755 if (ret) 756 return ret; 757 758 ret = ad7779_spi_write_mask(st, AD7779_REG_ADC_MUX_CONFIG, 759 AD7779_REFMUX_CTRL_MSK, 760 FIELD_PREP(AD7779_REFMUX_CTRL_MSK, 1)); 761 if (ret) 762 return ret; 763 764 ret = ad7779_set_sampling_frequency(st, AD7779_DEFAULT_SAMPLING_FREQ); 765 if (ret) 766 return ret; 767 768 gpiod_set_value(start_gpio, 0); 769 /* Start setup time */ 770 fsleep(15); 771 gpiod_set_value(start_gpio, 1); 772 /* Start setup time */ 773 fsleep(15); 774 gpiod_set_value(start_gpio, 0); 775 /* Start setup time */ 776 fsleep(15); 777 778 return 0; 779 } 780 781 static int ad7779_set_data_lines(struct iio_dev *indio_dev, u32 num_lanes) 782 { 783 struct ad7779_state *st = iio_priv(indio_dev); 784 int ret; 785 786 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) 787 return -EINVAL; 788 789 ret = ad7779_set_sampling_frequency(st, num_lanes * AD7779_DEFAULT_SAMPLING_1LINE); 790 if (ret) 791 return ret; 792 793 ret = iio_backend_num_lanes_set(st->back, num_lanes); 794 if (ret) 795 return ret; 796 797 return ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, 798 AD7779_DOUT_FORMAT_MSK, 799 FIELD_PREP(AD7779_DOUT_FORMAT_MSK, 2 - ilog2(num_lanes))); 800 } 801 802 static int ad7779_setup_channels(struct iio_dev *indio_dev, const struct ad7779_state *st) 803 { 804 struct iio_chan_spec *channels; 805 struct device *dev = &st->spi->dev; 806 807 channels = devm_kmemdup_array(dev, st->chip_info->channels, 808 ARRAY_SIZE(ad7779_channels), 809 sizeof(*channels), GFP_KERNEL); 810 if (!channels) 811 return -ENOMEM; 812 813 for (unsigned int i = 0; i < ARRAY_SIZE(ad7779_channels); i++) 814 channels[i].scan_type.endianness = IIO_CPU; 815 816 indio_dev->channels = channels; 817 indio_dev->num_channels = ARRAY_SIZE(ad7779_channels); 818 819 return 0; 820 } 821 822 static int ad7779_setup_without_backend(struct ad7779_state *st, struct iio_dev *indio_dev) 823 { 824 int ret; 825 struct device *dev = &st->spi->dev; 826 827 indio_dev->info = &ad7779_info; 828 indio_dev->channels = st->chip_info->channels; 829 indio_dev->num_channels = ARRAY_SIZE(ad7779_channels); 830 831 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 832 iio_device_id(indio_dev)); 833 if (!st->trig) 834 return -ENOMEM; 835 836 st->trig->ops = &ad7779_trigger_ops; 837 838 iio_trigger_set_drvdata(st->trig, st); 839 840 ret = devm_request_irq(dev, st->spi->irq, iio_trigger_generic_data_rdy_poll, 841 IRQF_NO_THREAD | IRQF_NO_AUTOEN, indio_dev->name, 842 st->trig); 843 if (ret) 844 return ret; 845 846 ret = devm_iio_trigger_register(dev, st->trig); 847 if (ret) 848 return ret; 849 850 indio_dev->trig = iio_trigger_get(st->trig); 851 852 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 853 &iio_pollfunc_store_time, 854 &ad7779_trigger_handler, 855 &ad7779_buffer_setup_ops); 856 if (ret) 857 return ret; 858 859 return ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, 860 AD7779_DCLK_CLK_DIV_MSK, 861 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 7)); 862 } 863 864 static int ad7779_setup_backend(struct ad7779_state *st, struct iio_dev *indio_dev) 865 { 866 struct device *dev = &st->spi->dev; 867 int ret; 868 u32 num_lanes; 869 870 indio_dev->info = &ad7779_info_data; 871 872 ret = ad7779_setup_channels(indio_dev, st); 873 if (ret) 874 return ret; 875 876 st->back = devm_iio_backend_get(dev, NULL); 877 if (IS_ERR(st->back)) 878 return dev_err_probe(dev, PTR_ERR(st->back), 879 "failed to get iio backend"); 880 881 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 882 if (ret) 883 return ret; 884 885 ret = devm_iio_backend_enable(dev, st->back); 886 if (ret) 887 return ret; 888 889 num_lanes = 4; 890 ret = device_property_read_u32(dev, "adi,num-lanes", &num_lanes); 891 if (ret && ret != -EINVAL) 892 return ret; 893 894 return ad7779_set_data_lines(indio_dev, num_lanes); 895 } 896 897 static int ad7779_probe(struct spi_device *spi) 898 { 899 struct iio_dev *indio_dev; 900 struct ad7779_state *st; 901 struct gpio_desc *reset_gpio, *start_gpio; 902 struct device *dev = &spi->dev; 903 int ret = -EINVAL; 904 905 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 906 if (!indio_dev) 907 return -ENOMEM; 908 909 st = iio_priv(indio_dev); 910 911 ret = devm_regulator_bulk_get_enable(dev, 912 ARRAY_SIZE(ad7779_power_supplies), 913 ad7779_power_supplies); 914 if (ret) 915 return dev_err_probe(dev, ret, 916 "failed to get and enable supplies\n"); 917 918 st->mclk = devm_clk_get_enabled(dev, "mclk"); 919 if (IS_ERR(st->mclk)) 920 return PTR_ERR(st->mclk); 921 922 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 923 if (IS_ERR(reset_gpio)) 924 return PTR_ERR(reset_gpio); 925 926 start_gpio = devm_gpiod_get(dev, "start", GPIOD_OUT_HIGH); 927 if (IS_ERR(start_gpio)) 928 return PTR_ERR(start_gpio); 929 930 crc8_populate_msb(ad7779_crc8_table, AD7779_CRC8_POLY); 931 st->spi = spi; 932 933 st->chip_info = spi_get_device_match_data(spi); 934 if (!st->chip_info) 935 return -ENODEV; 936 937 ret = ad7779_reset(indio_dev, reset_gpio); 938 if (ret) 939 return ret; 940 941 ret = ad7779_conf(st, start_gpio); 942 if (ret) 943 return ret; 944 945 indio_dev->name = st->chip_info->name; 946 indio_dev->modes = INDIO_DIRECT_MODE; 947 948 if (device_property_present(dev, "io-backends")) 949 ret = ad7779_setup_backend(st, indio_dev); 950 else 951 ret = ad7779_setup_without_backend(st, indio_dev); 952 if (ret) 953 return ret; 954 955 return devm_iio_device_register(dev, indio_dev); 956 } 957 958 static int ad7779_suspend(struct device *dev) 959 { 960 struct iio_dev *indio_dev = dev_get_drvdata(dev); 961 struct ad7779_state *st = iio_priv(indio_dev); 962 963 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, 964 AD7779_MOD_POWERMODE_MSK, 965 FIELD_PREP(AD7779_MOD_POWERMODE_MSK, 966 AD7779_LOW_POWER)); 967 } 968 969 static int ad7779_resume(struct device *dev) 970 { 971 struct iio_dev *indio_dev = dev_get_drvdata(dev); 972 struct ad7779_state *st = iio_priv(indio_dev); 973 974 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, 975 AD7779_MOD_POWERMODE_MSK, 976 FIELD_PREP(AD7779_MOD_POWERMODE_MSK, 977 AD7779_HIGH_POWER)); 978 } 979 980 static DEFINE_SIMPLE_DEV_PM_OPS(ad7779_pm_ops, ad7779_suspend, ad7779_resume); 981 982 static const struct ad7779_chip_info ad7770_chip_info = { 983 .name = "ad7770", 984 .channels = ad7779_channels, 985 }; 986 987 static const struct ad7779_chip_info ad7771_chip_info = { 988 .name = "ad7771", 989 .channels = ad7779_channels_filter, 990 }; 991 992 static const struct ad7779_chip_info ad7779_chip_info = { 993 .name = "ad7779", 994 .channels = ad7779_channels, 995 }; 996 997 static const struct spi_device_id ad7779_id[] = { 998 { 999 .name = "ad7770", 1000 .driver_data = (kernel_ulong_t)&ad7770_chip_info, 1001 }, 1002 { 1003 .name = "ad7771", 1004 .driver_data = (kernel_ulong_t)&ad7771_chip_info, 1005 }, 1006 { 1007 .name = "ad7779", 1008 .driver_data = (kernel_ulong_t)&ad7779_chip_info, 1009 }, 1010 { } 1011 }; 1012 MODULE_DEVICE_TABLE(spi, ad7779_id); 1013 1014 static const struct of_device_id ad7779_of_table[] = { 1015 { 1016 .compatible = "adi,ad7770", 1017 .data = &ad7770_chip_info, 1018 }, 1019 { 1020 .compatible = "adi,ad7771", 1021 .data = &ad7771_chip_info, 1022 }, 1023 { 1024 .compatible = "adi,ad7779", 1025 .data = &ad7779_chip_info, 1026 }, 1027 { } 1028 }; 1029 MODULE_DEVICE_TABLE(of, ad7779_of_table); 1030 1031 static struct spi_driver ad7779_driver = { 1032 .driver = { 1033 .name = "ad7779", 1034 .pm = pm_sleep_ptr(&ad7779_pm_ops), 1035 .of_match_table = ad7779_of_table, 1036 }, 1037 .probe = ad7779_probe, 1038 .id_table = ad7779_id, 1039 }; 1040 module_spi_driver(ad7779_driver); 1041 1042 MODULE_AUTHOR("Ramona Alexandra Nechita <ramona.nechita@analog.com>"); 1043 MODULE_DESCRIPTION("Analog Devices AD7779 ADC"); 1044 MODULE_LICENSE("GPL"); 1045 MODULE_IMPORT_NS("IIO_BACKEND"); 1046