1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7768-1 SPI ADC driver 4 * 5 * Copyright 2017 Analog Devices Inc. 6 */ 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/interrupt.h> 18 #include <linux/limits.h> 19 #include <linux/math.h> 20 #include <linux/minmax.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/rational.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/sysfs.h> 28 #include <linux/spi/spi.h> 29 #include <linux/unaligned.h> 30 #include <linux/units.h> 31 #include <linux/util_macros.h> 32 33 #include <linux/iio/buffer.h> 34 #include <linux/iio/iio.h> 35 #include <linux/iio/sysfs.h> 36 #include <linux/iio/trigger.h> 37 #include <linux/iio/triggered_buffer.h> 38 #include <linux/iio/trigger_consumer.h> 39 40 #include <dt-bindings/iio/adc/adi,ad7768-1.h> 41 42 /* AD7768 registers definition */ 43 #define AD7768_REG_CHIP_TYPE 0x3 44 #define AD7768_REG_PROD_ID_L 0x4 45 #define AD7768_REG_PROD_ID_H 0x5 46 #define AD7768_REG_CHIP_GRADE 0x6 47 #define AD7768_REG_SCRATCH_PAD 0x0A 48 #define AD7768_REG_VENDOR_L 0x0C 49 #define AD7768_REG_VENDOR_H 0x0D 50 #define AD7768_REG_INTERFACE_FORMAT 0x14 51 #define AD7768_REG_POWER_CLOCK 0x15 52 #define AD7768_REG_ANALOG 0x16 53 #define AD7768_REG_ANALOG2 0x17 54 #define AD7768_REG_CONVERSION 0x18 55 #define AD7768_REG_DIGITAL_FILTER 0x19 56 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A 57 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B 58 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C 59 #define AD7768_REG_SYNC_RESET 0x1D 60 #define AD7768_REG_GPIO_CONTROL 0x1E 61 #define AD7768_REG_GPIO_WRITE 0x1F 62 #define AD7768_REG_GPIO_READ 0x20 63 #define AD7768_REG_OFFSET_HI 0x21 64 #define AD7768_REG_OFFSET_MID 0x22 65 #define AD7768_REG_OFFSET_LO 0x23 66 #define AD7768_REG_GAIN_HI 0x24 67 #define AD7768_REG_GAIN_MID 0x25 68 #define AD7768_REG_GAIN_LO 0x26 69 #define AD7768_REG_SPI_DIAG_ENABLE 0x28 70 #define AD7768_REG_ADC_DIAG_ENABLE 0x29 71 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A 72 #define AD7768_REG24_ADC_DATA 0x2C 73 #define AD7768_REG_MASTER_STATUS 0x2D 74 #define AD7768_REG_SPI_DIAG_STATUS 0x2E 75 #define AD7768_REG_ADC_DIAG_STATUS 0x2F 76 #define AD7768_REG_DIG_DIAG_STATUS 0x30 77 #define AD7768_REG_MCLK_COUNTER 0x31 78 #define AD7768_REG_COEFF_CONTROL 0x32 79 #define AD7768_REG24_COEFF_DATA 0x33 80 #define AD7768_REG_ACCESS_KEY 0x34 81 82 /* AD7768_REG_POWER_CLOCK */ 83 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) 84 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) 85 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) 86 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 87 88 /* AD7768_REG_DIGITAL_FILTER */ 89 #define AD7768_DIG_FIL_EN_60HZ_REJ BIT(7) 90 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 91 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 92 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) 93 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) 94 95 /* AD7768_REG_CONVERSION */ 96 #define AD7768_CONV_MODE_MSK GENMASK(2, 0) 97 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 98 99 /* AD7768_REG_ANALOG2 */ 100 #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) 101 #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (x)) 102 103 /* AD7768_REG_GPIO_CONTROL */ 104 #define AD7768_GPIO_UNIVERSAL_EN BIT(7) 105 #define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) 106 107 /* AD7768_REG_GPIO_WRITE */ 108 #define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) 109 110 /* AD7768_REG_GPIO_READ */ 111 #define AD7768_GPIO_READ_MSK GENMASK(3, 0) 112 113 #define AD7768_VCM_OFF 0x07 114 115 #define ADAQ776X_GAIN_MAX_NANO (128 * NANO) 116 #define ADAQ776X_MAX_GAIN_MODES 8 117 118 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 119 120 #define AD7768_MAX_CHANNELS 1 121 122 #define ADAQ7768_PGA_PINS 3 123 124 enum ad7768_conv_mode { 125 AD7768_CONTINUOUS, 126 AD7768_ONE_SHOT, 127 AD7768_SINGLE, 128 AD7768_PERIODIC, 129 AD7768_STANDBY 130 }; 131 132 enum ad7768_pwrmode { 133 AD7768_ECO_MODE = 0, 134 AD7768_MED_MODE = 2, 135 AD7768_FAST_MODE = 3 136 }; 137 138 enum ad7768_mclk_div { 139 AD7768_MCLK_DIV_16, 140 AD7768_MCLK_DIV_8, 141 AD7768_MCLK_DIV_4, 142 AD7768_MCLK_DIV_2 143 }; 144 145 enum ad7768_filter_type { 146 AD7768_FILTER_SINC5, 147 AD7768_FILTER_SINC3, 148 AD7768_FILTER_WIDEBAND, 149 AD7768_FILTER_SINC3_REJ60, 150 }; 151 152 enum ad7768_filter_regval { 153 AD7768_FILTER_REGVAL_SINC5 = 0, 154 AD7768_FILTER_REGVAL_SINC5_X8 = 1, 155 AD7768_FILTER_REGVAL_SINC5_X16 = 2, 156 AD7768_FILTER_REGVAL_SINC3 = 3, 157 AD7768_FILTER_REGVAL_WIDEBAND = 4, 158 AD7768_FILTER_REGVAL_SINC3_REJ60 = 11, 159 }; 160 161 enum ad7768_scan_type { 162 AD7768_SCAN_TYPE_NORMAL, 163 AD7768_SCAN_TYPE_HIGH_SPEED, 164 }; 165 166 enum { 167 AD7768_PGA_GAIN_0, 168 AD7768_PGA_GAIN_1, 169 AD7768_PGA_GAIN_2, 170 AD7768_PGA_GAIN_3, 171 AD7768_PGA_GAIN_4, 172 AD7768_PGA_GAIN_5, 173 AD7768_PGA_GAIN_6, 174 AD7768_PGA_GAIN_7, 175 }; 176 177 enum { 178 AD7768_AAF_IN1, 179 AD7768_AAF_IN2, 180 AD7768_AAF_IN3, 181 }; 182 183 /* PGA and AAF gains in V/V */ 184 static const int adaq7768_gains[] = { 185 [AD7768_PGA_GAIN_0] = 325, /* 0.325 */ 186 [AD7768_PGA_GAIN_1] = 650, /* 0.650 */ 187 [AD7768_PGA_GAIN_2] = 1300, /* 1.300 */ 188 [AD7768_PGA_GAIN_3] = 2600, /* 2.600 */ 189 [AD7768_PGA_GAIN_4] = 5200, /* 5.200 */ 190 [AD7768_PGA_GAIN_5] = 10400, /* 10.400 */ 191 [AD7768_PGA_GAIN_6] = 20800, /* 20.800 */ 192 }; 193 194 static const int adaq7769_gains[] = { 195 [AD7768_PGA_GAIN_0] = 1000, /* 1.000 */ 196 [AD7768_PGA_GAIN_1] = 2000, /* 2.000 */ 197 [AD7768_PGA_GAIN_2] = 4000, /* 4.000 */ 198 [AD7768_PGA_GAIN_3] = 8000, /* 8.000 */ 199 [AD7768_PGA_GAIN_4] = 16000, /* 16.000 */ 200 [AD7768_PGA_GAIN_5] = 32000, /* 32.000 */ 201 [AD7768_PGA_GAIN_6] = 64000, /* 64.000 */ 202 [AD7768_PGA_GAIN_7] = 128000, /* 128.000 */ 203 }; 204 205 static const int ad7768_aaf_gains_bp[] = { 206 [AD7768_AAF_IN1] = 10000, /* 1.000 */ 207 [AD7768_AAF_IN2] = 3640, /* 0.364 */ 208 [AD7768_AAF_IN3] = 1430, /* 0.143 */ 209 }; 210 211 /* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */ 212 static const int ad7768_filter_3db_odr_multiplier[] = { 213 [AD7768_FILTER_SINC5] = 204, /* 0.204 */ 214 [AD7768_FILTER_SINC3] = 262, /* 0.2617 */ 215 [AD7768_FILTER_SINC3_REJ60] = 262, /* 0.2617 */ 216 [AD7768_FILTER_WIDEBAND] = 433, /* 0.433 */ 217 }; 218 219 static const int ad7768_mclk_div_rates[] = { 220 16, 8, 4, 2, 221 }; 222 223 static const int ad7768_dec_rate_values[8] = { 224 8, 16, 32, 64, 128, 256, 512, 1024, 225 }; 226 227 /* Decimation rate range for sinc3 filter */ 228 static const int ad7768_sinc3_dec_rate_range[3] = { 229 32, 32, 163840, 230 }; 231 232 /* 233 * The AD7768-1 supports three primary filter types: 234 * Sinc5, Sinc3, and Wideband. 235 * However, the filter register values can also encode additional parameters 236 * such as decimation rates and 60Hz rejection. This utility array separates 237 * the filter type from these parameters. 238 */ 239 static const int ad7768_filter_regval_to_type[] = { 240 [AD7768_FILTER_REGVAL_SINC5] = AD7768_FILTER_SINC5, 241 [AD7768_FILTER_REGVAL_SINC5_X8] = AD7768_FILTER_SINC5, 242 [AD7768_FILTER_REGVAL_SINC5_X16] = AD7768_FILTER_SINC5, 243 [AD7768_FILTER_REGVAL_SINC3] = AD7768_FILTER_SINC3, 244 [AD7768_FILTER_REGVAL_WIDEBAND] = AD7768_FILTER_WIDEBAND, 245 [AD7768_FILTER_REGVAL_SINC3_REJ60] = AD7768_FILTER_SINC3_REJ60, 246 }; 247 248 static const char * const ad7768_filter_enum[] = { 249 [AD7768_FILTER_SINC5] = "sinc5", 250 [AD7768_FILTER_SINC3] = "sinc3", 251 [AD7768_FILTER_WIDEBAND] = "wideband", 252 [AD7768_FILTER_SINC3_REJ60] = "sinc3+rej60", 253 }; 254 255 static const struct iio_scan_type ad7768_scan_type[] = { 256 [AD7768_SCAN_TYPE_NORMAL] = { 257 .sign = 's', 258 .realbits = 24, 259 .storagebits = 32, 260 .shift = 8, 261 .endianness = IIO_BE, 262 }, 263 [AD7768_SCAN_TYPE_HIGH_SPEED] = { 264 .sign = 's', 265 .realbits = 16, 266 .storagebits = 16, 267 .endianness = IIO_BE, 268 }, 269 }; 270 271 struct ad7768_chip_info { 272 const char *name; 273 const struct iio_chan_spec *channel_spec; 274 int num_channels; 275 const int *pga_gains; 276 int num_pga_modes; 277 int default_pga_mode; 278 int pgia_mode2pin_offset; 279 bool has_pga; 280 bool has_variable_aaf; 281 bool has_vcm_regulator; 282 }; 283 284 struct ad7768_state { 285 struct spi_device *spi; 286 struct regmap *regmap; 287 struct regmap *regmap24; 288 int vref_uv; 289 struct regulator_dev *vcm_rdev; 290 unsigned int vcm_output_sel; 291 struct clk *mclk; 292 unsigned int mclk_freq; 293 unsigned int mclk_div; 294 unsigned int oversampling_ratio; 295 enum ad7768_filter_type filter_type; 296 unsigned int samp_freq; 297 unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; 298 unsigned int samp_freq_avail_len; 299 unsigned int pga_gain_mode; 300 unsigned int aaf_gain; 301 int scale_tbl[ADAQ776X_MAX_GAIN_MODES][2]; 302 struct completion completion; 303 struct iio_trigger *trig; 304 struct gpio_descs *pga_gpios; 305 struct gpio_desc *gpio_sync_in; 306 struct gpio_desc *gpio_reset; 307 const char *labels[AD7768_MAX_CHANNELS]; 308 struct gpio_chip gpiochip; 309 const struct ad7768_chip_info *chip; 310 bool en_spi_sync; 311 struct mutex pga_lock; /* protect device internal state (PGA) */ 312 /* 313 * DMA (thus cache coherency maintenance) may require the 314 * transfer buffers to live in their own cache lines. 315 */ 316 union { 317 struct { 318 __be32 chan; 319 aligned_s64 timestamp; 320 } scan; 321 __be32 d32; 322 u8 d8[2]; 323 } data __aligned(IIO_DMA_MINALIGN); 324 }; 325 326 static const struct regmap_range ad7768_regmap_rd_ranges[] = { 327 regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE), 328 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 329 regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H), 330 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO), 331 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 332 regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL), 333 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 334 }; 335 336 static const struct regmap_access_table ad7768_regmap_rd_table = { 337 .yes_ranges = ad7768_regmap_rd_ranges, 338 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges), 339 }; 340 341 static const struct regmap_range ad7768_regmap_wr_ranges[] = { 342 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 343 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE), 344 regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO), 345 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 346 regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS), 347 regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL), 348 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 349 }; 350 351 static const struct regmap_access_table ad7768_regmap_wr_table = { 352 .yes_ranges = ad7768_regmap_wr_ranges, 353 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges), 354 }; 355 356 static const struct regmap_config ad7768_regmap_config = { 357 .name = "ad7768-1-8", 358 .reg_bits = 8, 359 .val_bits = 8, 360 .read_flag_mask = BIT(6), 361 .rd_table = &ad7768_regmap_rd_table, 362 .wr_table = &ad7768_regmap_wr_table, 363 .max_register = AD7768_REG_ACCESS_KEY, 364 .use_single_write = true, 365 .use_single_read = true, 366 }; 367 368 static const struct regmap_range ad7768_regmap24_rd_ranges[] = { 369 regmap_reg_range(AD7768_REG24_ADC_DATA, AD7768_REG24_ADC_DATA), 370 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 371 }; 372 373 static const struct regmap_access_table ad7768_regmap24_rd_table = { 374 .yes_ranges = ad7768_regmap24_rd_ranges, 375 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_rd_ranges), 376 }; 377 378 static const struct regmap_range ad7768_regmap24_wr_ranges[] = { 379 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 380 }; 381 382 static const struct regmap_access_table ad7768_regmap24_wr_table = { 383 .yes_ranges = ad7768_regmap24_wr_ranges, 384 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_wr_ranges), 385 }; 386 387 static const struct regmap_config ad7768_regmap24_config = { 388 .name = "ad7768-1-24", 389 .reg_bits = 8, 390 .val_bits = 24, 391 .read_flag_mask = BIT(6), 392 .rd_table = &ad7768_regmap24_rd_table, 393 .wr_table = &ad7768_regmap24_wr_table, 394 .max_register = AD7768_REG24_COEFF_DATA, 395 }; 396 397 static int ad7768_send_sync_pulse(struct ad7768_state *st) 398 { 399 if (st->en_spi_sync) 400 return regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x00); 401 402 /* 403 * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, 404 * where Tmclk is the MCLK period. The supported MCLK frequencies range 405 * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse 406 * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). 407 * 408 * Add a delay to ensure the pulse width is always sufficient to 409 * trigger synchronization. 410 */ 411 gpiod_set_value_cansleep(st->gpio_sync_in, 1); 412 fsleep(3); 413 gpiod_set_value_cansleep(st->gpio_sync_in, 0); 414 415 return 0; 416 } 417 418 static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) 419 { 420 unsigned int i, samp_freq_avail, freq_filtered; 421 unsigned int len = 0; 422 423 freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio); 424 for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { 425 samp_freq_avail = DIV_ROUND_CLOSEST(freq_filtered, ad7768_mclk_div_rates[i]); 426 /* Sampling frequency cannot be lower than the minimum of 50 SPS */ 427 if (samp_freq_avail < 50) 428 continue; 429 430 st->samp_freq_avail[len++] = samp_freq_avail; 431 } 432 433 st->samp_freq_avail_len = len; 434 } 435 436 static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div) 437 { 438 unsigned int mclk_div_value; 439 440 mclk_div_value = AD7768_PWR_MCLK_DIV(mclk_div); 441 /* 442 * Set power mode based on mclk_div value. 443 * ECO_MODE is only recommended for MCLK_DIV = 16. 444 */ 445 mclk_div_value |= mclk_div > AD7768_MCLK_DIV_16 ? 446 AD7768_PWR_PWRMODE(AD7768_FAST_MODE) : 447 AD7768_PWR_PWRMODE(AD7768_ECO_MODE); 448 449 return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK, 450 AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK, 451 mclk_div_value); 452 } 453 454 static int ad7768_set_mode(struct ad7768_state *st, 455 enum ad7768_conv_mode mode) 456 { 457 return regmap_update_bits(st->regmap, AD7768_REG_CONVERSION, 458 AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode)); 459 } 460 461 static int ad7768_scan_direct(struct iio_dev *indio_dev) 462 { 463 struct ad7768_state *st = iio_priv(indio_dev); 464 int readval, ret; 465 466 reinit_completion(&st->completion); 467 468 ret = ad7768_set_mode(st, AD7768_ONE_SHOT); 469 if (ret < 0) 470 return ret; 471 472 ret = wait_for_completion_timeout(&st->completion, 473 msecs_to_jiffies(1000)); 474 if (!ret) 475 return -ETIMEDOUT; 476 477 ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval); 478 if (ret) 479 return ret; 480 481 /* 482 * When the decimation rate is set to x8, the ADC data precision is 483 * reduced from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA 484 * register provides 24-bit data, the precision is reduced by 485 * right-shifting the read value by 8 bits. 486 */ 487 if (st->oversampling_ratio == 8) 488 readval >>= 8; 489 490 /* 491 * Any SPI configuration of the AD7768-1 can only be 492 * performed in continuous conversion mode. 493 */ 494 ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 495 if (ret < 0) 496 return ret; 497 498 return readval; 499 } 500 501 static int ad7768_reg_access(struct iio_dev *indio_dev, 502 unsigned int reg, 503 unsigned int writeval, 504 unsigned int *readval) 505 { 506 struct ad7768_state *st = iio_priv(indio_dev); 507 int ret; 508 509 if (!iio_device_claim_direct(indio_dev)) 510 return -EBUSY; 511 512 ret = -EINVAL; 513 if (readval) { 514 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_rd_table)) 515 ret = regmap_read(st->regmap, reg, readval); 516 517 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_rd_table)) 518 ret = regmap_read(st->regmap24, reg, readval); 519 520 } else { 521 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_wr_table)) 522 ret = regmap_write(st->regmap, reg, writeval); 523 524 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_wr_table)) 525 ret = regmap_write(st->regmap24, reg, writeval); 526 527 } 528 529 iio_device_release_direct(indio_dev); 530 531 return ret; 532 } 533 534 static void ad7768_fill_scale_tbl(struct iio_dev *dev) 535 { 536 struct ad7768_state *st = iio_priv(dev); 537 const struct iio_scan_type *scan_type; 538 int val, val2, tmp0, tmp1, i; 539 struct u32_fract fract; 540 unsigned long n, d; 541 u64 tmp2; 542 543 scan_type = iio_get_current_scan_type(dev, &dev->channels[0]); 544 if (scan_type->sign == 's') 545 val2 = scan_type->realbits - 1; 546 else 547 val2 = scan_type->realbits; 548 549 for (i = 0; i < st->chip->num_pga_modes; i++) { 550 /* Convert gain to a fraction format */ 551 fract.numerator = st->chip->pga_gains[i]; 552 fract.denominator = MILLI; 553 if (st->chip->has_variable_aaf) { 554 fract.numerator *= ad7768_aaf_gains_bp[st->aaf_gain]; 555 fract.denominator *= PERMYRIAD; 556 } 557 558 rational_best_approximation(fract.numerator, fract.denominator, 559 INT_MAX, INT_MAX, &n, &d); 560 561 val = mult_frac(st->vref_uv, d, n); 562 /* Would multiply by NANO here, but value is already in milli */ 563 tmp2 = ((u64)val * MICRO) >> val2; 564 tmp0 = div_u64_rem(tmp2, NANO, &tmp1); 565 st->scale_tbl[i][0] = tmp0; /* Integer part */ 566 st->scale_tbl[i][1] = abs(tmp1); /* Fractional part */ 567 } 568 } 569 570 static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, 571 unsigned int dec_rate) 572 { 573 unsigned int max_dec_rate; 574 u8 dec_rate_reg[2]; 575 u16 regval; 576 int ret; 577 578 /* 579 * Maximum dec_rate is limited by the MCLK_DIV value and by the ODR. 580 * The edge case is for MCLK_DIV = 2, ODR = 50 SPS. 581 * max_dec_rate <= MCLK / (2 * 50) 582 */ 583 max_dec_rate = st->mclk_freq / 100; 584 dec_rate = clamp(dec_rate, 32, max_dec_rate); 585 /* 586 * Calculate the equivalent value to sinc3 decimation ratio 587 * to be written on the SINC3_DEC_RATE register: 588 * Value = (DEC_RATE / 32) - 1 589 */ 590 dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1; 591 592 /* 593 * The SINC3_DEC_RATE value is a 13-bit value split across two 594 * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using 595 * FIELD_PREP() and store it with the right endianness in dec_rate_reg. 596 */ 597 regval = FIELD_PREP(GENMASK(12, 0), dec_rate); 598 put_unaligned_be16(regval, dec_rate_reg); 599 ret = regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, 600 dec_rate_reg, 2); 601 if (ret) 602 return ret; 603 604 st->oversampling_ratio = (dec_rate + 1) * 32; 605 606 return 0; 607 } 608 609 static int ad7768_configure_dig_fil(struct iio_dev *dev, 610 enum ad7768_filter_type filter_type, 611 unsigned int dec_rate) 612 { 613 struct ad7768_state *st = iio_priv(dev); 614 unsigned int dec_rate_idx, dig_filter_regval; 615 int ret; 616 617 switch (filter_type) { 618 case AD7768_FILTER_SINC3: 619 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3); 620 break; 621 case AD7768_FILTER_SINC3_REJ60: 622 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3) | 623 AD7768_DIG_FIL_EN_60HZ_REJ; 624 break; 625 case AD7768_FILTER_WIDEBAND: 626 /* Skip decimations 8 and 16, not supported by the wideband filter */ 627 dec_rate_idx = find_closest(dec_rate, &ad7768_dec_rate_values[2], 628 ARRAY_SIZE(ad7768_dec_rate_values) - 2); 629 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) | 630 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx); 631 /* Correct the index offset */ 632 dec_rate_idx += 2; 633 break; 634 case AD7768_FILTER_SINC5: 635 dec_rate_idx = find_closest(dec_rate, ad7768_dec_rate_values, 636 ARRAY_SIZE(ad7768_dec_rate_values)); 637 638 /* 639 * Decimations 8 (idx 0) and 16 (idx 1) are set in the 640 * FILTER[6:4] field. The other decimations are set in the 641 * DEC_RATE[2:0] field, and the idx needs to be offsetted by two. 642 */ 643 if (dec_rate_idx == 0) 644 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8); 645 else if (dec_rate_idx == 1) 646 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16); 647 else 648 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) | 649 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2); 650 break; 651 } 652 653 ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_regval); 654 if (ret) 655 return ret; 656 657 st->filter_type = filter_type; 658 /* 659 * The decimation for SINC3 filters are configured in different 660 * registers. 661 */ 662 if (filter_type == AD7768_FILTER_SINC3 || 663 filter_type == AD7768_FILTER_SINC3_REJ60) { 664 ret = ad7768_set_sinc3_dec_rate(st, dec_rate); 665 if (ret) 666 return ret; 667 } else { 668 st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx]; 669 } 670 671 /* Update scale table: scale values vary according to the precision */ 672 ad7768_fill_scale_tbl(dev); 673 674 ad7768_fill_samp_freq_tbl(st); 675 676 /* A sync-in pulse is required after every configuration change */ 677 return ad7768_send_sync_pulse(st); 678 } 679 680 static int ad7768_setup_pga(struct device *dev, struct ad7768_state *st) 681 { 682 st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); 683 if (IS_ERR(st->pga_gpios)) 684 return dev_err_probe(dev, PTR_ERR(st->pga_gpios), 685 "Failed to get PGA gpios.\n"); 686 687 if (st->pga_gpios->ndescs != ADAQ7768_PGA_PINS) 688 return dev_err_probe(dev, -EINVAL, 689 "Expected %d GPIOs for PGA control.\n", 690 ADAQ7768_PGA_PINS); 691 return 0; 692 } 693 694 static int ad7768_calc_pga_gain(struct ad7768_state *st, int gain_int, 695 int gain_fract, int precision) 696 { 697 u64 gain_nano; 698 u32 tmp; 699 700 gain_nano = gain_int * NANO + gain_fract; 701 gain_nano = clamp(gain_nano, 0, ADAQ776X_GAIN_MAX_NANO); 702 tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << precision, NANO); 703 gain_nano = DIV_ROUND_CLOSEST(st->vref_uv, tmp); 704 if (st->chip->has_variable_aaf) 705 gain_nano = DIV_ROUND_CLOSEST_ULL(gain_nano * PERMYRIAD, 706 ad7768_aaf_gains_bp[st->aaf_gain]); 707 708 return find_closest(gain_nano, st->chip->pga_gains, 709 (int)st->chip->num_pga_modes); 710 } 711 712 static int ad7768_set_pga_gain(struct ad7768_state *st, 713 int gain_mode) 714 { 715 int pgia_pins_value = abs(gain_mode - st->chip->pgia_mode2pin_offset); 716 DECLARE_BITMAP(bitmap, ADAQ7768_PGA_PINS) = { }; 717 int ret; 718 719 guard(mutex)(&st->pga_lock); 720 721 bitmap_write(bitmap, pgia_pins_value, 0, ADAQ7768_PGA_PINS); 722 ret = gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); 723 if (ret) 724 return ret; 725 726 st->pga_gain_mode = gain_mode; 727 728 return 0; 729 } 730 731 static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 732 { 733 struct iio_dev *indio_dev = gpiochip_get_data(chip); 734 struct ad7768_state *st = iio_priv(indio_dev); 735 int ret; 736 737 if (!iio_device_claim_direct(indio_dev)) 738 return -EBUSY; 739 740 ret = regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 741 BIT(offset)); 742 iio_device_release_direct(indio_dev); 743 744 return ret; 745 } 746 747 static int ad7768_gpio_direction_output(struct gpio_chip *chip, 748 unsigned int offset, int value) 749 { 750 struct iio_dev *indio_dev = gpiochip_get_data(chip); 751 struct ad7768_state *st = iio_priv(indio_dev); 752 int ret; 753 754 if (!iio_device_claim_direct(indio_dev)) 755 return -EBUSY; 756 757 ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 758 BIT(offset)); 759 iio_device_release_direct(indio_dev); 760 761 return ret; 762 } 763 764 static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) 765 { 766 struct iio_dev *indio_dev = gpiochip_get_data(chip); 767 struct ad7768_state *st = iio_priv(indio_dev); 768 unsigned int val; 769 int ret; 770 771 if (!iio_device_claim_direct(indio_dev)) 772 return -EBUSY; 773 774 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 775 if (ret) 776 goto err_release; 777 778 /* 779 * If the GPIO is configured as an output, read the current value from 780 * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from 781 * AD7768_REG_GPIO_READ. 782 */ 783 if (val & BIT(offset)) 784 ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); 785 else 786 ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); 787 if (ret) 788 goto err_release; 789 790 ret = !!(val & BIT(offset)); 791 err_release: 792 iio_device_release_direct(indio_dev); 793 794 return ret; 795 } 796 797 static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 798 { 799 struct iio_dev *indio_dev = gpiochip_get_data(chip); 800 struct ad7768_state *st = iio_priv(indio_dev); 801 unsigned int val; 802 int ret; 803 804 if (!iio_device_claim_direct(indio_dev)) 805 return -EBUSY; 806 807 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 808 if (ret) 809 goto err_release; 810 811 if (val & BIT(offset)) 812 ret = regmap_assign_bits(st->regmap, AD7768_REG_GPIO_WRITE, 813 BIT(offset), value); 814 815 err_release: 816 iio_device_release_direct(indio_dev); 817 818 return ret; 819 } 820 821 static int ad7768_gpio_init(struct iio_dev *indio_dev) 822 { 823 struct ad7768_state *st = iio_priv(indio_dev); 824 int ret; 825 826 ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, 827 AD7768_GPIO_UNIVERSAL_EN); 828 if (ret) 829 return ret; 830 831 st->gpiochip = (struct gpio_chip) { 832 .label = "ad7768_1_gpios", 833 .base = -1, 834 .ngpio = 4, 835 .parent = &st->spi->dev, 836 .can_sleep = true, 837 .direction_input = ad7768_gpio_direction_input, 838 .direction_output = ad7768_gpio_direction_output, 839 .get = ad7768_gpio_get, 840 .set = ad7768_gpio_set, 841 .owner = THIS_MODULE, 842 }; 843 844 return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); 845 } 846 847 static int ad7768_set_freq(struct ad7768_state *st, 848 unsigned int freq) 849 { 850 unsigned int idx, mclk_div; 851 int ret; 852 853 freq = clamp(freq, 50, 1024000); 854 855 mclk_div = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); 856 /* Find the closest match for the desired sampling frequency */ 857 idx = find_closest_descending(mclk_div, ad7768_mclk_div_rates, 858 ARRAY_SIZE(ad7768_mclk_div_rates)); 859 /* Set both the mclk_div and pwrmode */ 860 ret = ad7768_set_mclk_div(st, idx); 861 if (ret) 862 return ret; 863 864 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 865 ad7768_mclk_div_rates[idx] * st->oversampling_ratio); 866 867 /* A sync-in pulse is required after every configuration change */ 868 return ad7768_send_sync_pulse(st); 869 } 870 871 static int ad7768_set_filter_type_attr(struct iio_dev *dev, 872 const struct iio_chan_spec *chan, 873 unsigned int filter) 874 { 875 struct ad7768_state *st = iio_priv(dev); 876 int ret; 877 878 ret = ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); 879 if (ret) 880 return ret; 881 882 /* Update sampling frequency */ 883 return ad7768_set_freq(st, st->samp_freq); 884 } 885 886 static int ad7768_get_filter_type_attr(struct iio_dev *dev, 887 const struct iio_chan_spec *chan) 888 { 889 struct ad7768_state *st = iio_priv(dev); 890 int ret; 891 unsigned int mode, mask; 892 893 ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); 894 if (ret) 895 return ret; 896 897 mask = AD7768_DIG_FIL_EN_60HZ_REJ | AD7768_DIG_FIL_FIL_MSK; 898 /* From the register value, get the corresponding filter type */ 899 return ad7768_filter_regval_to_type[FIELD_GET(mask, mode)]; 900 } 901 902 static int ad7768_update_dec_rate(struct iio_dev *dev, unsigned int dec_rate) 903 { 904 struct ad7768_state *st = iio_priv(dev); 905 int ret; 906 907 ret = ad7768_configure_dig_fil(dev, st->filter_type, dec_rate); 908 if (ret) 909 return ret; 910 911 /* Update sampling frequency */ 912 return ad7768_set_freq(st, st->samp_freq); 913 } 914 915 static const struct iio_enum ad7768_filter_type_iio_enum = { 916 .items = ad7768_filter_enum, 917 .num_items = ARRAY_SIZE(ad7768_filter_enum), 918 .set = ad7768_set_filter_type_attr, 919 .get = ad7768_get_filter_type_attr, 920 }; 921 922 static const struct iio_chan_spec_ext_info ad7768_ext_info[] = { 923 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 924 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 925 { } 926 }; 927 928 #define AD7768_CHAN(_idx, _msk_avail) \ 929 { \ 930 .type = IIO_VOLTAGE, \ 931 .info_mask_separate_available = _msk_avail, \ 932 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 933 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 934 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 935 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 936 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 937 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 938 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 939 .ext_info = ad7768_ext_info, \ 940 .indexed = 1, \ 941 .channel = _idx, \ 942 .scan_index = _idx, \ 943 .has_ext_scan_type = 1, \ 944 .ext_scan_type = ad7768_scan_type, \ 945 .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), \ 946 } 947 948 static const struct iio_chan_spec ad7768_channels[] = { 949 AD7768_CHAN(0, 0), 950 }; 951 952 static const struct iio_chan_spec adaq776x_channels[] = { 953 AD7768_CHAN(0, BIT(IIO_CHAN_INFO_SCALE)), 954 }; 955 956 static int ad7768_read_raw(struct iio_dev *indio_dev, 957 struct iio_chan_spec const *chan, 958 int *val, int *val2, long info) 959 { 960 struct ad7768_state *st = iio_priv(indio_dev); 961 const struct iio_scan_type *scan_type; 962 int ret, temp; 963 964 scan_type = iio_get_current_scan_type(indio_dev, chan); 965 if (IS_ERR(scan_type)) 966 return PTR_ERR(scan_type); 967 968 switch (info) { 969 case IIO_CHAN_INFO_RAW: 970 if (!iio_device_claim_direct(indio_dev)) 971 return -EBUSY; 972 973 ret = ad7768_scan_direct(indio_dev); 974 975 iio_device_release_direct(indio_dev); 976 if (ret < 0) 977 return ret; 978 *val = sign_extend32(ret, scan_type->realbits - 1); 979 980 return IIO_VAL_INT; 981 982 case IIO_CHAN_INFO_SCALE: 983 if (st->chip->has_pga) { 984 guard(mutex)(&st->pga_lock); 985 986 *val = st->scale_tbl[st->pga_gain_mode][0]; 987 *val2 = st->scale_tbl[st->pga_gain_mode][1]; 988 return IIO_VAL_INT_PLUS_NANO; 989 } 990 991 temp = (st->vref_uv * 2) / 1000; 992 if (st->chip->has_variable_aaf) 993 temp = (temp * PERMYRIAD) / ad7768_aaf_gains_bp[st->aaf_gain]; 994 995 *val = temp; 996 *val2 = scan_type->realbits; 997 998 return IIO_VAL_FRACTIONAL_LOG2; 999 1000 case IIO_CHAN_INFO_SAMP_FREQ: 1001 *val = st->samp_freq; 1002 1003 return IIO_VAL_INT; 1004 1005 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1006 *val = st->oversampling_ratio; 1007 1008 return IIO_VAL_INT; 1009 1010 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1011 temp = st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_type]; 1012 *val = DIV_ROUND_CLOSEST(temp, MILLI); 1013 1014 return IIO_VAL_INT; 1015 } 1016 1017 return -EINVAL; 1018 } 1019 1020 static int ad7768_read_avail(struct iio_dev *indio_dev, 1021 struct iio_chan_spec const *chan, 1022 const int **vals, int *type, int *length, 1023 long info) 1024 { 1025 struct ad7768_state *st = iio_priv(indio_dev); 1026 unsigned int shift; 1027 1028 switch (info) { 1029 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1030 /* 1031 * Sinc3 filter allows a wider range of OSR values, so show 1032 * the available values in range format. 1033 */ 1034 if (st->filter_type == AD7768_FILTER_SINC3 || 1035 st->filter_type == AD7768_FILTER_SINC3_REJ60) { 1036 *vals = (int *)ad7768_sinc3_dec_rate_range; 1037 *type = IIO_VAL_INT; 1038 return IIO_AVAIL_RANGE; 1039 } 1040 1041 shift = st->filter_type == AD7768_FILTER_SINC5 ? 0 : 2; 1042 *vals = (int *)&ad7768_dec_rate_values[shift]; 1043 *length = ARRAY_SIZE(ad7768_dec_rate_values) - shift; 1044 *type = IIO_VAL_INT; 1045 return IIO_AVAIL_LIST; 1046 case IIO_CHAN_INFO_SAMP_FREQ: 1047 *vals = (int *)st->samp_freq_avail; 1048 *length = st->samp_freq_avail_len; 1049 *type = IIO_VAL_INT; 1050 return IIO_AVAIL_LIST; 1051 case IIO_CHAN_INFO_SCALE: 1052 *vals = (int *)st->scale_tbl; 1053 *length = st->chip->num_pga_modes * 2; 1054 *type = IIO_VAL_INT_PLUS_NANO; 1055 return IIO_AVAIL_LIST; 1056 default: 1057 return -EINVAL; 1058 } 1059 } 1060 1061 static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, 1062 struct iio_chan_spec const *chan, long mask) 1063 { 1064 switch (mask) { 1065 case IIO_CHAN_INFO_SCALE: 1066 return IIO_VAL_INT_PLUS_NANO; 1067 default: 1068 return IIO_VAL_INT_PLUS_MICRO; 1069 } 1070 } 1071 1072 static int ad7768_write_raw(struct iio_dev *indio_dev, 1073 struct iio_chan_spec const *chan, 1074 int val, int val2, long info) 1075 { 1076 struct ad7768_state *st = iio_priv(indio_dev); 1077 const struct iio_scan_type *scan_type; 1078 int ret; 1079 1080 scan_type = iio_get_current_scan_type(indio_dev, chan); 1081 if (IS_ERR(scan_type)) 1082 return PTR_ERR(scan_type); 1083 1084 switch (info) { 1085 case IIO_CHAN_INFO_SAMP_FREQ: 1086 if (!iio_device_claim_direct(indio_dev)) 1087 return -EBUSY; 1088 1089 ret = ad7768_set_freq(st, val); 1090 iio_device_release_direct(indio_dev); 1091 return ret; 1092 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1093 if (!iio_device_claim_direct(indio_dev)) 1094 return -EBUSY; 1095 1096 ret = ad7768_update_dec_rate(indio_dev, val); 1097 iio_device_release_direct(indio_dev); 1098 return ret; 1099 case IIO_CHAN_INFO_SCALE: { 1100 int gain_mode; 1101 1102 if (!st->chip->has_pga) 1103 return -EOPNOTSUPP; 1104 1105 if (scan_type->sign == 's') 1106 gain_mode = ad7768_calc_pga_gain(st, val, val2, 1107 scan_type->realbits - 1); 1108 else 1109 gain_mode = ad7768_calc_pga_gain(st, val, val2, 1110 scan_type->realbits); 1111 1112 return ad7768_set_pga_gain(st, gain_mode); 1113 } 1114 default: 1115 return -EINVAL; 1116 } 1117 } 1118 1119 static int ad7768_read_label(struct iio_dev *indio_dev, 1120 const struct iio_chan_spec *chan, char *label) 1121 { 1122 struct ad7768_state *st = iio_priv(indio_dev); 1123 1124 return sysfs_emit(label, "%s\n", st->labels[chan->channel]); 1125 } 1126 1127 static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, 1128 const struct iio_chan_spec *chan) 1129 { 1130 struct ad7768_state *st = iio_priv(indio_dev); 1131 1132 return st->oversampling_ratio == 8 ? 1133 AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; 1134 } 1135 1136 static const struct iio_info ad7768_info = { 1137 .read_raw = &ad7768_read_raw, 1138 .read_avail = &ad7768_read_avail, 1139 .write_raw = &ad7768_write_raw, 1140 .write_raw_get_fmt = &ad7768_write_raw_get_fmt, 1141 .read_label = ad7768_read_label, 1142 .get_current_scan_type = &ad7768_get_current_scan_type, 1143 .debugfs_reg_access = &ad7768_reg_access, 1144 }; 1145 1146 static struct fwnode_handle * 1147 ad7768_fwnode_find_reference_args(const struct fwnode_handle *fwnode, 1148 const char *name, const char *nargs_prop, 1149 unsigned int nargs, unsigned int index, 1150 struct fwnode_reference_args *args) 1151 { 1152 int ret; 1153 1154 ret = fwnode_property_get_reference_args(fwnode, name, nargs_prop, 1155 nargs, index, args); 1156 return ret ? ERR_PTR(ret) : args->fwnode; 1157 } 1158 1159 static int ad7768_trigger_sources_sync_setup(struct device *dev, 1160 struct fwnode_handle *fwnode, 1161 struct ad7768_state *st) 1162 { 1163 struct fwnode_reference_args args; 1164 1165 struct fwnode_handle *ref __free(fwnode_handle) = 1166 ad7768_fwnode_find_reference_args(fwnode, "trigger-sources", 1167 "#trigger-source-cells", 0, 1168 AD7768_TRIGGER_SOURCE_SYNC_IDX, 1169 &args); 1170 if (IS_ERR(ref)) 1171 return PTR_ERR(ref); 1172 1173 ref = args.fwnode; 1174 /* First, try getting the GPIO trigger source */ 1175 if (fwnode_device_is_compatible(ref, "gpio-trigger")) { 1176 st->gpio_sync_in = devm_fwnode_gpiod_get_index(dev, ref, NULL, 0, 1177 GPIOD_OUT_LOW, 1178 "sync-in"); 1179 return PTR_ERR_OR_ZERO(st->gpio_sync_in); 1180 } 1181 1182 /* 1183 * TODO: Support the other cases when we have a trigger subsystem 1184 * to reliably handle other types of devices as trigger sources. 1185 * 1186 * For now, return an error message. For self triggering, omit the 1187 * trigger-sources property. 1188 */ 1189 return dev_err_probe(dev, -EOPNOTSUPP, "Invalid synchronization trigger source\n"); 1190 } 1191 1192 static int ad7768_trigger_sources_get_sync(struct device *dev, 1193 struct ad7768_state *st) 1194 { 1195 struct fwnode_handle *fwnode = dev_fwnode(dev); 1196 1197 /* 1198 * The AD7768-1 allows two primary methods for driving the SYNC_IN pin 1199 * to synchronize one or more devices: 1200 * 1. Using an external GPIO. 1201 * 2. Using a SPI command, where the SYNC_OUT pin generates a 1202 * synchronization pulse that drives the SYNC_IN pin. 1203 */ 1204 if (fwnode_property_present(fwnode, "trigger-sources")) 1205 return ad7768_trigger_sources_sync_setup(dev, fwnode, st); 1206 1207 /* 1208 * In the absence of trigger-sources property, enable self 1209 * synchronization over SPI (SYNC_OUT). 1210 */ 1211 st->en_spi_sync = true; 1212 1213 return 0; 1214 } 1215 1216 static int ad7768_setup(struct iio_dev *indio_dev) 1217 { 1218 struct ad7768_state *st = iio_priv(indio_dev); 1219 int ret; 1220 1221 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", 1222 GPIOD_OUT_HIGH); 1223 if (IS_ERR(st->gpio_reset)) 1224 return PTR_ERR(st->gpio_reset); 1225 1226 if (st->gpio_reset) { 1227 fsleep(10); 1228 gpiod_set_value_cansleep(st->gpio_reset, 0); 1229 fsleep(200); 1230 } else { 1231 /* 1232 * Two writes to the SPI_RESET[1:0] bits are required to initiate 1233 * a software reset. The bits must first be set to 11, and then 1234 * to 10. When the sequence is detected, the reset occurs. 1235 * See the datasheet, page 70. 1236 */ 1237 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3); 1238 if (ret) 1239 return ret; 1240 1241 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2); 1242 if (ret) 1243 return ret; 1244 } 1245 1246 /* For backwards compatibility, try the adi,sync-in-gpios property */ 1247 st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", 1248 GPIOD_OUT_LOW); 1249 if (IS_ERR(st->gpio_sync_in)) 1250 return PTR_ERR(st->gpio_sync_in); 1251 1252 /* 1253 * If the synchronization is not defined by adi,sync-in-gpios, try the 1254 * trigger-sources. 1255 */ 1256 if (!st->gpio_sync_in) { 1257 ret = ad7768_trigger_sources_get_sync(&st->spi->dev, st); 1258 if (ret) 1259 return ret; 1260 } 1261 1262 /* Only create a Chip GPIO if flagged for it */ 1263 if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { 1264 ret = ad7768_gpio_init(indio_dev); 1265 if (ret) 1266 return ret; 1267 } 1268 1269 /* 1270 * Set Default Digital Filter configuration: 1271 * SINC5 filter with x32 Decimation rate 1272 */ 1273 ret = ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32); 1274 if (ret) 1275 return ret; 1276 1277 /* Set the default sampling frequency to 32000 kSPS */ 1278 return ad7768_set_freq(st, 32000); 1279 } 1280 1281 static irqreturn_t ad7768_trigger_handler(int irq, void *p) 1282 { 1283 struct iio_poll_func *pf = p; 1284 struct iio_dev *indio_dev = pf->indio_dev; 1285 struct ad7768_state *st = iio_priv(indio_dev); 1286 const struct iio_scan_type *scan_type; 1287 int ret; 1288 1289 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1290 if (IS_ERR(scan_type)) 1291 goto out; 1292 1293 ret = spi_read(st->spi, &st->data.scan.chan, 1294 BITS_TO_BYTES(scan_type->realbits)); 1295 if (ret < 0) 1296 goto out; 1297 1298 iio_push_to_buffers_with_ts(indio_dev, &st->data.scan, 1299 sizeof(st->data.scan), 1300 iio_get_time_ns(indio_dev)); 1301 1302 out: 1303 iio_trigger_notify_done(indio_dev->trig); 1304 1305 return IRQ_HANDLED; 1306 } 1307 1308 static irqreturn_t ad7768_interrupt(int irq, void *dev_id) 1309 { 1310 struct iio_dev *indio_dev = dev_id; 1311 struct ad7768_state *st = iio_priv(indio_dev); 1312 1313 if (iio_buffer_enabled(indio_dev)) 1314 iio_trigger_poll(st->trig); 1315 else 1316 complete(&st->completion); 1317 1318 return IRQ_HANDLED; 1319 }; 1320 1321 static int ad7768_buffer_postenable(struct iio_dev *indio_dev) 1322 { 1323 struct ad7768_state *st = iio_priv(indio_dev); 1324 1325 /* 1326 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 1327 * continuous read mode. Subsequent data reads do not require an 1328 * initial 8-bit write to query the ADC_DATA register. 1329 */ 1330 return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01); 1331 } 1332 1333 static int ad7768_buffer_predisable(struct iio_dev *indio_dev) 1334 { 1335 struct ad7768_state *st = iio_priv(indio_dev); 1336 unsigned int unused; 1337 1338 /* 1339 * To exit continuous read mode, perform a single read of the ADC_DATA 1340 * reg (0x2C), which allows further configuration of the device. 1341 */ 1342 return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1343 } 1344 1345 static const struct iio_buffer_setup_ops ad7768_buffer_ops = { 1346 .postenable = &ad7768_buffer_postenable, 1347 .predisable = &ad7768_buffer_predisable, 1348 }; 1349 1350 static const struct iio_trigger_ops ad7768_trigger_ops = { 1351 .validate_device = iio_trigger_validate_own_device, 1352 }; 1353 1354 static int ad7768_set_channel_label(struct iio_dev *indio_dev, 1355 int num_channels) 1356 { 1357 struct ad7768_state *st = iio_priv(indio_dev); 1358 struct device *device = indio_dev->dev.parent; 1359 const char *label; 1360 int crt_ch = 0; 1361 1362 device_for_each_child_node_scoped(device, child) { 1363 if (fwnode_property_read_u32(child, "reg", &crt_ch)) 1364 continue; 1365 1366 if (crt_ch >= num_channels) 1367 continue; 1368 1369 if (fwnode_property_read_string(child, "label", &label)) 1370 continue; 1371 1372 st->labels[crt_ch] = label; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev) 1379 { 1380 struct ad7768_state *st = iio_priv(indio_dev); 1381 int ret; 1382 1383 st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", 1384 indio_dev->name, 1385 iio_device_id(indio_dev)); 1386 if (!st->trig) 1387 return -ENOMEM; 1388 1389 st->trig->ops = &ad7768_trigger_ops; 1390 iio_trigger_set_drvdata(st->trig, indio_dev); 1391 ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig); 1392 if (ret) 1393 return ret; 1394 1395 indio_dev->trig = iio_trigger_get(st->trig); 1396 1397 return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, 1398 &iio_pollfunc_store_time, 1399 &ad7768_trigger_handler, 1400 &ad7768_buffer_ops); 1401 } 1402 1403 static int ad7768_vcm_enable(struct regulator_dev *rdev) 1404 { 1405 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1406 struct ad7768_state *st = iio_priv(indio_dev); 1407 int ret, regval; 1408 1409 if (!iio_device_claim_direct(indio_dev)) 1410 return -EBUSY; 1411 1412 /* To enable, set the last selected output */ 1413 regval = AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1); 1414 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1415 AD7768_REG_ANALOG2_VCM_MSK, regval); 1416 iio_device_release_direct(indio_dev); 1417 1418 return ret; 1419 } 1420 1421 static int ad7768_vcm_disable(struct regulator_dev *rdev) 1422 { 1423 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1424 struct ad7768_state *st = iio_priv(indio_dev); 1425 int ret; 1426 1427 if (!iio_device_claim_direct(indio_dev)) 1428 return -EBUSY; 1429 1430 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1431 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1432 iio_device_release_direct(indio_dev); 1433 1434 return ret; 1435 } 1436 1437 static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) 1438 { 1439 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1440 struct ad7768_state *st = iio_priv(indio_dev); 1441 int ret, val; 1442 1443 if (!iio_device_claim_direct(indio_dev)) 1444 return -EBUSY; 1445 1446 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1447 iio_device_release_direct(indio_dev); 1448 if (ret) 1449 return ret; 1450 1451 return FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val) != AD7768_VCM_OFF; 1452 } 1453 1454 static int ad7768_set_voltage_sel(struct regulator_dev *rdev, 1455 unsigned int selector) 1456 { 1457 unsigned int regval = AD7768_REG_ANALOG2_VCM(selector + 1); 1458 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1459 struct ad7768_state *st = iio_priv(indio_dev); 1460 int ret; 1461 1462 if (!iio_device_claim_direct(indio_dev)) 1463 return -EBUSY; 1464 1465 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1466 AD7768_REG_ANALOG2_VCM_MSK, regval); 1467 iio_device_release_direct(indio_dev); 1468 if (ret) 1469 return ret; 1470 1471 st->vcm_output_sel = selector; 1472 1473 return 0; 1474 } 1475 1476 static int ad7768_get_voltage_sel(struct regulator_dev *rdev) 1477 { 1478 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1479 struct ad7768_state *st = iio_priv(indio_dev); 1480 int ret, val; 1481 1482 if (!iio_device_claim_direct(indio_dev)) 1483 return -EBUSY; 1484 1485 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1486 iio_device_release_direct(indio_dev); 1487 if (ret) 1488 return ret; 1489 1490 val = FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val); 1491 1492 return clamp(val, 1, rdev->desc->n_voltages) - 1; 1493 } 1494 1495 static const struct regulator_ops vcm_regulator_ops = { 1496 .enable = ad7768_vcm_enable, 1497 .disable = ad7768_vcm_disable, 1498 .is_enabled = ad7768_vcm_is_enabled, 1499 .list_voltage = regulator_list_voltage_table, 1500 .set_voltage_sel = ad7768_set_voltage_sel, 1501 .get_voltage_sel = ad7768_get_voltage_sel, 1502 }; 1503 1504 static const unsigned int vcm_voltage_table[] = { 1505 2500000, 1506 2050000, 1507 1650000, 1508 1900000, 1509 1100000, 1510 900000, 1511 }; 1512 1513 static const struct regulator_desc vcm_desc = { 1514 .name = "ad7768-1-vcm", 1515 .of_match = "vcm-output", 1516 .regulators_node = "regulators", 1517 .n_voltages = ARRAY_SIZE(vcm_voltage_table), 1518 .volt_table = vcm_voltage_table, 1519 .ops = &vcm_regulator_ops, 1520 .type = REGULATOR_VOLTAGE, 1521 .owner = THIS_MODULE, 1522 }; 1523 1524 static int ad7768_register_vcm_regulator(struct device *dev, 1525 struct ad7768_state *st, 1526 struct iio_dev *indio_dev) 1527 { 1528 struct regulator_config config = { 1529 .dev = dev, 1530 .driver_data = indio_dev, 1531 }; 1532 int ret; 1533 1534 /* Disable the regulator before registering it */ 1535 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1536 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1537 if (ret) 1538 return ret; 1539 1540 st->vcm_rdev = devm_regulator_register(dev, &vcm_desc, &config); 1541 if (IS_ERR(st->vcm_rdev)) 1542 return dev_err_probe(dev, PTR_ERR(st->vcm_rdev), 1543 "failed to register VCM regulator\n"); 1544 1545 return 0; 1546 } 1547 1548 static int ad7768_parse_aaf_gain(struct device *dev, struct ad7768_state *st) 1549 { 1550 u32 val; 1551 int ret; 1552 1553 ret = device_property_read_u32(dev, "adi,aaf-gain-bp", &val); 1554 if (ret == -EINVAL) { 1555 /* If controllable, use default */ 1556 if (st->chip->has_variable_aaf) 1557 st->aaf_gain = AD7768_AAF_IN1; 1558 return 0; 1559 } 1560 if (ret) 1561 return dev_err_probe(dev, ret, "Failed to get AAF gain value\n"); 1562 1563 if (!st->chip->has_variable_aaf) 1564 return dev_err_probe(dev, -EOPNOTSUPP, 1565 "AAF gain provided, but not supported for %s\n", st->chip->name); 1566 1567 switch (val) { 1568 case 10000: 1569 st->aaf_gain = AD7768_AAF_IN1; 1570 break; 1571 case 3640: 1572 st->aaf_gain = AD7768_AAF_IN2; 1573 break; 1574 case 1430: 1575 st->aaf_gain = AD7768_AAF_IN3; 1576 break; 1577 default: 1578 return dev_err_probe(dev, -EINVAL, "Invalid firmware provided AAF gain\n"); 1579 } 1580 1581 return 0; 1582 } 1583 1584 static const struct ad7768_chip_info ad7768_chip_info = { 1585 .name = "ad7768-1", 1586 .channel_spec = ad7768_channels, 1587 .num_channels = ARRAY_SIZE(ad7768_channels), 1588 .has_vcm_regulator = true, 1589 }; 1590 1591 static const struct ad7768_chip_info adaq7767_chip_info = { 1592 .name = "adaq7767-1", 1593 .channel_spec = ad7768_channels, 1594 .num_channels = ARRAY_SIZE(ad7768_channels), 1595 .has_variable_aaf = true, 1596 }; 1597 1598 static const struct ad7768_chip_info adaq7768_chip_info = { 1599 .name = "adaq7768-1", 1600 .channel_spec = adaq776x_channels, 1601 .num_channels = ARRAY_SIZE(adaq776x_channels), 1602 .pga_gains = adaq7768_gains, 1603 .default_pga_mode = AD7768_PGA_GAIN_2, 1604 .num_pga_modes = ARRAY_SIZE(adaq7768_gains), 1605 .pgia_mode2pin_offset = 6, 1606 .has_pga = true, 1607 }; 1608 1609 static const struct ad7768_chip_info adaq7769_chip_info = { 1610 .name = "adaq7769-1", 1611 .channel_spec = adaq776x_channels, 1612 .num_channels = ARRAY_SIZE(adaq776x_channels), 1613 .pga_gains = adaq7769_gains, 1614 .default_pga_mode = AD7768_PGA_GAIN_0, 1615 .num_pga_modes = ARRAY_SIZE(adaq7769_gains), 1616 .pgia_mode2pin_offset = 0, 1617 .has_pga = true, 1618 .has_variable_aaf = true, 1619 }; 1620 1621 static int ad7768_probe(struct spi_device *spi) 1622 { 1623 struct ad7768_state *st; 1624 struct iio_dev *indio_dev; 1625 int ret; 1626 1627 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1628 if (!indio_dev) 1629 return -ENOMEM; 1630 1631 st = iio_priv(indio_dev); 1632 /* 1633 * Datasheet recommends SDI line to be kept high when data is not being 1634 * clocked out of the controller and the spi clock is free running, 1635 * to prevent accidental reset. 1636 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag 1637 * yet, only request the MOSI idle state to enable if the controller 1638 * supports it. 1639 */ 1640 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) { 1641 spi->mode |= SPI_MOSI_IDLE_HIGH; 1642 ret = spi_setup(spi); 1643 if (ret < 0) 1644 return ret; 1645 } 1646 1647 st->chip = spi_get_device_match_data(spi); 1648 st->spi = spi; 1649 1650 st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config); 1651 if (IS_ERR(st->regmap)) 1652 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), 1653 "Failed to initialize regmap"); 1654 1655 st->regmap24 = devm_regmap_init_spi(spi, &ad7768_regmap24_config); 1656 if (IS_ERR(st->regmap24)) 1657 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap24), 1658 "Failed to initialize regmap24"); 1659 1660 ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); 1661 if (ret < 0) 1662 return dev_err_probe(&spi->dev, ret, 1663 "Failed to get VREF voltage\n"); 1664 st->vref_uv = ret; 1665 1666 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 1667 if (IS_ERR(st->mclk)) 1668 return PTR_ERR(st->mclk); 1669 1670 st->mclk_freq = clk_get_rate(st->mclk); 1671 1672 indio_dev->channels = st->chip->channel_spec; 1673 indio_dev->num_channels = st->chip->num_channels; 1674 indio_dev->name = st->chip->name; 1675 indio_dev->info = &ad7768_info; 1676 indio_dev->modes = INDIO_DIRECT_MODE; 1677 1678 /* Register VCM output regulator */ 1679 if (st->chip->has_vcm_regulator) { 1680 ret = ad7768_register_vcm_regulator(&spi->dev, st, indio_dev); 1681 if (ret) 1682 return ret; 1683 } 1684 1685 ret = ad7768_parse_aaf_gain(&spi->dev, st); 1686 if (ret) 1687 return ret; 1688 1689 ret = ad7768_setup(indio_dev); 1690 if (ret < 0) { 1691 dev_err(&spi->dev, "AD7768 setup failed\n"); 1692 return ret; 1693 } 1694 1695 init_completion(&st->completion); 1696 ret = devm_mutex_init(&spi->dev, &st->pga_lock); 1697 if (ret) 1698 return ret; 1699 1700 if (st->chip->has_pga) { 1701 ret = ad7768_setup_pga(&spi->dev, st); 1702 if (ret) 1703 return ret; 1704 1705 ret = ad7768_set_pga_gain(st, st->chip->default_pga_mode); 1706 if (ret) 1707 return ret; 1708 } 1709 1710 ret = ad7768_set_channel_label(indio_dev, st->chip->num_channels); 1711 if (ret) 1712 return ret; 1713 1714 ret = devm_request_irq(&spi->dev, spi->irq, &ad7768_interrupt, 1715 IRQF_TRIGGER_RISING | IRQF_NO_THREAD, 1716 indio_dev->name, indio_dev); 1717 if (ret) 1718 return ret; 1719 1720 ret = ad7768_triggered_buffer_alloc(indio_dev); 1721 if (ret) 1722 return ret; 1723 1724 return devm_iio_device_register(&spi->dev, indio_dev); 1725 } 1726 1727 static const struct spi_device_id ad7768_id_table[] = { 1728 { "ad7768-1", (kernel_ulong_t)&ad7768_chip_info }, 1729 { "adaq7767-1", (kernel_ulong_t)&adaq7767_chip_info }, 1730 { "adaq7768-1", (kernel_ulong_t)&adaq7768_chip_info }, 1731 { "adaq7769-1", (kernel_ulong_t)&adaq7769_chip_info }, 1732 { } 1733 }; 1734 MODULE_DEVICE_TABLE(spi, ad7768_id_table); 1735 1736 static const struct of_device_id ad7768_of_match[] = { 1737 { .compatible = "adi,ad7768-1", .data = &ad7768_chip_info }, 1738 { .compatible = "adi,adaq7767-1", .data = &adaq7767_chip_info }, 1739 { .compatible = "adi,adaq7768-1", .data = &adaq7768_chip_info }, 1740 { .compatible = "adi,adaq7769-1", .data = &adaq7769_chip_info }, 1741 { } 1742 }; 1743 MODULE_DEVICE_TABLE(of, ad7768_of_match); 1744 1745 static struct spi_driver ad7768_driver = { 1746 .driver = { 1747 .name = "ad7768-1", 1748 .of_match_table = ad7768_of_match, 1749 }, 1750 .probe = ad7768_probe, 1751 .id_table = ad7768_id_table, 1752 }; 1753 module_spi_driver(ad7768_driver); 1754 1755 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1756 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 1757 MODULE_LICENSE("GPL v2"); 1758