1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7768-1 SPI ADC driver 4 * 5 * Copyright 2017 Analog Devices Inc. 6 */ 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/interrupt.h> 18 #include <linux/limits.h> 19 #include <linux/math.h> 20 #include <linux/minmax.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/rational.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/sysfs.h> 28 #include <linux/spi/offload/consumer.h> 29 #include <linux/spi/offload/provider.h> 30 #include <linux/spi/spi.h> 31 #include <linux/unaligned.h> 32 #include <linux/units.h> 33 #include <linux/util_macros.h> 34 35 #include <linux/iio/buffer.h> 36 #include <linux/iio/buffer-dmaengine.h> 37 #include <linux/iio/iio.h> 38 #include <linux/iio/sysfs.h> 39 #include <linux/iio/trigger.h> 40 #include <linux/iio/triggered_buffer.h> 41 #include <linux/iio/trigger_consumer.h> 42 43 #include <dt-bindings/iio/adc/adi,ad7768-1.h> 44 45 /* AD7768 registers definition */ 46 #define AD7768_REG_CHIP_TYPE 0x3 47 #define AD7768_REG_PROD_ID_L 0x4 48 #define AD7768_REG_PROD_ID_H 0x5 49 #define AD7768_REG_CHIP_GRADE 0x6 50 #define AD7768_REG_SCRATCH_PAD 0x0A 51 #define AD7768_REG_VENDOR_L 0x0C 52 #define AD7768_REG_VENDOR_H 0x0D 53 #define AD7768_REG_INTERFACE_FORMAT 0x14 54 #define AD7768_REG_POWER_CLOCK 0x15 55 #define AD7768_REG_ANALOG 0x16 56 #define AD7768_REG_ANALOG2 0x17 57 #define AD7768_REG_CONVERSION 0x18 58 #define AD7768_REG_DIGITAL_FILTER 0x19 59 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A 60 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B 61 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C 62 #define AD7768_REG_SYNC_RESET 0x1D 63 #define AD7768_REG_GPIO_CONTROL 0x1E 64 #define AD7768_REG_GPIO_WRITE 0x1F 65 #define AD7768_REG_GPIO_READ 0x20 66 #define AD7768_REG_OFFSET_HI 0x21 67 #define AD7768_REG_OFFSET_MID 0x22 68 #define AD7768_REG_OFFSET_LO 0x23 69 #define AD7768_REG_GAIN_HI 0x24 70 #define AD7768_REG_GAIN_MID 0x25 71 #define AD7768_REG_GAIN_LO 0x26 72 #define AD7768_REG_SPI_DIAG_ENABLE 0x28 73 #define AD7768_REG_ADC_DIAG_ENABLE 0x29 74 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A 75 #define AD7768_REG24_ADC_DATA 0x2C 76 #define AD7768_REG_MASTER_STATUS 0x2D 77 #define AD7768_REG_SPI_DIAG_STATUS 0x2E 78 #define AD7768_REG_ADC_DIAG_STATUS 0x2F 79 #define AD7768_REG_DIG_DIAG_STATUS 0x30 80 #define AD7768_REG_MCLK_COUNTER 0x31 81 #define AD7768_REG_COEFF_CONTROL 0x32 82 #define AD7768_REG24_COEFF_DATA 0x33 83 #define AD7768_REG_ACCESS_KEY 0x34 84 85 /* AD7768_REG_POWER_CLOCK */ 86 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) 87 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) 88 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) 89 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 90 91 /* AD7768_REG_DIGITAL_FILTER */ 92 #define AD7768_DIG_FIL_EN_60HZ_REJ BIT(7) 93 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 94 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 95 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) 96 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) 97 98 /* AD7768_REG_CONVERSION */ 99 #define AD7768_CONV_MODE_MSK GENMASK(2, 0) 100 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 101 102 /* AD7768_REG_ANALOG2 */ 103 #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) 104 #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (x)) 105 106 /* AD7768_REG_GPIO_CONTROL */ 107 #define AD7768_GPIO_UNIVERSAL_EN BIT(7) 108 #define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) 109 110 /* AD7768_REG_GPIO_WRITE */ 111 #define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) 112 113 /* AD7768_REG_GPIO_READ */ 114 #define AD7768_GPIO_READ_MSK GENMASK(3, 0) 115 116 #define AD7768_VCM_OFF 0x07 117 118 #define ADAQ776X_GAIN_MAX_NANO (128 * NANO) 119 #define ADAQ776X_MAX_GAIN_MODES 8 120 121 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 122 123 #define AD7768_MAX_CHANNELS 1 124 125 #define ADAQ7768_PGA_PINS 3 126 127 enum ad7768_conv_mode { 128 AD7768_CONTINUOUS, 129 AD7768_ONE_SHOT, 130 AD7768_SINGLE, 131 AD7768_PERIODIC, 132 AD7768_STANDBY 133 }; 134 135 enum ad7768_pwrmode { 136 AD7768_ECO_MODE = 0, 137 AD7768_MED_MODE = 2, 138 AD7768_FAST_MODE = 3 139 }; 140 141 enum ad7768_mclk_div { 142 AD7768_MCLK_DIV_16, 143 AD7768_MCLK_DIV_8, 144 AD7768_MCLK_DIV_4, 145 AD7768_MCLK_DIV_2 146 }; 147 148 enum ad7768_filter_type { 149 AD7768_FILTER_SINC5, 150 AD7768_FILTER_SINC3, 151 AD7768_FILTER_WIDEBAND, 152 AD7768_FILTER_SINC3_REJ60, 153 }; 154 155 enum ad7768_filter_regval { 156 AD7768_FILTER_REGVAL_SINC5 = 0, 157 AD7768_FILTER_REGVAL_SINC5_X8 = 1, 158 AD7768_FILTER_REGVAL_SINC5_X16 = 2, 159 AD7768_FILTER_REGVAL_SINC3 = 3, 160 AD7768_FILTER_REGVAL_WIDEBAND = 4, 161 AD7768_FILTER_REGVAL_SINC3_REJ60 = 11, 162 }; 163 164 enum ad7768_scan_type { 165 AD7768_SCAN_TYPE_NORMAL, 166 AD7768_SCAN_TYPE_HIGH_SPEED, 167 AD7768_SCAN_TYPE_OFFLOAD_NORMAL, 168 AD7768_SCAN_TYPE_OFFLOAD_HIGH_SPEED, 169 }; 170 171 enum { 172 AD7768_PGA_GAIN_0, 173 AD7768_PGA_GAIN_1, 174 AD7768_PGA_GAIN_2, 175 AD7768_PGA_GAIN_3, 176 AD7768_PGA_GAIN_4, 177 AD7768_PGA_GAIN_5, 178 AD7768_PGA_GAIN_6, 179 AD7768_PGA_GAIN_7, 180 }; 181 182 enum { 183 AD7768_AAF_IN1, 184 AD7768_AAF_IN2, 185 AD7768_AAF_IN3, 186 }; 187 188 /* PGA and AAF gains in V/V */ 189 static const int adaq7768_gains[] = { 190 [AD7768_PGA_GAIN_0] = 325, /* 0.325 */ 191 [AD7768_PGA_GAIN_1] = 650, /* 0.650 */ 192 [AD7768_PGA_GAIN_2] = 1300, /* 1.300 */ 193 [AD7768_PGA_GAIN_3] = 2600, /* 2.600 */ 194 [AD7768_PGA_GAIN_4] = 5200, /* 5.200 */ 195 [AD7768_PGA_GAIN_5] = 10400, /* 10.400 */ 196 [AD7768_PGA_GAIN_6] = 20800, /* 20.800 */ 197 }; 198 199 static const int adaq7769_gains[] = { 200 [AD7768_PGA_GAIN_0] = 1000, /* 1.000 */ 201 [AD7768_PGA_GAIN_1] = 2000, /* 2.000 */ 202 [AD7768_PGA_GAIN_2] = 4000, /* 4.000 */ 203 [AD7768_PGA_GAIN_3] = 8000, /* 8.000 */ 204 [AD7768_PGA_GAIN_4] = 16000, /* 16.000 */ 205 [AD7768_PGA_GAIN_5] = 32000, /* 32.000 */ 206 [AD7768_PGA_GAIN_6] = 64000, /* 64.000 */ 207 [AD7768_PGA_GAIN_7] = 128000, /* 128.000 */ 208 }; 209 210 static const int ad7768_aaf_gains_bp[] = { 211 [AD7768_AAF_IN1] = 10000, /* 1.000 */ 212 [AD7768_AAF_IN2] = 3640, /* 0.364 */ 213 [AD7768_AAF_IN3] = 1430, /* 0.143 */ 214 }; 215 216 /* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */ 217 static const int ad7768_filter_3db_odr_multiplier[] = { 218 [AD7768_FILTER_SINC5] = 204, /* 0.204 */ 219 [AD7768_FILTER_SINC3] = 262, /* 0.2617 */ 220 [AD7768_FILTER_SINC3_REJ60] = 262, /* 0.2617 */ 221 [AD7768_FILTER_WIDEBAND] = 433, /* 0.433 */ 222 }; 223 224 static const int ad7768_mclk_div_rates[] = { 225 16, 8, 4, 2, 226 }; 227 228 static const int ad7768_dec_rate_values[8] = { 229 8, 16, 32, 64, 128, 256, 512, 1024, 230 }; 231 232 /* Decimation rate range for sinc3 filter */ 233 static const int ad7768_sinc3_dec_rate_range[3] = { 234 32, 32, 163840, 235 }; 236 237 /* 238 * The AD7768-1 supports three primary filter types: 239 * Sinc5, Sinc3, and Wideband. 240 * However, the filter register values can also encode additional parameters 241 * such as decimation rates and 60Hz rejection. This utility array separates 242 * the filter type from these parameters. 243 */ 244 static const int ad7768_filter_regval_to_type[] = { 245 [AD7768_FILTER_REGVAL_SINC5] = AD7768_FILTER_SINC5, 246 [AD7768_FILTER_REGVAL_SINC5_X8] = AD7768_FILTER_SINC5, 247 [AD7768_FILTER_REGVAL_SINC5_X16] = AD7768_FILTER_SINC5, 248 [AD7768_FILTER_REGVAL_SINC3] = AD7768_FILTER_SINC3, 249 [AD7768_FILTER_REGVAL_WIDEBAND] = AD7768_FILTER_WIDEBAND, 250 [AD7768_FILTER_REGVAL_SINC3_REJ60] = AD7768_FILTER_SINC3_REJ60, 251 }; 252 253 static const char * const ad7768_filter_enum[] = { 254 [AD7768_FILTER_SINC5] = "sinc5", 255 [AD7768_FILTER_SINC3] = "sinc3", 256 [AD7768_FILTER_WIDEBAND] = "wideband", 257 [AD7768_FILTER_SINC3_REJ60] = "sinc3+rej60", 258 }; 259 260 static const struct iio_scan_type ad7768_scan_type[] = { 261 [AD7768_SCAN_TYPE_NORMAL] = { 262 .sign = 's', 263 .realbits = 24, 264 .storagebits = 32, 265 .shift = 8, 266 .endianness = IIO_BE, 267 }, 268 [AD7768_SCAN_TYPE_HIGH_SPEED] = { 269 .sign = 's', 270 .realbits = 16, 271 .storagebits = 16, 272 .endianness = IIO_BE, 273 }, 274 [AD7768_SCAN_TYPE_OFFLOAD_NORMAL] = { 275 .sign = 's', 276 .realbits = 24, 277 .storagebits = 32, 278 .endianness = IIO_CPU, 279 }, 280 [AD7768_SCAN_TYPE_OFFLOAD_HIGH_SPEED] = { 281 .sign = 's', 282 .realbits = 16, 283 .storagebits = 32, 284 .endianness = IIO_CPU, 285 }, 286 }; 287 288 struct ad7768_chip_info { 289 const char *name; 290 const struct iio_chan_spec *channel_spec; 291 int num_channels; 292 const int *pga_gains; 293 int num_pga_modes; 294 int default_pga_mode; 295 int pgia_mode2pin_offset; 296 bool has_pga; 297 bool has_variable_aaf; 298 bool has_vcm_regulator; 299 }; 300 301 struct ad7768_state { 302 struct spi_device *spi; 303 struct spi_offload *offload; 304 struct spi_offload_trigger *offload_trigger; 305 struct regmap *regmap; 306 struct regmap *regmap24; 307 int vref_uv; 308 struct regulator_dev *vcm_rdev; 309 unsigned int vcm_output_sel; 310 struct clk *mclk; 311 unsigned int mclk_freq; 312 unsigned int oversampling_ratio; 313 enum ad7768_filter_type filter_type; 314 unsigned int samp_freq; 315 unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; 316 unsigned int samp_freq_avail_len; 317 unsigned int pga_gain_mode; 318 unsigned int aaf_gain; 319 int scale_tbl[ADAQ776X_MAX_GAIN_MODES][2]; 320 struct completion completion; 321 struct iio_trigger *trig; 322 struct gpio_descs *pga_gpios; 323 struct gpio_desc *gpio_sync_in; 324 struct gpio_desc *gpio_reset; 325 const char *labels[AD7768_MAX_CHANNELS]; 326 struct gpio_chip gpiochip; 327 struct spi_transfer offload_xfer; 328 struct spi_message offload_msg; 329 const struct ad7768_chip_info *chip; 330 bool en_spi_sync; 331 struct mutex pga_lock; /* protect device internal state (PGA) */ 332 /* 333 * DMA (thus cache coherency maintenance) may require the 334 * transfer buffers to live in their own cache lines. 335 */ 336 union { 337 struct { 338 __be32 chan; 339 aligned_s64 timestamp; 340 } scan; 341 __be32 d32; 342 u8 d8[2]; 343 } data __aligned(IIO_DMA_MINALIGN); 344 }; 345 346 static const struct regmap_range ad7768_regmap_rd_ranges[] = { 347 regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE), 348 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 349 regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H), 350 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO), 351 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 352 regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL), 353 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 354 }; 355 356 static const struct regmap_access_table ad7768_regmap_rd_table = { 357 .yes_ranges = ad7768_regmap_rd_ranges, 358 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges), 359 }; 360 361 static const struct regmap_range ad7768_regmap_wr_ranges[] = { 362 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 363 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE), 364 regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO), 365 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 366 regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS), 367 regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL), 368 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 369 }; 370 371 static const struct regmap_access_table ad7768_regmap_wr_table = { 372 .yes_ranges = ad7768_regmap_wr_ranges, 373 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges), 374 }; 375 376 static const struct regmap_config ad7768_regmap_config = { 377 .name = "ad7768-1-8", 378 .reg_bits = 8, 379 .val_bits = 8, 380 .read_flag_mask = BIT(6), 381 .rd_table = &ad7768_regmap_rd_table, 382 .wr_table = &ad7768_regmap_wr_table, 383 .max_register = AD7768_REG_ACCESS_KEY, 384 .use_single_write = true, 385 .use_single_read = true, 386 }; 387 388 static const struct regmap_range ad7768_regmap24_rd_ranges[] = { 389 regmap_reg_range(AD7768_REG24_ADC_DATA, AD7768_REG24_ADC_DATA), 390 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 391 }; 392 393 static const struct regmap_access_table ad7768_regmap24_rd_table = { 394 .yes_ranges = ad7768_regmap24_rd_ranges, 395 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_rd_ranges), 396 }; 397 398 static const struct regmap_range ad7768_regmap24_wr_ranges[] = { 399 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 400 }; 401 402 static const struct regmap_access_table ad7768_regmap24_wr_table = { 403 .yes_ranges = ad7768_regmap24_wr_ranges, 404 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_wr_ranges), 405 }; 406 407 static const struct regmap_config ad7768_regmap24_config = { 408 .name = "ad7768-1-24", 409 .reg_bits = 8, 410 .val_bits = 24, 411 .read_flag_mask = BIT(6), 412 .rd_table = &ad7768_regmap24_rd_table, 413 .wr_table = &ad7768_regmap24_wr_table, 414 .max_register = AD7768_REG24_COEFF_DATA, 415 }; 416 417 static int ad7768_send_sync_pulse(struct ad7768_state *st) 418 { 419 if (st->en_spi_sync) 420 return regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x00); 421 422 /* 423 * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, 424 * where Tmclk is the MCLK period. The supported MCLK frequencies range 425 * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse 426 * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). 427 * 428 * Add a delay to ensure the pulse width is always sufficient to 429 * trigger synchronization. 430 */ 431 gpiod_set_value_cansleep(st->gpio_sync_in, 1); 432 fsleep(3); 433 gpiod_set_value_cansleep(st->gpio_sync_in, 0); 434 435 return 0; 436 } 437 438 static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) 439 { 440 unsigned int i, samp_freq_avail, freq_filtered; 441 unsigned int len = 0; 442 443 freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio); 444 for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { 445 samp_freq_avail = DIV_ROUND_CLOSEST(freq_filtered, ad7768_mclk_div_rates[i]); 446 /* Sampling frequency cannot be lower than the minimum of 50 SPS */ 447 if (samp_freq_avail < 50) 448 continue; 449 450 st->samp_freq_avail[len++] = samp_freq_avail; 451 } 452 453 st->samp_freq_avail_len = len; 454 } 455 456 static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div) 457 { 458 unsigned int mclk_div_value; 459 460 mclk_div_value = AD7768_PWR_MCLK_DIV(mclk_div); 461 /* 462 * Set power mode based on mclk_div value. 463 * ECO_MODE is only recommended for MCLK_DIV = 16. 464 */ 465 mclk_div_value |= mclk_div > AD7768_MCLK_DIV_16 ? 466 AD7768_PWR_PWRMODE(AD7768_FAST_MODE) : 467 AD7768_PWR_PWRMODE(AD7768_ECO_MODE); 468 469 return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK, 470 AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK, 471 mclk_div_value); 472 } 473 474 static int ad7768_set_mode(struct ad7768_state *st, 475 enum ad7768_conv_mode mode) 476 { 477 return regmap_update_bits(st->regmap, AD7768_REG_CONVERSION, 478 AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode)); 479 } 480 481 static int ad7768_scan_direct(struct iio_dev *indio_dev) 482 { 483 struct ad7768_state *st = iio_priv(indio_dev); 484 int readval, ret; 485 486 reinit_completion(&st->completion); 487 enable_irq(st->spi->irq); 488 489 ret = wait_for_completion_timeout(&st->completion, 490 msecs_to_jiffies(1000)); 491 disable_irq(st->spi->irq); 492 if (!ret) 493 return -ETIMEDOUT; 494 495 ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval); 496 if (ret) 497 return ret; 498 499 /* 500 * When the decimation rate is set to x8, the ADC data precision is 501 * reduced from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA 502 * register provides 24-bit data, the precision is reduced by 503 * right-shifting the read value by 8 bits. 504 */ 505 if (st->oversampling_ratio == 8) 506 readval >>= 8; 507 508 return readval; 509 } 510 511 static int ad7768_reg_access(struct iio_dev *indio_dev, 512 unsigned int reg, 513 unsigned int writeval, 514 unsigned int *readval) 515 { 516 struct ad7768_state *st = iio_priv(indio_dev); 517 int ret; 518 519 if (!iio_device_claim_direct(indio_dev)) 520 return -EBUSY; 521 522 ret = -EINVAL; 523 if (readval) { 524 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_rd_table)) 525 ret = regmap_read(st->regmap, reg, readval); 526 527 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_rd_table)) 528 ret = regmap_read(st->regmap24, reg, readval); 529 530 } else { 531 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_wr_table)) 532 ret = regmap_write(st->regmap, reg, writeval); 533 534 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_wr_table)) 535 ret = regmap_write(st->regmap24, reg, writeval); 536 537 } 538 539 iio_device_release_direct(indio_dev); 540 541 return ret; 542 } 543 544 static int ad7768_fill_scale_tbl(struct iio_dev *dev) 545 { 546 struct ad7768_state *st = iio_priv(dev); 547 const struct iio_scan_type *scan_type; 548 int val, val2, tmp0, tmp1, i; 549 struct u32_fract fract; 550 unsigned long n, d; 551 u64 tmp2; 552 553 scan_type = iio_get_current_scan_type(dev, &dev->channels[0]); 554 if (IS_ERR(scan_type)) { 555 dev_err(&st->spi->dev, "Failed to get scan type.\n"); 556 return PTR_ERR(scan_type); 557 } 558 559 if (scan_type->sign == 's') 560 val2 = scan_type->realbits - 1; 561 else 562 val2 = scan_type->realbits; 563 564 for (i = 0; i < st->chip->num_pga_modes; i++) { 565 /* Convert gain to a fraction format */ 566 fract.numerator = st->chip->pga_gains[i]; 567 fract.denominator = MILLI; 568 if (st->chip->has_variable_aaf) { 569 fract.numerator *= ad7768_aaf_gains_bp[st->aaf_gain]; 570 fract.denominator *= PERMYRIAD; 571 } 572 573 rational_best_approximation(fract.numerator, fract.denominator, 574 INT_MAX, INT_MAX, &n, &d); 575 576 val = mult_frac(st->vref_uv, d, n); 577 /* Would multiply by NANO here, but value is already in milli */ 578 tmp2 = ((u64)val * MICRO) >> val2; 579 tmp0 = div_u64_rem(tmp2, NANO, &tmp1); 580 st->scale_tbl[i][0] = tmp0; /* Integer part */ 581 st->scale_tbl[i][1] = abs(tmp1); /* Fractional part */ 582 } 583 584 return 0; 585 } 586 587 static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, 588 unsigned int dec_rate) 589 { 590 unsigned int max_dec_rate; 591 u8 dec_rate_reg[2]; 592 u16 regval; 593 int ret; 594 595 /* 596 * Maximum dec_rate is limited by the MCLK_DIV value and by the ODR. 597 * The edge case is for MCLK_DIV = 2, ODR = 50 SPS. 598 * max_dec_rate <= MCLK / (2 * 50) 599 */ 600 max_dec_rate = st->mclk_freq / 100; 601 dec_rate = clamp(dec_rate, 32, max_dec_rate); 602 /* 603 * Calculate the equivalent value to sinc3 decimation ratio 604 * to be written on the SINC3_DEC_RATE register: 605 * Value = (DEC_RATE / 32) - 1 606 */ 607 dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1; 608 609 /* 610 * The SINC3_DEC_RATE value is a 13-bit value split across two 611 * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using 612 * FIELD_PREP() and store it with the right endianness in dec_rate_reg. 613 */ 614 regval = FIELD_PREP(GENMASK(12, 0), dec_rate); 615 put_unaligned_be16(regval, dec_rate_reg); 616 ret = regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, 617 dec_rate_reg, 2); 618 if (ret) 619 return ret; 620 621 st->oversampling_ratio = (dec_rate + 1) * 32; 622 623 return 0; 624 } 625 626 static int ad7768_configure_dig_fil(struct iio_dev *dev, 627 enum ad7768_filter_type filter_type, 628 unsigned int dec_rate) 629 { 630 struct ad7768_state *st = iio_priv(dev); 631 unsigned int dec_rate_idx, dig_filter_regval; 632 int ret; 633 634 switch (filter_type) { 635 case AD7768_FILTER_SINC3: 636 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3); 637 break; 638 case AD7768_FILTER_SINC3_REJ60: 639 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3) | 640 AD7768_DIG_FIL_EN_60HZ_REJ; 641 break; 642 case AD7768_FILTER_WIDEBAND: 643 /* Skip decimations 8 and 16, not supported by the wideband filter */ 644 dec_rate_idx = find_closest(dec_rate, &ad7768_dec_rate_values[2], 645 ARRAY_SIZE(ad7768_dec_rate_values) - 2); 646 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) | 647 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx); 648 /* Correct the index offset */ 649 dec_rate_idx += 2; 650 break; 651 case AD7768_FILTER_SINC5: 652 dec_rate_idx = find_closest(dec_rate, ad7768_dec_rate_values, 653 ARRAY_SIZE(ad7768_dec_rate_values)); 654 655 /* 656 * Decimations 8 (idx 0) and 16 (idx 1) are set in the 657 * FILTER[6:4] field. The other decimations are set in the 658 * DEC_RATE[2:0] field, and the idx needs to be offsetted by two. 659 */ 660 if (dec_rate_idx == 0) 661 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8); 662 else if (dec_rate_idx == 1) 663 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16); 664 else 665 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) | 666 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2); 667 break; 668 } 669 670 ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_regval); 671 if (ret) 672 return ret; 673 674 st->filter_type = filter_type; 675 /* 676 * The decimation for SINC3 filters are configured in different 677 * registers. 678 */ 679 if (filter_type == AD7768_FILTER_SINC3 || 680 filter_type == AD7768_FILTER_SINC3_REJ60) { 681 ret = ad7768_set_sinc3_dec_rate(st, dec_rate); 682 if (ret) 683 return ret; 684 } else { 685 st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx]; 686 } 687 688 /* Update scale table: scale values vary according to the precision */ 689 ret = ad7768_fill_scale_tbl(dev); 690 if (ret) 691 return ret; 692 693 ad7768_fill_samp_freq_tbl(st); 694 695 /* A sync-in pulse is required after every configuration change */ 696 return ad7768_send_sync_pulse(st); 697 } 698 699 static int ad7768_setup_pga(struct device *dev, struct ad7768_state *st) 700 { 701 st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); 702 if (IS_ERR(st->pga_gpios)) 703 return dev_err_probe(dev, PTR_ERR(st->pga_gpios), 704 "Failed to get PGA gpios.\n"); 705 706 if (st->pga_gpios->ndescs != ADAQ7768_PGA_PINS) 707 return dev_err_probe(dev, -EINVAL, 708 "Expected %d GPIOs for PGA control.\n", 709 ADAQ7768_PGA_PINS); 710 return 0; 711 } 712 713 static int ad7768_calc_pga_gain(struct ad7768_state *st, int gain_int, 714 int gain_fract, int precision) 715 { 716 u64 gain_nano; 717 u32 tmp; 718 719 gain_nano = gain_int * NANO + gain_fract; 720 gain_nano = clamp(gain_nano, 0, ADAQ776X_GAIN_MAX_NANO); 721 tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << precision, NANO); 722 gain_nano = DIV_ROUND_CLOSEST(st->vref_uv, tmp); 723 if (st->chip->has_variable_aaf) 724 gain_nano = DIV_ROUND_CLOSEST_ULL(gain_nano * PERMYRIAD, 725 ad7768_aaf_gains_bp[st->aaf_gain]); 726 727 return find_closest(gain_nano, st->chip->pga_gains, 728 (int)st->chip->num_pga_modes); 729 } 730 731 static int ad7768_set_pga_gain(struct ad7768_state *st, 732 int gain_mode) 733 { 734 int pgia_pins_value = abs(gain_mode - st->chip->pgia_mode2pin_offset); 735 DECLARE_BITMAP(bitmap, ADAQ7768_PGA_PINS) = { }; 736 int ret; 737 738 guard(mutex)(&st->pga_lock); 739 740 bitmap_write(bitmap, pgia_pins_value, 0, ADAQ7768_PGA_PINS); 741 ret = gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); 742 if (ret) 743 return ret; 744 745 st->pga_gain_mode = gain_mode; 746 747 return 0; 748 } 749 750 static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 751 { 752 struct iio_dev *indio_dev = gpiochip_get_data(chip); 753 struct ad7768_state *st = iio_priv(indio_dev); 754 int ret; 755 756 if (!iio_device_claim_direct(indio_dev)) 757 return -EBUSY; 758 759 ret = regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 760 BIT(offset)); 761 iio_device_release_direct(indio_dev); 762 763 return ret; 764 } 765 766 static int ad7768_gpio_direction_output(struct gpio_chip *chip, 767 unsigned int offset, int value) 768 { 769 struct iio_dev *indio_dev = gpiochip_get_data(chip); 770 struct ad7768_state *st = iio_priv(indio_dev); 771 int ret; 772 773 if (!iio_device_claim_direct(indio_dev)) 774 return -EBUSY; 775 776 ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 777 BIT(offset)); 778 iio_device_release_direct(indio_dev); 779 780 return ret; 781 } 782 783 static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) 784 { 785 struct iio_dev *indio_dev = gpiochip_get_data(chip); 786 struct ad7768_state *st = iio_priv(indio_dev); 787 unsigned int val; 788 int ret; 789 790 if (!iio_device_claim_direct(indio_dev)) 791 return -EBUSY; 792 793 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 794 if (ret) 795 goto err_release; 796 797 /* 798 * If the GPIO is configured as an output, read the current value from 799 * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from 800 * AD7768_REG_GPIO_READ. 801 */ 802 if (val & BIT(offset)) 803 ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); 804 else 805 ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); 806 if (ret) 807 goto err_release; 808 809 ret = !!(val & BIT(offset)); 810 err_release: 811 iio_device_release_direct(indio_dev); 812 813 return ret; 814 } 815 816 static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 817 { 818 struct iio_dev *indio_dev = gpiochip_get_data(chip); 819 struct ad7768_state *st = iio_priv(indio_dev); 820 unsigned int val; 821 int ret; 822 823 if (!iio_device_claim_direct(indio_dev)) 824 return -EBUSY; 825 826 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 827 if (ret) 828 goto err_release; 829 830 if (val & BIT(offset)) 831 ret = regmap_assign_bits(st->regmap, AD7768_REG_GPIO_WRITE, 832 BIT(offset), value); 833 834 err_release: 835 iio_device_release_direct(indio_dev); 836 837 return ret; 838 } 839 840 static int ad7768_gpio_init(struct iio_dev *indio_dev) 841 { 842 struct ad7768_state *st = iio_priv(indio_dev); 843 int ret; 844 845 ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, 846 AD7768_GPIO_UNIVERSAL_EN); 847 if (ret) 848 return ret; 849 850 st->gpiochip = (struct gpio_chip) { 851 .label = "ad7768_1_gpios", 852 .base = -1, 853 .ngpio = 4, 854 .parent = &st->spi->dev, 855 .can_sleep = true, 856 .direction_input = ad7768_gpio_direction_input, 857 .direction_output = ad7768_gpio_direction_output, 858 .get = ad7768_gpio_get, 859 .set = ad7768_gpio_set, 860 .owner = THIS_MODULE, 861 }; 862 863 return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); 864 } 865 866 static int ad7768_set_freq(struct ad7768_state *st, 867 unsigned int freq) 868 { 869 unsigned int idx, mclk_div; 870 int ret; 871 872 freq = clamp(freq, 50, 1024000); 873 874 mclk_div = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); 875 /* Find the closest match for the desired sampling frequency */ 876 idx = find_closest_descending(mclk_div, ad7768_mclk_div_rates, 877 ARRAY_SIZE(ad7768_mclk_div_rates)); 878 /* Set both the mclk_div and pwrmode */ 879 ret = ad7768_set_mclk_div(st, idx); 880 if (ret) 881 return ret; 882 883 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 884 ad7768_mclk_div_rates[idx] * st->oversampling_ratio); 885 886 /* A sync-in pulse is required after every configuration change */ 887 return ad7768_send_sync_pulse(st); 888 } 889 890 static int ad7768_set_filter_type_attr(struct iio_dev *dev, 891 const struct iio_chan_spec *chan, 892 unsigned int filter) 893 { 894 struct ad7768_state *st = iio_priv(dev); 895 int ret; 896 897 ret = ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); 898 if (ret) 899 return ret; 900 901 /* Update sampling frequency */ 902 return ad7768_set_freq(st, st->samp_freq); 903 } 904 905 static int ad7768_get_filter_type_attr(struct iio_dev *dev, 906 const struct iio_chan_spec *chan) 907 { 908 struct ad7768_state *st = iio_priv(dev); 909 int ret; 910 unsigned int mode, mask; 911 912 ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); 913 if (ret) 914 return ret; 915 916 mask = AD7768_DIG_FIL_EN_60HZ_REJ | AD7768_DIG_FIL_FIL_MSK; 917 /* From the register value, get the corresponding filter type */ 918 return ad7768_filter_regval_to_type[FIELD_GET(mask, mode)]; 919 } 920 921 static int ad7768_update_dec_rate(struct iio_dev *dev, unsigned int dec_rate) 922 { 923 struct ad7768_state *st = iio_priv(dev); 924 int ret; 925 926 ret = ad7768_configure_dig_fil(dev, st->filter_type, dec_rate); 927 if (ret) 928 return ret; 929 930 /* Update sampling frequency */ 931 return ad7768_set_freq(st, st->samp_freq); 932 } 933 934 static const struct iio_enum ad7768_filter_type_iio_enum = { 935 .items = ad7768_filter_enum, 936 .num_items = ARRAY_SIZE(ad7768_filter_enum), 937 .set = ad7768_set_filter_type_attr, 938 .get = ad7768_get_filter_type_attr, 939 }; 940 941 static const struct iio_chan_spec_ext_info ad7768_ext_info[] = { 942 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 943 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 944 { } 945 }; 946 947 #define AD7768_CHAN(_idx, _msk_avail) \ 948 { \ 949 .type = IIO_VOLTAGE, \ 950 .info_mask_separate_available = _msk_avail, \ 951 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 952 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 953 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 954 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 955 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 956 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 957 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 958 .ext_info = ad7768_ext_info, \ 959 .indexed = 1, \ 960 .channel = _idx, \ 961 .scan_index = _idx, \ 962 .has_ext_scan_type = 1, \ 963 .ext_scan_type = ad7768_scan_type, \ 964 .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), \ 965 } 966 967 static const struct iio_chan_spec ad7768_channels[] = { 968 AD7768_CHAN(0, 0), 969 }; 970 971 static const struct iio_chan_spec adaq776x_channels[] = { 972 AD7768_CHAN(0, BIT(IIO_CHAN_INFO_SCALE)), 973 }; 974 975 static int ad7768_read_raw(struct iio_dev *indio_dev, 976 struct iio_chan_spec const *chan, 977 int *val, int *val2, long info) 978 { 979 struct ad7768_state *st = iio_priv(indio_dev); 980 const struct iio_scan_type *scan_type; 981 int ret, temp; 982 983 scan_type = iio_get_current_scan_type(indio_dev, chan); 984 if (IS_ERR(scan_type)) 985 return PTR_ERR(scan_type); 986 987 switch (info) { 988 case IIO_CHAN_INFO_RAW: 989 if (!iio_device_claim_direct(indio_dev)) 990 return -EBUSY; 991 992 ret = ad7768_scan_direct(indio_dev); 993 994 iio_device_release_direct(indio_dev); 995 if (ret < 0) 996 return ret; 997 *val = sign_extend32(ret, scan_type->realbits - 1); 998 999 return IIO_VAL_INT; 1000 1001 case IIO_CHAN_INFO_SCALE: 1002 if (st->chip->has_pga) { 1003 guard(mutex)(&st->pga_lock); 1004 1005 *val = st->scale_tbl[st->pga_gain_mode][0]; 1006 *val2 = st->scale_tbl[st->pga_gain_mode][1]; 1007 return IIO_VAL_INT_PLUS_NANO; 1008 } 1009 1010 temp = (st->vref_uv * 2) / 1000; 1011 if (st->chip->has_variable_aaf) 1012 temp = (temp * PERMYRIAD) / ad7768_aaf_gains_bp[st->aaf_gain]; 1013 1014 *val = temp; 1015 *val2 = scan_type->realbits; 1016 1017 return IIO_VAL_FRACTIONAL_LOG2; 1018 1019 case IIO_CHAN_INFO_SAMP_FREQ: 1020 *val = st->samp_freq; 1021 1022 return IIO_VAL_INT; 1023 1024 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1025 *val = st->oversampling_ratio; 1026 1027 return IIO_VAL_INT; 1028 1029 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1030 temp = st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_type]; 1031 *val = DIV_ROUND_CLOSEST(temp, MILLI); 1032 1033 return IIO_VAL_INT; 1034 } 1035 1036 return -EINVAL; 1037 } 1038 1039 static int ad7768_read_avail(struct iio_dev *indio_dev, 1040 struct iio_chan_spec const *chan, 1041 const int **vals, int *type, int *length, 1042 long info) 1043 { 1044 struct ad7768_state *st = iio_priv(indio_dev); 1045 unsigned int shift; 1046 1047 switch (info) { 1048 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1049 /* 1050 * Sinc3 filter allows a wider range of OSR values, so show 1051 * the available values in range format. 1052 */ 1053 if (st->filter_type == AD7768_FILTER_SINC3 || 1054 st->filter_type == AD7768_FILTER_SINC3_REJ60) { 1055 *vals = (int *)ad7768_sinc3_dec_rate_range; 1056 *type = IIO_VAL_INT; 1057 return IIO_AVAIL_RANGE; 1058 } 1059 1060 shift = st->filter_type == AD7768_FILTER_SINC5 ? 0 : 2; 1061 *vals = (int *)&ad7768_dec_rate_values[shift]; 1062 *length = ARRAY_SIZE(ad7768_dec_rate_values) - shift; 1063 *type = IIO_VAL_INT; 1064 return IIO_AVAIL_LIST; 1065 case IIO_CHAN_INFO_SAMP_FREQ: 1066 *vals = (int *)st->samp_freq_avail; 1067 *length = st->samp_freq_avail_len; 1068 *type = IIO_VAL_INT; 1069 return IIO_AVAIL_LIST; 1070 case IIO_CHAN_INFO_SCALE: 1071 *vals = (int *)st->scale_tbl; 1072 *length = st->chip->num_pga_modes * 2; 1073 *type = IIO_VAL_INT_PLUS_NANO; 1074 return IIO_AVAIL_LIST; 1075 default: 1076 return -EINVAL; 1077 } 1078 } 1079 1080 static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, 1081 struct iio_chan_spec const *chan, long mask) 1082 { 1083 switch (mask) { 1084 case IIO_CHAN_INFO_SCALE: 1085 return IIO_VAL_INT_PLUS_NANO; 1086 default: 1087 return IIO_VAL_INT_PLUS_MICRO; 1088 } 1089 } 1090 1091 static int ad7768_write_raw(struct iio_dev *indio_dev, 1092 struct iio_chan_spec const *chan, 1093 int val, int val2, long info) 1094 { 1095 struct ad7768_state *st = iio_priv(indio_dev); 1096 const struct iio_scan_type *scan_type; 1097 int ret; 1098 1099 scan_type = iio_get_current_scan_type(indio_dev, chan); 1100 if (IS_ERR(scan_type)) 1101 return PTR_ERR(scan_type); 1102 1103 switch (info) { 1104 case IIO_CHAN_INFO_SAMP_FREQ: 1105 if (!iio_device_claim_direct(indio_dev)) 1106 return -EBUSY; 1107 1108 ret = ad7768_set_freq(st, val); 1109 iio_device_release_direct(indio_dev); 1110 return ret; 1111 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1112 if (!iio_device_claim_direct(indio_dev)) 1113 return -EBUSY; 1114 1115 ret = ad7768_update_dec_rate(indio_dev, val); 1116 iio_device_release_direct(indio_dev); 1117 return ret; 1118 case IIO_CHAN_INFO_SCALE: { 1119 int gain_mode; 1120 1121 if (!st->chip->has_pga) 1122 return -EOPNOTSUPP; 1123 1124 if (scan_type->sign == 's') 1125 gain_mode = ad7768_calc_pga_gain(st, val, val2, 1126 scan_type->realbits - 1); 1127 else 1128 gain_mode = ad7768_calc_pga_gain(st, val, val2, 1129 scan_type->realbits); 1130 1131 return ad7768_set_pga_gain(st, gain_mode); 1132 } 1133 default: 1134 return -EINVAL; 1135 } 1136 } 1137 1138 static int ad7768_read_label(struct iio_dev *indio_dev, 1139 const struct iio_chan_spec *chan, char *label) 1140 { 1141 struct ad7768_state *st = iio_priv(indio_dev); 1142 1143 return sysfs_emit(label, "%s\n", st->labels[chan->channel]); 1144 } 1145 1146 static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, 1147 const struct iio_chan_spec *chan) 1148 { 1149 struct ad7768_state *st = iio_priv(indio_dev); 1150 1151 if (st->offload) 1152 return st->oversampling_ratio == 8 ? 1153 AD7768_SCAN_TYPE_OFFLOAD_HIGH_SPEED : AD7768_SCAN_TYPE_OFFLOAD_NORMAL; 1154 1155 return st->oversampling_ratio == 8 ? 1156 AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; 1157 } 1158 1159 static const struct iio_info ad7768_info = { 1160 .read_raw = &ad7768_read_raw, 1161 .read_avail = &ad7768_read_avail, 1162 .write_raw = &ad7768_write_raw, 1163 .write_raw_get_fmt = &ad7768_write_raw_get_fmt, 1164 .read_label = ad7768_read_label, 1165 .get_current_scan_type = &ad7768_get_current_scan_type, 1166 .debugfs_reg_access = &ad7768_reg_access, 1167 }; 1168 1169 static struct fwnode_handle * 1170 ad7768_fwnode_find_reference_args(const struct fwnode_handle *fwnode, 1171 const char *name, const char *nargs_prop, 1172 unsigned int nargs, unsigned int index, 1173 struct fwnode_reference_args *args) 1174 { 1175 int ret; 1176 1177 ret = fwnode_property_get_reference_args(fwnode, name, nargs_prop, 1178 nargs, index, args); 1179 return ret ? ERR_PTR(ret) : args->fwnode; 1180 } 1181 1182 static int ad7768_trigger_sources_sync_setup(struct device *dev, 1183 struct fwnode_handle *fwnode, 1184 struct ad7768_state *st) 1185 { 1186 struct fwnode_reference_args args; 1187 1188 struct fwnode_handle *ref __free(fwnode_handle) = 1189 ad7768_fwnode_find_reference_args(fwnode, "trigger-sources", 1190 "#trigger-source-cells", 0, 1191 AD7768_TRIGGER_SOURCE_SYNC_IDX, 1192 &args); 1193 if (IS_ERR(ref)) 1194 return PTR_ERR(ref); 1195 1196 ref = args.fwnode; 1197 /* First, try getting the GPIO trigger source */ 1198 if (fwnode_device_is_compatible(ref, "gpio-trigger")) { 1199 st->gpio_sync_in = devm_fwnode_gpiod_get_index(dev, ref, NULL, 0, 1200 GPIOD_OUT_LOW, 1201 "sync-in"); 1202 return PTR_ERR_OR_ZERO(st->gpio_sync_in); 1203 } 1204 1205 /* 1206 * TODO: Support the other cases when we have a trigger subsystem 1207 * to reliably handle other types of devices as trigger sources. 1208 * 1209 * For now, return an error message. For self triggering, omit the 1210 * trigger-sources property. 1211 */ 1212 return dev_err_probe(dev, -EOPNOTSUPP, "Invalid synchronization trigger source\n"); 1213 } 1214 1215 static int ad7768_trigger_sources_get_sync(struct device *dev, 1216 struct ad7768_state *st) 1217 { 1218 struct fwnode_handle *fwnode = dev_fwnode(dev); 1219 1220 /* 1221 * The AD7768-1 allows two primary methods for driving the SYNC_IN pin 1222 * to synchronize one or more devices: 1223 * 1. Using an external GPIO. 1224 * 2. Using a SPI command, where the SYNC_OUT pin generates a 1225 * synchronization pulse that drives the SYNC_IN pin. 1226 */ 1227 if (fwnode_property_present(fwnode, "trigger-sources")) 1228 return ad7768_trigger_sources_sync_setup(dev, fwnode, st); 1229 1230 /* 1231 * In the absence of trigger-sources property, enable self 1232 * synchronization over SPI (SYNC_OUT). 1233 */ 1234 st->en_spi_sync = true; 1235 1236 return 0; 1237 } 1238 1239 static int ad7768_setup(struct iio_dev *indio_dev) 1240 { 1241 struct ad7768_state *st = iio_priv(indio_dev); 1242 int ret; 1243 1244 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", 1245 GPIOD_OUT_HIGH); 1246 if (IS_ERR(st->gpio_reset)) 1247 return PTR_ERR(st->gpio_reset); 1248 1249 if (st->gpio_reset) { 1250 fsleep(10); 1251 gpiod_set_value_cansleep(st->gpio_reset, 0); 1252 fsleep(200); 1253 } else { 1254 /* 1255 * Two writes to the SPI_RESET[1:0] bits are required to initiate 1256 * a software reset. The bits must first be set to 11, and then 1257 * to 10. When the sequence is detected, the reset occurs. 1258 * See the datasheet, page 70. 1259 */ 1260 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3); 1261 if (ret) 1262 return ret; 1263 1264 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2); 1265 if (ret) 1266 return ret; 1267 } 1268 1269 ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 1270 if (ret) 1271 return ret; 1272 1273 /* For backwards compatibility, try the adi,sync-in-gpios property */ 1274 st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", 1275 GPIOD_OUT_LOW); 1276 if (IS_ERR(st->gpio_sync_in)) 1277 return PTR_ERR(st->gpio_sync_in); 1278 1279 /* 1280 * If the synchronization is not defined by adi,sync-in-gpios, try the 1281 * trigger-sources. 1282 */ 1283 if (!st->gpio_sync_in) { 1284 ret = ad7768_trigger_sources_get_sync(&st->spi->dev, st); 1285 if (ret) 1286 return ret; 1287 } 1288 1289 /* Only create a Chip GPIO if flagged for it */ 1290 if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { 1291 ret = ad7768_gpio_init(indio_dev); 1292 if (ret) 1293 return ret; 1294 } 1295 1296 /* 1297 * Set Default Digital Filter configuration: 1298 * SINC5 filter with x32 Decimation rate 1299 */ 1300 ret = ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32); 1301 if (ret) 1302 return ret; 1303 1304 /* Set the default sampling frequency to 32000 kSPS */ 1305 return ad7768_set_freq(st, 32000); 1306 } 1307 1308 static irqreturn_t ad7768_trigger_handler(int irq, void *p) 1309 { 1310 struct iio_poll_func *pf = p; 1311 struct iio_dev *indio_dev = pf->indio_dev; 1312 struct ad7768_state *st = iio_priv(indio_dev); 1313 const struct iio_scan_type *scan_type; 1314 int ret; 1315 1316 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1317 if (IS_ERR(scan_type)) 1318 goto out; 1319 1320 ret = spi_read(st->spi, &st->data.scan.chan, 1321 BITS_TO_BYTES(scan_type->realbits)); 1322 if (ret < 0) 1323 goto out; 1324 1325 iio_push_to_buffers_with_ts(indio_dev, &st->data.scan, 1326 sizeof(st->data.scan), 1327 iio_get_time_ns(indio_dev)); 1328 1329 out: 1330 iio_trigger_notify_done(indio_dev->trig); 1331 1332 return IRQ_HANDLED; 1333 } 1334 1335 static irqreturn_t ad7768_interrupt(int irq, void *dev_id) 1336 { 1337 struct iio_dev *indio_dev = dev_id; 1338 struct ad7768_state *st = iio_priv(indio_dev); 1339 1340 if (iio_buffer_enabled(indio_dev)) 1341 iio_trigger_poll(st->trig); 1342 else 1343 complete(&st->completion); 1344 1345 return IRQ_HANDLED; 1346 }; 1347 1348 static int ad7768_buffer_postenable(struct iio_dev *indio_dev) 1349 { 1350 struct ad7768_state *st = iio_priv(indio_dev); 1351 1352 /* 1353 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 1354 * continuous read mode. Subsequent data reads do not require an 1355 * initial 8-bit write to query the ADC_DATA register. 1356 */ 1357 return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01); 1358 } 1359 1360 static int ad7768_buffer_predisable(struct iio_dev *indio_dev) 1361 { 1362 struct ad7768_state *st = iio_priv(indio_dev); 1363 unsigned int unused; 1364 1365 /* 1366 * To exit continuous read mode, perform a single read of the ADC_DATA 1367 * reg (0x2C), which allows further configuration of the device. 1368 */ 1369 return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1370 } 1371 1372 static const struct iio_buffer_setup_ops ad7768_buffer_ops = { 1373 .postenable = &ad7768_buffer_postenable, 1374 .predisable = &ad7768_buffer_predisable, 1375 }; 1376 1377 static int ad7768_offload_buffer_postenable(struct iio_dev *indio_dev) 1378 { 1379 struct ad7768_state *st = iio_priv(indio_dev); 1380 struct spi_offload_trigger_config config = { 1381 .type = SPI_OFFLOAD_TRIGGER_DATA_READY, 1382 }; 1383 const struct iio_scan_type *scan_type; 1384 unsigned int unused; 1385 int ret; 1386 1387 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1388 if (IS_ERR(scan_type)) 1389 return PTR_ERR(scan_type); 1390 1391 st->offload_xfer.len = spi_bpw_to_bytes(scan_type->realbits); 1392 st->offload_xfer.bits_per_word = scan_type->realbits; 1393 st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1394 1395 spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 1396 st->offload_msg.offload = st->offload; 1397 1398 ret = spi_optimize_message(st->spi, &st->offload_msg); 1399 if (ret) { 1400 dev_err(&st->spi->dev, "failed to prepare offload, err: %d\n", ret); 1401 return ret; 1402 } 1403 1404 /* 1405 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 1406 * continuous read mode. Subsequent data reads do not require an 1407 * initial 8-bit write to query the ADC_DATA register. 1408 */ 1409 ret = regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01); 1410 if (ret) 1411 goto err_unoptimize_message; 1412 1413 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, 1414 &config); 1415 if (ret) 1416 goto err_exit_continuous_read_mode; 1417 1418 return 0; 1419 1420 err_exit_continuous_read_mode: 1421 regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1422 1423 err_unoptimize_message: 1424 spi_unoptimize_message(&st->offload_msg); 1425 1426 return ret; 1427 } 1428 1429 static int ad7768_offload_buffer_predisable(struct iio_dev *indio_dev) 1430 { 1431 struct ad7768_state *st = iio_priv(indio_dev); 1432 unsigned int unused; 1433 1434 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1435 spi_unoptimize_message(&st->offload_msg); 1436 1437 /* 1438 * To exit continuous read mode, perform a single read of the ADC_DATA 1439 * reg (0x2C), which allows further configuration of the device. 1440 */ 1441 return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1442 } 1443 1444 static const struct iio_buffer_setup_ops ad7768_offload_buffer_ops = { 1445 .postenable = ad7768_offload_buffer_postenable, 1446 .predisable = ad7768_offload_buffer_predisable, 1447 }; 1448 1449 static int ad7768_set_trigger_state(struct iio_trigger *trig, bool enable) 1450 { 1451 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1452 struct ad7768_state *st = iio_priv(indio_dev); 1453 1454 if (enable) 1455 enable_irq(st->spi->irq); 1456 else 1457 disable_irq(st->spi->irq); 1458 1459 return 0; 1460 } 1461 1462 static const struct iio_trigger_ops ad7768_trigger_ops = { 1463 .validate_device = iio_trigger_validate_own_device, 1464 .set_trigger_state = ad7768_set_trigger_state, 1465 }; 1466 1467 static int ad7768_set_channel_label(struct iio_dev *indio_dev, 1468 int num_channels) 1469 { 1470 struct ad7768_state *st = iio_priv(indio_dev); 1471 struct device *device = indio_dev->dev.parent; 1472 const char *label; 1473 int crt_ch = 0; 1474 1475 device_for_each_child_node_scoped(device, child) { 1476 if (fwnode_property_read_u32(child, "reg", &crt_ch)) 1477 continue; 1478 1479 if (crt_ch >= num_channels) 1480 continue; 1481 1482 if (fwnode_property_read_string(child, "label", &label)) 1483 continue; 1484 1485 st->labels[crt_ch] = label; 1486 } 1487 1488 return 0; 1489 } 1490 1491 static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev) 1492 { 1493 struct ad7768_state *st = iio_priv(indio_dev); 1494 int ret; 1495 1496 st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", 1497 indio_dev->name, 1498 iio_device_id(indio_dev)); 1499 if (!st->trig) 1500 return -ENOMEM; 1501 1502 st->trig->ops = &ad7768_trigger_ops; 1503 iio_trigger_set_drvdata(st->trig, indio_dev); 1504 ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig); 1505 if (ret) 1506 return ret; 1507 1508 indio_dev->trig = iio_trigger_get(st->trig); 1509 1510 return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, 1511 &iio_pollfunc_store_time, 1512 &ad7768_trigger_handler, 1513 &ad7768_buffer_ops); 1514 } 1515 1516 static int ad7768_vcm_enable(struct regulator_dev *rdev) 1517 { 1518 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1519 struct ad7768_state *st = iio_priv(indio_dev); 1520 int ret, regval; 1521 1522 if (!iio_device_claim_direct(indio_dev)) 1523 return -EBUSY; 1524 1525 /* To enable, set the last selected output */ 1526 regval = AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1); 1527 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1528 AD7768_REG_ANALOG2_VCM_MSK, regval); 1529 iio_device_release_direct(indio_dev); 1530 1531 return ret; 1532 } 1533 1534 static int ad7768_vcm_disable(struct regulator_dev *rdev) 1535 { 1536 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1537 struct ad7768_state *st = iio_priv(indio_dev); 1538 int ret; 1539 1540 if (!iio_device_claim_direct(indio_dev)) 1541 return -EBUSY; 1542 1543 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1544 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1545 iio_device_release_direct(indio_dev); 1546 1547 return ret; 1548 } 1549 1550 static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) 1551 { 1552 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1553 struct ad7768_state *st = iio_priv(indio_dev); 1554 int ret, val; 1555 1556 if (!iio_device_claim_direct(indio_dev)) 1557 return -EBUSY; 1558 1559 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1560 iio_device_release_direct(indio_dev); 1561 if (ret) 1562 return ret; 1563 1564 return FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val) != AD7768_VCM_OFF; 1565 } 1566 1567 static int ad7768_set_voltage_sel(struct regulator_dev *rdev, 1568 unsigned int selector) 1569 { 1570 unsigned int regval = AD7768_REG_ANALOG2_VCM(selector + 1); 1571 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1572 struct ad7768_state *st = iio_priv(indio_dev); 1573 int ret; 1574 1575 if (!iio_device_claim_direct(indio_dev)) 1576 return -EBUSY; 1577 1578 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1579 AD7768_REG_ANALOG2_VCM_MSK, regval); 1580 iio_device_release_direct(indio_dev); 1581 if (ret) 1582 return ret; 1583 1584 st->vcm_output_sel = selector; 1585 1586 return 0; 1587 } 1588 1589 static int ad7768_get_voltage_sel(struct regulator_dev *rdev) 1590 { 1591 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1592 struct ad7768_state *st = iio_priv(indio_dev); 1593 int ret, val; 1594 1595 if (!iio_device_claim_direct(indio_dev)) 1596 return -EBUSY; 1597 1598 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1599 iio_device_release_direct(indio_dev); 1600 if (ret) 1601 return ret; 1602 1603 val = FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val); 1604 1605 return clamp(val, 1, rdev->desc->n_voltages) - 1; 1606 } 1607 1608 static const struct regulator_ops vcm_regulator_ops = { 1609 .enable = ad7768_vcm_enable, 1610 .disable = ad7768_vcm_disable, 1611 .is_enabled = ad7768_vcm_is_enabled, 1612 .list_voltage = regulator_list_voltage_table, 1613 .set_voltage_sel = ad7768_set_voltage_sel, 1614 .get_voltage_sel = ad7768_get_voltage_sel, 1615 }; 1616 1617 static const unsigned int vcm_voltage_table[] = { 1618 2500000, 1619 2050000, 1620 1650000, 1621 1900000, 1622 1100000, 1623 900000, 1624 }; 1625 1626 static const struct regulator_desc vcm_desc = { 1627 .name = "ad7768-1-vcm", 1628 .of_match = "vcm-output", 1629 .regulators_node = "regulators", 1630 .n_voltages = ARRAY_SIZE(vcm_voltage_table), 1631 .volt_table = vcm_voltage_table, 1632 .ops = &vcm_regulator_ops, 1633 .type = REGULATOR_VOLTAGE, 1634 .owner = THIS_MODULE, 1635 }; 1636 1637 static int ad7768_register_vcm_regulator(struct device *dev, 1638 struct ad7768_state *st, 1639 struct iio_dev *indio_dev) 1640 { 1641 struct regulator_config config = { 1642 .dev = dev, 1643 .driver_data = indio_dev, 1644 }; 1645 int ret; 1646 1647 /* Disable the regulator before registering it */ 1648 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1649 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1650 if (ret) 1651 return ret; 1652 1653 st->vcm_rdev = devm_regulator_register(dev, &vcm_desc, &config); 1654 if (IS_ERR(st->vcm_rdev)) 1655 return dev_err_probe(dev, PTR_ERR(st->vcm_rdev), 1656 "failed to register VCM regulator\n"); 1657 1658 return 0; 1659 } 1660 1661 static int ad7768_parse_aaf_gain(struct device *dev, struct ad7768_state *st) 1662 { 1663 u32 val; 1664 int ret; 1665 1666 ret = device_property_read_u32(dev, "adi,aaf-gain-bp", &val); 1667 if (ret == -EINVAL) { 1668 /* If controllable, use default */ 1669 if (st->chip->has_variable_aaf) 1670 st->aaf_gain = AD7768_AAF_IN1; 1671 return 0; 1672 } 1673 if (ret) 1674 return dev_err_probe(dev, ret, "Failed to get AAF gain value\n"); 1675 1676 if (!st->chip->has_variable_aaf) 1677 return dev_err_probe(dev, -EOPNOTSUPP, 1678 "AAF gain provided, but not supported for %s\n", st->chip->name); 1679 1680 switch (val) { 1681 case 10000: 1682 st->aaf_gain = AD7768_AAF_IN1; 1683 break; 1684 case 3640: 1685 st->aaf_gain = AD7768_AAF_IN2; 1686 break; 1687 case 1430: 1688 st->aaf_gain = AD7768_AAF_IN3; 1689 break; 1690 default: 1691 return dev_err_probe(dev, -EINVAL, "Invalid firmware provided AAF gain\n"); 1692 } 1693 1694 return 0; 1695 } 1696 1697 static bool ad7768_offload_trigger_match(struct spi_offload_trigger *trigger, 1698 enum spi_offload_trigger_type type, 1699 u64 *args, u32 nargs) 1700 { 1701 if (type != SPI_OFFLOAD_TRIGGER_DATA_READY) 1702 return false; 1703 1704 /* Up to 2 args are allowed, but only 1 is used */ 1705 if (nargs == 0 || nargs > 2 || args[0] != AD7768_TRIGGER_SOURCE_DRDY) 1706 return false; 1707 1708 return true; 1709 } 1710 1711 static int ad7768_offload_trigger_request(struct spi_offload_trigger *trigger, 1712 enum spi_offload_trigger_type type, 1713 u64 *args, u32 nargs) 1714 { 1715 /* Should already be validated by match, but just in case */ 1716 if (nargs == 0 || nargs > 2) 1717 return -EINVAL; 1718 1719 return 0; 1720 } 1721 1722 static const struct spi_offload_trigger_ops ad7768_offload_trigger_ops = { 1723 .match = ad7768_offload_trigger_match, 1724 .request = ad7768_offload_trigger_request, 1725 }; 1726 1727 static const struct ad7768_chip_info ad7768_chip_info = { 1728 .name = "ad7768-1", 1729 .channel_spec = ad7768_channels, 1730 .num_channels = ARRAY_SIZE(ad7768_channels), 1731 .has_vcm_regulator = true, 1732 }; 1733 1734 static const struct ad7768_chip_info adaq7767_chip_info = { 1735 .name = "adaq7767-1", 1736 .channel_spec = ad7768_channels, 1737 .num_channels = ARRAY_SIZE(ad7768_channels), 1738 .has_variable_aaf = true, 1739 }; 1740 1741 static const struct ad7768_chip_info adaq7768_chip_info = { 1742 .name = "adaq7768-1", 1743 .channel_spec = adaq776x_channels, 1744 .num_channels = ARRAY_SIZE(adaq776x_channels), 1745 .pga_gains = adaq7768_gains, 1746 .default_pga_mode = AD7768_PGA_GAIN_2, 1747 .num_pga_modes = ARRAY_SIZE(adaq7768_gains), 1748 .pgia_mode2pin_offset = 6, 1749 .has_pga = true, 1750 }; 1751 1752 static const struct ad7768_chip_info adaq7769_chip_info = { 1753 .name = "adaq7769-1", 1754 .channel_spec = adaq776x_channels, 1755 .num_channels = ARRAY_SIZE(adaq776x_channels), 1756 .pga_gains = adaq7769_gains, 1757 .default_pga_mode = AD7768_PGA_GAIN_0, 1758 .num_pga_modes = ARRAY_SIZE(adaq7769_gains), 1759 .pgia_mode2pin_offset = 0, 1760 .has_pga = true, 1761 .has_variable_aaf = true, 1762 }; 1763 1764 static const struct spi_offload_config ad7768_spi_offload_config = { 1765 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | SPI_OFFLOAD_CAP_RX_STREAM_DMA, 1766 }; 1767 1768 static int ad7768_spi_offload_probe(struct iio_dev *indio_dev, 1769 struct ad7768_state *st) 1770 { 1771 struct device *dev = &st->spi->dev; 1772 struct spi_offload_trigger_info trigger_info = { 1773 .fwnode = dev_fwnode(dev), 1774 .ops = &ad7768_offload_trigger_ops, 1775 .priv = st, 1776 }; 1777 struct dma_chan *rx_dma; 1778 int ret; 1779 1780 ret = devm_spi_offload_trigger_register(dev, &trigger_info); 1781 if (ret) 1782 return dev_err_probe(dev, ret, "failed to register offload trigger\n"); 1783 1784 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1785 SPI_OFFLOAD_TRIGGER_DATA_READY); 1786 if (IS_ERR(st->offload_trigger)) 1787 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1788 "failed to get offload trigger\n"); 1789 1790 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1791 if (IS_ERR(rx_dma)) 1792 return dev_err_probe(dev, PTR_ERR(rx_dma), "failed to get offload RX DMA\n"); 1793 1794 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 1795 IIO_BUFFER_DIRECTION_IN); 1796 if (ret) 1797 return dev_err_probe(dev, ret, "failed to setup offload RX DMA\n"); 1798 1799 indio_dev->setup_ops = &ad7768_offload_buffer_ops; 1800 1801 return 0; 1802 } 1803 1804 static int ad7768_probe(struct spi_device *spi) 1805 { 1806 struct ad7768_state *st; 1807 struct iio_dev *indio_dev; 1808 struct device *dev = &spi->dev; 1809 int ret; 1810 1811 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1812 if (!indio_dev) 1813 return -ENOMEM; 1814 1815 st = iio_priv(indio_dev); 1816 /* 1817 * Datasheet recommends SDI line to be kept high when data is not being 1818 * clocked out of the controller and the spi clock is free running, 1819 * to prevent accidental reset. 1820 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag 1821 * yet, only request the MOSI idle state to enable if the controller 1822 * supports it. 1823 */ 1824 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) { 1825 spi->mode |= SPI_MOSI_IDLE_HIGH; 1826 ret = spi_setup(spi); 1827 if (ret < 0) 1828 return ret; 1829 } 1830 1831 st->chip = spi_get_device_match_data(spi); 1832 st->spi = spi; 1833 1834 st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config); 1835 if (IS_ERR(st->regmap)) 1836 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), 1837 "Failed to initialize regmap"); 1838 1839 st->regmap24 = devm_regmap_init_spi(spi, &ad7768_regmap24_config); 1840 if (IS_ERR(st->regmap24)) 1841 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap24), 1842 "Failed to initialize regmap24"); 1843 1844 ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); 1845 if (ret < 0) 1846 return dev_err_probe(&spi->dev, ret, 1847 "Failed to get VREF voltage\n"); 1848 st->vref_uv = ret; 1849 1850 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 1851 if (IS_ERR(st->mclk)) 1852 return PTR_ERR(st->mclk); 1853 1854 st->mclk_freq = clk_get_rate(st->mclk); 1855 1856 indio_dev->channels = st->chip->channel_spec; 1857 indio_dev->num_channels = st->chip->num_channels; 1858 indio_dev->name = st->chip->name; 1859 indio_dev->info = &ad7768_info; 1860 indio_dev->modes = INDIO_DIRECT_MODE; 1861 1862 /* Register VCM output regulator */ 1863 if (st->chip->has_vcm_regulator) { 1864 ret = ad7768_register_vcm_regulator(&spi->dev, st, indio_dev); 1865 if (ret) 1866 return ret; 1867 } 1868 1869 ret = ad7768_parse_aaf_gain(&spi->dev, st); 1870 if (ret) 1871 return ret; 1872 1873 ret = ad7768_setup(indio_dev); 1874 if (ret < 0) { 1875 dev_err(&spi->dev, "AD7768 setup failed\n"); 1876 return ret; 1877 } 1878 1879 init_completion(&st->completion); 1880 ret = devm_mutex_init(&spi->dev, &st->pga_lock); 1881 if (ret) 1882 return ret; 1883 1884 if (st->chip->has_pga) { 1885 ret = ad7768_setup_pga(&spi->dev, st); 1886 if (ret) 1887 return ret; 1888 1889 ret = ad7768_set_pga_gain(st, st->chip->default_pga_mode); 1890 if (ret) 1891 return ret; 1892 } 1893 1894 ret = ad7768_set_channel_label(indio_dev, st->chip->num_channels); 1895 if (ret) 1896 return ret; 1897 1898 ret = devm_request_irq(&spi->dev, spi->irq, &ad7768_interrupt, 1899 IRQF_TRIGGER_RISING | IRQF_NO_THREAD | IRQF_NO_AUTOEN, 1900 indio_dev->name, indio_dev); 1901 if (ret) 1902 return ret; 1903 1904 st->offload = devm_spi_offload_get(dev, spi, &ad7768_spi_offload_config); 1905 ret = PTR_ERR_OR_ZERO(st->offload); 1906 if (ret == -ENODEV) { 1907 /* If not using SPI offload, fall back to low speed usage */ 1908 ret = ad7768_triggered_buffer_alloc(indio_dev); 1909 if (ret) 1910 return ret; 1911 } else if (ret) { 1912 return dev_err_probe(dev, ret, "failed to get SPI offload\n"); 1913 } else { 1914 ret = ad7768_spi_offload_probe(indio_dev, st); 1915 if (ret) 1916 return ret; 1917 } 1918 1919 return devm_iio_device_register(&spi->dev, indio_dev); 1920 } 1921 1922 static const struct spi_device_id ad7768_id_table[] = { 1923 { "ad7768-1", (kernel_ulong_t)&ad7768_chip_info }, 1924 { "adaq7767-1", (kernel_ulong_t)&adaq7767_chip_info }, 1925 { "adaq7768-1", (kernel_ulong_t)&adaq7768_chip_info }, 1926 { "adaq7769-1", (kernel_ulong_t)&adaq7769_chip_info }, 1927 { } 1928 }; 1929 MODULE_DEVICE_TABLE(spi, ad7768_id_table); 1930 1931 static const struct of_device_id ad7768_of_match[] = { 1932 { .compatible = "adi,ad7768-1", .data = &ad7768_chip_info }, 1933 { .compatible = "adi,adaq7767-1", .data = &adaq7767_chip_info }, 1934 { .compatible = "adi,adaq7768-1", .data = &adaq7768_chip_info }, 1935 { .compatible = "adi,adaq7769-1", .data = &adaq7769_chip_info }, 1936 { } 1937 }; 1938 MODULE_DEVICE_TABLE(of, ad7768_of_match); 1939 1940 static struct spi_driver ad7768_driver = { 1941 .driver = { 1942 .name = "ad7768-1", 1943 .of_match_table = ad7768_of_match, 1944 }, 1945 .probe = ad7768_probe, 1946 .id_table = ad7768_id_table, 1947 }; 1948 module_spi_driver(ad7768_driver); 1949 1950 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1951 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 1952 MODULE_LICENSE("GPL v2"); 1953 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 1954