1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7768-1 SPI ADC driver 4 * 5 * Copyright 2017 Analog Devices Inc. 6 */ 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/interrupt.h> 17 #include <linux/minmax.h> 18 #include <linux/module.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/regulator/driver.h> 22 #include <linux/sysfs.h> 23 #include <linux/spi/spi.h> 24 #include <linux/unaligned.h> 25 #include <linux/units.h> 26 #include <linux/util_macros.h> 27 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/sysfs.h> 31 #include <linux/iio/trigger.h> 32 #include <linux/iio/triggered_buffer.h> 33 #include <linux/iio/trigger_consumer.h> 34 35 #include <dt-bindings/iio/adc/adi,ad7768-1.h> 36 37 /* AD7768 registers definition */ 38 #define AD7768_REG_CHIP_TYPE 0x3 39 #define AD7768_REG_PROD_ID_L 0x4 40 #define AD7768_REG_PROD_ID_H 0x5 41 #define AD7768_REG_CHIP_GRADE 0x6 42 #define AD7768_REG_SCRATCH_PAD 0x0A 43 #define AD7768_REG_VENDOR_L 0x0C 44 #define AD7768_REG_VENDOR_H 0x0D 45 #define AD7768_REG_INTERFACE_FORMAT 0x14 46 #define AD7768_REG_POWER_CLOCK 0x15 47 #define AD7768_REG_ANALOG 0x16 48 #define AD7768_REG_ANALOG2 0x17 49 #define AD7768_REG_CONVERSION 0x18 50 #define AD7768_REG_DIGITAL_FILTER 0x19 51 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A 52 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B 53 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C 54 #define AD7768_REG_SYNC_RESET 0x1D 55 #define AD7768_REG_GPIO_CONTROL 0x1E 56 #define AD7768_REG_GPIO_WRITE 0x1F 57 #define AD7768_REG_GPIO_READ 0x20 58 #define AD7768_REG_OFFSET_HI 0x21 59 #define AD7768_REG_OFFSET_MID 0x22 60 #define AD7768_REG_OFFSET_LO 0x23 61 #define AD7768_REG_GAIN_HI 0x24 62 #define AD7768_REG_GAIN_MID 0x25 63 #define AD7768_REG_GAIN_LO 0x26 64 #define AD7768_REG_SPI_DIAG_ENABLE 0x28 65 #define AD7768_REG_ADC_DIAG_ENABLE 0x29 66 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A 67 #define AD7768_REG24_ADC_DATA 0x2C 68 #define AD7768_REG_MASTER_STATUS 0x2D 69 #define AD7768_REG_SPI_DIAG_STATUS 0x2E 70 #define AD7768_REG_ADC_DIAG_STATUS 0x2F 71 #define AD7768_REG_DIG_DIAG_STATUS 0x30 72 #define AD7768_REG_MCLK_COUNTER 0x31 73 #define AD7768_REG_COEFF_CONTROL 0x32 74 #define AD7768_REG24_COEFF_DATA 0x33 75 #define AD7768_REG_ACCESS_KEY 0x34 76 77 /* AD7768_REG_POWER_CLOCK */ 78 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) 79 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) 80 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) 81 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 82 83 /* AD7768_REG_DIGITAL_FILTER */ 84 #define AD7768_DIG_FIL_EN_60HZ_REJ BIT(7) 85 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 86 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 87 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) 88 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) 89 90 /* AD7768_REG_CONVERSION */ 91 #define AD7768_CONV_MODE_MSK GENMASK(2, 0) 92 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 93 94 /* AD7768_REG_ANALOG2 */ 95 #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) 96 #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (x)) 97 98 /* AD7768_REG_GPIO_CONTROL */ 99 #define AD7768_GPIO_UNIVERSAL_EN BIT(7) 100 #define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) 101 102 /* AD7768_REG_GPIO_WRITE */ 103 #define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) 104 105 /* AD7768_REG_GPIO_READ */ 106 #define AD7768_GPIO_READ_MSK GENMASK(3, 0) 107 108 #define AD7768_VCM_OFF 0x07 109 110 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 111 112 #define AD7768_MAX_CHANNELS 1 113 114 enum ad7768_conv_mode { 115 AD7768_CONTINUOUS, 116 AD7768_ONE_SHOT, 117 AD7768_SINGLE, 118 AD7768_PERIODIC, 119 AD7768_STANDBY 120 }; 121 122 enum ad7768_pwrmode { 123 AD7768_ECO_MODE = 0, 124 AD7768_MED_MODE = 2, 125 AD7768_FAST_MODE = 3 126 }; 127 128 enum ad7768_mclk_div { 129 AD7768_MCLK_DIV_16, 130 AD7768_MCLK_DIV_8, 131 AD7768_MCLK_DIV_4, 132 AD7768_MCLK_DIV_2 133 }; 134 135 enum ad7768_filter_type { 136 AD7768_FILTER_SINC5, 137 AD7768_FILTER_SINC3, 138 AD7768_FILTER_WIDEBAND, 139 AD7768_FILTER_SINC3_REJ60, 140 }; 141 142 enum ad7768_filter_regval { 143 AD7768_FILTER_REGVAL_SINC5 = 0, 144 AD7768_FILTER_REGVAL_SINC5_X8 = 1, 145 AD7768_FILTER_REGVAL_SINC5_X16 = 2, 146 AD7768_FILTER_REGVAL_SINC3 = 3, 147 AD7768_FILTER_REGVAL_WIDEBAND = 4, 148 AD7768_FILTER_REGVAL_SINC3_REJ60 = 11, 149 }; 150 151 enum ad7768_scan_type { 152 AD7768_SCAN_TYPE_NORMAL, 153 AD7768_SCAN_TYPE_HIGH_SPEED, 154 }; 155 156 /* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */ 157 static const int ad7768_filter_3db_odr_multiplier[] = { 158 [AD7768_FILTER_SINC5] = 204, /* 0.204 */ 159 [AD7768_FILTER_SINC3] = 262, /* 0.2617 */ 160 [AD7768_FILTER_SINC3_REJ60] = 262, /* 0.2617 */ 161 [AD7768_FILTER_WIDEBAND] = 433, /* 0.433 */ 162 }; 163 164 static const int ad7768_mclk_div_rates[] = { 165 16, 8, 4, 2, 166 }; 167 168 static const int ad7768_dec_rate_values[8] = { 169 8, 16, 32, 64, 128, 256, 512, 1024, 170 }; 171 172 /* Decimation rate range for sinc3 filter */ 173 static const int ad7768_sinc3_dec_rate_range[3] = { 174 32, 32, 163840, 175 }; 176 177 /* 178 * The AD7768-1 supports three primary filter types: 179 * Sinc5, Sinc3, and Wideband. 180 * However, the filter register values can also encode additional parameters 181 * such as decimation rates and 60Hz rejection. This utility array separates 182 * the filter type from these parameters. 183 */ 184 static const int ad7768_filter_regval_to_type[] = { 185 [AD7768_FILTER_REGVAL_SINC5] = AD7768_FILTER_SINC5, 186 [AD7768_FILTER_REGVAL_SINC5_X8] = AD7768_FILTER_SINC5, 187 [AD7768_FILTER_REGVAL_SINC5_X16] = AD7768_FILTER_SINC5, 188 [AD7768_FILTER_REGVAL_SINC3] = AD7768_FILTER_SINC3, 189 [AD7768_FILTER_REGVAL_WIDEBAND] = AD7768_FILTER_WIDEBAND, 190 [AD7768_FILTER_REGVAL_SINC3_REJ60] = AD7768_FILTER_SINC3_REJ60, 191 }; 192 193 static const char * const ad7768_filter_enum[] = { 194 [AD7768_FILTER_SINC5] = "sinc5", 195 [AD7768_FILTER_SINC3] = "sinc3", 196 [AD7768_FILTER_WIDEBAND] = "wideband", 197 [AD7768_FILTER_SINC3_REJ60] = "sinc3+rej60", 198 }; 199 200 static const struct iio_scan_type ad7768_scan_type[] = { 201 [AD7768_SCAN_TYPE_NORMAL] = { 202 .sign = 's', 203 .realbits = 24, 204 .storagebits = 32, 205 .shift = 8, 206 .endianness = IIO_BE, 207 }, 208 [AD7768_SCAN_TYPE_HIGH_SPEED] = { 209 .sign = 's', 210 .realbits = 16, 211 .storagebits = 16, 212 .endianness = IIO_BE, 213 }, 214 }; 215 216 struct ad7768_state { 217 struct spi_device *spi; 218 struct regmap *regmap; 219 struct regmap *regmap24; 220 int vref_uv; 221 struct regulator_dev *vcm_rdev; 222 unsigned int vcm_output_sel; 223 struct clk *mclk; 224 unsigned int mclk_freq; 225 unsigned int mclk_div; 226 unsigned int oversampling_ratio; 227 enum ad7768_filter_type filter_type; 228 unsigned int samp_freq; 229 unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; 230 unsigned int samp_freq_avail_len; 231 struct completion completion; 232 struct iio_trigger *trig; 233 struct gpio_desc *gpio_sync_in; 234 struct gpio_desc *gpio_reset; 235 const char *labels[AD7768_MAX_CHANNELS]; 236 struct gpio_chip gpiochip; 237 bool en_spi_sync; 238 /* 239 * DMA (thus cache coherency maintenance) may require the 240 * transfer buffers to live in their own cache lines. 241 */ 242 union { 243 struct { 244 __be32 chan; 245 aligned_s64 timestamp; 246 } scan; 247 __be32 d32; 248 u8 d8[2]; 249 } data __aligned(IIO_DMA_MINALIGN); 250 }; 251 252 static const struct regmap_range ad7768_regmap_rd_ranges[] = { 253 regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE), 254 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 255 regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H), 256 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO), 257 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 258 regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL), 259 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 260 }; 261 262 static const struct regmap_access_table ad7768_regmap_rd_table = { 263 .yes_ranges = ad7768_regmap_rd_ranges, 264 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges), 265 }; 266 267 static const struct regmap_range ad7768_regmap_wr_ranges[] = { 268 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 269 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE), 270 regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO), 271 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 272 regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS), 273 regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL), 274 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 275 }; 276 277 static const struct regmap_access_table ad7768_regmap_wr_table = { 278 .yes_ranges = ad7768_regmap_wr_ranges, 279 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges), 280 }; 281 282 static const struct regmap_config ad7768_regmap_config = { 283 .name = "ad7768-1-8", 284 .reg_bits = 8, 285 .val_bits = 8, 286 .read_flag_mask = BIT(6), 287 .rd_table = &ad7768_regmap_rd_table, 288 .wr_table = &ad7768_regmap_wr_table, 289 .max_register = AD7768_REG_ACCESS_KEY, 290 .use_single_write = true, 291 .use_single_read = true, 292 }; 293 294 static const struct regmap_range ad7768_regmap24_rd_ranges[] = { 295 regmap_reg_range(AD7768_REG24_ADC_DATA, AD7768_REG24_ADC_DATA), 296 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 297 }; 298 299 static const struct regmap_access_table ad7768_regmap24_rd_table = { 300 .yes_ranges = ad7768_regmap24_rd_ranges, 301 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_rd_ranges), 302 }; 303 304 static const struct regmap_range ad7768_regmap24_wr_ranges[] = { 305 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 306 }; 307 308 static const struct regmap_access_table ad7768_regmap24_wr_table = { 309 .yes_ranges = ad7768_regmap24_wr_ranges, 310 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_wr_ranges), 311 }; 312 313 static const struct regmap_config ad7768_regmap24_config = { 314 .name = "ad7768-1-24", 315 .reg_bits = 8, 316 .val_bits = 24, 317 .read_flag_mask = BIT(6), 318 .rd_table = &ad7768_regmap24_rd_table, 319 .wr_table = &ad7768_regmap24_wr_table, 320 .max_register = AD7768_REG24_COEFF_DATA, 321 }; 322 323 static int ad7768_send_sync_pulse(struct ad7768_state *st) 324 { 325 if (st->en_spi_sync) 326 return regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x00); 327 328 /* 329 * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, 330 * where Tmclk is the MCLK period. The supported MCLK frequencies range 331 * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse 332 * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). 333 * 334 * Add a delay to ensure the pulse width is always sufficient to 335 * trigger synchronization. 336 */ 337 gpiod_set_value_cansleep(st->gpio_sync_in, 1); 338 fsleep(3); 339 gpiod_set_value_cansleep(st->gpio_sync_in, 0); 340 341 return 0; 342 } 343 344 static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) 345 { 346 unsigned int i, samp_freq_avail, freq_filtered; 347 unsigned int len = 0; 348 349 freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio); 350 for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { 351 samp_freq_avail = DIV_ROUND_CLOSEST(freq_filtered, ad7768_mclk_div_rates[i]); 352 /* Sampling frequency cannot be lower than the minimum of 50 SPS */ 353 if (samp_freq_avail < 50) 354 continue; 355 356 st->samp_freq_avail[len++] = samp_freq_avail; 357 } 358 359 st->samp_freq_avail_len = len; 360 } 361 362 static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div) 363 { 364 unsigned int mclk_div_value; 365 366 mclk_div_value = AD7768_PWR_MCLK_DIV(mclk_div); 367 /* 368 * Set power mode based on mclk_div value. 369 * ECO_MODE is only recommended for MCLK_DIV = 16. 370 */ 371 mclk_div_value |= mclk_div > AD7768_MCLK_DIV_16 ? 372 AD7768_PWR_PWRMODE(AD7768_FAST_MODE) : 373 AD7768_PWR_PWRMODE(AD7768_ECO_MODE); 374 375 return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK, 376 AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK, 377 mclk_div_value); 378 } 379 380 static int ad7768_set_mode(struct ad7768_state *st, 381 enum ad7768_conv_mode mode) 382 { 383 return regmap_update_bits(st->regmap, AD7768_REG_CONVERSION, 384 AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode)); 385 } 386 387 static int ad7768_scan_direct(struct iio_dev *indio_dev) 388 { 389 struct ad7768_state *st = iio_priv(indio_dev); 390 int readval, ret; 391 392 reinit_completion(&st->completion); 393 394 ret = ad7768_set_mode(st, AD7768_ONE_SHOT); 395 if (ret < 0) 396 return ret; 397 398 ret = wait_for_completion_timeout(&st->completion, 399 msecs_to_jiffies(1000)); 400 if (!ret) 401 return -ETIMEDOUT; 402 403 ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval); 404 if (ret) 405 return ret; 406 407 /* 408 * When the decimation rate is set to x8, the ADC data precision is 409 * reduced from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA 410 * register provides 24-bit data, the precision is reduced by 411 * right-shifting the read value by 8 bits. 412 */ 413 if (st->oversampling_ratio == 8) 414 readval >>= 8; 415 416 /* 417 * Any SPI configuration of the AD7768-1 can only be 418 * performed in continuous conversion mode. 419 */ 420 ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 421 if (ret < 0) 422 return ret; 423 424 return readval; 425 } 426 427 static int ad7768_reg_access(struct iio_dev *indio_dev, 428 unsigned int reg, 429 unsigned int writeval, 430 unsigned int *readval) 431 { 432 struct ad7768_state *st = iio_priv(indio_dev); 433 int ret; 434 435 if (!iio_device_claim_direct(indio_dev)) 436 return -EBUSY; 437 438 ret = -EINVAL; 439 if (readval) { 440 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_rd_table)) 441 ret = regmap_read(st->regmap, reg, readval); 442 443 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_rd_table)) 444 ret = regmap_read(st->regmap24, reg, readval); 445 446 } else { 447 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_wr_table)) 448 ret = regmap_write(st->regmap, reg, writeval); 449 450 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_wr_table)) 451 ret = regmap_write(st->regmap24, reg, writeval); 452 453 } 454 455 iio_device_release_direct(indio_dev); 456 457 return ret; 458 } 459 460 static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, 461 unsigned int dec_rate) 462 { 463 unsigned int max_dec_rate; 464 u8 dec_rate_reg[2]; 465 u16 regval; 466 int ret; 467 468 /* 469 * Maximum dec_rate is limited by the MCLK_DIV value and by the ODR. 470 * The edge case is for MCLK_DIV = 2, ODR = 50 SPS. 471 * max_dec_rate <= MCLK / (2 * 50) 472 */ 473 max_dec_rate = st->mclk_freq / 100; 474 dec_rate = clamp(dec_rate, 32, max_dec_rate); 475 /* 476 * Calculate the equivalent value to sinc3 decimation ratio 477 * to be written on the SINC3_DEC_RATE register: 478 * Value = (DEC_RATE / 32) - 1 479 */ 480 dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1; 481 482 /* 483 * The SINC3_DEC_RATE value is a 13-bit value split across two 484 * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using 485 * FIELD_PREP() and store it with the right endianness in dec_rate_reg. 486 */ 487 regval = FIELD_PREP(GENMASK(12, 0), dec_rate); 488 put_unaligned_be16(regval, dec_rate_reg); 489 ret = regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, 490 dec_rate_reg, 2); 491 if (ret) 492 return ret; 493 494 st->oversampling_ratio = (dec_rate + 1) * 32; 495 496 return 0; 497 } 498 499 static int ad7768_configure_dig_fil(struct iio_dev *dev, 500 enum ad7768_filter_type filter_type, 501 unsigned int dec_rate) 502 { 503 struct ad7768_state *st = iio_priv(dev); 504 unsigned int dec_rate_idx, dig_filter_regval; 505 int ret; 506 507 switch (filter_type) { 508 case AD7768_FILTER_SINC3: 509 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3); 510 break; 511 case AD7768_FILTER_SINC3_REJ60: 512 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3) | 513 AD7768_DIG_FIL_EN_60HZ_REJ; 514 break; 515 case AD7768_FILTER_WIDEBAND: 516 /* Skip decimations 8 and 16, not supported by the wideband filter */ 517 dec_rate_idx = find_closest(dec_rate, &ad7768_dec_rate_values[2], 518 ARRAY_SIZE(ad7768_dec_rate_values) - 2); 519 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) | 520 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx); 521 /* Correct the index offset */ 522 dec_rate_idx += 2; 523 break; 524 case AD7768_FILTER_SINC5: 525 dec_rate_idx = find_closest(dec_rate, ad7768_dec_rate_values, 526 ARRAY_SIZE(ad7768_dec_rate_values)); 527 528 /* 529 * Decimations 8 (idx 0) and 16 (idx 1) are set in the 530 * FILTER[6:4] field. The other decimations are set in the 531 * DEC_RATE[2:0] field, and the idx needs to be offsetted by two. 532 */ 533 if (dec_rate_idx == 0) 534 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8); 535 else if (dec_rate_idx == 1) 536 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16); 537 else 538 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) | 539 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2); 540 break; 541 } 542 543 ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_regval); 544 if (ret) 545 return ret; 546 547 st->filter_type = filter_type; 548 /* 549 * The decimation for SINC3 filters are configured in different 550 * registers. 551 */ 552 if (filter_type == AD7768_FILTER_SINC3 || 553 filter_type == AD7768_FILTER_SINC3_REJ60) { 554 ret = ad7768_set_sinc3_dec_rate(st, dec_rate); 555 if (ret) 556 return ret; 557 } else { 558 st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx]; 559 } 560 561 ad7768_fill_samp_freq_tbl(st); 562 563 /* A sync-in pulse is required after every configuration change */ 564 return ad7768_send_sync_pulse(st); 565 } 566 567 static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 568 { 569 struct iio_dev *indio_dev = gpiochip_get_data(chip); 570 struct ad7768_state *st = iio_priv(indio_dev); 571 int ret; 572 573 if (!iio_device_claim_direct(indio_dev)) 574 return -EBUSY; 575 576 ret = regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 577 BIT(offset)); 578 iio_device_release_direct(indio_dev); 579 580 return ret; 581 } 582 583 static int ad7768_gpio_direction_output(struct gpio_chip *chip, 584 unsigned int offset, int value) 585 { 586 struct iio_dev *indio_dev = gpiochip_get_data(chip); 587 struct ad7768_state *st = iio_priv(indio_dev); 588 int ret; 589 590 if (!iio_device_claim_direct(indio_dev)) 591 return -EBUSY; 592 593 ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 594 BIT(offset)); 595 iio_device_release_direct(indio_dev); 596 597 return ret; 598 } 599 600 static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) 601 { 602 struct iio_dev *indio_dev = gpiochip_get_data(chip); 603 struct ad7768_state *st = iio_priv(indio_dev); 604 unsigned int val; 605 int ret; 606 607 if (!iio_device_claim_direct(indio_dev)) 608 return -EBUSY; 609 610 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 611 if (ret) 612 goto err_release; 613 614 /* 615 * If the GPIO is configured as an output, read the current value from 616 * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from 617 * AD7768_REG_GPIO_READ. 618 */ 619 if (val & BIT(offset)) 620 ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); 621 else 622 ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); 623 if (ret) 624 goto err_release; 625 626 ret = !!(val & BIT(offset)); 627 err_release: 628 iio_device_release_direct(indio_dev); 629 630 return ret; 631 } 632 633 static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 634 { 635 struct iio_dev *indio_dev = gpiochip_get_data(chip); 636 struct ad7768_state *st = iio_priv(indio_dev); 637 unsigned int val; 638 int ret; 639 640 if (!iio_device_claim_direct(indio_dev)) 641 return -EBUSY; 642 643 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 644 if (ret) 645 goto err_release; 646 647 if (val & BIT(offset)) 648 ret = regmap_assign_bits(st->regmap, AD7768_REG_GPIO_WRITE, 649 BIT(offset), value); 650 651 err_release: 652 iio_device_release_direct(indio_dev); 653 654 return ret; 655 } 656 657 static int ad7768_gpio_init(struct iio_dev *indio_dev) 658 { 659 struct ad7768_state *st = iio_priv(indio_dev); 660 int ret; 661 662 ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, 663 AD7768_GPIO_UNIVERSAL_EN); 664 if (ret) 665 return ret; 666 667 st->gpiochip = (struct gpio_chip) { 668 .label = "ad7768_1_gpios", 669 .base = -1, 670 .ngpio = 4, 671 .parent = &st->spi->dev, 672 .can_sleep = true, 673 .direction_input = ad7768_gpio_direction_input, 674 .direction_output = ad7768_gpio_direction_output, 675 .get = ad7768_gpio_get, 676 .set = ad7768_gpio_set, 677 .owner = THIS_MODULE, 678 }; 679 680 return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); 681 } 682 683 static int ad7768_set_freq(struct ad7768_state *st, 684 unsigned int freq) 685 { 686 unsigned int idx, mclk_div; 687 int ret; 688 689 freq = clamp(freq, 50, 1024000); 690 691 mclk_div = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); 692 /* Find the closest match for the desired sampling frequency */ 693 idx = find_closest_descending(mclk_div, ad7768_mclk_div_rates, 694 ARRAY_SIZE(ad7768_mclk_div_rates)); 695 /* Set both the mclk_div and pwrmode */ 696 ret = ad7768_set_mclk_div(st, idx); 697 if (ret) 698 return ret; 699 700 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 701 ad7768_mclk_div_rates[idx] * st->oversampling_ratio); 702 703 /* A sync-in pulse is required after every configuration change */ 704 return ad7768_send_sync_pulse(st); 705 } 706 707 static int ad7768_set_filter_type_attr(struct iio_dev *dev, 708 const struct iio_chan_spec *chan, 709 unsigned int filter) 710 { 711 struct ad7768_state *st = iio_priv(dev); 712 int ret; 713 714 ret = ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); 715 if (ret) 716 return ret; 717 718 /* Update sampling frequency */ 719 return ad7768_set_freq(st, st->samp_freq); 720 } 721 722 static int ad7768_get_filter_type_attr(struct iio_dev *dev, 723 const struct iio_chan_spec *chan) 724 { 725 struct ad7768_state *st = iio_priv(dev); 726 int ret; 727 unsigned int mode, mask; 728 729 ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); 730 if (ret) 731 return ret; 732 733 mask = AD7768_DIG_FIL_EN_60HZ_REJ | AD7768_DIG_FIL_FIL_MSK; 734 /* From the register value, get the corresponding filter type */ 735 return ad7768_filter_regval_to_type[FIELD_GET(mask, mode)]; 736 } 737 738 static const struct iio_enum ad7768_filter_type_iio_enum = { 739 .items = ad7768_filter_enum, 740 .num_items = ARRAY_SIZE(ad7768_filter_enum), 741 .set = ad7768_set_filter_type_attr, 742 .get = ad7768_get_filter_type_attr, 743 }; 744 745 static const struct iio_chan_spec_ext_info ad7768_ext_info[] = { 746 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 747 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 748 { } 749 }; 750 751 static const struct iio_chan_spec ad7768_channels[] = { 752 { 753 .type = IIO_VOLTAGE, 754 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 755 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 756 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | 757 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 758 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 759 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 760 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 761 .ext_info = ad7768_ext_info, 762 .indexed = 1, 763 .channel = 0, 764 .scan_index = 0, 765 .has_ext_scan_type = 1, 766 .ext_scan_type = ad7768_scan_type, 767 .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), 768 }, 769 }; 770 771 static int ad7768_read_raw(struct iio_dev *indio_dev, 772 struct iio_chan_spec const *chan, 773 int *val, int *val2, long info) 774 { 775 struct ad7768_state *st = iio_priv(indio_dev); 776 const struct iio_scan_type *scan_type; 777 int ret, temp; 778 779 scan_type = iio_get_current_scan_type(indio_dev, chan); 780 if (IS_ERR(scan_type)) 781 return PTR_ERR(scan_type); 782 783 switch (info) { 784 case IIO_CHAN_INFO_RAW: 785 if (!iio_device_claim_direct(indio_dev)) 786 return -EBUSY; 787 788 ret = ad7768_scan_direct(indio_dev); 789 790 iio_device_release_direct(indio_dev); 791 if (ret < 0) 792 return ret; 793 *val = sign_extend32(ret, scan_type->realbits - 1); 794 795 return IIO_VAL_INT; 796 797 case IIO_CHAN_INFO_SCALE: 798 *val = (st->vref_uv * 2) / 1000; 799 *val2 = scan_type->realbits; 800 801 return IIO_VAL_FRACTIONAL_LOG2; 802 803 case IIO_CHAN_INFO_SAMP_FREQ: 804 *val = st->samp_freq; 805 806 return IIO_VAL_INT; 807 808 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 809 *val = st->oversampling_ratio; 810 811 return IIO_VAL_INT; 812 813 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 814 temp = st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_type]; 815 *val = DIV_ROUND_CLOSEST(temp, MILLI); 816 817 return IIO_VAL_INT; 818 } 819 820 return -EINVAL; 821 } 822 823 static int ad7768_read_avail(struct iio_dev *indio_dev, 824 struct iio_chan_spec const *chan, 825 const int **vals, int *type, int *length, 826 long info) 827 { 828 struct ad7768_state *st = iio_priv(indio_dev); 829 unsigned int shift; 830 831 switch (info) { 832 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 833 /* 834 * Sinc3 filter allows a wider range of OSR values, so show 835 * the available values in range format. 836 */ 837 if (st->filter_type == AD7768_FILTER_SINC3 || 838 st->filter_type == AD7768_FILTER_SINC3_REJ60) { 839 *vals = (int *)ad7768_sinc3_dec_rate_range; 840 *type = IIO_VAL_INT; 841 return IIO_AVAIL_RANGE; 842 } 843 844 shift = st->filter_type == AD7768_FILTER_SINC5 ? 0 : 2; 845 *vals = (int *)&ad7768_dec_rate_values[shift]; 846 *length = ARRAY_SIZE(ad7768_dec_rate_values) - shift; 847 *type = IIO_VAL_INT; 848 return IIO_AVAIL_LIST; 849 case IIO_CHAN_INFO_SAMP_FREQ: 850 *vals = (int *)st->samp_freq_avail; 851 *length = st->samp_freq_avail_len; 852 *type = IIO_VAL_INT; 853 return IIO_AVAIL_LIST; 854 default: 855 return -EINVAL; 856 } 857 } 858 859 static int __ad7768_write_raw(struct iio_dev *indio_dev, 860 struct iio_chan_spec const *chan, 861 int val, int val2, long info) 862 { 863 struct ad7768_state *st = iio_priv(indio_dev); 864 int ret; 865 866 switch (info) { 867 case IIO_CHAN_INFO_SAMP_FREQ: 868 return ad7768_set_freq(st, val); 869 870 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 871 ret = ad7768_configure_dig_fil(indio_dev, st->filter_type, val); 872 if (ret) 873 return ret; 874 875 /* Update sampling frequency */ 876 return ad7768_set_freq(st, st->samp_freq); 877 default: 878 return -EINVAL; 879 } 880 } 881 882 static int ad7768_write_raw(struct iio_dev *indio_dev, 883 struct iio_chan_spec const *chan, 884 int val, int val2, long info) 885 { 886 int ret; 887 888 if (!iio_device_claim_direct(indio_dev)) 889 return -EBUSY; 890 891 ret = __ad7768_write_raw(indio_dev, chan, val, val2, info); 892 iio_device_release_direct(indio_dev); 893 894 return ret; 895 } 896 897 static int ad7768_read_label(struct iio_dev *indio_dev, 898 const struct iio_chan_spec *chan, char *label) 899 { 900 struct ad7768_state *st = iio_priv(indio_dev); 901 902 return sprintf(label, "%s\n", st->labels[chan->channel]); 903 } 904 905 static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, 906 const struct iio_chan_spec *chan) 907 { 908 struct ad7768_state *st = iio_priv(indio_dev); 909 910 return st->oversampling_ratio == 8 ? 911 AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; 912 } 913 914 static const struct iio_info ad7768_info = { 915 .read_raw = &ad7768_read_raw, 916 .read_avail = &ad7768_read_avail, 917 .write_raw = &ad7768_write_raw, 918 .read_label = ad7768_read_label, 919 .get_current_scan_type = &ad7768_get_current_scan_type, 920 .debugfs_reg_access = &ad7768_reg_access, 921 }; 922 923 static struct fwnode_handle * 924 ad7768_fwnode_find_reference_args(const struct fwnode_handle *fwnode, 925 const char *name, const char *nargs_prop, 926 unsigned int nargs, unsigned int index, 927 struct fwnode_reference_args *args) 928 { 929 int ret; 930 931 ret = fwnode_property_get_reference_args(fwnode, name, nargs_prop, 932 nargs, index, args); 933 return ret ? ERR_PTR(ret) : args->fwnode; 934 } 935 936 static int ad7768_trigger_sources_sync_setup(struct device *dev, 937 struct fwnode_handle *fwnode, 938 struct ad7768_state *st) 939 { 940 struct fwnode_reference_args args; 941 942 struct fwnode_handle *ref __free(fwnode_handle) = 943 ad7768_fwnode_find_reference_args(fwnode, "trigger-sources", 944 "#trigger-source-cells", 0, 945 AD7768_TRIGGER_SOURCE_SYNC_IDX, 946 &args); 947 if (IS_ERR(ref)) 948 return PTR_ERR(ref); 949 950 ref = args.fwnode; 951 /* First, try getting the GPIO trigger source */ 952 if (fwnode_device_is_compatible(ref, "gpio-trigger")) { 953 st->gpio_sync_in = devm_fwnode_gpiod_get_index(dev, ref, NULL, 0, 954 GPIOD_OUT_LOW, 955 "sync-in"); 956 return PTR_ERR_OR_ZERO(st->gpio_sync_in); 957 } 958 959 /* 960 * TODO: Support the other cases when we have a trigger subsystem 961 * to reliably handle other types of devices as trigger sources. 962 * 963 * For now, return an error message. For self triggering, omit the 964 * trigger-sources property. 965 */ 966 return dev_err_probe(dev, -EOPNOTSUPP, "Invalid synchronization trigger source\n"); 967 } 968 969 static int ad7768_trigger_sources_get_sync(struct device *dev, 970 struct ad7768_state *st) 971 { 972 struct fwnode_handle *fwnode = dev_fwnode(dev); 973 974 /* 975 * The AD7768-1 allows two primary methods for driving the SYNC_IN pin 976 * to synchronize one or more devices: 977 * 1. Using an external GPIO. 978 * 2. Using a SPI command, where the SYNC_OUT pin generates a 979 * synchronization pulse that drives the SYNC_IN pin. 980 */ 981 if (fwnode_property_present(fwnode, "trigger-sources")) 982 return ad7768_trigger_sources_sync_setup(dev, fwnode, st); 983 984 /* 985 * In the absence of trigger-sources property, enable self 986 * synchronization over SPI (SYNC_OUT). 987 */ 988 st->en_spi_sync = true; 989 990 return 0; 991 } 992 993 static int ad7768_setup(struct iio_dev *indio_dev) 994 { 995 struct ad7768_state *st = iio_priv(indio_dev); 996 int ret; 997 998 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", 999 GPIOD_OUT_HIGH); 1000 if (IS_ERR(st->gpio_reset)) 1001 return PTR_ERR(st->gpio_reset); 1002 1003 if (st->gpio_reset) { 1004 fsleep(10); 1005 gpiod_set_value_cansleep(st->gpio_reset, 0); 1006 fsleep(200); 1007 } else { 1008 /* 1009 * Two writes to the SPI_RESET[1:0] bits are required to initiate 1010 * a software reset. The bits must first be set to 11, and then 1011 * to 10. When the sequence is detected, the reset occurs. 1012 * See the datasheet, page 70. 1013 */ 1014 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3); 1015 if (ret) 1016 return ret; 1017 1018 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2); 1019 if (ret) 1020 return ret; 1021 } 1022 1023 /* For backwards compatibility, try the adi,sync-in-gpios property */ 1024 st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", 1025 GPIOD_OUT_LOW); 1026 if (IS_ERR(st->gpio_sync_in)) 1027 return PTR_ERR(st->gpio_sync_in); 1028 1029 /* 1030 * If the synchronization is not defined by adi,sync-in-gpios, try the 1031 * trigger-sources. 1032 */ 1033 if (!st->gpio_sync_in) { 1034 ret = ad7768_trigger_sources_get_sync(&st->spi->dev, st); 1035 if (ret) 1036 return ret; 1037 } 1038 1039 /* Only create a Chip GPIO if flagged for it */ 1040 if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { 1041 ret = ad7768_gpio_init(indio_dev); 1042 if (ret) 1043 return ret; 1044 } 1045 1046 /* 1047 * Set Default Digital Filter configuration: 1048 * SINC5 filter with x32 Decimation rate 1049 */ 1050 ret = ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32); 1051 if (ret) 1052 return ret; 1053 1054 /* Set the default sampling frequency to 32000 kSPS */ 1055 return ad7768_set_freq(st, 32000); 1056 } 1057 1058 static irqreturn_t ad7768_trigger_handler(int irq, void *p) 1059 { 1060 struct iio_poll_func *pf = p; 1061 struct iio_dev *indio_dev = pf->indio_dev; 1062 struct ad7768_state *st = iio_priv(indio_dev); 1063 const struct iio_scan_type *scan_type; 1064 int ret; 1065 1066 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1067 if (IS_ERR(scan_type)) 1068 goto out; 1069 1070 ret = spi_read(st->spi, &st->data.scan.chan, 1071 BITS_TO_BYTES(scan_type->realbits)); 1072 if (ret < 0) 1073 goto out; 1074 1075 iio_push_to_buffers_with_ts(indio_dev, &st->data.scan, 1076 sizeof(st->data.scan), 1077 iio_get_time_ns(indio_dev)); 1078 1079 out: 1080 iio_trigger_notify_done(indio_dev->trig); 1081 1082 return IRQ_HANDLED; 1083 } 1084 1085 static irqreturn_t ad7768_interrupt(int irq, void *dev_id) 1086 { 1087 struct iio_dev *indio_dev = dev_id; 1088 struct ad7768_state *st = iio_priv(indio_dev); 1089 1090 if (iio_buffer_enabled(indio_dev)) 1091 iio_trigger_poll(st->trig); 1092 else 1093 complete(&st->completion); 1094 1095 return IRQ_HANDLED; 1096 }; 1097 1098 static int ad7768_buffer_postenable(struct iio_dev *indio_dev) 1099 { 1100 struct ad7768_state *st = iio_priv(indio_dev); 1101 1102 /* 1103 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 1104 * continuous read mode. Subsequent data reads do not require an 1105 * initial 8-bit write to query the ADC_DATA register. 1106 */ 1107 return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01); 1108 } 1109 1110 static int ad7768_buffer_predisable(struct iio_dev *indio_dev) 1111 { 1112 struct ad7768_state *st = iio_priv(indio_dev); 1113 unsigned int unused; 1114 1115 /* 1116 * To exit continuous read mode, perform a single read of the ADC_DATA 1117 * reg (0x2C), which allows further configuration of the device. 1118 */ 1119 return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1120 } 1121 1122 static const struct iio_buffer_setup_ops ad7768_buffer_ops = { 1123 .postenable = &ad7768_buffer_postenable, 1124 .predisable = &ad7768_buffer_predisable, 1125 }; 1126 1127 static const struct iio_trigger_ops ad7768_trigger_ops = { 1128 .validate_device = iio_trigger_validate_own_device, 1129 }; 1130 1131 static int ad7768_set_channel_label(struct iio_dev *indio_dev, 1132 int num_channels) 1133 { 1134 struct ad7768_state *st = iio_priv(indio_dev); 1135 struct device *device = indio_dev->dev.parent; 1136 const char *label; 1137 int crt_ch = 0; 1138 1139 device_for_each_child_node_scoped(device, child) { 1140 if (fwnode_property_read_u32(child, "reg", &crt_ch)) 1141 continue; 1142 1143 if (crt_ch >= num_channels) 1144 continue; 1145 1146 if (fwnode_property_read_string(child, "label", &label)) 1147 continue; 1148 1149 st->labels[crt_ch] = label; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev) 1156 { 1157 struct ad7768_state *st = iio_priv(indio_dev); 1158 int ret; 1159 1160 st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", 1161 indio_dev->name, 1162 iio_device_id(indio_dev)); 1163 if (!st->trig) 1164 return -ENOMEM; 1165 1166 st->trig->ops = &ad7768_trigger_ops; 1167 iio_trigger_set_drvdata(st->trig, indio_dev); 1168 ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig); 1169 if (ret) 1170 return ret; 1171 1172 indio_dev->trig = iio_trigger_get(st->trig); 1173 1174 return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, 1175 &iio_pollfunc_store_time, 1176 &ad7768_trigger_handler, 1177 &ad7768_buffer_ops); 1178 } 1179 1180 static int ad7768_vcm_enable(struct regulator_dev *rdev) 1181 { 1182 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1183 struct ad7768_state *st = iio_priv(indio_dev); 1184 int ret, regval; 1185 1186 if (!iio_device_claim_direct(indio_dev)) 1187 return -EBUSY; 1188 1189 /* To enable, set the last selected output */ 1190 regval = AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1); 1191 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1192 AD7768_REG_ANALOG2_VCM_MSK, regval); 1193 iio_device_release_direct(indio_dev); 1194 1195 return ret; 1196 } 1197 1198 static int ad7768_vcm_disable(struct regulator_dev *rdev) 1199 { 1200 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1201 struct ad7768_state *st = iio_priv(indio_dev); 1202 int ret; 1203 1204 if (!iio_device_claim_direct(indio_dev)) 1205 return -EBUSY; 1206 1207 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1208 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1209 iio_device_release_direct(indio_dev); 1210 1211 return ret; 1212 } 1213 1214 static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) 1215 { 1216 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1217 struct ad7768_state *st = iio_priv(indio_dev); 1218 int ret, val; 1219 1220 if (!iio_device_claim_direct(indio_dev)) 1221 return -EBUSY; 1222 1223 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1224 iio_device_release_direct(indio_dev); 1225 if (ret) 1226 return ret; 1227 1228 return FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val) != AD7768_VCM_OFF; 1229 } 1230 1231 static int ad7768_set_voltage_sel(struct regulator_dev *rdev, 1232 unsigned int selector) 1233 { 1234 unsigned int regval = AD7768_REG_ANALOG2_VCM(selector + 1); 1235 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1236 struct ad7768_state *st = iio_priv(indio_dev); 1237 int ret; 1238 1239 if (!iio_device_claim_direct(indio_dev)) 1240 return -EBUSY; 1241 1242 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1243 AD7768_REG_ANALOG2_VCM_MSK, regval); 1244 iio_device_release_direct(indio_dev); 1245 if (ret) 1246 return ret; 1247 1248 st->vcm_output_sel = selector; 1249 1250 return 0; 1251 } 1252 1253 static int ad7768_get_voltage_sel(struct regulator_dev *rdev) 1254 { 1255 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1256 struct ad7768_state *st = iio_priv(indio_dev); 1257 int ret, val; 1258 1259 if (!iio_device_claim_direct(indio_dev)) 1260 return -EBUSY; 1261 1262 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1263 iio_device_release_direct(indio_dev); 1264 if (ret) 1265 return ret; 1266 1267 val = FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val); 1268 1269 return clamp(val, 1, rdev->desc->n_voltages) - 1; 1270 } 1271 1272 static const struct regulator_ops vcm_regulator_ops = { 1273 .enable = ad7768_vcm_enable, 1274 .disable = ad7768_vcm_disable, 1275 .is_enabled = ad7768_vcm_is_enabled, 1276 .list_voltage = regulator_list_voltage_table, 1277 .set_voltage_sel = ad7768_set_voltage_sel, 1278 .get_voltage_sel = ad7768_get_voltage_sel, 1279 }; 1280 1281 static const unsigned int vcm_voltage_table[] = { 1282 2500000, 1283 2050000, 1284 1650000, 1285 1900000, 1286 1100000, 1287 900000, 1288 }; 1289 1290 static const struct regulator_desc vcm_desc = { 1291 .name = "ad7768-1-vcm", 1292 .of_match = "vcm-output", 1293 .regulators_node = "regulators", 1294 .n_voltages = ARRAY_SIZE(vcm_voltage_table), 1295 .volt_table = vcm_voltage_table, 1296 .ops = &vcm_regulator_ops, 1297 .type = REGULATOR_VOLTAGE, 1298 .owner = THIS_MODULE, 1299 }; 1300 1301 static int ad7768_register_regulators(struct device *dev, struct ad7768_state *st, 1302 struct iio_dev *indio_dev) 1303 { 1304 struct regulator_config config = { 1305 .dev = dev, 1306 .driver_data = indio_dev, 1307 }; 1308 int ret; 1309 1310 /* Disable the regulator before registering it */ 1311 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1312 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1313 if (ret) 1314 return ret; 1315 1316 st->vcm_rdev = devm_regulator_register(dev, &vcm_desc, &config); 1317 if (IS_ERR(st->vcm_rdev)) 1318 return dev_err_probe(dev, PTR_ERR(st->vcm_rdev), 1319 "failed to register VCM regulator\n"); 1320 1321 return 0; 1322 } 1323 1324 static int ad7768_probe(struct spi_device *spi) 1325 { 1326 struct ad7768_state *st; 1327 struct iio_dev *indio_dev; 1328 int ret; 1329 1330 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1331 if (!indio_dev) 1332 return -ENOMEM; 1333 1334 st = iio_priv(indio_dev); 1335 /* 1336 * Datasheet recommends SDI line to be kept high when data is not being 1337 * clocked out of the controller and the spi clock is free running, 1338 * to prevent accidental reset. 1339 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag 1340 * yet, only request the MOSI idle state to enable if the controller 1341 * supports it. 1342 */ 1343 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) { 1344 spi->mode |= SPI_MOSI_IDLE_HIGH; 1345 ret = spi_setup(spi); 1346 if (ret < 0) 1347 return ret; 1348 } 1349 1350 st->spi = spi; 1351 1352 st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config); 1353 if (IS_ERR(st->regmap)) 1354 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), 1355 "Failed to initialize regmap"); 1356 1357 st->regmap24 = devm_regmap_init_spi(spi, &ad7768_regmap24_config); 1358 if (IS_ERR(st->regmap24)) 1359 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap24), 1360 "Failed to initialize regmap24"); 1361 1362 ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); 1363 if (ret < 0) 1364 return dev_err_probe(&spi->dev, ret, 1365 "Failed to get VREF voltage\n"); 1366 st->vref_uv = ret; 1367 1368 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 1369 if (IS_ERR(st->mclk)) 1370 return PTR_ERR(st->mclk); 1371 1372 st->mclk_freq = clk_get_rate(st->mclk); 1373 1374 indio_dev->channels = ad7768_channels; 1375 indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); 1376 indio_dev->name = spi_get_device_id(spi)->name; 1377 indio_dev->info = &ad7768_info; 1378 indio_dev->modes = INDIO_DIRECT_MODE; 1379 1380 /* Register VCM output regulator */ 1381 ret = ad7768_register_regulators(&spi->dev, st, indio_dev); 1382 if (ret) 1383 return ret; 1384 1385 ret = ad7768_setup(indio_dev); 1386 if (ret < 0) { 1387 dev_err(&spi->dev, "AD7768 setup failed\n"); 1388 return ret; 1389 } 1390 1391 init_completion(&st->completion); 1392 1393 ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels)); 1394 if (ret) 1395 return ret; 1396 1397 ret = devm_request_irq(&spi->dev, spi->irq, 1398 &ad7768_interrupt, 1399 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1400 indio_dev->name, indio_dev); 1401 if (ret) 1402 return ret; 1403 1404 ret = ad7768_triggered_buffer_alloc(indio_dev); 1405 if (ret) 1406 return ret; 1407 1408 return devm_iio_device_register(&spi->dev, indio_dev); 1409 } 1410 1411 static const struct spi_device_id ad7768_id_table[] = { 1412 { "ad7768-1", 0 }, 1413 { } 1414 }; 1415 MODULE_DEVICE_TABLE(spi, ad7768_id_table); 1416 1417 static const struct of_device_id ad7768_of_match[] = { 1418 { .compatible = "adi,ad7768-1" }, 1419 { } 1420 }; 1421 MODULE_DEVICE_TABLE(of, ad7768_of_match); 1422 1423 static struct spi_driver ad7768_driver = { 1424 .driver = { 1425 .name = "ad7768-1", 1426 .of_match_table = ad7768_of_match, 1427 }, 1428 .probe = ad7768_probe, 1429 .id_table = ad7768_id_table, 1430 }; 1431 module_spi_driver(ad7768_driver); 1432 1433 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1434 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 1435 MODULE_LICENSE("GPL v2"); 1436