1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7768-1 SPI ADC driver 4 * 5 * Copyright 2017 Analog Devices Inc. 6 */ 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/interrupt.h> 18 #include <linux/limits.h> 19 #include <linux/math.h> 20 #include <linux/minmax.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/rational.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/sysfs.h> 28 #include <linux/spi/spi.h> 29 #include <linux/unaligned.h> 30 #include <linux/units.h> 31 #include <linux/util_macros.h> 32 33 #include <linux/iio/buffer.h> 34 #include <linux/iio/iio.h> 35 #include <linux/iio/sysfs.h> 36 #include <linux/iio/trigger.h> 37 #include <linux/iio/triggered_buffer.h> 38 #include <linux/iio/trigger_consumer.h> 39 40 #include <dt-bindings/iio/adc/adi,ad7768-1.h> 41 42 /* AD7768 registers definition */ 43 #define AD7768_REG_CHIP_TYPE 0x3 44 #define AD7768_REG_PROD_ID_L 0x4 45 #define AD7768_REG_PROD_ID_H 0x5 46 #define AD7768_REG_CHIP_GRADE 0x6 47 #define AD7768_REG_SCRATCH_PAD 0x0A 48 #define AD7768_REG_VENDOR_L 0x0C 49 #define AD7768_REG_VENDOR_H 0x0D 50 #define AD7768_REG_INTERFACE_FORMAT 0x14 51 #define AD7768_REG_POWER_CLOCK 0x15 52 #define AD7768_REG_ANALOG 0x16 53 #define AD7768_REG_ANALOG2 0x17 54 #define AD7768_REG_CONVERSION 0x18 55 #define AD7768_REG_DIGITAL_FILTER 0x19 56 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A 57 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B 58 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C 59 #define AD7768_REG_SYNC_RESET 0x1D 60 #define AD7768_REG_GPIO_CONTROL 0x1E 61 #define AD7768_REG_GPIO_WRITE 0x1F 62 #define AD7768_REG_GPIO_READ 0x20 63 #define AD7768_REG_OFFSET_HI 0x21 64 #define AD7768_REG_OFFSET_MID 0x22 65 #define AD7768_REG_OFFSET_LO 0x23 66 #define AD7768_REG_GAIN_HI 0x24 67 #define AD7768_REG_GAIN_MID 0x25 68 #define AD7768_REG_GAIN_LO 0x26 69 #define AD7768_REG_SPI_DIAG_ENABLE 0x28 70 #define AD7768_REG_ADC_DIAG_ENABLE 0x29 71 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A 72 #define AD7768_REG24_ADC_DATA 0x2C 73 #define AD7768_REG_MASTER_STATUS 0x2D 74 #define AD7768_REG_SPI_DIAG_STATUS 0x2E 75 #define AD7768_REG_ADC_DIAG_STATUS 0x2F 76 #define AD7768_REG_DIG_DIAG_STATUS 0x30 77 #define AD7768_REG_MCLK_COUNTER 0x31 78 #define AD7768_REG_COEFF_CONTROL 0x32 79 #define AD7768_REG24_COEFF_DATA 0x33 80 #define AD7768_REG_ACCESS_KEY 0x34 81 82 /* AD7768_REG_POWER_CLOCK */ 83 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) 84 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) 85 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) 86 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 87 88 /* AD7768_REG_DIGITAL_FILTER */ 89 #define AD7768_DIG_FIL_EN_60HZ_REJ BIT(7) 90 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 91 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 92 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) 93 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) 94 95 /* AD7768_REG_CONVERSION */ 96 #define AD7768_CONV_MODE_MSK GENMASK(2, 0) 97 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 98 99 /* AD7768_REG_ANALOG2 */ 100 #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) 101 #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (x)) 102 103 /* AD7768_REG_GPIO_CONTROL */ 104 #define AD7768_GPIO_UNIVERSAL_EN BIT(7) 105 #define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) 106 107 /* AD7768_REG_GPIO_WRITE */ 108 #define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) 109 110 /* AD7768_REG_GPIO_READ */ 111 #define AD7768_GPIO_READ_MSK GENMASK(3, 0) 112 113 #define AD7768_VCM_OFF 0x07 114 115 #define ADAQ776X_GAIN_MAX_NANO (128 * NANO) 116 #define ADAQ776X_MAX_GAIN_MODES 8 117 118 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 119 120 #define AD7768_MAX_CHANNELS 1 121 122 #define ADAQ7768_PGA_PINS 3 123 124 enum ad7768_conv_mode { 125 AD7768_CONTINUOUS, 126 AD7768_ONE_SHOT, 127 AD7768_SINGLE, 128 AD7768_PERIODIC, 129 AD7768_STANDBY 130 }; 131 132 enum ad7768_pwrmode { 133 AD7768_ECO_MODE = 0, 134 AD7768_MED_MODE = 2, 135 AD7768_FAST_MODE = 3 136 }; 137 138 enum ad7768_mclk_div { 139 AD7768_MCLK_DIV_16, 140 AD7768_MCLK_DIV_8, 141 AD7768_MCLK_DIV_4, 142 AD7768_MCLK_DIV_2 143 }; 144 145 enum ad7768_filter_type { 146 AD7768_FILTER_SINC5, 147 AD7768_FILTER_SINC3, 148 AD7768_FILTER_WIDEBAND, 149 AD7768_FILTER_SINC3_REJ60, 150 }; 151 152 enum ad7768_filter_regval { 153 AD7768_FILTER_REGVAL_SINC5 = 0, 154 AD7768_FILTER_REGVAL_SINC5_X8 = 1, 155 AD7768_FILTER_REGVAL_SINC5_X16 = 2, 156 AD7768_FILTER_REGVAL_SINC3 = 3, 157 AD7768_FILTER_REGVAL_WIDEBAND = 4, 158 AD7768_FILTER_REGVAL_SINC3_REJ60 = 11, 159 }; 160 161 enum ad7768_scan_type { 162 AD7768_SCAN_TYPE_NORMAL, 163 AD7768_SCAN_TYPE_HIGH_SPEED, 164 }; 165 166 enum { 167 AD7768_PGA_GAIN_0, 168 AD7768_PGA_GAIN_1, 169 AD7768_PGA_GAIN_2, 170 AD7768_PGA_GAIN_3, 171 AD7768_PGA_GAIN_4, 172 AD7768_PGA_GAIN_5, 173 AD7768_PGA_GAIN_6, 174 AD7768_PGA_GAIN_7, 175 }; 176 177 enum { 178 AD7768_AAF_IN1, 179 AD7768_AAF_IN2, 180 AD7768_AAF_IN3, 181 }; 182 183 /* PGA and AAF gains in V/V */ 184 static const int adaq7768_gains[] = { 185 [AD7768_PGA_GAIN_0] = 325, /* 0.325 */ 186 [AD7768_PGA_GAIN_1] = 650, /* 0.650 */ 187 [AD7768_PGA_GAIN_2] = 1300, /* 1.300 */ 188 [AD7768_PGA_GAIN_3] = 2600, /* 2.600 */ 189 [AD7768_PGA_GAIN_4] = 5200, /* 5.200 */ 190 [AD7768_PGA_GAIN_5] = 10400, /* 10.400 */ 191 [AD7768_PGA_GAIN_6] = 20800, /* 20.800 */ 192 }; 193 194 static const int adaq7769_gains[] = { 195 [AD7768_PGA_GAIN_0] = 1000, /* 1.000 */ 196 [AD7768_PGA_GAIN_1] = 2000, /* 2.000 */ 197 [AD7768_PGA_GAIN_2] = 4000, /* 4.000 */ 198 [AD7768_PGA_GAIN_3] = 8000, /* 8.000 */ 199 [AD7768_PGA_GAIN_4] = 16000, /* 16.000 */ 200 [AD7768_PGA_GAIN_5] = 32000, /* 32.000 */ 201 [AD7768_PGA_GAIN_6] = 64000, /* 64.000 */ 202 [AD7768_PGA_GAIN_7] = 128000, /* 128.000 */ 203 }; 204 205 static const int ad7768_aaf_gains_bp[] = { 206 [AD7768_AAF_IN1] = 10000, /* 1.000 */ 207 [AD7768_AAF_IN2] = 3640, /* 0.364 */ 208 [AD7768_AAF_IN3] = 1430, /* 0.143 */ 209 }; 210 211 /* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */ 212 static const int ad7768_filter_3db_odr_multiplier[] = { 213 [AD7768_FILTER_SINC5] = 204, /* 0.204 */ 214 [AD7768_FILTER_SINC3] = 262, /* 0.2617 */ 215 [AD7768_FILTER_SINC3_REJ60] = 262, /* 0.2617 */ 216 [AD7768_FILTER_WIDEBAND] = 433, /* 0.433 */ 217 }; 218 219 static const int ad7768_mclk_div_rates[] = { 220 16, 8, 4, 2, 221 }; 222 223 static const int ad7768_dec_rate_values[8] = { 224 8, 16, 32, 64, 128, 256, 512, 1024, 225 }; 226 227 /* Decimation rate range for sinc3 filter */ 228 static const int ad7768_sinc3_dec_rate_range[3] = { 229 32, 32, 163840, 230 }; 231 232 /* 233 * The AD7768-1 supports three primary filter types: 234 * Sinc5, Sinc3, and Wideband. 235 * However, the filter register values can also encode additional parameters 236 * such as decimation rates and 60Hz rejection. This utility array separates 237 * the filter type from these parameters. 238 */ 239 static const int ad7768_filter_regval_to_type[] = { 240 [AD7768_FILTER_REGVAL_SINC5] = AD7768_FILTER_SINC5, 241 [AD7768_FILTER_REGVAL_SINC5_X8] = AD7768_FILTER_SINC5, 242 [AD7768_FILTER_REGVAL_SINC5_X16] = AD7768_FILTER_SINC5, 243 [AD7768_FILTER_REGVAL_SINC3] = AD7768_FILTER_SINC3, 244 [AD7768_FILTER_REGVAL_WIDEBAND] = AD7768_FILTER_WIDEBAND, 245 [AD7768_FILTER_REGVAL_SINC3_REJ60] = AD7768_FILTER_SINC3_REJ60, 246 }; 247 248 static const char * const ad7768_filter_enum[] = { 249 [AD7768_FILTER_SINC5] = "sinc5", 250 [AD7768_FILTER_SINC3] = "sinc3", 251 [AD7768_FILTER_WIDEBAND] = "wideband", 252 [AD7768_FILTER_SINC3_REJ60] = "sinc3+rej60", 253 }; 254 255 static const struct iio_scan_type ad7768_scan_type[] = { 256 [AD7768_SCAN_TYPE_NORMAL] = { 257 .sign = 's', 258 .realbits = 24, 259 .storagebits = 32, 260 .shift = 8, 261 .endianness = IIO_BE, 262 }, 263 [AD7768_SCAN_TYPE_HIGH_SPEED] = { 264 .sign = 's', 265 .realbits = 16, 266 .storagebits = 16, 267 .endianness = IIO_BE, 268 }, 269 }; 270 271 struct ad7768_chip_info { 272 const char *name; 273 const struct iio_chan_spec *channel_spec; 274 int num_channels; 275 const int *pga_gains; 276 int num_pga_modes; 277 int default_pga_mode; 278 int pgia_mode2pin_offset; 279 bool has_pga; 280 bool has_variable_aaf; 281 bool has_vcm_regulator; 282 }; 283 284 struct ad7768_state { 285 struct spi_device *spi; 286 struct regmap *regmap; 287 struct regmap *regmap24; 288 int vref_uv; 289 struct regulator_dev *vcm_rdev; 290 unsigned int vcm_output_sel; 291 struct clk *mclk; 292 unsigned int mclk_freq; 293 unsigned int mclk_div; 294 unsigned int oversampling_ratio; 295 enum ad7768_filter_type filter_type; 296 unsigned int samp_freq; 297 unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; 298 unsigned int samp_freq_avail_len; 299 unsigned int pga_gain_mode; 300 unsigned int aaf_gain; 301 int scale_tbl[ADAQ776X_MAX_GAIN_MODES][2]; 302 struct completion completion; 303 struct iio_trigger *trig; 304 struct gpio_descs *pga_gpios; 305 struct gpio_desc *gpio_sync_in; 306 struct gpio_desc *gpio_reset; 307 const char *labels[AD7768_MAX_CHANNELS]; 308 struct gpio_chip gpiochip; 309 const struct ad7768_chip_info *chip; 310 bool en_spi_sync; 311 struct mutex pga_lock; /* protect device internal state (PGA) */ 312 /* 313 * DMA (thus cache coherency maintenance) may require the 314 * transfer buffers to live in their own cache lines. 315 */ 316 union { 317 struct { 318 __be32 chan; 319 aligned_s64 timestamp; 320 } scan; 321 __be32 d32; 322 u8 d8[2]; 323 } data __aligned(IIO_DMA_MINALIGN); 324 }; 325 326 static const struct regmap_range ad7768_regmap_rd_ranges[] = { 327 regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE), 328 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 329 regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H), 330 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO), 331 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 332 regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL), 333 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 334 }; 335 336 static const struct regmap_access_table ad7768_regmap_rd_table = { 337 .yes_ranges = ad7768_regmap_rd_ranges, 338 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges), 339 }; 340 341 static const struct regmap_range ad7768_regmap_wr_ranges[] = { 342 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD), 343 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE), 344 regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO), 345 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE), 346 regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS), 347 regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL), 348 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY), 349 }; 350 351 static const struct regmap_access_table ad7768_regmap_wr_table = { 352 .yes_ranges = ad7768_regmap_wr_ranges, 353 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges), 354 }; 355 356 static const struct regmap_config ad7768_regmap_config = { 357 .name = "ad7768-1-8", 358 .reg_bits = 8, 359 .val_bits = 8, 360 .read_flag_mask = BIT(6), 361 .rd_table = &ad7768_regmap_rd_table, 362 .wr_table = &ad7768_regmap_wr_table, 363 .max_register = AD7768_REG_ACCESS_KEY, 364 .use_single_write = true, 365 .use_single_read = true, 366 }; 367 368 static const struct regmap_range ad7768_regmap24_rd_ranges[] = { 369 regmap_reg_range(AD7768_REG24_ADC_DATA, AD7768_REG24_ADC_DATA), 370 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 371 }; 372 373 static const struct regmap_access_table ad7768_regmap24_rd_table = { 374 .yes_ranges = ad7768_regmap24_rd_ranges, 375 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_rd_ranges), 376 }; 377 378 static const struct regmap_range ad7768_regmap24_wr_ranges[] = { 379 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA), 380 }; 381 382 static const struct regmap_access_table ad7768_regmap24_wr_table = { 383 .yes_ranges = ad7768_regmap24_wr_ranges, 384 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_wr_ranges), 385 }; 386 387 static const struct regmap_config ad7768_regmap24_config = { 388 .name = "ad7768-1-24", 389 .reg_bits = 8, 390 .val_bits = 24, 391 .read_flag_mask = BIT(6), 392 .rd_table = &ad7768_regmap24_rd_table, 393 .wr_table = &ad7768_regmap24_wr_table, 394 .max_register = AD7768_REG24_COEFF_DATA, 395 }; 396 397 static int ad7768_send_sync_pulse(struct ad7768_state *st) 398 { 399 if (st->en_spi_sync) 400 return regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x00); 401 402 /* 403 * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, 404 * where Tmclk is the MCLK period. The supported MCLK frequencies range 405 * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse 406 * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). 407 * 408 * Add a delay to ensure the pulse width is always sufficient to 409 * trigger synchronization. 410 */ 411 gpiod_set_value_cansleep(st->gpio_sync_in, 1); 412 fsleep(3); 413 gpiod_set_value_cansleep(st->gpio_sync_in, 0); 414 415 return 0; 416 } 417 418 static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) 419 { 420 unsigned int i, samp_freq_avail, freq_filtered; 421 unsigned int len = 0; 422 423 freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio); 424 for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { 425 samp_freq_avail = DIV_ROUND_CLOSEST(freq_filtered, ad7768_mclk_div_rates[i]); 426 /* Sampling frequency cannot be lower than the minimum of 50 SPS */ 427 if (samp_freq_avail < 50) 428 continue; 429 430 st->samp_freq_avail[len++] = samp_freq_avail; 431 } 432 433 st->samp_freq_avail_len = len; 434 } 435 436 static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div) 437 { 438 unsigned int mclk_div_value; 439 440 mclk_div_value = AD7768_PWR_MCLK_DIV(mclk_div); 441 /* 442 * Set power mode based on mclk_div value. 443 * ECO_MODE is only recommended for MCLK_DIV = 16. 444 */ 445 mclk_div_value |= mclk_div > AD7768_MCLK_DIV_16 ? 446 AD7768_PWR_PWRMODE(AD7768_FAST_MODE) : 447 AD7768_PWR_PWRMODE(AD7768_ECO_MODE); 448 449 return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK, 450 AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK, 451 mclk_div_value); 452 } 453 454 static int ad7768_set_mode(struct ad7768_state *st, 455 enum ad7768_conv_mode mode) 456 { 457 return regmap_update_bits(st->regmap, AD7768_REG_CONVERSION, 458 AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode)); 459 } 460 461 static int ad7768_scan_direct(struct iio_dev *indio_dev) 462 { 463 struct ad7768_state *st = iio_priv(indio_dev); 464 int readval, ret; 465 466 reinit_completion(&st->completion); 467 468 ret = ad7768_set_mode(st, AD7768_ONE_SHOT); 469 if (ret < 0) 470 return ret; 471 472 ret = wait_for_completion_timeout(&st->completion, 473 msecs_to_jiffies(1000)); 474 if (!ret) 475 return -ETIMEDOUT; 476 477 ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval); 478 if (ret) 479 return ret; 480 481 /* 482 * When the decimation rate is set to x8, the ADC data precision is 483 * reduced from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA 484 * register provides 24-bit data, the precision is reduced by 485 * right-shifting the read value by 8 bits. 486 */ 487 if (st->oversampling_ratio == 8) 488 readval >>= 8; 489 490 /* 491 * Any SPI configuration of the AD7768-1 can only be 492 * performed in continuous conversion mode. 493 */ 494 ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 495 if (ret < 0) 496 return ret; 497 498 return readval; 499 } 500 501 static int ad7768_reg_access(struct iio_dev *indio_dev, 502 unsigned int reg, 503 unsigned int writeval, 504 unsigned int *readval) 505 { 506 struct ad7768_state *st = iio_priv(indio_dev); 507 int ret; 508 509 if (!iio_device_claim_direct(indio_dev)) 510 return -EBUSY; 511 512 ret = -EINVAL; 513 if (readval) { 514 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_rd_table)) 515 ret = regmap_read(st->regmap, reg, readval); 516 517 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_rd_table)) 518 ret = regmap_read(st->regmap24, reg, readval); 519 520 } else { 521 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_wr_table)) 522 ret = regmap_write(st->regmap, reg, writeval); 523 524 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_wr_table)) 525 ret = regmap_write(st->regmap24, reg, writeval); 526 527 } 528 529 iio_device_release_direct(indio_dev); 530 531 return ret; 532 } 533 534 static int ad7768_fill_scale_tbl(struct iio_dev *dev) 535 { 536 struct ad7768_state *st = iio_priv(dev); 537 const struct iio_scan_type *scan_type; 538 int val, val2, tmp0, tmp1, i; 539 struct u32_fract fract; 540 unsigned long n, d; 541 u64 tmp2; 542 543 scan_type = iio_get_current_scan_type(dev, &dev->channels[0]); 544 if (IS_ERR(scan_type)) { 545 dev_err(&st->spi->dev, "Failed to get scan type.\n"); 546 return PTR_ERR(scan_type); 547 } 548 549 if (scan_type->sign == 's') 550 val2 = scan_type->realbits - 1; 551 else 552 val2 = scan_type->realbits; 553 554 for (i = 0; i < st->chip->num_pga_modes; i++) { 555 /* Convert gain to a fraction format */ 556 fract.numerator = st->chip->pga_gains[i]; 557 fract.denominator = MILLI; 558 if (st->chip->has_variable_aaf) { 559 fract.numerator *= ad7768_aaf_gains_bp[st->aaf_gain]; 560 fract.denominator *= PERMYRIAD; 561 } 562 563 rational_best_approximation(fract.numerator, fract.denominator, 564 INT_MAX, INT_MAX, &n, &d); 565 566 val = mult_frac(st->vref_uv, d, n); 567 /* Would multiply by NANO here, but value is already in milli */ 568 tmp2 = ((u64)val * MICRO) >> val2; 569 tmp0 = div_u64_rem(tmp2, NANO, &tmp1); 570 st->scale_tbl[i][0] = tmp0; /* Integer part */ 571 st->scale_tbl[i][1] = abs(tmp1); /* Fractional part */ 572 } 573 574 return 0; 575 } 576 577 static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, 578 unsigned int dec_rate) 579 { 580 unsigned int max_dec_rate; 581 u8 dec_rate_reg[2]; 582 u16 regval; 583 int ret; 584 585 /* 586 * Maximum dec_rate is limited by the MCLK_DIV value and by the ODR. 587 * The edge case is for MCLK_DIV = 2, ODR = 50 SPS. 588 * max_dec_rate <= MCLK / (2 * 50) 589 */ 590 max_dec_rate = st->mclk_freq / 100; 591 dec_rate = clamp(dec_rate, 32, max_dec_rate); 592 /* 593 * Calculate the equivalent value to sinc3 decimation ratio 594 * to be written on the SINC3_DEC_RATE register: 595 * Value = (DEC_RATE / 32) - 1 596 */ 597 dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1; 598 599 /* 600 * The SINC3_DEC_RATE value is a 13-bit value split across two 601 * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using 602 * FIELD_PREP() and store it with the right endianness in dec_rate_reg. 603 */ 604 regval = FIELD_PREP(GENMASK(12, 0), dec_rate); 605 put_unaligned_be16(regval, dec_rate_reg); 606 ret = regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, 607 dec_rate_reg, 2); 608 if (ret) 609 return ret; 610 611 st->oversampling_ratio = (dec_rate + 1) * 32; 612 613 return 0; 614 } 615 616 static int ad7768_configure_dig_fil(struct iio_dev *dev, 617 enum ad7768_filter_type filter_type, 618 unsigned int dec_rate) 619 { 620 struct ad7768_state *st = iio_priv(dev); 621 unsigned int dec_rate_idx, dig_filter_regval; 622 int ret; 623 624 switch (filter_type) { 625 case AD7768_FILTER_SINC3: 626 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3); 627 break; 628 case AD7768_FILTER_SINC3_REJ60: 629 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3) | 630 AD7768_DIG_FIL_EN_60HZ_REJ; 631 break; 632 case AD7768_FILTER_WIDEBAND: 633 /* Skip decimations 8 and 16, not supported by the wideband filter */ 634 dec_rate_idx = find_closest(dec_rate, &ad7768_dec_rate_values[2], 635 ARRAY_SIZE(ad7768_dec_rate_values) - 2); 636 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) | 637 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx); 638 /* Correct the index offset */ 639 dec_rate_idx += 2; 640 break; 641 case AD7768_FILTER_SINC5: 642 dec_rate_idx = find_closest(dec_rate, ad7768_dec_rate_values, 643 ARRAY_SIZE(ad7768_dec_rate_values)); 644 645 /* 646 * Decimations 8 (idx 0) and 16 (idx 1) are set in the 647 * FILTER[6:4] field. The other decimations are set in the 648 * DEC_RATE[2:0] field, and the idx needs to be offsetted by two. 649 */ 650 if (dec_rate_idx == 0) 651 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8); 652 else if (dec_rate_idx == 1) 653 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16); 654 else 655 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) | 656 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2); 657 break; 658 } 659 660 ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_regval); 661 if (ret) 662 return ret; 663 664 st->filter_type = filter_type; 665 /* 666 * The decimation for SINC3 filters are configured in different 667 * registers. 668 */ 669 if (filter_type == AD7768_FILTER_SINC3 || 670 filter_type == AD7768_FILTER_SINC3_REJ60) { 671 ret = ad7768_set_sinc3_dec_rate(st, dec_rate); 672 if (ret) 673 return ret; 674 } else { 675 st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx]; 676 } 677 678 /* Update scale table: scale values vary according to the precision */ 679 ret = ad7768_fill_scale_tbl(dev); 680 if (ret) 681 return ret; 682 683 ad7768_fill_samp_freq_tbl(st); 684 685 /* A sync-in pulse is required after every configuration change */ 686 return ad7768_send_sync_pulse(st); 687 } 688 689 static int ad7768_setup_pga(struct device *dev, struct ad7768_state *st) 690 { 691 st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); 692 if (IS_ERR(st->pga_gpios)) 693 return dev_err_probe(dev, PTR_ERR(st->pga_gpios), 694 "Failed to get PGA gpios.\n"); 695 696 if (st->pga_gpios->ndescs != ADAQ7768_PGA_PINS) 697 return dev_err_probe(dev, -EINVAL, 698 "Expected %d GPIOs for PGA control.\n", 699 ADAQ7768_PGA_PINS); 700 return 0; 701 } 702 703 static int ad7768_calc_pga_gain(struct ad7768_state *st, int gain_int, 704 int gain_fract, int precision) 705 { 706 u64 gain_nano; 707 u32 tmp; 708 709 gain_nano = gain_int * NANO + gain_fract; 710 gain_nano = clamp(gain_nano, 0, ADAQ776X_GAIN_MAX_NANO); 711 tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << precision, NANO); 712 gain_nano = DIV_ROUND_CLOSEST(st->vref_uv, tmp); 713 if (st->chip->has_variable_aaf) 714 gain_nano = DIV_ROUND_CLOSEST_ULL(gain_nano * PERMYRIAD, 715 ad7768_aaf_gains_bp[st->aaf_gain]); 716 717 return find_closest(gain_nano, st->chip->pga_gains, 718 (int)st->chip->num_pga_modes); 719 } 720 721 static int ad7768_set_pga_gain(struct ad7768_state *st, 722 int gain_mode) 723 { 724 int pgia_pins_value = abs(gain_mode - st->chip->pgia_mode2pin_offset); 725 DECLARE_BITMAP(bitmap, ADAQ7768_PGA_PINS) = { }; 726 int ret; 727 728 guard(mutex)(&st->pga_lock); 729 730 bitmap_write(bitmap, pgia_pins_value, 0, ADAQ7768_PGA_PINS); 731 ret = gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); 732 if (ret) 733 return ret; 734 735 st->pga_gain_mode = gain_mode; 736 737 return 0; 738 } 739 740 static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 741 { 742 struct iio_dev *indio_dev = gpiochip_get_data(chip); 743 struct ad7768_state *st = iio_priv(indio_dev); 744 int ret; 745 746 if (!iio_device_claim_direct(indio_dev)) 747 return -EBUSY; 748 749 ret = regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 750 BIT(offset)); 751 iio_device_release_direct(indio_dev); 752 753 return ret; 754 } 755 756 static int ad7768_gpio_direction_output(struct gpio_chip *chip, 757 unsigned int offset, int value) 758 { 759 struct iio_dev *indio_dev = gpiochip_get_data(chip); 760 struct ad7768_state *st = iio_priv(indio_dev); 761 int ret; 762 763 if (!iio_device_claim_direct(indio_dev)) 764 return -EBUSY; 765 766 ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, 767 BIT(offset)); 768 iio_device_release_direct(indio_dev); 769 770 return ret; 771 } 772 773 static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) 774 { 775 struct iio_dev *indio_dev = gpiochip_get_data(chip); 776 struct ad7768_state *st = iio_priv(indio_dev); 777 unsigned int val; 778 int ret; 779 780 if (!iio_device_claim_direct(indio_dev)) 781 return -EBUSY; 782 783 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 784 if (ret) 785 goto err_release; 786 787 /* 788 * If the GPIO is configured as an output, read the current value from 789 * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from 790 * AD7768_REG_GPIO_READ. 791 */ 792 if (val & BIT(offset)) 793 ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); 794 else 795 ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); 796 if (ret) 797 goto err_release; 798 799 ret = !!(val & BIT(offset)); 800 err_release: 801 iio_device_release_direct(indio_dev); 802 803 return ret; 804 } 805 806 static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 807 { 808 struct iio_dev *indio_dev = gpiochip_get_data(chip); 809 struct ad7768_state *st = iio_priv(indio_dev); 810 unsigned int val; 811 int ret; 812 813 if (!iio_device_claim_direct(indio_dev)) 814 return -EBUSY; 815 816 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); 817 if (ret) 818 goto err_release; 819 820 if (val & BIT(offset)) 821 ret = regmap_assign_bits(st->regmap, AD7768_REG_GPIO_WRITE, 822 BIT(offset), value); 823 824 err_release: 825 iio_device_release_direct(indio_dev); 826 827 return ret; 828 } 829 830 static int ad7768_gpio_init(struct iio_dev *indio_dev) 831 { 832 struct ad7768_state *st = iio_priv(indio_dev); 833 int ret; 834 835 ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, 836 AD7768_GPIO_UNIVERSAL_EN); 837 if (ret) 838 return ret; 839 840 st->gpiochip = (struct gpio_chip) { 841 .label = "ad7768_1_gpios", 842 .base = -1, 843 .ngpio = 4, 844 .parent = &st->spi->dev, 845 .can_sleep = true, 846 .direction_input = ad7768_gpio_direction_input, 847 .direction_output = ad7768_gpio_direction_output, 848 .get = ad7768_gpio_get, 849 .set = ad7768_gpio_set, 850 .owner = THIS_MODULE, 851 }; 852 853 return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); 854 } 855 856 static int ad7768_set_freq(struct ad7768_state *st, 857 unsigned int freq) 858 { 859 unsigned int idx, mclk_div; 860 int ret; 861 862 freq = clamp(freq, 50, 1024000); 863 864 mclk_div = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); 865 /* Find the closest match for the desired sampling frequency */ 866 idx = find_closest_descending(mclk_div, ad7768_mclk_div_rates, 867 ARRAY_SIZE(ad7768_mclk_div_rates)); 868 /* Set both the mclk_div and pwrmode */ 869 ret = ad7768_set_mclk_div(st, idx); 870 if (ret) 871 return ret; 872 873 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 874 ad7768_mclk_div_rates[idx] * st->oversampling_ratio); 875 876 /* A sync-in pulse is required after every configuration change */ 877 return ad7768_send_sync_pulse(st); 878 } 879 880 static int ad7768_set_filter_type_attr(struct iio_dev *dev, 881 const struct iio_chan_spec *chan, 882 unsigned int filter) 883 { 884 struct ad7768_state *st = iio_priv(dev); 885 int ret; 886 887 ret = ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); 888 if (ret) 889 return ret; 890 891 /* Update sampling frequency */ 892 return ad7768_set_freq(st, st->samp_freq); 893 } 894 895 static int ad7768_get_filter_type_attr(struct iio_dev *dev, 896 const struct iio_chan_spec *chan) 897 { 898 struct ad7768_state *st = iio_priv(dev); 899 int ret; 900 unsigned int mode, mask; 901 902 ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); 903 if (ret) 904 return ret; 905 906 mask = AD7768_DIG_FIL_EN_60HZ_REJ | AD7768_DIG_FIL_FIL_MSK; 907 /* From the register value, get the corresponding filter type */ 908 return ad7768_filter_regval_to_type[FIELD_GET(mask, mode)]; 909 } 910 911 static int ad7768_update_dec_rate(struct iio_dev *dev, unsigned int dec_rate) 912 { 913 struct ad7768_state *st = iio_priv(dev); 914 int ret; 915 916 ret = ad7768_configure_dig_fil(dev, st->filter_type, dec_rate); 917 if (ret) 918 return ret; 919 920 /* Update sampling frequency */ 921 return ad7768_set_freq(st, st->samp_freq); 922 } 923 924 static const struct iio_enum ad7768_filter_type_iio_enum = { 925 .items = ad7768_filter_enum, 926 .num_items = ARRAY_SIZE(ad7768_filter_enum), 927 .set = ad7768_set_filter_type_attr, 928 .get = ad7768_get_filter_type_attr, 929 }; 930 931 static const struct iio_chan_spec_ext_info ad7768_ext_info[] = { 932 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 933 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), 934 { } 935 }; 936 937 #define AD7768_CHAN(_idx, _msk_avail) \ 938 { \ 939 .type = IIO_VOLTAGE, \ 940 .info_mask_separate_available = _msk_avail, \ 941 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 942 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 943 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 944 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 945 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 946 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 947 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 948 .ext_info = ad7768_ext_info, \ 949 .indexed = 1, \ 950 .channel = _idx, \ 951 .scan_index = _idx, \ 952 .has_ext_scan_type = 1, \ 953 .ext_scan_type = ad7768_scan_type, \ 954 .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), \ 955 } 956 957 static const struct iio_chan_spec ad7768_channels[] = { 958 AD7768_CHAN(0, 0), 959 }; 960 961 static const struct iio_chan_spec adaq776x_channels[] = { 962 AD7768_CHAN(0, BIT(IIO_CHAN_INFO_SCALE)), 963 }; 964 965 static int ad7768_read_raw(struct iio_dev *indio_dev, 966 struct iio_chan_spec const *chan, 967 int *val, int *val2, long info) 968 { 969 struct ad7768_state *st = iio_priv(indio_dev); 970 const struct iio_scan_type *scan_type; 971 int ret, temp; 972 973 scan_type = iio_get_current_scan_type(indio_dev, chan); 974 if (IS_ERR(scan_type)) 975 return PTR_ERR(scan_type); 976 977 switch (info) { 978 case IIO_CHAN_INFO_RAW: 979 if (!iio_device_claim_direct(indio_dev)) 980 return -EBUSY; 981 982 ret = ad7768_scan_direct(indio_dev); 983 984 iio_device_release_direct(indio_dev); 985 if (ret < 0) 986 return ret; 987 *val = sign_extend32(ret, scan_type->realbits - 1); 988 989 return IIO_VAL_INT; 990 991 case IIO_CHAN_INFO_SCALE: 992 if (st->chip->has_pga) { 993 guard(mutex)(&st->pga_lock); 994 995 *val = st->scale_tbl[st->pga_gain_mode][0]; 996 *val2 = st->scale_tbl[st->pga_gain_mode][1]; 997 return IIO_VAL_INT_PLUS_NANO; 998 } 999 1000 temp = (st->vref_uv * 2) / 1000; 1001 if (st->chip->has_variable_aaf) 1002 temp = (temp * PERMYRIAD) / ad7768_aaf_gains_bp[st->aaf_gain]; 1003 1004 *val = temp; 1005 *val2 = scan_type->realbits; 1006 1007 return IIO_VAL_FRACTIONAL_LOG2; 1008 1009 case IIO_CHAN_INFO_SAMP_FREQ: 1010 *val = st->samp_freq; 1011 1012 return IIO_VAL_INT; 1013 1014 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1015 *val = st->oversampling_ratio; 1016 1017 return IIO_VAL_INT; 1018 1019 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1020 temp = st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_type]; 1021 *val = DIV_ROUND_CLOSEST(temp, MILLI); 1022 1023 return IIO_VAL_INT; 1024 } 1025 1026 return -EINVAL; 1027 } 1028 1029 static int ad7768_read_avail(struct iio_dev *indio_dev, 1030 struct iio_chan_spec const *chan, 1031 const int **vals, int *type, int *length, 1032 long info) 1033 { 1034 struct ad7768_state *st = iio_priv(indio_dev); 1035 unsigned int shift; 1036 1037 switch (info) { 1038 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1039 /* 1040 * Sinc3 filter allows a wider range of OSR values, so show 1041 * the available values in range format. 1042 */ 1043 if (st->filter_type == AD7768_FILTER_SINC3 || 1044 st->filter_type == AD7768_FILTER_SINC3_REJ60) { 1045 *vals = (int *)ad7768_sinc3_dec_rate_range; 1046 *type = IIO_VAL_INT; 1047 return IIO_AVAIL_RANGE; 1048 } 1049 1050 shift = st->filter_type == AD7768_FILTER_SINC5 ? 0 : 2; 1051 *vals = (int *)&ad7768_dec_rate_values[shift]; 1052 *length = ARRAY_SIZE(ad7768_dec_rate_values) - shift; 1053 *type = IIO_VAL_INT; 1054 return IIO_AVAIL_LIST; 1055 case IIO_CHAN_INFO_SAMP_FREQ: 1056 *vals = (int *)st->samp_freq_avail; 1057 *length = st->samp_freq_avail_len; 1058 *type = IIO_VAL_INT; 1059 return IIO_AVAIL_LIST; 1060 case IIO_CHAN_INFO_SCALE: 1061 *vals = (int *)st->scale_tbl; 1062 *length = st->chip->num_pga_modes * 2; 1063 *type = IIO_VAL_INT_PLUS_NANO; 1064 return IIO_AVAIL_LIST; 1065 default: 1066 return -EINVAL; 1067 } 1068 } 1069 1070 static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, 1071 struct iio_chan_spec const *chan, long mask) 1072 { 1073 switch (mask) { 1074 case IIO_CHAN_INFO_SCALE: 1075 return IIO_VAL_INT_PLUS_NANO; 1076 default: 1077 return IIO_VAL_INT_PLUS_MICRO; 1078 } 1079 } 1080 1081 static int ad7768_write_raw(struct iio_dev *indio_dev, 1082 struct iio_chan_spec const *chan, 1083 int val, int val2, long info) 1084 { 1085 struct ad7768_state *st = iio_priv(indio_dev); 1086 const struct iio_scan_type *scan_type; 1087 int ret; 1088 1089 scan_type = iio_get_current_scan_type(indio_dev, chan); 1090 if (IS_ERR(scan_type)) 1091 return PTR_ERR(scan_type); 1092 1093 switch (info) { 1094 case IIO_CHAN_INFO_SAMP_FREQ: 1095 if (!iio_device_claim_direct(indio_dev)) 1096 return -EBUSY; 1097 1098 ret = ad7768_set_freq(st, val); 1099 iio_device_release_direct(indio_dev); 1100 return ret; 1101 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1102 if (!iio_device_claim_direct(indio_dev)) 1103 return -EBUSY; 1104 1105 ret = ad7768_update_dec_rate(indio_dev, val); 1106 iio_device_release_direct(indio_dev); 1107 return ret; 1108 case IIO_CHAN_INFO_SCALE: { 1109 int gain_mode; 1110 1111 if (!st->chip->has_pga) 1112 return -EOPNOTSUPP; 1113 1114 if (scan_type->sign == 's') 1115 gain_mode = ad7768_calc_pga_gain(st, val, val2, 1116 scan_type->realbits - 1); 1117 else 1118 gain_mode = ad7768_calc_pga_gain(st, val, val2, 1119 scan_type->realbits); 1120 1121 return ad7768_set_pga_gain(st, gain_mode); 1122 } 1123 default: 1124 return -EINVAL; 1125 } 1126 } 1127 1128 static int ad7768_read_label(struct iio_dev *indio_dev, 1129 const struct iio_chan_spec *chan, char *label) 1130 { 1131 struct ad7768_state *st = iio_priv(indio_dev); 1132 1133 return sysfs_emit(label, "%s\n", st->labels[chan->channel]); 1134 } 1135 1136 static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, 1137 const struct iio_chan_spec *chan) 1138 { 1139 struct ad7768_state *st = iio_priv(indio_dev); 1140 1141 return st->oversampling_ratio == 8 ? 1142 AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; 1143 } 1144 1145 static const struct iio_info ad7768_info = { 1146 .read_raw = &ad7768_read_raw, 1147 .read_avail = &ad7768_read_avail, 1148 .write_raw = &ad7768_write_raw, 1149 .write_raw_get_fmt = &ad7768_write_raw_get_fmt, 1150 .read_label = ad7768_read_label, 1151 .get_current_scan_type = &ad7768_get_current_scan_type, 1152 .debugfs_reg_access = &ad7768_reg_access, 1153 }; 1154 1155 static struct fwnode_handle * 1156 ad7768_fwnode_find_reference_args(const struct fwnode_handle *fwnode, 1157 const char *name, const char *nargs_prop, 1158 unsigned int nargs, unsigned int index, 1159 struct fwnode_reference_args *args) 1160 { 1161 int ret; 1162 1163 ret = fwnode_property_get_reference_args(fwnode, name, nargs_prop, 1164 nargs, index, args); 1165 return ret ? ERR_PTR(ret) : args->fwnode; 1166 } 1167 1168 static int ad7768_trigger_sources_sync_setup(struct device *dev, 1169 struct fwnode_handle *fwnode, 1170 struct ad7768_state *st) 1171 { 1172 struct fwnode_reference_args args; 1173 1174 struct fwnode_handle *ref __free(fwnode_handle) = 1175 ad7768_fwnode_find_reference_args(fwnode, "trigger-sources", 1176 "#trigger-source-cells", 0, 1177 AD7768_TRIGGER_SOURCE_SYNC_IDX, 1178 &args); 1179 if (IS_ERR(ref)) 1180 return PTR_ERR(ref); 1181 1182 ref = args.fwnode; 1183 /* First, try getting the GPIO trigger source */ 1184 if (fwnode_device_is_compatible(ref, "gpio-trigger")) { 1185 st->gpio_sync_in = devm_fwnode_gpiod_get_index(dev, ref, NULL, 0, 1186 GPIOD_OUT_LOW, 1187 "sync-in"); 1188 return PTR_ERR_OR_ZERO(st->gpio_sync_in); 1189 } 1190 1191 /* 1192 * TODO: Support the other cases when we have a trigger subsystem 1193 * to reliably handle other types of devices as trigger sources. 1194 * 1195 * For now, return an error message. For self triggering, omit the 1196 * trigger-sources property. 1197 */ 1198 return dev_err_probe(dev, -EOPNOTSUPP, "Invalid synchronization trigger source\n"); 1199 } 1200 1201 static int ad7768_trigger_sources_get_sync(struct device *dev, 1202 struct ad7768_state *st) 1203 { 1204 struct fwnode_handle *fwnode = dev_fwnode(dev); 1205 1206 /* 1207 * The AD7768-1 allows two primary methods for driving the SYNC_IN pin 1208 * to synchronize one or more devices: 1209 * 1. Using an external GPIO. 1210 * 2. Using a SPI command, where the SYNC_OUT pin generates a 1211 * synchronization pulse that drives the SYNC_IN pin. 1212 */ 1213 if (fwnode_property_present(fwnode, "trigger-sources")) 1214 return ad7768_trigger_sources_sync_setup(dev, fwnode, st); 1215 1216 /* 1217 * In the absence of trigger-sources property, enable self 1218 * synchronization over SPI (SYNC_OUT). 1219 */ 1220 st->en_spi_sync = true; 1221 1222 return 0; 1223 } 1224 1225 static int ad7768_setup(struct iio_dev *indio_dev) 1226 { 1227 struct ad7768_state *st = iio_priv(indio_dev); 1228 int ret; 1229 1230 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", 1231 GPIOD_OUT_HIGH); 1232 if (IS_ERR(st->gpio_reset)) 1233 return PTR_ERR(st->gpio_reset); 1234 1235 if (st->gpio_reset) { 1236 fsleep(10); 1237 gpiod_set_value_cansleep(st->gpio_reset, 0); 1238 fsleep(200); 1239 } else { 1240 /* 1241 * Two writes to the SPI_RESET[1:0] bits are required to initiate 1242 * a software reset. The bits must first be set to 11, and then 1243 * to 10. When the sequence is detected, the reset occurs. 1244 * See the datasheet, page 70. 1245 */ 1246 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3); 1247 if (ret) 1248 return ret; 1249 1250 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2); 1251 if (ret) 1252 return ret; 1253 } 1254 1255 /* For backwards compatibility, try the adi,sync-in-gpios property */ 1256 st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", 1257 GPIOD_OUT_LOW); 1258 if (IS_ERR(st->gpio_sync_in)) 1259 return PTR_ERR(st->gpio_sync_in); 1260 1261 /* 1262 * If the synchronization is not defined by adi,sync-in-gpios, try the 1263 * trigger-sources. 1264 */ 1265 if (!st->gpio_sync_in) { 1266 ret = ad7768_trigger_sources_get_sync(&st->spi->dev, st); 1267 if (ret) 1268 return ret; 1269 } 1270 1271 /* Only create a Chip GPIO if flagged for it */ 1272 if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { 1273 ret = ad7768_gpio_init(indio_dev); 1274 if (ret) 1275 return ret; 1276 } 1277 1278 /* 1279 * Set Default Digital Filter configuration: 1280 * SINC5 filter with x32 Decimation rate 1281 */ 1282 ret = ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32); 1283 if (ret) 1284 return ret; 1285 1286 /* Set the default sampling frequency to 32000 kSPS */ 1287 return ad7768_set_freq(st, 32000); 1288 } 1289 1290 static irqreturn_t ad7768_trigger_handler(int irq, void *p) 1291 { 1292 struct iio_poll_func *pf = p; 1293 struct iio_dev *indio_dev = pf->indio_dev; 1294 struct ad7768_state *st = iio_priv(indio_dev); 1295 const struct iio_scan_type *scan_type; 1296 int ret; 1297 1298 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1299 if (IS_ERR(scan_type)) 1300 goto out; 1301 1302 ret = spi_read(st->spi, &st->data.scan.chan, 1303 BITS_TO_BYTES(scan_type->realbits)); 1304 if (ret < 0) 1305 goto out; 1306 1307 iio_push_to_buffers_with_ts(indio_dev, &st->data.scan, 1308 sizeof(st->data.scan), 1309 iio_get_time_ns(indio_dev)); 1310 1311 out: 1312 iio_trigger_notify_done(indio_dev->trig); 1313 1314 return IRQ_HANDLED; 1315 } 1316 1317 static irqreturn_t ad7768_interrupt(int irq, void *dev_id) 1318 { 1319 struct iio_dev *indio_dev = dev_id; 1320 struct ad7768_state *st = iio_priv(indio_dev); 1321 1322 if (iio_buffer_enabled(indio_dev)) 1323 iio_trigger_poll(st->trig); 1324 else 1325 complete(&st->completion); 1326 1327 return IRQ_HANDLED; 1328 }; 1329 1330 static int ad7768_buffer_postenable(struct iio_dev *indio_dev) 1331 { 1332 struct ad7768_state *st = iio_priv(indio_dev); 1333 1334 /* 1335 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 1336 * continuous read mode. Subsequent data reads do not require an 1337 * initial 8-bit write to query the ADC_DATA register. 1338 */ 1339 return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01); 1340 } 1341 1342 static int ad7768_buffer_predisable(struct iio_dev *indio_dev) 1343 { 1344 struct ad7768_state *st = iio_priv(indio_dev); 1345 unsigned int unused; 1346 1347 /* 1348 * To exit continuous read mode, perform a single read of the ADC_DATA 1349 * reg (0x2C), which allows further configuration of the device. 1350 */ 1351 return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1352 } 1353 1354 static const struct iio_buffer_setup_ops ad7768_buffer_ops = { 1355 .postenable = &ad7768_buffer_postenable, 1356 .predisable = &ad7768_buffer_predisable, 1357 }; 1358 1359 static const struct iio_trigger_ops ad7768_trigger_ops = { 1360 .validate_device = iio_trigger_validate_own_device, 1361 }; 1362 1363 static int ad7768_set_channel_label(struct iio_dev *indio_dev, 1364 int num_channels) 1365 { 1366 struct ad7768_state *st = iio_priv(indio_dev); 1367 struct device *device = indio_dev->dev.parent; 1368 const char *label; 1369 int crt_ch = 0; 1370 1371 device_for_each_child_node_scoped(device, child) { 1372 if (fwnode_property_read_u32(child, "reg", &crt_ch)) 1373 continue; 1374 1375 if (crt_ch >= num_channels) 1376 continue; 1377 1378 if (fwnode_property_read_string(child, "label", &label)) 1379 continue; 1380 1381 st->labels[crt_ch] = label; 1382 } 1383 1384 return 0; 1385 } 1386 1387 static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev) 1388 { 1389 struct ad7768_state *st = iio_priv(indio_dev); 1390 int ret; 1391 1392 st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", 1393 indio_dev->name, 1394 iio_device_id(indio_dev)); 1395 if (!st->trig) 1396 return -ENOMEM; 1397 1398 st->trig->ops = &ad7768_trigger_ops; 1399 iio_trigger_set_drvdata(st->trig, indio_dev); 1400 ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig); 1401 if (ret) 1402 return ret; 1403 1404 indio_dev->trig = iio_trigger_get(st->trig); 1405 1406 return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, 1407 &iio_pollfunc_store_time, 1408 &ad7768_trigger_handler, 1409 &ad7768_buffer_ops); 1410 } 1411 1412 static int ad7768_vcm_enable(struct regulator_dev *rdev) 1413 { 1414 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1415 struct ad7768_state *st = iio_priv(indio_dev); 1416 int ret, regval; 1417 1418 if (!iio_device_claim_direct(indio_dev)) 1419 return -EBUSY; 1420 1421 /* To enable, set the last selected output */ 1422 regval = AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1); 1423 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1424 AD7768_REG_ANALOG2_VCM_MSK, regval); 1425 iio_device_release_direct(indio_dev); 1426 1427 return ret; 1428 } 1429 1430 static int ad7768_vcm_disable(struct regulator_dev *rdev) 1431 { 1432 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1433 struct ad7768_state *st = iio_priv(indio_dev); 1434 int ret; 1435 1436 if (!iio_device_claim_direct(indio_dev)) 1437 return -EBUSY; 1438 1439 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1440 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1441 iio_device_release_direct(indio_dev); 1442 1443 return ret; 1444 } 1445 1446 static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) 1447 { 1448 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1449 struct ad7768_state *st = iio_priv(indio_dev); 1450 int ret, val; 1451 1452 if (!iio_device_claim_direct(indio_dev)) 1453 return -EBUSY; 1454 1455 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1456 iio_device_release_direct(indio_dev); 1457 if (ret) 1458 return ret; 1459 1460 return FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val) != AD7768_VCM_OFF; 1461 } 1462 1463 static int ad7768_set_voltage_sel(struct regulator_dev *rdev, 1464 unsigned int selector) 1465 { 1466 unsigned int regval = AD7768_REG_ANALOG2_VCM(selector + 1); 1467 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1468 struct ad7768_state *st = iio_priv(indio_dev); 1469 int ret; 1470 1471 if (!iio_device_claim_direct(indio_dev)) 1472 return -EBUSY; 1473 1474 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1475 AD7768_REG_ANALOG2_VCM_MSK, regval); 1476 iio_device_release_direct(indio_dev); 1477 if (ret) 1478 return ret; 1479 1480 st->vcm_output_sel = selector; 1481 1482 return 0; 1483 } 1484 1485 static int ad7768_get_voltage_sel(struct regulator_dev *rdev) 1486 { 1487 struct iio_dev *indio_dev = rdev_get_drvdata(rdev); 1488 struct ad7768_state *st = iio_priv(indio_dev); 1489 int ret, val; 1490 1491 if (!iio_device_claim_direct(indio_dev)) 1492 return -EBUSY; 1493 1494 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); 1495 iio_device_release_direct(indio_dev); 1496 if (ret) 1497 return ret; 1498 1499 val = FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val); 1500 1501 return clamp(val, 1, rdev->desc->n_voltages) - 1; 1502 } 1503 1504 static const struct regulator_ops vcm_regulator_ops = { 1505 .enable = ad7768_vcm_enable, 1506 .disable = ad7768_vcm_disable, 1507 .is_enabled = ad7768_vcm_is_enabled, 1508 .list_voltage = regulator_list_voltage_table, 1509 .set_voltage_sel = ad7768_set_voltage_sel, 1510 .get_voltage_sel = ad7768_get_voltage_sel, 1511 }; 1512 1513 static const unsigned int vcm_voltage_table[] = { 1514 2500000, 1515 2050000, 1516 1650000, 1517 1900000, 1518 1100000, 1519 900000, 1520 }; 1521 1522 static const struct regulator_desc vcm_desc = { 1523 .name = "ad7768-1-vcm", 1524 .of_match = "vcm-output", 1525 .regulators_node = "regulators", 1526 .n_voltages = ARRAY_SIZE(vcm_voltage_table), 1527 .volt_table = vcm_voltage_table, 1528 .ops = &vcm_regulator_ops, 1529 .type = REGULATOR_VOLTAGE, 1530 .owner = THIS_MODULE, 1531 }; 1532 1533 static int ad7768_register_vcm_regulator(struct device *dev, 1534 struct ad7768_state *st, 1535 struct iio_dev *indio_dev) 1536 { 1537 struct regulator_config config = { 1538 .dev = dev, 1539 .driver_data = indio_dev, 1540 }; 1541 int ret; 1542 1543 /* Disable the regulator before registering it */ 1544 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, 1545 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); 1546 if (ret) 1547 return ret; 1548 1549 st->vcm_rdev = devm_regulator_register(dev, &vcm_desc, &config); 1550 if (IS_ERR(st->vcm_rdev)) 1551 return dev_err_probe(dev, PTR_ERR(st->vcm_rdev), 1552 "failed to register VCM regulator\n"); 1553 1554 return 0; 1555 } 1556 1557 static int ad7768_parse_aaf_gain(struct device *dev, struct ad7768_state *st) 1558 { 1559 u32 val; 1560 int ret; 1561 1562 ret = device_property_read_u32(dev, "adi,aaf-gain-bp", &val); 1563 if (ret == -EINVAL) { 1564 /* If controllable, use default */ 1565 if (st->chip->has_variable_aaf) 1566 st->aaf_gain = AD7768_AAF_IN1; 1567 return 0; 1568 } 1569 if (ret) 1570 return dev_err_probe(dev, ret, "Failed to get AAF gain value\n"); 1571 1572 if (!st->chip->has_variable_aaf) 1573 return dev_err_probe(dev, -EOPNOTSUPP, 1574 "AAF gain provided, but not supported for %s\n", st->chip->name); 1575 1576 switch (val) { 1577 case 10000: 1578 st->aaf_gain = AD7768_AAF_IN1; 1579 break; 1580 case 3640: 1581 st->aaf_gain = AD7768_AAF_IN2; 1582 break; 1583 case 1430: 1584 st->aaf_gain = AD7768_AAF_IN3; 1585 break; 1586 default: 1587 return dev_err_probe(dev, -EINVAL, "Invalid firmware provided AAF gain\n"); 1588 } 1589 1590 return 0; 1591 } 1592 1593 static const struct ad7768_chip_info ad7768_chip_info = { 1594 .name = "ad7768-1", 1595 .channel_spec = ad7768_channels, 1596 .num_channels = ARRAY_SIZE(ad7768_channels), 1597 .has_vcm_regulator = true, 1598 }; 1599 1600 static const struct ad7768_chip_info adaq7767_chip_info = { 1601 .name = "adaq7767-1", 1602 .channel_spec = ad7768_channels, 1603 .num_channels = ARRAY_SIZE(ad7768_channels), 1604 .has_variable_aaf = true, 1605 }; 1606 1607 static const struct ad7768_chip_info adaq7768_chip_info = { 1608 .name = "adaq7768-1", 1609 .channel_spec = adaq776x_channels, 1610 .num_channels = ARRAY_SIZE(adaq776x_channels), 1611 .pga_gains = adaq7768_gains, 1612 .default_pga_mode = AD7768_PGA_GAIN_2, 1613 .num_pga_modes = ARRAY_SIZE(adaq7768_gains), 1614 .pgia_mode2pin_offset = 6, 1615 .has_pga = true, 1616 }; 1617 1618 static const struct ad7768_chip_info adaq7769_chip_info = { 1619 .name = "adaq7769-1", 1620 .channel_spec = adaq776x_channels, 1621 .num_channels = ARRAY_SIZE(adaq776x_channels), 1622 .pga_gains = adaq7769_gains, 1623 .default_pga_mode = AD7768_PGA_GAIN_0, 1624 .num_pga_modes = ARRAY_SIZE(adaq7769_gains), 1625 .pgia_mode2pin_offset = 0, 1626 .has_pga = true, 1627 .has_variable_aaf = true, 1628 }; 1629 1630 static int ad7768_probe(struct spi_device *spi) 1631 { 1632 struct ad7768_state *st; 1633 struct iio_dev *indio_dev; 1634 int ret; 1635 1636 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1637 if (!indio_dev) 1638 return -ENOMEM; 1639 1640 st = iio_priv(indio_dev); 1641 /* 1642 * Datasheet recommends SDI line to be kept high when data is not being 1643 * clocked out of the controller and the spi clock is free running, 1644 * to prevent accidental reset. 1645 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag 1646 * yet, only request the MOSI idle state to enable if the controller 1647 * supports it. 1648 */ 1649 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) { 1650 spi->mode |= SPI_MOSI_IDLE_HIGH; 1651 ret = spi_setup(spi); 1652 if (ret < 0) 1653 return ret; 1654 } 1655 1656 st->chip = spi_get_device_match_data(spi); 1657 st->spi = spi; 1658 1659 st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config); 1660 if (IS_ERR(st->regmap)) 1661 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), 1662 "Failed to initialize regmap"); 1663 1664 st->regmap24 = devm_regmap_init_spi(spi, &ad7768_regmap24_config); 1665 if (IS_ERR(st->regmap24)) 1666 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap24), 1667 "Failed to initialize regmap24"); 1668 1669 ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); 1670 if (ret < 0) 1671 return dev_err_probe(&spi->dev, ret, 1672 "Failed to get VREF voltage\n"); 1673 st->vref_uv = ret; 1674 1675 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 1676 if (IS_ERR(st->mclk)) 1677 return PTR_ERR(st->mclk); 1678 1679 st->mclk_freq = clk_get_rate(st->mclk); 1680 1681 indio_dev->channels = st->chip->channel_spec; 1682 indio_dev->num_channels = st->chip->num_channels; 1683 indio_dev->name = st->chip->name; 1684 indio_dev->info = &ad7768_info; 1685 indio_dev->modes = INDIO_DIRECT_MODE; 1686 1687 /* Register VCM output regulator */ 1688 if (st->chip->has_vcm_regulator) { 1689 ret = ad7768_register_vcm_regulator(&spi->dev, st, indio_dev); 1690 if (ret) 1691 return ret; 1692 } 1693 1694 ret = ad7768_parse_aaf_gain(&spi->dev, st); 1695 if (ret) 1696 return ret; 1697 1698 ret = ad7768_setup(indio_dev); 1699 if (ret < 0) { 1700 dev_err(&spi->dev, "AD7768 setup failed\n"); 1701 return ret; 1702 } 1703 1704 init_completion(&st->completion); 1705 ret = devm_mutex_init(&spi->dev, &st->pga_lock); 1706 if (ret) 1707 return ret; 1708 1709 if (st->chip->has_pga) { 1710 ret = ad7768_setup_pga(&spi->dev, st); 1711 if (ret) 1712 return ret; 1713 1714 ret = ad7768_set_pga_gain(st, st->chip->default_pga_mode); 1715 if (ret) 1716 return ret; 1717 } 1718 1719 ret = ad7768_set_channel_label(indio_dev, st->chip->num_channels); 1720 if (ret) 1721 return ret; 1722 1723 ret = devm_request_irq(&spi->dev, spi->irq, &ad7768_interrupt, 1724 IRQF_TRIGGER_RISING | IRQF_NO_THREAD, 1725 indio_dev->name, indio_dev); 1726 if (ret) 1727 return ret; 1728 1729 ret = ad7768_triggered_buffer_alloc(indio_dev); 1730 if (ret) 1731 return ret; 1732 1733 return devm_iio_device_register(&spi->dev, indio_dev); 1734 } 1735 1736 static const struct spi_device_id ad7768_id_table[] = { 1737 { "ad7768-1", (kernel_ulong_t)&ad7768_chip_info }, 1738 { "adaq7767-1", (kernel_ulong_t)&adaq7767_chip_info }, 1739 { "adaq7768-1", (kernel_ulong_t)&adaq7768_chip_info }, 1740 { "adaq7769-1", (kernel_ulong_t)&adaq7769_chip_info }, 1741 { } 1742 }; 1743 MODULE_DEVICE_TABLE(spi, ad7768_id_table); 1744 1745 static const struct of_device_id ad7768_of_match[] = { 1746 { .compatible = "adi,ad7768-1", .data = &ad7768_chip_info }, 1747 { .compatible = "adi,adaq7767-1", .data = &adaq7767_chip_info }, 1748 { .compatible = "adi,adaq7768-1", .data = &adaq7768_chip_info }, 1749 { .compatible = "adi,adaq7769-1", .data = &adaq7769_chip_info }, 1750 { } 1751 }; 1752 MODULE_DEVICE_TABLE(of, ad7768_of_match); 1753 1754 static struct spi_driver ad7768_driver = { 1755 .driver = { 1756 .name = "ad7768-1", 1757 .of_match_table = ad7768_of_match, 1758 }, 1759 .probe = ad7768_probe, 1760 .id_table = ad7768_id_table, 1761 }; 1762 module_spi_driver(ad7768_driver); 1763 1764 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1765 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 1766 MODULE_LICENSE("GPL v2"); 1767