1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7768-1 SPI ADC driver 4 * 5 * Copyright 2017 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/sysfs.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/iio/buffer.h> 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/trigger.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/iio/trigger_consumer.h> 25 26 /* AD7768 registers definition */ 27 #define AD7768_REG_CHIP_TYPE 0x3 28 #define AD7768_REG_PROD_ID_L 0x4 29 #define AD7768_REG_PROD_ID_H 0x5 30 #define AD7768_REG_CHIP_GRADE 0x6 31 #define AD7768_REG_SCRATCH_PAD 0x0A 32 #define AD7768_REG_VENDOR_L 0x0C 33 #define AD7768_REG_VENDOR_H 0x0D 34 #define AD7768_REG_INTERFACE_FORMAT 0x14 35 #define AD7768_REG_POWER_CLOCK 0x15 36 #define AD7768_REG_ANALOG 0x16 37 #define AD7768_REG_ANALOG2 0x17 38 #define AD7768_REG_CONVERSION 0x18 39 #define AD7768_REG_DIGITAL_FILTER 0x19 40 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A 41 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B 42 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C 43 #define AD7768_REG_SYNC_RESET 0x1D 44 #define AD7768_REG_GPIO_CONTROL 0x1E 45 #define AD7768_REG_GPIO_WRITE 0x1F 46 #define AD7768_REG_GPIO_READ 0x20 47 #define AD7768_REG_OFFSET_HI 0x21 48 #define AD7768_REG_OFFSET_MID 0x22 49 #define AD7768_REG_OFFSET_LO 0x23 50 #define AD7768_REG_GAIN_HI 0x24 51 #define AD7768_REG_GAIN_MID 0x25 52 #define AD7768_REG_GAIN_LO 0x26 53 #define AD7768_REG_SPI_DIAG_ENABLE 0x28 54 #define AD7768_REG_ADC_DIAG_ENABLE 0x29 55 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A 56 #define AD7768_REG_ADC_DATA 0x2C 57 #define AD7768_REG_MASTER_STATUS 0x2D 58 #define AD7768_REG_SPI_DIAG_STATUS 0x2E 59 #define AD7768_REG_ADC_DIAG_STATUS 0x2F 60 #define AD7768_REG_DIG_DIAG_STATUS 0x30 61 #define AD7768_REG_MCLK_COUNTER 0x31 62 63 /* AD7768_REG_POWER_CLOCK */ 64 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) 65 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) 66 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) 67 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 68 69 /* AD7768_REG_DIGITAL_FILTER */ 70 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 71 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 72 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) 73 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) 74 75 /* AD7768_REG_CONVERSION */ 76 #define AD7768_CONV_MODE_MSK GENMASK(2, 0) 77 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 78 79 #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) 80 #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) 81 82 enum ad7768_conv_mode { 83 AD7768_CONTINUOUS, 84 AD7768_ONE_SHOT, 85 AD7768_SINGLE, 86 AD7768_PERIODIC, 87 AD7768_STANDBY 88 }; 89 90 enum ad7768_pwrmode { 91 AD7768_ECO_MODE = 0, 92 AD7768_MED_MODE = 2, 93 AD7768_FAST_MODE = 3 94 }; 95 96 enum ad7768_mclk_div { 97 AD7768_MCLK_DIV_16, 98 AD7768_MCLK_DIV_8, 99 AD7768_MCLK_DIV_4, 100 AD7768_MCLK_DIV_2 101 }; 102 103 enum ad7768_dec_rate { 104 AD7768_DEC_RATE_32 = 0, 105 AD7768_DEC_RATE_64 = 1, 106 AD7768_DEC_RATE_128 = 2, 107 AD7768_DEC_RATE_256 = 3, 108 AD7768_DEC_RATE_512 = 4, 109 AD7768_DEC_RATE_1024 = 5, 110 AD7768_DEC_RATE_8 = 9, 111 AD7768_DEC_RATE_16 = 10 112 }; 113 114 struct ad7768_clk_configuration { 115 enum ad7768_mclk_div mclk_div; 116 enum ad7768_dec_rate dec_rate; 117 unsigned int clk_div; 118 enum ad7768_pwrmode pwrmode; 119 }; 120 121 static const struct ad7768_clk_configuration ad7768_clk_config[] = { 122 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, 123 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, 124 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, 125 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, 126 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, 127 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, 128 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, 129 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, 130 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, 131 { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, 132 { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, 133 }; 134 135 static const struct iio_chan_spec ad7768_channels[] = { 136 { 137 .type = IIO_VOLTAGE, 138 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 139 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 140 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 141 .indexed = 1, 142 .channel = 0, 143 .scan_index = 0, 144 .scan_type = { 145 .sign = 's', 146 .realbits = 24, 147 .storagebits = 32, 148 .shift = 8, 149 .endianness = IIO_BE, 150 }, 151 }, 152 }; 153 154 struct ad7768_state { 155 struct spi_device *spi; 156 struct regulator *vref; 157 struct clk *mclk; 158 unsigned int mclk_freq; 159 unsigned int samp_freq; 160 struct completion completion; 161 struct iio_trigger *trig; 162 struct gpio_desc *gpio_sync_in; 163 const char *labels[ARRAY_SIZE(ad7768_channels)]; 164 /* 165 * DMA (thus cache coherency maintenance) may require the 166 * transfer buffers to live in their own cache lines. 167 */ 168 union { 169 struct { 170 __be32 chan; 171 s64 timestamp; 172 } scan; 173 __be32 d32; 174 u8 d8[2]; 175 } data __aligned(IIO_DMA_MINALIGN); 176 }; 177 178 static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, 179 unsigned int len) 180 { 181 unsigned int shift; 182 int ret; 183 184 shift = 32 - (8 * len); 185 st->data.d8[0] = AD7768_RD_FLAG_MSK(addr); 186 187 ret = spi_write_then_read(st->spi, st->data.d8, 1, 188 &st->data.d32, len); 189 if (ret < 0) 190 return ret; 191 192 return (be32_to_cpu(st->data.d32) >> shift); 193 } 194 195 static int ad7768_spi_reg_write(struct ad7768_state *st, 196 unsigned int addr, 197 unsigned int val) 198 { 199 st->data.d8[0] = AD7768_WR_FLAG_MSK(addr); 200 st->data.d8[1] = val & 0xFF; 201 202 return spi_write(st->spi, st->data.d8, 2); 203 } 204 205 static int ad7768_set_mode(struct ad7768_state *st, 206 enum ad7768_conv_mode mode) 207 { 208 int regval; 209 210 regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); 211 if (regval < 0) 212 return regval; 213 214 regval &= ~AD7768_CONV_MODE_MSK; 215 regval |= AD7768_CONV_MODE(mode); 216 217 return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval); 218 } 219 220 static int ad7768_scan_direct(struct iio_dev *indio_dev) 221 { 222 struct ad7768_state *st = iio_priv(indio_dev); 223 int readval, ret; 224 225 reinit_completion(&st->completion); 226 227 ret = ad7768_set_mode(st, AD7768_ONE_SHOT); 228 if (ret < 0) 229 return ret; 230 231 ret = wait_for_completion_timeout(&st->completion, 232 msecs_to_jiffies(1000)); 233 if (!ret) 234 return -ETIMEDOUT; 235 236 readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); 237 if (readval < 0) 238 return readval; 239 /* 240 * Any SPI configuration of the AD7768-1 can only be 241 * performed in continuous conversion mode. 242 */ 243 ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 244 if (ret < 0) 245 return ret; 246 247 return readval; 248 } 249 250 static int ad7768_reg_access(struct iio_dev *indio_dev, 251 unsigned int reg, 252 unsigned int writeval, 253 unsigned int *readval) 254 { 255 struct ad7768_state *st = iio_priv(indio_dev); 256 int ret; 257 258 if (!iio_device_claim_direct(indio_dev)) 259 return -EBUSY; 260 261 if (readval) { 262 ret = ad7768_spi_reg_read(st, reg, 1); 263 if (ret < 0) 264 goto err_release; 265 *readval = ret; 266 ret = 0; 267 } else { 268 ret = ad7768_spi_reg_write(st, reg, writeval); 269 } 270 err_release: 271 iio_device_release_direct(indio_dev); 272 273 return ret; 274 } 275 276 static int ad7768_set_dig_fil(struct ad7768_state *st, 277 enum ad7768_dec_rate dec_rate) 278 { 279 unsigned int mode; 280 int ret; 281 282 if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) 283 mode = AD7768_DIG_FIL_FIL(dec_rate); 284 else 285 mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); 286 287 ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); 288 if (ret < 0) 289 return ret; 290 291 /* A sync-in pulse is required every time the filter dec rate changes */ 292 gpiod_set_value(st->gpio_sync_in, 1); 293 gpiod_set_value(st->gpio_sync_in, 0); 294 295 return 0; 296 } 297 298 static int ad7768_set_freq(struct ad7768_state *st, 299 unsigned int freq) 300 { 301 unsigned int diff_new, diff_old, pwr_mode, i, idx; 302 int res, ret; 303 304 diff_old = U32_MAX; 305 idx = 0; 306 307 res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); 308 309 /* Find the closest match for the desired sampling frequency */ 310 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 311 diff_new = abs(res - ad7768_clk_config[i].clk_div); 312 if (diff_new < diff_old) { 313 diff_old = diff_new; 314 idx = i; 315 } 316 } 317 318 /* 319 * Set both the mclk_div and pwrmode with a single write to the 320 * POWER_CLOCK register 321 */ 322 pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | 323 AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); 324 ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode); 325 if (ret < 0) 326 return ret; 327 328 ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); 329 if (ret < 0) 330 return ret; 331 332 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 333 ad7768_clk_config[idx].clk_div); 334 335 return 0; 336 } 337 338 static ssize_t ad7768_sampling_freq_avail(struct device *dev, 339 struct device_attribute *attr, 340 char *buf) 341 { 342 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 343 struct ad7768_state *st = iio_priv(indio_dev); 344 unsigned int freq; 345 int i, len = 0; 346 347 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 348 freq = DIV_ROUND_CLOSEST(st->mclk_freq, 349 ad7768_clk_config[i].clk_div); 350 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); 351 } 352 353 buf[len - 1] = '\n'; 354 355 return len; 356 } 357 358 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); 359 360 static int ad7768_read_raw(struct iio_dev *indio_dev, 361 struct iio_chan_spec const *chan, 362 int *val, int *val2, long info) 363 { 364 struct ad7768_state *st = iio_priv(indio_dev); 365 int scale_uv, ret; 366 367 switch (info) { 368 case IIO_CHAN_INFO_RAW: 369 if (!iio_device_claim_direct(indio_dev)) 370 return -EBUSY; 371 372 ret = ad7768_scan_direct(indio_dev); 373 374 iio_device_release_direct(indio_dev); 375 if (ret < 0) 376 return ret; 377 *val = sign_extend32(ret, chan->scan_type.realbits - 1); 378 379 return IIO_VAL_INT; 380 381 case IIO_CHAN_INFO_SCALE: 382 scale_uv = regulator_get_voltage(st->vref); 383 if (scale_uv < 0) 384 return scale_uv; 385 386 *val = (scale_uv * 2) / 1000; 387 *val2 = chan->scan_type.realbits; 388 389 return IIO_VAL_FRACTIONAL_LOG2; 390 391 case IIO_CHAN_INFO_SAMP_FREQ: 392 *val = st->samp_freq; 393 394 return IIO_VAL_INT; 395 } 396 397 return -EINVAL; 398 } 399 400 static int ad7768_write_raw(struct iio_dev *indio_dev, 401 struct iio_chan_spec const *chan, 402 int val, int val2, long info) 403 { 404 struct ad7768_state *st = iio_priv(indio_dev); 405 406 switch (info) { 407 case IIO_CHAN_INFO_SAMP_FREQ: 408 return ad7768_set_freq(st, val); 409 default: 410 return -EINVAL; 411 } 412 } 413 414 static int ad7768_read_label(struct iio_dev *indio_dev, 415 const struct iio_chan_spec *chan, char *label) 416 { 417 struct ad7768_state *st = iio_priv(indio_dev); 418 419 return sprintf(label, "%s\n", st->labels[chan->channel]); 420 } 421 422 static struct attribute *ad7768_attributes[] = { 423 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 424 NULL 425 }; 426 427 static const struct attribute_group ad7768_group = { 428 .attrs = ad7768_attributes, 429 }; 430 431 static const struct iio_info ad7768_info = { 432 .attrs = &ad7768_group, 433 .read_raw = &ad7768_read_raw, 434 .write_raw = &ad7768_write_raw, 435 .read_label = ad7768_read_label, 436 .debugfs_reg_access = &ad7768_reg_access, 437 }; 438 439 static int ad7768_setup(struct ad7768_state *st) 440 { 441 int ret; 442 443 /* 444 * Two writes to the SPI_RESET[1:0] bits are required to initiate 445 * a software reset. The bits must first be set to 11, and then 446 * to 10. When the sequence is detected, the reset occurs. 447 * See the datasheet, page 70. 448 */ 449 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3); 450 if (ret) 451 return ret; 452 453 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2); 454 if (ret) 455 return ret; 456 457 st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", 458 GPIOD_OUT_LOW); 459 if (IS_ERR(st->gpio_sync_in)) 460 return PTR_ERR(st->gpio_sync_in); 461 462 /* Set the default sampling frequency to 32000 kSPS */ 463 return ad7768_set_freq(st, 32000); 464 } 465 466 static irqreturn_t ad7768_trigger_handler(int irq, void *p) 467 { 468 struct iio_poll_func *pf = p; 469 struct iio_dev *indio_dev = pf->indio_dev; 470 struct ad7768_state *st = iio_priv(indio_dev); 471 int ret; 472 473 ret = spi_read(st->spi, &st->data.scan.chan, 3); 474 if (ret < 0) 475 goto out; 476 477 iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan, 478 iio_get_time_ns(indio_dev)); 479 480 out: 481 iio_trigger_notify_done(indio_dev->trig); 482 483 return IRQ_HANDLED; 484 } 485 486 static irqreturn_t ad7768_interrupt(int irq, void *dev_id) 487 { 488 struct iio_dev *indio_dev = dev_id; 489 struct ad7768_state *st = iio_priv(indio_dev); 490 491 if (iio_buffer_enabled(indio_dev)) 492 iio_trigger_poll(st->trig); 493 else 494 complete(&st->completion); 495 496 return IRQ_HANDLED; 497 }; 498 499 static int ad7768_buffer_postenable(struct iio_dev *indio_dev) 500 { 501 struct ad7768_state *st = iio_priv(indio_dev); 502 503 /* 504 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 505 * continuous read mode. Subsequent data reads do not require an 506 * initial 8-bit write to query the ADC_DATA register. 507 */ 508 return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01); 509 } 510 511 static int ad7768_buffer_predisable(struct iio_dev *indio_dev) 512 { 513 struct ad7768_state *st = iio_priv(indio_dev); 514 515 /* 516 * To exit continuous read mode, perform a single read of the ADC_DATA 517 * reg (0x2C), which allows further configuration of the device. 518 */ 519 return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); 520 } 521 522 static const struct iio_buffer_setup_ops ad7768_buffer_ops = { 523 .postenable = &ad7768_buffer_postenable, 524 .predisable = &ad7768_buffer_predisable, 525 }; 526 527 static const struct iio_trigger_ops ad7768_trigger_ops = { 528 .validate_device = iio_trigger_validate_own_device, 529 }; 530 531 static void ad7768_regulator_disable(void *data) 532 { 533 struct ad7768_state *st = data; 534 535 regulator_disable(st->vref); 536 } 537 538 static int ad7768_set_channel_label(struct iio_dev *indio_dev, 539 int num_channels) 540 { 541 struct ad7768_state *st = iio_priv(indio_dev); 542 struct device *device = indio_dev->dev.parent; 543 const char *label; 544 int crt_ch = 0; 545 546 device_for_each_child_node_scoped(device, child) { 547 if (fwnode_property_read_u32(child, "reg", &crt_ch)) 548 continue; 549 550 if (crt_ch >= num_channels) 551 continue; 552 553 if (fwnode_property_read_string(child, "label", &label)) 554 continue; 555 556 st->labels[crt_ch] = label; 557 } 558 559 return 0; 560 } 561 562 static int ad7768_probe(struct spi_device *spi) 563 { 564 struct ad7768_state *st; 565 struct iio_dev *indio_dev; 566 int ret; 567 568 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 569 if (!indio_dev) 570 return -ENOMEM; 571 572 st = iio_priv(indio_dev); 573 /* 574 * Datasheet recommends SDI line to be kept high when data is not being 575 * clocked out of the controller and the spi clock is free running, 576 * to prevent accidental reset. 577 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag 578 * yet, only request the MOSI idle state to enable if the controller 579 * supports it. 580 */ 581 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) { 582 spi->mode |= SPI_MOSI_IDLE_HIGH; 583 ret = spi_setup(spi); 584 if (ret < 0) 585 return ret; 586 } 587 588 st->spi = spi; 589 590 st->vref = devm_regulator_get(&spi->dev, "vref"); 591 if (IS_ERR(st->vref)) 592 return PTR_ERR(st->vref); 593 594 ret = regulator_enable(st->vref); 595 if (ret) { 596 dev_err(&spi->dev, "Failed to enable specified vref supply\n"); 597 return ret; 598 } 599 600 ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st); 601 if (ret) 602 return ret; 603 604 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 605 if (IS_ERR(st->mclk)) 606 return PTR_ERR(st->mclk); 607 608 st->mclk_freq = clk_get_rate(st->mclk); 609 610 indio_dev->channels = ad7768_channels; 611 indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); 612 indio_dev->name = spi_get_device_id(spi)->name; 613 indio_dev->info = &ad7768_info; 614 indio_dev->modes = INDIO_DIRECT_MODE; 615 616 ret = ad7768_setup(st); 617 if (ret < 0) { 618 dev_err(&spi->dev, "AD7768 setup failed\n"); 619 return ret; 620 } 621 622 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", 623 indio_dev->name, 624 iio_device_id(indio_dev)); 625 if (!st->trig) 626 return -ENOMEM; 627 628 st->trig->ops = &ad7768_trigger_ops; 629 iio_trigger_set_drvdata(st->trig, indio_dev); 630 ret = devm_iio_trigger_register(&spi->dev, st->trig); 631 if (ret) 632 return ret; 633 634 indio_dev->trig = iio_trigger_get(st->trig); 635 636 init_completion(&st->completion); 637 638 ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels)); 639 if (ret) 640 return ret; 641 642 ret = devm_request_irq(&spi->dev, spi->irq, 643 &ad7768_interrupt, 644 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 645 indio_dev->name, indio_dev); 646 if (ret) 647 return ret; 648 649 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 650 &iio_pollfunc_store_time, 651 &ad7768_trigger_handler, 652 &ad7768_buffer_ops); 653 if (ret) 654 return ret; 655 656 return devm_iio_device_register(&spi->dev, indio_dev); 657 } 658 659 static const struct spi_device_id ad7768_id_table[] = { 660 { "ad7768-1", 0 }, 661 {} 662 }; 663 MODULE_DEVICE_TABLE(spi, ad7768_id_table); 664 665 static const struct of_device_id ad7768_of_match[] = { 666 { .compatible = "adi,ad7768-1" }, 667 { } 668 }; 669 MODULE_DEVICE_TABLE(of, ad7768_of_match); 670 671 static struct spi_driver ad7768_driver = { 672 .driver = { 673 .name = "ad7768-1", 674 .of_match_table = ad7768_of_match, 675 }, 676 .probe = ad7768_probe, 677 .id_table = ad7768_id_table, 678 }; 679 module_spi_driver(ad7768_driver); 680 681 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 682 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 683 MODULE_LICENSE("GPL v2"); 684