1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7768-1 SPI ADC driver 4 * 5 * Copyright 2017 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/sysfs.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/iio/buffer.h> 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/trigger.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/iio/trigger_consumer.h> 25 26 /* AD7768 registers definition */ 27 #define AD7768_REG_CHIP_TYPE 0x3 28 #define AD7768_REG_PROD_ID_L 0x4 29 #define AD7768_REG_PROD_ID_H 0x5 30 #define AD7768_REG_CHIP_GRADE 0x6 31 #define AD7768_REG_SCRATCH_PAD 0x0A 32 #define AD7768_REG_VENDOR_L 0x0C 33 #define AD7768_REG_VENDOR_H 0x0D 34 #define AD7768_REG_INTERFACE_FORMAT 0x14 35 #define AD7768_REG_POWER_CLOCK 0x15 36 #define AD7768_REG_ANALOG 0x16 37 #define AD7768_REG_ANALOG2 0x17 38 #define AD7768_REG_CONVERSION 0x18 39 #define AD7768_REG_DIGITAL_FILTER 0x19 40 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A 41 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B 42 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C 43 #define AD7768_REG_SYNC_RESET 0x1D 44 #define AD7768_REG_GPIO_CONTROL 0x1E 45 #define AD7768_REG_GPIO_WRITE 0x1F 46 #define AD7768_REG_GPIO_READ 0x20 47 #define AD7768_REG_OFFSET_HI 0x21 48 #define AD7768_REG_OFFSET_MID 0x22 49 #define AD7768_REG_OFFSET_LO 0x23 50 #define AD7768_REG_GAIN_HI 0x24 51 #define AD7768_REG_GAIN_MID 0x25 52 #define AD7768_REG_GAIN_LO 0x26 53 #define AD7768_REG_SPI_DIAG_ENABLE 0x28 54 #define AD7768_REG_ADC_DIAG_ENABLE 0x29 55 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A 56 #define AD7768_REG_ADC_DATA 0x2C 57 #define AD7768_REG_MASTER_STATUS 0x2D 58 #define AD7768_REG_SPI_DIAG_STATUS 0x2E 59 #define AD7768_REG_ADC_DIAG_STATUS 0x2F 60 #define AD7768_REG_DIG_DIAG_STATUS 0x30 61 #define AD7768_REG_MCLK_COUNTER 0x31 62 63 /* AD7768_REG_POWER_CLOCK */ 64 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) 65 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) 66 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) 67 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 68 69 /* AD7768_REG_DIGITAL_FILTER */ 70 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 71 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 72 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) 73 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) 74 75 /* AD7768_REG_CONVERSION */ 76 #define AD7768_CONV_MODE_MSK GENMASK(2, 0) 77 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 78 79 #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) 80 #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) 81 82 enum ad7768_conv_mode { 83 AD7768_CONTINUOUS, 84 AD7768_ONE_SHOT, 85 AD7768_SINGLE, 86 AD7768_PERIODIC, 87 AD7768_STANDBY 88 }; 89 90 enum ad7768_pwrmode { 91 AD7768_ECO_MODE = 0, 92 AD7768_MED_MODE = 2, 93 AD7768_FAST_MODE = 3 94 }; 95 96 enum ad7768_mclk_div { 97 AD7768_MCLK_DIV_16, 98 AD7768_MCLK_DIV_8, 99 AD7768_MCLK_DIV_4, 100 AD7768_MCLK_DIV_2 101 }; 102 103 enum ad7768_dec_rate { 104 AD7768_DEC_RATE_32 = 0, 105 AD7768_DEC_RATE_64 = 1, 106 AD7768_DEC_RATE_128 = 2, 107 AD7768_DEC_RATE_256 = 3, 108 AD7768_DEC_RATE_512 = 4, 109 AD7768_DEC_RATE_1024 = 5, 110 AD7768_DEC_RATE_8 = 9, 111 AD7768_DEC_RATE_16 = 10 112 }; 113 114 struct ad7768_clk_configuration { 115 enum ad7768_mclk_div mclk_div; 116 enum ad7768_dec_rate dec_rate; 117 unsigned int clk_div; 118 enum ad7768_pwrmode pwrmode; 119 }; 120 121 static const struct ad7768_clk_configuration ad7768_clk_config[] = { 122 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, 123 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, 124 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, 125 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, 126 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, 127 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, 128 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, 129 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, 130 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, 131 { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, 132 { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, 133 }; 134 135 static const struct iio_chan_spec ad7768_channels[] = { 136 { 137 .type = IIO_VOLTAGE, 138 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 139 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 140 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 141 .indexed = 1, 142 .channel = 0, 143 .scan_index = 0, 144 .scan_type = { 145 .sign = 'u', 146 .realbits = 24, 147 .storagebits = 32, 148 .shift = 8, 149 .endianness = IIO_BE, 150 }, 151 }, 152 }; 153 154 struct ad7768_state { 155 struct spi_device *spi; 156 struct regulator *vref; 157 struct mutex lock; 158 struct clk *mclk; 159 unsigned int mclk_freq; 160 unsigned int samp_freq; 161 struct completion completion; 162 struct iio_trigger *trig; 163 struct gpio_desc *gpio_sync_in; 164 const char *labels[ARRAY_SIZE(ad7768_channels)]; 165 /* 166 * DMA (thus cache coherency maintenance) requires the 167 * transfer buffers to live in their own cache lines. 168 */ 169 union { 170 __be32 d32; 171 u8 d8[2]; 172 } data ____cacheline_aligned; 173 }; 174 175 static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, 176 unsigned int len) 177 { 178 unsigned int shift; 179 int ret; 180 181 shift = 32 - (8 * len); 182 st->data.d8[0] = AD7768_RD_FLAG_MSK(addr); 183 184 ret = spi_write_then_read(st->spi, st->data.d8, 1, 185 &st->data.d32, len); 186 if (ret < 0) 187 return ret; 188 189 return (be32_to_cpu(st->data.d32) >> shift); 190 } 191 192 static int ad7768_spi_reg_write(struct ad7768_state *st, 193 unsigned int addr, 194 unsigned int val) 195 { 196 st->data.d8[0] = AD7768_WR_FLAG_MSK(addr); 197 st->data.d8[1] = val & 0xFF; 198 199 return spi_write(st->spi, st->data.d8, 2); 200 } 201 202 static int ad7768_set_mode(struct ad7768_state *st, 203 enum ad7768_conv_mode mode) 204 { 205 int regval; 206 207 regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); 208 if (regval < 0) 209 return regval; 210 211 regval &= ~AD7768_CONV_MODE_MSK; 212 regval |= AD7768_CONV_MODE(mode); 213 214 return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval); 215 } 216 217 static int ad7768_scan_direct(struct iio_dev *indio_dev) 218 { 219 struct ad7768_state *st = iio_priv(indio_dev); 220 int readval, ret; 221 222 reinit_completion(&st->completion); 223 224 ret = ad7768_set_mode(st, AD7768_ONE_SHOT); 225 if (ret < 0) 226 return ret; 227 228 ret = wait_for_completion_timeout(&st->completion, 229 msecs_to_jiffies(1000)); 230 if (!ret) 231 return -ETIMEDOUT; 232 233 readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); 234 if (readval < 0) 235 return readval; 236 /* 237 * Any SPI configuration of the AD7768-1 can only be 238 * performed in continuous conversion mode. 239 */ 240 ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 241 if (ret < 0) 242 return ret; 243 244 return readval; 245 } 246 247 static int ad7768_reg_access(struct iio_dev *indio_dev, 248 unsigned int reg, 249 unsigned int writeval, 250 unsigned int *readval) 251 { 252 struct ad7768_state *st = iio_priv(indio_dev); 253 int ret; 254 255 mutex_lock(&st->lock); 256 if (readval) { 257 ret = ad7768_spi_reg_read(st, reg, 1); 258 if (ret < 0) 259 goto err_unlock; 260 *readval = ret; 261 ret = 0; 262 } else { 263 ret = ad7768_spi_reg_write(st, reg, writeval); 264 } 265 err_unlock: 266 mutex_unlock(&st->lock); 267 268 return ret; 269 } 270 271 static int ad7768_set_dig_fil(struct ad7768_state *st, 272 enum ad7768_dec_rate dec_rate) 273 { 274 unsigned int mode; 275 int ret; 276 277 if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) 278 mode = AD7768_DIG_FIL_FIL(dec_rate); 279 else 280 mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); 281 282 ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); 283 if (ret < 0) 284 return ret; 285 286 /* A sync-in pulse is required every time the filter dec rate changes */ 287 gpiod_set_value(st->gpio_sync_in, 1); 288 gpiod_set_value(st->gpio_sync_in, 0); 289 290 return 0; 291 } 292 293 static int ad7768_set_freq(struct ad7768_state *st, 294 unsigned int freq) 295 { 296 unsigned int diff_new, diff_old, pwr_mode, i, idx; 297 int res, ret; 298 299 diff_old = U32_MAX; 300 idx = 0; 301 302 res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); 303 304 /* Find the closest match for the desired sampling frequency */ 305 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 306 diff_new = abs(res - ad7768_clk_config[i].clk_div); 307 if (diff_new < diff_old) { 308 diff_old = diff_new; 309 idx = i; 310 } 311 } 312 313 /* 314 * Set both the mclk_div and pwrmode with a single write to the 315 * POWER_CLOCK register 316 */ 317 pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | 318 AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); 319 ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode); 320 if (ret < 0) 321 return ret; 322 323 ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); 324 if (ret < 0) 325 return ret; 326 327 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 328 ad7768_clk_config[idx].clk_div); 329 330 return 0; 331 } 332 333 static ssize_t ad7768_sampling_freq_avail(struct device *dev, 334 struct device_attribute *attr, 335 char *buf) 336 { 337 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 338 struct ad7768_state *st = iio_priv(indio_dev); 339 unsigned int freq; 340 int i, len = 0; 341 342 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 343 freq = DIV_ROUND_CLOSEST(st->mclk_freq, 344 ad7768_clk_config[i].clk_div); 345 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); 346 } 347 348 buf[len - 1] = '\n'; 349 350 return len; 351 } 352 353 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); 354 355 static int ad7768_read_raw(struct iio_dev *indio_dev, 356 struct iio_chan_spec const *chan, 357 int *val, int *val2, long info) 358 { 359 struct ad7768_state *st = iio_priv(indio_dev); 360 int scale_uv, ret; 361 362 switch (info) { 363 case IIO_CHAN_INFO_RAW: 364 ret = iio_device_claim_direct_mode(indio_dev); 365 if (ret) 366 return ret; 367 368 ret = ad7768_scan_direct(indio_dev); 369 if (ret >= 0) 370 *val = ret; 371 372 iio_device_release_direct_mode(indio_dev); 373 if (ret < 0) 374 return ret; 375 376 return IIO_VAL_INT; 377 378 case IIO_CHAN_INFO_SCALE: 379 scale_uv = regulator_get_voltage(st->vref); 380 if (scale_uv < 0) 381 return scale_uv; 382 383 *val = (scale_uv * 2) / 1000; 384 *val2 = chan->scan_type.realbits; 385 386 return IIO_VAL_FRACTIONAL_LOG2; 387 388 case IIO_CHAN_INFO_SAMP_FREQ: 389 *val = st->samp_freq; 390 391 return IIO_VAL_INT; 392 } 393 394 return -EINVAL; 395 } 396 397 static int ad7768_write_raw(struct iio_dev *indio_dev, 398 struct iio_chan_spec const *chan, 399 int val, int val2, long info) 400 { 401 struct ad7768_state *st = iio_priv(indio_dev); 402 403 switch (info) { 404 case IIO_CHAN_INFO_SAMP_FREQ: 405 return ad7768_set_freq(st, val); 406 default: 407 return -EINVAL; 408 } 409 } 410 411 static int ad7768_read_label(struct iio_dev *indio_dev, 412 const struct iio_chan_spec *chan, char *label) 413 { 414 struct ad7768_state *st = iio_priv(indio_dev); 415 416 return sprintf(label, "%s\n", st->labels[chan->channel]); 417 } 418 419 static struct attribute *ad7768_attributes[] = { 420 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 421 NULL 422 }; 423 424 static const struct attribute_group ad7768_group = { 425 .attrs = ad7768_attributes, 426 }; 427 428 static const struct iio_info ad7768_info = { 429 .attrs = &ad7768_group, 430 .read_raw = &ad7768_read_raw, 431 .write_raw = &ad7768_write_raw, 432 .read_label = ad7768_read_label, 433 .debugfs_reg_access = &ad7768_reg_access, 434 }; 435 436 static int ad7768_setup(struct ad7768_state *st) 437 { 438 int ret; 439 440 /* 441 * Two writes to the SPI_RESET[1:0] bits are required to initiate 442 * a software reset. The bits must first be set to 11, and then 443 * to 10. When the sequence is detected, the reset occurs. 444 * See the datasheet, page 70. 445 */ 446 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3); 447 if (ret) 448 return ret; 449 450 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2); 451 if (ret) 452 return ret; 453 454 st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", 455 GPIOD_OUT_LOW); 456 if (IS_ERR(st->gpio_sync_in)) 457 return PTR_ERR(st->gpio_sync_in); 458 459 /* Set the default sampling frequency to 32000 kSPS */ 460 return ad7768_set_freq(st, 32000); 461 } 462 463 static irqreturn_t ad7768_trigger_handler(int irq, void *p) 464 { 465 struct iio_poll_func *pf = p; 466 struct iio_dev *indio_dev = pf->indio_dev; 467 struct ad7768_state *st = iio_priv(indio_dev); 468 int ret; 469 470 mutex_lock(&st->lock); 471 472 ret = spi_read(st->spi, &st->data.d32, 3); 473 if (ret < 0) 474 goto err_unlock; 475 476 iio_push_to_buffers_with_timestamp(indio_dev, &st->data.d32, 477 iio_get_time_ns(indio_dev)); 478 479 iio_trigger_notify_done(indio_dev->trig); 480 err_unlock: 481 mutex_unlock(&st->lock); 482 483 return IRQ_HANDLED; 484 } 485 486 static irqreturn_t ad7768_interrupt(int irq, void *dev_id) 487 { 488 struct iio_dev *indio_dev = dev_id; 489 struct ad7768_state *st = iio_priv(indio_dev); 490 491 if (iio_buffer_enabled(indio_dev)) 492 iio_trigger_poll(st->trig); 493 else 494 complete(&st->completion); 495 496 return IRQ_HANDLED; 497 }; 498 499 static int ad7768_buffer_postenable(struct iio_dev *indio_dev) 500 { 501 struct ad7768_state *st = iio_priv(indio_dev); 502 503 /* 504 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 505 * continuous read mode. Subsequent data reads do not require an 506 * initial 8-bit write to query the ADC_DATA register. 507 */ 508 return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01); 509 } 510 511 static int ad7768_buffer_predisable(struct iio_dev *indio_dev) 512 { 513 struct ad7768_state *st = iio_priv(indio_dev); 514 515 /* 516 * To exit continuous read mode, perform a single read of the ADC_DATA 517 * reg (0x2C), which allows further configuration of the device. 518 */ 519 return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); 520 } 521 522 static const struct iio_buffer_setup_ops ad7768_buffer_ops = { 523 .postenable = &ad7768_buffer_postenable, 524 .predisable = &ad7768_buffer_predisable, 525 }; 526 527 static const struct iio_trigger_ops ad7768_trigger_ops = { 528 .validate_device = iio_trigger_validate_own_device, 529 }; 530 531 static void ad7768_regulator_disable(void *data) 532 { 533 struct ad7768_state *st = data; 534 535 regulator_disable(st->vref); 536 } 537 538 static void ad7768_clk_disable(void *data) 539 { 540 struct ad7768_state *st = data; 541 542 clk_disable_unprepare(st->mclk); 543 } 544 545 static int ad7768_set_channel_label(struct iio_dev *indio_dev, 546 int num_channels) 547 { 548 struct ad7768_state *st = iio_priv(indio_dev); 549 struct device *device = indio_dev->dev.parent; 550 struct fwnode_handle *fwnode; 551 struct fwnode_handle *child; 552 const char *label; 553 int crt_ch = 0; 554 555 fwnode = dev_fwnode(device); 556 fwnode_for_each_child_node(fwnode, child) { 557 if (fwnode_property_read_u32(child, "reg", &crt_ch)) 558 continue; 559 560 if (crt_ch >= num_channels) 561 continue; 562 563 if (fwnode_property_read_string(child, "label", &label)) 564 continue; 565 566 st->labels[crt_ch] = label; 567 } 568 569 return 0; 570 } 571 572 static int ad7768_probe(struct spi_device *spi) 573 { 574 struct ad7768_state *st; 575 struct iio_dev *indio_dev; 576 int ret; 577 578 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 579 if (!indio_dev) 580 return -ENOMEM; 581 582 st = iio_priv(indio_dev); 583 st->spi = spi; 584 585 st->vref = devm_regulator_get(&spi->dev, "vref"); 586 if (IS_ERR(st->vref)) 587 return PTR_ERR(st->vref); 588 589 ret = regulator_enable(st->vref); 590 if (ret) { 591 dev_err(&spi->dev, "Failed to enable specified vref supply\n"); 592 return ret; 593 } 594 595 ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st); 596 if (ret) 597 return ret; 598 599 st->mclk = devm_clk_get(&spi->dev, "mclk"); 600 if (IS_ERR(st->mclk)) 601 return PTR_ERR(st->mclk); 602 603 ret = clk_prepare_enable(st->mclk); 604 if (ret < 0) 605 return ret; 606 607 ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st); 608 if (ret) 609 return ret; 610 611 st->mclk_freq = clk_get_rate(st->mclk); 612 613 spi_set_drvdata(spi, indio_dev); 614 mutex_init(&st->lock); 615 616 indio_dev->channels = ad7768_channels; 617 indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); 618 indio_dev->name = spi_get_device_id(spi)->name; 619 indio_dev->info = &ad7768_info; 620 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; 621 622 ret = ad7768_setup(st); 623 if (ret < 0) { 624 dev_err(&spi->dev, "AD7768 setup failed\n"); 625 return ret; 626 } 627 628 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", 629 indio_dev->name, indio_dev->id); 630 if (!st->trig) 631 return -ENOMEM; 632 633 st->trig->ops = &ad7768_trigger_ops; 634 iio_trigger_set_drvdata(st->trig, indio_dev); 635 ret = devm_iio_trigger_register(&spi->dev, st->trig); 636 if (ret) 637 return ret; 638 639 indio_dev->trig = iio_trigger_get(st->trig); 640 641 init_completion(&st->completion); 642 643 ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels)); 644 if (ret) 645 return ret; 646 647 ret = devm_request_irq(&spi->dev, spi->irq, 648 &ad7768_interrupt, 649 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 650 indio_dev->name, indio_dev); 651 if (ret) 652 return ret; 653 654 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 655 &iio_pollfunc_store_time, 656 &ad7768_trigger_handler, 657 &ad7768_buffer_ops); 658 if (ret) 659 return ret; 660 661 return devm_iio_device_register(&spi->dev, indio_dev); 662 } 663 664 static const struct spi_device_id ad7768_id_table[] = { 665 { "ad7768-1", 0 }, 666 {} 667 }; 668 MODULE_DEVICE_TABLE(spi, ad7768_id_table); 669 670 static const struct of_device_id ad7768_of_match[] = { 671 { .compatible = "adi,ad7768-1" }, 672 { }, 673 }; 674 MODULE_DEVICE_TABLE(of, ad7768_of_match); 675 676 static struct spi_driver ad7768_driver = { 677 .driver = { 678 .name = "ad7768-1", 679 .of_match_table = ad7768_of_match, 680 }, 681 .probe = ad7768_probe, 682 .id_table = ad7768_id_table, 683 }; 684 module_spi_driver(ad7768_driver); 685 686 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 687 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 688 MODULE_LICENSE("GPL v2"); 689