1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7606 SPI ADC driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/err.h> 9 #include <linux/module.h> 10 #include <linux/spi/spi.h> 11 #include <linux/types.h> 12 13 #include <linux/iio/iio.h> 14 #include "ad7606.h" 15 16 #define MAX_SPI_FREQ_HZ 23500000 /* VDRIVE above 4.75 V */ 17 18 #define AD7616_CONFIGURATION_REGISTER 0x02 19 #define AD7616_OS_MASK GENMASK(4, 2) 20 #define AD7616_BURST_MODE BIT(6) 21 #define AD7616_SEQEN_MODE BIT(5) 22 #define AD7616_RANGE_CH_A_ADDR_OFF 0x04 23 #define AD7616_RANGE_CH_B_ADDR_OFF 0x06 24 /* 25 * Range of channels from a group are stored in 2 registers. 26 * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register. 27 * For channels from second group(8-15) the order is the same, only with 28 * an offset of 2 for register address. 29 */ 30 #define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) 31 /* The range of the channel is stored in 2 bits */ 32 #define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) 33 #define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) 34 35 #define AD7606_CONFIGURATION_REGISTER 0x02 36 #define AD7606_SINGLE_DOUT 0x00 37 38 /* 39 * Range for AD7606B channels are stored in registers starting with address 0x3. 40 * Each register stores range for 2 channels(4 bits per channel). 41 */ 42 #define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) 43 #define AD7606_RANGE_CH_MODE(ch, mode) \ 44 ((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1))) 45 #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) 46 #define AD7606_OS_MODE 0x08 47 48 static const struct iio_chan_spec ad7616_sw_channels[] = { 49 IIO_CHAN_SOFT_TIMESTAMP(16), 50 AD7616_CHANNEL(0), 51 AD7616_CHANNEL(1), 52 AD7616_CHANNEL(2), 53 AD7616_CHANNEL(3), 54 AD7616_CHANNEL(4), 55 AD7616_CHANNEL(5), 56 AD7616_CHANNEL(6), 57 AD7616_CHANNEL(7), 58 AD7616_CHANNEL(8), 59 AD7616_CHANNEL(9), 60 AD7616_CHANNEL(10), 61 AD7616_CHANNEL(11), 62 AD7616_CHANNEL(12), 63 AD7616_CHANNEL(13), 64 AD7616_CHANNEL(14), 65 AD7616_CHANNEL(15), 66 }; 67 68 static const struct iio_chan_spec ad7606b_sw_channels[] = { 69 IIO_CHAN_SOFT_TIMESTAMP(8), 70 AD7606_SW_CHANNEL(0, 16), 71 AD7606_SW_CHANNEL(1, 16), 72 AD7606_SW_CHANNEL(2, 16), 73 AD7606_SW_CHANNEL(3, 16), 74 AD7606_SW_CHANNEL(4, 16), 75 AD7606_SW_CHANNEL(5, 16), 76 AD7606_SW_CHANNEL(6, 16), 77 AD7606_SW_CHANNEL(7, 16), 78 }; 79 80 static const struct iio_chan_spec ad7606c_18_sw_channels[] = { 81 IIO_CHAN_SOFT_TIMESTAMP(8), 82 AD7606_SW_CHANNEL(0, 18), 83 AD7606_SW_CHANNEL(1, 18), 84 AD7606_SW_CHANNEL(2, 18), 85 AD7606_SW_CHANNEL(3, 18), 86 AD7606_SW_CHANNEL(4, 18), 87 AD7606_SW_CHANNEL(5, 18), 88 AD7606_SW_CHANNEL(6, 18), 89 AD7606_SW_CHANNEL(7, 18), 90 }; 91 92 static const unsigned int ad7606B_oversampling_avail[9] = { 93 1, 2, 4, 8, 16, 32, 64, 128, 256 94 }; 95 96 static u16 ad7616_spi_rd_wr_cmd(int addr, char isWriteOp) 97 { 98 /* 99 * The address of register consist of one w/r bit 100 * 6 bits of address followed by one reserved bit. 101 */ 102 return ((addr & 0x7F) << 1) | ((isWriteOp & 0x1) << 7); 103 } 104 105 static u16 ad7606B_spi_rd_wr_cmd(int addr, char is_write_op) 106 { 107 /* 108 * The address of register consists of one bit which 109 * specifies a read command placed in bit 6, followed by 110 * 6 bits of address. 111 */ 112 return (addr & 0x3F) | (((~is_write_op) & 0x1) << 6); 113 } 114 115 static int ad7606_spi_read_block(struct device *dev, 116 int count, void *buf) 117 { 118 struct spi_device *spi = to_spi_device(dev); 119 int i, ret; 120 unsigned short *data = buf; 121 __be16 *bdata = buf; 122 123 ret = spi_read(spi, buf, count * 2); 124 if (ret < 0) { 125 dev_err(&spi->dev, "SPI read error\n"); 126 return ret; 127 } 128 129 for (i = 0; i < count; i++) 130 data[i] = be16_to_cpu(bdata[i]); 131 132 return 0; 133 } 134 135 static int ad7606_spi_read_block18to32(struct device *dev, 136 int count, void *buf) 137 { 138 struct spi_device *spi = to_spi_device(dev); 139 struct spi_transfer xfer = { 140 .bits_per_word = 18, 141 .len = count * sizeof(u32), 142 .rx_buf = buf, 143 }; 144 145 return spi_sync_transfer(spi, &xfer, 1); 146 } 147 148 static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr) 149 { 150 struct spi_device *spi = to_spi_device(st->dev); 151 struct spi_transfer t[] = { 152 { 153 .tx_buf = &st->d16[0], 154 .len = 2, 155 .cs_change = 0, 156 }, { 157 .rx_buf = &st->d16[1], 158 .len = 2, 159 }, 160 }; 161 int ret; 162 163 st->d16[0] = cpu_to_be16(st->bops->rd_wr_cmd(addr, 0) << 8); 164 165 ret = spi_sync_transfer(spi, t, ARRAY_SIZE(t)); 166 if (ret < 0) 167 return ret; 168 169 return be16_to_cpu(st->d16[1]); 170 } 171 172 static int ad7606_spi_reg_write(struct ad7606_state *st, 173 unsigned int addr, 174 unsigned int val) 175 { 176 struct spi_device *spi = to_spi_device(st->dev); 177 178 st->d16[0] = cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) | 179 (val & 0x1FF)); 180 181 return spi_write(spi, &st->d16[0], sizeof(st->d16[0])); 182 } 183 184 static int ad7606_spi_write_mask(struct ad7606_state *st, 185 unsigned int addr, 186 unsigned long mask, 187 unsigned int val) 188 { 189 int readval; 190 191 readval = st->bops->reg_read(st, addr); 192 if (readval < 0) 193 return readval; 194 195 readval &= ~mask; 196 readval |= val; 197 198 return st->bops->reg_write(st, addr, readval); 199 } 200 201 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) 202 { 203 struct ad7606_state *st = iio_priv(indio_dev); 204 unsigned int ch_addr, mode, ch_index; 205 206 207 /* 208 * Ad7616 has 16 channels divided in group A and group B. 209 * The range of channels from A are stored in registers with address 4 210 * while channels from B are stored in register with address 6. 211 * The last bit from channels determines if it is from group A or B 212 * because the order of channels in iio is 0A, 0B, 1A, 1B... 213 */ 214 ch_index = ch >> 1; 215 216 ch_addr = AD7616_RANGE_CH_ADDR(ch_index); 217 218 if ((ch & 0x1) == 0) /* channel A */ 219 ch_addr += AD7616_RANGE_CH_A_ADDR_OFF; 220 else /* channel B */ 221 ch_addr += AD7616_RANGE_CH_B_ADDR_OFF; 222 223 /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ 224 mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); 225 return st->bops->write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), 226 mode); 227 } 228 229 static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) 230 { 231 struct ad7606_state *st = iio_priv(indio_dev); 232 233 return st->bops->write_mask(st, AD7616_CONFIGURATION_REGISTER, 234 AD7616_OS_MASK, val << 2); 235 } 236 237 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) 238 { 239 struct ad7606_state *st = iio_priv(indio_dev); 240 241 return ad7606_spi_write_mask(st, 242 AD7606_RANGE_CH_ADDR(ch), 243 AD7606_RANGE_CH_MSK(ch), 244 AD7606_RANGE_CH_MODE(ch, val)); 245 } 246 247 static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) 248 { 249 struct ad7606_state *st = iio_priv(indio_dev); 250 251 return ad7606_spi_reg_write(st, AD7606_OS_MODE, val); 252 } 253 254 static int ad7616_sw_mode_config(struct iio_dev *indio_dev) 255 { 256 struct ad7606_state *st = iio_priv(indio_dev); 257 258 /* 259 * Scale can be configured individually for each channel 260 * in software mode. 261 */ 262 indio_dev->channels = ad7616_sw_channels; 263 264 st->write_scale = ad7616_write_scale_sw; 265 st->write_os = &ad7616_write_os_sw; 266 267 /* Activate Burst mode and SEQEN MODE */ 268 return st->bops->write_mask(st, 269 AD7616_CONFIGURATION_REGISTER, 270 AD7616_BURST_MODE | AD7616_SEQEN_MODE, 271 AD7616_BURST_MODE | AD7616_SEQEN_MODE); 272 } 273 274 static int ad7606B_sw_mode_config(struct iio_dev *indio_dev) 275 { 276 struct ad7606_state *st = iio_priv(indio_dev); 277 DECLARE_BITMAP(os, 3); 278 279 bitmap_fill(os, 3); 280 /* 281 * Software mode is enabled when all three oversampling 282 * pins are set to high. If oversampling gpios are defined 283 * in the device tree, then they need to be set to high, 284 * otherwise, they must be hardwired to VDD 285 */ 286 if (st->gpio_os) { 287 gpiod_set_array_value(st->gpio_os->ndescs, 288 st->gpio_os->desc, st->gpio_os->info, os); 289 } 290 /* OS of 128 and 256 are available only in software mode */ 291 st->oversampling_avail = ad7606B_oversampling_avail; 292 st->num_os_ratios = ARRAY_SIZE(ad7606B_oversampling_avail); 293 294 st->write_scale = ad7606_write_scale_sw; 295 st->write_os = &ad7606_write_os_sw; 296 297 /* Configure device spi to output on a single channel */ 298 st->bops->reg_write(st, 299 AD7606_CONFIGURATION_REGISTER, 300 AD7606_SINGLE_DOUT); 301 302 /* 303 * Scale can be configured individually for each channel 304 * in software mode. 305 */ 306 indio_dev->channels = ad7606b_sw_channels; 307 308 return 0; 309 } 310 311 static int ad7606c_18_sw_mode_config(struct iio_dev *indio_dev) 312 { 313 int ret; 314 315 ret = ad7606B_sw_mode_config(indio_dev); 316 if (ret) 317 return ret; 318 319 indio_dev->channels = ad7606c_18_sw_channels; 320 321 return 0; 322 } 323 324 static const struct ad7606_bus_ops ad7606_spi_bops = { 325 .read_block = ad7606_spi_read_block, 326 }; 327 328 static const struct ad7606_bus_ops ad7616_spi_bops = { 329 .read_block = ad7606_spi_read_block, 330 .reg_read = ad7606_spi_reg_read, 331 .reg_write = ad7606_spi_reg_write, 332 .write_mask = ad7606_spi_write_mask, 333 .rd_wr_cmd = ad7616_spi_rd_wr_cmd, 334 .sw_mode_config = ad7616_sw_mode_config, 335 }; 336 337 static const struct ad7606_bus_ops ad7606B_spi_bops = { 338 .read_block = ad7606_spi_read_block, 339 .reg_read = ad7606_spi_reg_read, 340 .reg_write = ad7606_spi_reg_write, 341 .write_mask = ad7606_spi_write_mask, 342 .rd_wr_cmd = ad7606B_spi_rd_wr_cmd, 343 .sw_mode_config = ad7606B_sw_mode_config, 344 }; 345 346 static const struct ad7606_bus_ops ad7606c_18_spi_bops = { 347 .read_block = ad7606_spi_read_block18to32, 348 .reg_read = ad7606_spi_reg_read, 349 .reg_write = ad7606_spi_reg_write, 350 .write_mask = ad7606_spi_write_mask, 351 .rd_wr_cmd = ad7606B_spi_rd_wr_cmd, 352 .sw_mode_config = ad7606c_18_sw_mode_config, 353 }; 354 355 static int ad7606_spi_probe(struct spi_device *spi) 356 { 357 const struct spi_device_id *id = spi_get_device_id(spi); 358 const struct ad7606_bus_ops *bops; 359 360 switch (id->driver_data) { 361 case ID_AD7616: 362 bops = &ad7616_spi_bops; 363 break; 364 case ID_AD7606B: 365 case ID_AD7606C_16: 366 bops = &ad7606B_spi_bops; 367 break; 368 case ID_AD7606C_18: 369 bops = &ad7606c_18_spi_bops; 370 break; 371 default: 372 bops = &ad7606_spi_bops; 373 break; 374 } 375 376 return ad7606_probe(&spi->dev, spi->irq, NULL, 377 id->name, id->driver_data, 378 bops); 379 } 380 381 static const struct spi_device_id ad7606_id_table[] = { 382 { "ad7605-4", ID_AD7605_4 }, 383 { "ad7606-4", ID_AD7606_4 }, 384 { "ad7606-6", ID_AD7606_6 }, 385 { "ad7606-8", ID_AD7606_8 }, 386 { "ad7606b", ID_AD7606B }, 387 { "ad7606c-16", ID_AD7606C_16 }, 388 { "ad7606c-18", ID_AD7606C_18 }, 389 { "ad7616", ID_AD7616 }, 390 { } 391 }; 392 MODULE_DEVICE_TABLE(spi, ad7606_id_table); 393 394 static const struct of_device_id ad7606_of_match[] = { 395 { .compatible = "adi,ad7605-4" }, 396 { .compatible = "adi,ad7606-4" }, 397 { .compatible = "adi,ad7606-6" }, 398 { .compatible = "adi,ad7606-8" }, 399 { .compatible = "adi,ad7606b" }, 400 { .compatible = "adi,ad7606c-16" }, 401 { .compatible = "adi,ad7606c-18" }, 402 { .compatible = "adi,ad7616" }, 403 { } 404 }; 405 MODULE_DEVICE_TABLE(of, ad7606_of_match); 406 407 static struct spi_driver ad7606_driver = { 408 .driver = { 409 .name = "ad7606", 410 .of_match_table = ad7606_of_match, 411 .pm = AD7606_PM_OPS, 412 }, 413 .probe = ad7606_spi_probe, 414 .id_table = ad7606_id_table, 415 }; 416 module_spi_driver(ad7606_driver); 417 418 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 419 MODULE_DESCRIPTION("Analog Devices AD7606 ADC"); 420 MODULE_LICENSE("GPL v2"); 421 MODULE_IMPORT_NS(IIO_AD7606); 422