1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD738x Simultaneous Sampling SAR ADCs 4 * 5 * Copyright 2017 Analog Devices Inc. 6 * Copyright 2024 BayLibre, SAS 7 * 8 * Datasheets of supported parts: 9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf 10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf 11 * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-7388.pdf 12 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf 13 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf 14 * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf 15 * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387-4-7388-4.pdf 16 * ad7389-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7389-4.pdf 17 * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4370-4.pdf 18 * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4380-4.pdf 19 * adaq4381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4381-4.pdf 20 * 21 * HDL ad738x_fmc: https://analogdevicesinc.github.io/hdl/projects/ad738x_fmc/index.html 22 * 23 */ 24 25 #include <linux/align.h> 26 #include <linux/bitfield.h> 27 #include <linux/bitops.h> 28 #include <linux/cleanup.h> 29 #include <linux/device.h> 30 #include <linux/err.h> 31 #include <linux/kernel.h> 32 #include <linux/math.h> 33 #include <linux/module.h> 34 #include <linux/regmap.h> 35 #include <linux/regulator/consumer.h> 36 #include <linux/slab.h> 37 #include <linux/spi/offload/consumer.h> 38 #include <linux/spi/spi.h> 39 #include <linux/units.h> 40 #include <linux/util_macros.h> 41 42 #include <linux/iio/buffer.h> 43 #include <linux/iio/buffer-dmaengine.h> 44 #include <linux/iio/events.h> 45 #include <linux/iio/iio.h> 46 #include <linux/iio/trigger_consumer.h> 47 #include <linux/iio/triggered_buffer.h> 48 49 #define MAX_NUM_CHANNELS 8 50 /* 2.5V internal reference voltage */ 51 #define AD7380_INTERNAL_REF_MV 2500 52 /* 3.3V internal reference voltage for ADAQ */ 53 #define ADAQ4380_INTERNAL_REF_MV 3300 54 55 /* reading and writing registers is more reliable at lower than max speed */ 56 #define AD7380_REG_WR_SPEED_HZ 10000000 57 58 #define AD7380_REG_WR BIT(15) 59 #define AD7380_REG_REGADDR GENMASK(14, 12) 60 #define AD7380_REG_DATA GENMASK(11, 0) 61 62 #define AD7380_REG_ADDR_NOP 0x0 63 #define AD7380_REG_ADDR_CONFIG1 0x1 64 #define AD7380_REG_ADDR_CONFIG2 0x2 65 #define AD7380_REG_ADDR_ALERT 0x3 66 #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 67 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 68 69 #define AD7380_CONFIG1_CH BIT(11) 70 #define AD7380_CONFIG1_SEQ BIT(10) 71 #define AD7380_CONFIG1_OS_MODE BIT(9) 72 #define AD7380_CONFIG1_OSR GENMASK(8, 6) 73 #define AD7380_CONFIG1_CRC_W BIT(5) 74 #define AD7380_CONFIG1_CRC_R BIT(4) 75 #define AD7380_CONFIG1_ALERTEN BIT(3) 76 #define AD7380_CONFIG1_RES BIT(2) 77 #define AD7380_CONFIG1_REFSEL BIT(1) 78 #define AD7380_CONFIG1_PMODE BIT(0) 79 80 #define AD7380_CONFIG2_SDO2 GENMASK(9, 8) 81 #define AD7380_CONFIG2_SDO BIT(8) 82 #define AD7380_CONFIG2_RESET GENMASK(7, 0) 83 84 #define AD7380_CONFIG2_RESET_SOFT 0x3C 85 #define AD7380_CONFIG2_RESET_HARD 0xFF 86 87 #define AD7380_ALERT_LOW_TH GENMASK(11, 0) 88 #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) 89 90 #define T_CONVERT_NS 190 /* conversion time */ 91 #define T_CONVERT_0_NS 10 /* 1st conversion start time (oversampling) */ 92 #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ 93 #define T_POWERUP_US 5000 /* Power up */ 94 95 /* 96 * AD738x support several SDO lines to increase throughput, but driver currently 97 * supports only 1 SDO line (standard SPI transaction) 98 */ 99 #define AD7380_NUM_SDO_LINES 1 100 #define AD7380_DEFAULT_GAIN_MILLI 1000 101 102 /* 103 * Using SPI offload, storagebits is always 32, so can't be used to compute struct 104 * spi_transfer.len. Using realbits instead. 105 */ 106 #define AD7380_SPI_BYTES(scan_type) ((scan_type)->realbits > 16 ? 4 : 2) 107 108 struct ad7380_timing_specs { 109 const unsigned int t_csh_ns; /* CS minimum high time */ 110 }; 111 112 struct ad7380_chip_info { 113 const char *name; 114 const struct iio_chan_spec *channels; 115 const struct iio_chan_spec *offload_channels; 116 unsigned int num_channels; 117 unsigned int num_simult_channels; 118 bool has_hardware_gain; 119 bool has_mux; 120 const char * const *supplies; 121 unsigned int num_supplies; 122 bool external_ref_only; 123 bool internal_ref_only; 124 unsigned int internal_ref_mv; 125 const char * const *vcm_supplies; 126 unsigned int num_vcm_supplies; 127 const unsigned long *available_scan_masks; 128 const struct ad7380_timing_specs *timing_specs; 129 u32 max_conversion_rate_hz; 130 }; 131 132 static const struct iio_event_spec ad7380_events[] = { 133 { 134 .type = IIO_EV_TYPE_THRESH, 135 .dir = IIO_EV_DIR_RISING, 136 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE), 137 }, 138 { 139 .type = IIO_EV_TYPE_THRESH, 140 .dir = IIO_EV_DIR_FALLING, 141 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE), 142 }, 143 { 144 .type = IIO_EV_TYPE_THRESH, 145 .dir = IIO_EV_DIR_EITHER, 146 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 147 }, 148 }; 149 150 enum { 151 AD7380_SCAN_TYPE_NORMAL, 152 AD7380_SCAN_TYPE_RESOLUTION_BOOST, 153 }; 154 155 /* Extended scan types for 12-bit unsigned chips. */ 156 static const struct iio_scan_type ad7380_scan_type_12_u[] = { 157 [AD7380_SCAN_TYPE_NORMAL] = { 158 .sign = 'u', 159 .realbits = 12, 160 .storagebits = 16, 161 .endianness = IIO_CPU, 162 }, 163 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 164 .sign = 'u', 165 .realbits = 14, 166 .storagebits = 16, 167 .endianness = IIO_CPU, 168 }, 169 }; 170 171 /* Extended scan types for 14-bit signed chips. */ 172 static const struct iio_scan_type ad7380_scan_type_14_s[] = { 173 [AD7380_SCAN_TYPE_NORMAL] = { 174 .sign = 's', 175 .realbits = 14, 176 .storagebits = 16, 177 .endianness = IIO_CPU, 178 }, 179 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 180 .sign = 's', 181 .realbits = 16, 182 .storagebits = 16, 183 .endianness = IIO_CPU, 184 }, 185 }; 186 187 /* Extended scan types for 14-bit unsigned chips. */ 188 static const struct iio_scan_type ad7380_scan_type_14_u[] = { 189 [AD7380_SCAN_TYPE_NORMAL] = { 190 .sign = 'u', 191 .realbits = 14, 192 .storagebits = 16, 193 .endianness = IIO_CPU, 194 }, 195 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 196 .sign = 'u', 197 .realbits = 16, 198 .storagebits = 16, 199 .endianness = IIO_CPU, 200 }, 201 }; 202 203 /* Extended scan types for 16-bit signed_chips. */ 204 static const struct iio_scan_type ad7380_scan_type_16_s[] = { 205 [AD7380_SCAN_TYPE_NORMAL] = { 206 .sign = 's', 207 .realbits = 16, 208 .storagebits = 16, 209 .endianness = IIO_CPU, 210 }, 211 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 212 .sign = 's', 213 .realbits = 18, 214 .storagebits = 32, 215 .endianness = IIO_CPU, 216 }, 217 }; 218 219 /* Extended scan types for 16-bit unsigned chips. */ 220 static const struct iio_scan_type ad7380_scan_type_16_u[] = { 221 [AD7380_SCAN_TYPE_NORMAL] = { 222 .sign = 'u', 223 .realbits = 16, 224 .storagebits = 16, 225 .endianness = IIO_CPU, 226 }, 227 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 228 .sign = 'u', 229 .realbits = 18, 230 .storagebits = 32, 231 .endianness = IIO_CPU, 232 }, 233 }; 234 235 /* 236 * Defining here scan types for offload mode, since with current available HDL 237 * only a value of 32 for storagebits is supported. 238 */ 239 240 /* Extended scan types for 12-bit unsigned chips, offload support. */ 241 static const struct iio_scan_type ad7380_scan_type_12_u_offload[] = { 242 [AD7380_SCAN_TYPE_NORMAL] = { 243 .sign = 'u', 244 .realbits = 12, 245 .storagebits = 32, 246 .endianness = IIO_CPU, 247 }, 248 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 249 .sign = 'u', 250 .realbits = 14, 251 .storagebits = 32, 252 .endianness = IIO_CPU, 253 }, 254 }; 255 256 /* Extended scan types for 14-bit signed chips, offload support. */ 257 static const struct iio_scan_type ad7380_scan_type_14_s_offload[] = { 258 [AD7380_SCAN_TYPE_NORMAL] = { 259 .sign = 's', 260 .realbits = 14, 261 .storagebits = 32, 262 .endianness = IIO_CPU, 263 }, 264 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 265 .sign = 's', 266 .realbits = 16, 267 .storagebits = 32, 268 .endianness = IIO_CPU, 269 }, 270 }; 271 272 /* Extended scan types for 14-bit unsigned chips, offload support. */ 273 static const struct iio_scan_type ad7380_scan_type_14_u_offload[] = { 274 [AD7380_SCAN_TYPE_NORMAL] = { 275 .sign = 'u', 276 .realbits = 14, 277 .storagebits = 32, 278 .endianness = IIO_CPU, 279 }, 280 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 281 .sign = 'u', 282 .realbits = 16, 283 .storagebits = 32, 284 .endianness = IIO_CPU, 285 }, 286 }; 287 288 /* Extended scan types for 16-bit signed_chips, offload support. */ 289 static const struct iio_scan_type ad7380_scan_type_16_s_offload[] = { 290 [AD7380_SCAN_TYPE_NORMAL] = { 291 .sign = 's', 292 .realbits = 16, 293 .storagebits = 32, 294 .endianness = IIO_CPU, 295 }, 296 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 297 .sign = 's', 298 .realbits = 18, 299 .storagebits = 32, 300 .endianness = IIO_CPU, 301 }, 302 }; 303 304 /* Extended scan types for 16-bit unsigned chips, offload support. */ 305 static const struct iio_scan_type ad7380_scan_type_16_u_offload[] = { 306 [AD7380_SCAN_TYPE_NORMAL] = { 307 .sign = 'u', 308 .realbits = 16, 309 .storagebits = 32, 310 .endianness = IIO_CPU, 311 }, 312 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 313 .sign = 'u', 314 .realbits = 18, 315 .storagebits = 32, 316 .endianness = IIO_CPU, 317 }, 318 }; 319 320 #define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \ 321 .type = IIO_VOLTAGE, \ 322 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 323 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 324 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 325 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ 326 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 327 .info_mask_shared_by_type_available = \ 328 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 329 .indexed = 1, \ 330 .differential = (diff), \ 331 .channel = (diff) ? (2 * (index)) : (index), \ 332 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 333 .scan_index = (index), \ 334 .has_ext_scan_type = 1, \ 335 .ext_scan_type = ad7380_scan_type_##bits##_##sign, \ 336 .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ 337 .event_spec = ad7380_events, \ 338 .num_event_specs = ARRAY_SIZE(ad7380_events), \ 339 } 340 341 #define _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, gain) { \ 342 .type = IIO_VOLTAGE, \ 343 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 344 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 345 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 346 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ 347 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ 348 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 349 .info_mask_shared_by_type_available = \ 350 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ 351 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 352 .indexed = 1, \ 353 .differential = (diff), \ 354 .channel = (diff) ? (2 * (index)) : (index), \ 355 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 356 .scan_index = (index), \ 357 .has_ext_scan_type = 1, \ 358 .ext_scan_type = ad7380_scan_type_##bits##_##sign##_offload, \ 359 .num_ext_scan_type = \ 360 ARRAY_SIZE(ad7380_scan_type_##bits##_##sign##_offload), \ 361 .event_spec = ad7380_events, \ 362 .num_event_specs = ARRAY_SIZE(ad7380_events), \ 363 } 364 365 /* 366 * Notes on the offload channels: 367 * - There is no soft timestamp since everything is done in hardware. 368 * - There is a sampling frequency attribute added. This controls the SPI 369 * offload trigger. 370 * - The storagebits value depends on the SPI offload provider. Currently there 371 * is only one supported provider, namely the ADI PULSAR ADC HDL project, 372 * which always uses 32-bit words for data values, even for <= 16-bit ADCs. 373 * So the value is just hardcoded to 32 for now. 374 */ 375 376 #define AD7380_CHANNEL(index, bits, diff, sign) \ 377 _AD7380_CHANNEL(index, bits, diff, sign, false) 378 379 #define ADAQ4380_CHANNEL(index, bits, diff, sign) \ 380 _AD7380_CHANNEL(index, bits, diff, sign, true) 381 382 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ 383 static const struct iio_chan_spec name[] = { \ 384 AD7380_CHANNEL(0, bits, diff, sign), \ 385 AD7380_CHANNEL(1, bits, diff, sign), \ 386 IIO_CHAN_SOFT_TIMESTAMP(2), \ 387 } 388 389 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \ 390 static const struct iio_chan_spec name[] = { \ 391 AD7380_CHANNEL(0, bits, diff, sign), \ 392 AD7380_CHANNEL(1, bits, diff, sign), \ 393 AD7380_CHANNEL(2, bits, diff, sign), \ 394 AD7380_CHANNEL(3, bits, diff, sign), \ 395 IIO_CHAN_SOFT_TIMESTAMP(4), \ 396 } 397 398 #define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \ 399 static const struct iio_chan_spec name[] = { \ 400 ADAQ4380_CHANNEL(0, bits, diff, sign), \ 401 ADAQ4380_CHANNEL(1, bits, diff, sign), \ 402 ADAQ4380_CHANNEL(2, bits, diff, sign), \ 403 ADAQ4380_CHANNEL(3, bits, diff, sign), \ 404 IIO_CHAN_SOFT_TIMESTAMP(4), \ 405 } 406 407 #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ 408 static const struct iio_chan_spec name[] = { \ 409 AD7380_CHANNEL(0, bits, diff, sign), \ 410 AD7380_CHANNEL(1, bits, diff, sign), \ 411 AD7380_CHANNEL(2, bits, diff, sign), \ 412 AD7380_CHANNEL(3, bits, diff, sign), \ 413 AD7380_CHANNEL(4, bits, diff, sign), \ 414 AD7380_CHANNEL(5, bits, diff, sign), \ 415 AD7380_CHANNEL(6, bits, diff, sign), \ 416 AD7380_CHANNEL(7, bits, diff, sign), \ 417 IIO_CHAN_SOFT_TIMESTAMP(8), \ 418 } 419 420 #define AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ 421 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, false) 422 423 #define ADAQ4380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ 424 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, true) 425 426 #define DEFINE_AD7380_2_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 427 static const struct iio_chan_spec name[] = { \ 428 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 429 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 430 } 431 432 #define DEFINE_AD7380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 433 static const struct iio_chan_spec name[] = { \ 434 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 435 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 436 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 437 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 438 } 439 440 #define DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 441 static const struct iio_chan_spec name[] = { \ 442 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 443 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 444 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 445 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 446 } 447 448 #define DEFINE_AD7380_8_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 449 static const struct iio_chan_spec name[] = { \ 450 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 451 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 452 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 453 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 454 AD7380_OFFLOAD_CHANNEL(4, bits, diff, sign), \ 455 AD7380_OFFLOAD_CHANNEL(5, bits, diff, sign), \ 456 AD7380_OFFLOAD_CHANNEL(6, bits, diff, sign), \ 457 AD7380_OFFLOAD_CHANNEL(7, bits, diff, sign), \ 458 } 459 460 /* fully differential */ 461 DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); 462 DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); 463 DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); 464 DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); 465 DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s); 466 DEFINE_ADAQ4380_4_CHANNEL(adaq4381_4_channels, 14, 1, s); 467 /* pseudo differential */ 468 DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); 469 DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); 470 DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s); 471 DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s); 472 473 /* Single ended */ 474 DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u); 475 DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u); 476 DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u); 477 DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u); 478 DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u); 479 DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u); 480 481 /* offload channels */ 482 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7380_offload_channels, 16, 1, s); 483 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7381_offload_channels, 14, 1, s); 484 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7380_4_offload_channels, 16, 1, s); 485 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7381_4_offload_channels, 14, 1, s); 486 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4380_4_offload_channels, 16, 1, s); 487 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4381_4_offload_channels, 14, 1, s); 488 489 /* pseudo differential */ 490 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7383_offload_channels, 16, 0, s); 491 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7384_offload_channels, 14, 0, s); 492 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7383_4_offload_channels, 16, 0, s); 493 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7384_4_offload_channels, 14, 0, s); 494 495 /* Single ended */ 496 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7386_offload_channels, 16, 0, u); 497 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7387_offload_channels, 14, 0, u); 498 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7388_offload_channels, 12, 0, u); 499 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7386_4_offload_channels, 16, 0, u); 500 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7387_4_offload_channels, 14, 0, u); 501 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7388_4_offload_channels, 12, 0, u); 502 503 static const char * const ad7380_supplies[] = { 504 "vcc", "vlogic", 505 }; 506 507 static const char * const adaq4380_supplies[] = { 508 "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin", 509 }; 510 511 static const char * const ad7380_2_channel_vcm_supplies[] = { 512 "aina", "ainb", 513 }; 514 515 static const char * const ad7380_4_channel_vcm_supplies[] = { 516 "aina", "ainb", "ainc", "aind", 517 }; 518 519 /* Since this is simultaneous sampling, we don't allow individual channels. */ 520 static const unsigned long ad7380_2_channel_scan_masks[] = { 521 GENMASK(1, 0), 522 0 523 }; 524 525 static const unsigned long ad7380_4_channel_scan_masks[] = { 526 GENMASK(3, 0), 527 0 528 }; 529 530 /* 531 * Single ended parts have a 2:1 multiplexer in front of each ADC. 532 * 533 * From an IIO point of view, all inputs are exported, i.e ad7386/7/8 534 * export 4 channels and ad7386-4/7-4/8-4 export 8 channels. 535 * 536 * Inputs AinX0 of multiplexers correspond to the first half of IIO channels 537 * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or 538 * 4-7). Example for AD7386/7/8 (2 channels parts): 539 * 540 * IIO | AD7386/7/8 541 * | +---------------------------- 542 * | | _____ ______ 543 * | | | | | | 544 * voltage0 | AinA0 --|--->| | | | 545 * | | | mux |----->| ADCA |--- 546 * voltage2 | AinA1 --|--->| | | | 547 * | | |_____| |_____ | 548 * | | _____ ______ 549 * | | | | | | 550 * voltage1 | AinB0 --|--->| | | | 551 * | | | mux |----->| ADCB |--- 552 * voltage3 | AinB1 --|--->| | | | 553 * | | |_____| |______| 554 * | | 555 * | +---------------------------- 556 * 557 * Since this is simultaneous sampling for AinX0 OR AinX1 we have two separate 558 * scan masks. 559 * When sequencer mode is enabled, chip automatically cycles through 560 * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all 561 * channels, at the cost of an extra read, thus dividing the maximum rate by 562 * two. 563 */ 564 enum { 565 AD7380_SCAN_MASK_CH_0, 566 AD7380_SCAN_MASK_CH_1, 567 AD7380_SCAN_MASK_SEQ, 568 }; 569 570 static const unsigned long ad7380_2x2_channel_scan_masks[] = { 571 [AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0), 572 [AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2), 573 [AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0), 574 0 575 }; 576 577 static const unsigned long ad7380_2x4_channel_scan_masks[] = { 578 [AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0), 579 [AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4), 580 [AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0), 581 0 582 }; 583 584 static const struct ad7380_timing_specs ad7380_timing = { 585 .t_csh_ns = 10, 586 }; 587 588 static const struct ad7380_timing_specs ad7380_4_timing = { 589 .t_csh_ns = 20, 590 }; 591 592 /* 593 * Available oversampling ratios. The indices correspond with the bit value 594 * expected by the chip. The available ratios depend on the averaging mode, 595 * only normal averaging is supported for now. 596 */ 597 static const int ad7380_oversampling_ratios[] = { 598 1, 2, 4, 8, 16, 32, 599 }; 600 601 /* Gains stored as fractions of 1000 so they can be expressed by integers. */ 602 static const int ad7380_gains[] = { 603 300, 600, 1000, 1600, 604 }; 605 606 static const struct ad7380_chip_info ad7380_chip_info = { 607 .name = "ad7380", 608 .channels = ad7380_channels, 609 .offload_channels = ad7380_offload_channels, 610 .num_channels = ARRAY_SIZE(ad7380_channels), 611 .num_simult_channels = 2, 612 .supplies = ad7380_supplies, 613 .num_supplies = ARRAY_SIZE(ad7380_supplies), 614 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 615 .available_scan_masks = ad7380_2_channel_scan_masks, 616 .timing_specs = &ad7380_timing, 617 .max_conversion_rate_hz = 4 * MEGA, 618 }; 619 620 static const struct ad7380_chip_info ad7381_chip_info = { 621 .name = "ad7381", 622 .channels = ad7381_channels, 623 .offload_channels = ad7381_offload_channels, 624 .num_channels = ARRAY_SIZE(ad7381_channels), 625 .num_simult_channels = 2, 626 .supplies = ad7380_supplies, 627 .num_supplies = ARRAY_SIZE(ad7380_supplies), 628 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 629 .available_scan_masks = ad7380_2_channel_scan_masks, 630 .timing_specs = &ad7380_timing, 631 .max_conversion_rate_hz = 4 * MEGA, 632 }; 633 634 static const struct ad7380_chip_info ad7383_chip_info = { 635 .name = "ad7383", 636 .channels = ad7383_channels, 637 .offload_channels = ad7383_offload_channels, 638 .num_channels = ARRAY_SIZE(ad7383_channels), 639 .num_simult_channels = 2, 640 .supplies = ad7380_supplies, 641 .num_supplies = ARRAY_SIZE(ad7380_supplies), 642 .vcm_supplies = ad7380_2_channel_vcm_supplies, 643 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 644 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 645 .available_scan_masks = ad7380_2_channel_scan_masks, 646 .timing_specs = &ad7380_timing, 647 .max_conversion_rate_hz = 4 * MEGA, 648 }; 649 650 static const struct ad7380_chip_info ad7384_chip_info = { 651 .name = "ad7384", 652 .channels = ad7384_channels, 653 .offload_channels = ad7384_offload_channels, 654 .num_channels = ARRAY_SIZE(ad7384_channels), 655 .num_simult_channels = 2, 656 .supplies = ad7380_supplies, 657 .num_supplies = ARRAY_SIZE(ad7380_supplies), 658 .vcm_supplies = ad7380_2_channel_vcm_supplies, 659 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 660 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 661 .available_scan_masks = ad7380_2_channel_scan_masks, 662 .timing_specs = &ad7380_timing, 663 .max_conversion_rate_hz = 4 * MEGA, 664 }; 665 666 static const struct ad7380_chip_info ad7386_chip_info = { 667 .name = "ad7386", 668 .channels = ad7386_channels, 669 .offload_channels = ad7386_offload_channels, 670 .num_channels = ARRAY_SIZE(ad7386_channels), 671 .num_simult_channels = 2, 672 .supplies = ad7380_supplies, 673 .num_supplies = ARRAY_SIZE(ad7380_supplies), 674 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 675 .has_mux = true, 676 .available_scan_masks = ad7380_2x2_channel_scan_masks, 677 .timing_specs = &ad7380_timing, 678 .max_conversion_rate_hz = 4 * MEGA, 679 }; 680 681 static const struct ad7380_chip_info ad7387_chip_info = { 682 .name = "ad7387", 683 .channels = ad7387_channels, 684 .offload_channels = ad7387_offload_channels, 685 .num_channels = ARRAY_SIZE(ad7387_channels), 686 .num_simult_channels = 2, 687 .supplies = ad7380_supplies, 688 .num_supplies = ARRAY_SIZE(ad7380_supplies), 689 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 690 .has_mux = true, 691 .available_scan_masks = ad7380_2x2_channel_scan_masks, 692 .timing_specs = &ad7380_timing, 693 .max_conversion_rate_hz = 4 * MEGA, 694 }; 695 696 static const struct ad7380_chip_info ad7388_chip_info = { 697 .name = "ad7388", 698 .channels = ad7388_channels, 699 .offload_channels = ad7388_offload_channels, 700 .num_channels = ARRAY_SIZE(ad7388_channels), 701 .num_simult_channels = 2, 702 .supplies = ad7380_supplies, 703 .num_supplies = ARRAY_SIZE(ad7380_supplies), 704 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 705 .has_mux = true, 706 .available_scan_masks = ad7380_2x2_channel_scan_masks, 707 .timing_specs = &ad7380_timing, 708 .max_conversion_rate_hz = 4 * MEGA, 709 }; 710 711 static const struct ad7380_chip_info ad7380_4_chip_info = { 712 .name = "ad7380-4", 713 .channels = ad7380_4_channels, 714 .offload_channels = ad7380_4_offload_channels, 715 .num_channels = ARRAY_SIZE(ad7380_4_channels), 716 .num_simult_channels = 4, 717 .supplies = ad7380_supplies, 718 .num_supplies = ARRAY_SIZE(ad7380_supplies), 719 .external_ref_only = true, 720 .available_scan_masks = ad7380_4_channel_scan_masks, 721 .timing_specs = &ad7380_4_timing, 722 .max_conversion_rate_hz = 4 * MEGA, 723 }; 724 725 static const struct ad7380_chip_info ad7381_4_chip_info = { 726 .name = "ad7381-4", 727 .channels = ad7381_4_channels, 728 .offload_channels = ad7381_4_offload_channels, 729 .num_channels = ARRAY_SIZE(ad7381_4_channels), 730 .num_simult_channels = 4, 731 .supplies = ad7380_supplies, 732 .num_supplies = ARRAY_SIZE(ad7380_supplies), 733 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 734 .available_scan_masks = ad7380_4_channel_scan_masks, 735 .timing_specs = &ad7380_4_timing, 736 .max_conversion_rate_hz = 4 * MEGA, 737 }; 738 739 static const struct ad7380_chip_info ad7383_4_chip_info = { 740 .name = "ad7383-4", 741 .channels = ad7383_4_channels, 742 .offload_channels = ad7383_4_offload_channels, 743 .num_channels = ARRAY_SIZE(ad7383_4_channels), 744 .num_simult_channels = 4, 745 .supplies = ad7380_supplies, 746 .num_supplies = ARRAY_SIZE(ad7380_supplies), 747 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 748 .vcm_supplies = ad7380_4_channel_vcm_supplies, 749 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 750 .available_scan_masks = ad7380_4_channel_scan_masks, 751 .timing_specs = &ad7380_4_timing, 752 .max_conversion_rate_hz = 4 * MEGA, 753 }; 754 755 static const struct ad7380_chip_info ad7384_4_chip_info = { 756 .name = "ad7384-4", 757 .channels = ad7384_4_channels, 758 .offload_channels = ad7384_4_offload_channels, 759 .num_channels = ARRAY_SIZE(ad7384_4_channels), 760 .num_simult_channels = 4, 761 .supplies = ad7380_supplies, 762 .num_supplies = ARRAY_SIZE(ad7380_supplies), 763 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 764 .vcm_supplies = ad7380_4_channel_vcm_supplies, 765 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 766 .available_scan_masks = ad7380_4_channel_scan_masks, 767 .timing_specs = &ad7380_4_timing, 768 .max_conversion_rate_hz = 4 * MEGA, 769 }; 770 771 static const struct ad7380_chip_info ad7386_4_chip_info = { 772 .name = "ad7386-4", 773 .channels = ad7386_4_channels, 774 .offload_channels = ad7386_4_offload_channels, 775 .num_channels = ARRAY_SIZE(ad7386_4_channels), 776 .num_simult_channels = 4, 777 .supplies = ad7380_supplies, 778 .num_supplies = ARRAY_SIZE(ad7380_supplies), 779 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 780 .has_mux = true, 781 .available_scan_masks = ad7380_2x4_channel_scan_masks, 782 .timing_specs = &ad7380_4_timing, 783 .max_conversion_rate_hz = 4 * MEGA, 784 }; 785 786 static const struct ad7380_chip_info ad7387_4_chip_info = { 787 .name = "ad7387-4", 788 .channels = ad7387_4_channels, 789 .offload_channels = ad7387_4_offload_channels, 790 .num_channels = ARRAY_SIZE(ad7387_4_channels), 791 .num_simult_channels = 4, 792 .supplies = ad7380_supplies, 793 .num_supplies = ARRAY_SIZE(ad7380_supplies), 794 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 795 .has_mux = true, 796 .available_scan_masks = ad7380_2x4_channel_scan_masks, 797 .timing_specs = &ad7380_4_timing, 798 .max_conversion_rate_hz = 4 * MEGA, 799 }; 800 801 static const struct ad7380_chip_info ad7388_4_chip_info = { 802 .name = "ad7388-4", 803 .channels = ad7388_4_channels, 804 .offload_channels = ad7388_4_offload_channels, 805 .num_channels = ARRAY_SIZE(ad7388_4_channels), 806 .num_simult_channels = 4, 807 .supplies = ad7380_supplies, 808 .num_supplies = ARRAY_SIZE(ad7380_supplies), 809 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 810 .has_mux = true, 811 .available_scan_masks = ad7380_2x4_channel_scan_masks, 812 .timing_specs = &ad7380_4_timing, 813 .max_conversion_rate_hz = 4 * MEGA, 814 }; 815 816 static const struct ad7380_chip_info ad7389_4_chip_info = { 817 .name = "ad7389-4", 818 .channels = ad7380_4_channels, 819 .offload_channels = ad7380_4_offload_channels, 820 .num_channels = ARRAY_SIZE(ad7380_4_channels), 821 .num_simult_channels = 4, 822 .supplies = ad7380_supplies, 823 .num_supplies = ARRAY_SIZE(ad7380_supplies), 824 .internal_ref_only = true, 825 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 826 .available_scan_masks = ad7380_4_channel_scan_masks, 827 .timing_specs = &ad7380_4_timing, 828 .max_conversion_rate_hz = 4 * MEGA, 829 }; 830 831 static const struct ad7380_chip_info adaq4370_4_chip_info = { 832 .name = "adaq4370-4", 833 .channels = adaq4380_4_channels, 834 .offload_channels = adaq4380_4_offload_channels, 835 .num_channels = ARRAY_SIZE(adaq4380_4_channels), 836 .num_simult_channels = 4, 837 .supplies = adaq4380_supplies, 838 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 839 .internal_ref_only = true, 840 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 841 .has_hardware_gain = true, 842 .available_scan_masks = ad7380_4_channel_scan_masks, 843 .timing_specs = &ad7380_4_timing, 844 .max_conversion_rate_hz = 2 * MEGA, 845 }; 846 847 static const struct ad7380_chip_info adaq4380_4_chip_info = { 848 .name = "adaq4380-4", 849 .channels = adaq4380_4_channels, 850 .offload_channels = adaq4380_4_offload_channels, 851 .num_channels = ARRAY_SIZE(adaq4380_4_channels), 852 .num_simult_channels = 4, 853 .supplies = adaq4380_supplies, 854 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 855 .internal_ref_only = true, 856 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 857 .has_hardware_gain = true, 858 .available_scan_masks = ad7380_4_channel_scan_masks, 859 .timing_specs = &ad7380_4_timing, 860 .max_conversion_rate_hz = 4 * MEGA, 861 }; 862 863 static const struct ad7380_chip_info adaq4381_4_chip_info = { 864 .name = "adaq4381-4", 865 .channels = adaq4381_4_channels, 866 .offload_channels = adaq4381_4_offload_channels, 867 .num_channels = ARRAY_SIZE(adaq4381_4_channels), 868 .num_simult_channels = 4, 869 .supplies = adaq4380_supplies, 870 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 871 .internal_ref_only = true, 872 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 873 .has_hardware_gain = true, 874 .available_scan_masks = ad7380_4_channel_scan_masks, 875 .timing_specs = &ad7380_4_timing, 876 }; 877 878 static const struct spi_offload_config ad7380_offload_config = { 879 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 880 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 881 }; 882 883 struct ad7380_state { 884 const struct ad7380_chip_info *chip_info; 885 struct spi_device *spi; 886 struct regmap *regmap; 887 bool resolution_boost_enabled; 888 unsigned int ch; 889 bool seq; 890 unsigned int vref_mv; 891 unsigned int vcm_mv[MAX_NUM_CHANNELS]; 892 unsigned int gain_milli[MAX_NUM_CHANNELS]; 893 /* xfers, message an buffer for reading sample data */ 894 struct spi_transfer normal_xfer[2]; 895 struct spi_message normal_msg; 896 struct spi_transfer seq_xfer[4]; 897 struct spi_message seq_msg; 898 struct spi_transfer offload_xfer; 899 struct spi_message offload_msg; 900 struct spi_offload *offload; 901 struct spi_offload_trigger *offload_trigger; 902 unsigned long offload_trigger_hz; 903 904 int sample_freq_range[3]; 905 /* 906 * DMA (thus cache coherency maintenance) requires the transfer buffers 907 * to live in their own cache lines. 908 * 909 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and 910 * one 64-bit aligned 64-bit timestamp. 911 */ 912 IIO_DECLARE_DMA_BUFFER_WITH_TS(u8, scan_data, MAX_NUM_CHANNELS * sizeof(u32)); 913 /* buffers for reading/writing registers */ 914 u16 tx; 915 u16 rx; 916 }; 917 918 static int ad7380_regmap_reg_write(void *context, unsigned int reg, 919 unsigned int val) 920 { 921 struct ad7380_state *st = context; 922 struct spi_transfer xfer = { 923 .speed_hz = AD7380_REG_WR_SPEED_HZ, 924 .bits_per_word = 16, 925 .len = 2, 926 .tx_buf = &st->tx, 927 }; 928 929 st->tx = FIELD_PREP(AD7380_REG_WR, 1) | 930 FIELD_PREP(AD7380_REG_REGADDR, reg) | 931 FIELD_PREP(AD7380_REG_DATA, val); 932 933 return spi_sync_transfer(st->spi, &xfer, 1); 934 } 935 936 static int ad7380_regmap_reg_read(void *context, unsigned int reg, 937 unsigned int *val) 938 { 939 struct ad7380_state *st = context; 940 struct spi_transfer xfers[] = { 941 { 942 .speed_hz = AD7380_REG_WR_SPEED_HZ, 943 .bits_per_word = 16, 944 .len = 2, 945 .tx_buf = &st->tx, 946 .cs_change = 1, 947 .cs_change_delay = { 948 .value = st->chip_info->timing_specs->t_csh_ns, 949 .unit = SPI_DELAY_UNIT_NSECS, 950 }, 951 }, { 952 .speed_hz = AD7380_REG_WR_SPEED_HZ, 953 .bits_per_word = 16, 954 .len = 2, 955 .rx_buf = &st->rx, 956 }, 957 }; 958 int ret; 959 960 st->tx = FIELD_PREP(AD7380_REG_WR, 0) | 961 FIELD_PREP(AD7380_REG_REGADDR, reg) | 962 FIELD_PREP(AD7380_REG_DATA, 0); 963 964 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 965 if (ret < 0) 966 return ret; 967 968 *val = FIELD_GET(AD7380_REG_DATA, st->rx); 969 970 return 0; 971 } 972 973 static const struct reg_default ad7380_reg_defaults[] = { 974 { AD7380_REG_ADDR_ALERT_LOW_TH, 0x800 }, 975 { AD7380_REG_ADDR_ALERT_HIGH_TH, 0x7FF }, 976 }; 977 978 static const struct regmap_range ad7380_volatile_reg_ranges[] = { 979 regmap_reg_range(AD7380_REG_ADDR_CONFIG2, AD7380_REG_ADDR_ALERT), 980 }; 981 982 static const struct regmap_access_table ad7380_volatile_regs = { 983 .yes_ranges = ad7380_volatile_reg_ranges, 984 .n_yes_ranges = ARRAY_SIZE(ad7380_volatile_reg_ranges), 985 }; 986 987 static const struct regmap_config ad7380_regmap_config = { 988 .reg_bits = 3, 989 .val_bits = 12, 990 .reg_read = ad7380_regmap_reg_read, 991 .reg_write = ad7380_regmap_reg_write, 992 .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH, 993 .can_sleep = true, 994 .reg_defaults = ad7380_reg_defaults, 995 .num_reg_defaults = ARRAY_SIZE(ad7380_reg_defaults), 996 .volatile_table = &ad7380_volatile_regs, 997 .cache_type = REGCACHE_MAPLE, 998 }; 999 1000 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, 1001 u32 writeval, u32 *readval) 1002 { 1003 struct ad7380_state *st = iio_priv(indio_dev); 1004 int ret; 1005 1006 if (!iio_device_claim_direct(indio_dev)) 1007 return -EBUSY; 1008 1009 if (readval) 1010 ret = regmap_read(st->regmap, reg, readval); 1011 else 1012 ret = regmap_write(st->regmap, reg, writeval); 1013 1014 iio_device_release_direct(indio_dev); 1015 1016 return ret; 1017 } 1018 1019 /** 1020 * ad7380_regval_to_osr - convert OSR register value to ratio 1021 * @regval: register value to check 1022 * 1023 * Returns: the ratio corresponding to the OSR register. If regval is not in 1024 * bound, return 1 (oversampling disabled) 1025 * 1026 */ 1027 static int ad7380_regval_to_osr(unsigned int regval) 1028 { 1029 if (regval >= ARRAY_SIZE(ad7380_oversampling_ratios)) 1030 return 1; 1031 1032 return ad7380_oversampling_ratios[regval]; 1033 } 1034 1035 static int ad7380_get_osr(struct ad7380_state *st, int *val) 1036 { 1037 u32 tmp; 1038 int ret; 1039 1040 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); 1041 if (ret) 1042 return ret; 1043 1044 *val = ad7380_regval_to_osr(FIELD_GET(AD7380_CONFIG1_OSR, tmp)); 1045 1046 return 0; 1047 } 1048 1049 /* 1050 * When switching channel, the ADC require an additional settling time. 1051 * According to the datasheet, data is value on the third CS low. We already 1052 * have an extra toggle before each read (either direct reads or buffered reads) 1053 * to sample correct data, so we just add a single CS toggle at the end of the 1054 * register write. 1055 */ 1056 static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch) 1057 { 1058 struct spi_transfer xfer = { 1059 .delay = { 1060 .value = T_CONVERT_NS, 1061 .unit = SPI_DELAY_UNIT_NSECS, 1062 } 1063 }; 1064 int oversampling_ratio, ret; 1065 1066 if (st->ch == ch) 1067 return 0; 1068 1069 ret = ad7380_get_osr(st, &oversampling_ratio); 1070 if (ret) 1071 return ret; 1072 1073 ret = regmap_update_bits(st->regmap, 1074 AD7380_REG_ADDR_CONFIG1, 1075 AD7380_CONFIG1_CH, 1076 FIELD_PREP(AD7380_CONFIG1_CH, ch)); 1077 1078 if (ret) 1079 return ret; 1080 1081 st->ch = ch; 1082 1083 if (oversampling_ratio > 1) 1084 xfer.delay.value = T_CONVERT_0_NS + 1085 T_CONVERT_X_NS * (oversampling_ratio - 1) * 1086 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; 1087 1088 return spi_sync_transfer(st->spi, &xfer, 1); 1089 } 1090 1091 /** 1092 * ad7380_update_xfers - update the SPI transfers base on the current scan type 1093 * @st: device instance specific state 1094 * @scan_type: current scan type 1095 */ 1096 static int ad7380_update_xfers(struct ad7380_state *st, 1097 const struct iio_scan_type *scan_type) 1098 { 1099 struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer; 1100 unsigned int t_convert = T_CONVERT_NS; 1101 int oversampling_ratio, ret; 1102 1103 /* 1104 * In the case of oversampling, conversion time is higher than in normal 1105 * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use 1106 * the maximum value for simplicity for now. 1107 */ 1108 ret = ad7380_get_osr(st, &oversampling_ratio); 1109 if (ret) 1110 return ret; 1111 1112 if (oversampling_ratio > 1) 1113 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS * 1114 (oversampling_ratio - 1) * 1115 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; 1116 1117 if (st->seq) { 1118 xfer[0].delay.value = xfer[1].delay.value = t_convert; 1119 xfer[0].delay.unit = xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS; 1120 xfer[2].bits_per_word = xfer[3].bits_per_word = 1121 scan_type->realbits; 1122 xfer[2].len = xfer[3].len = 1123 AD7380_SPI_BYTES(scan_type) * 1124 st->chip_info->num_simult_channels; 1125 xfer[3].rx_buf = xfer[2].rx_buf + xfer[2].len; 1126 /* Additional delay required here when oversampling is enabled */ 1127 if (oversampling_ratio > 1) 1128 xfer[2].delay.value = t_convert; 1129 else 1130 xfer[2].delay.value = 0; 1131 xfer[2].delay.unit = SPI_DELAY_UNIT_NSECS; 1132 } else { 1133 xfer[0].delay.value = t_convert; 1134 xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS; 1135 xfer[1].bits_per_word = scan_type->realbits; 1136 xfer[1].len = AD7380_SPI_BYTES(scan_type) * 1137 st->chip_info->num_simult_channels; 1138 } 1139 1140 return 0; 1141 } 1142 1143 static int ad7380_set_sample_freq(struct ad7380_state *st, int val) 1144 { 1145 struct spi_offload_trigger_config config = { 1146 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1147 .periodic = { 1148 .frequency_hz = val, 1149 }, 1150 }; 1151 int ret; 1152 1153 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 1154 if (ret) 1155 return ret; 1156 1157 st->offload_trigger_hz = config.periodic.frequency_hz; 1158 1159 return 0; 1160 } 1161 1162 static int ad7380_init_offload_msg(struct ad7380_state *st, 1163 struct iio_dev *indio_dev) 1164 { 1165 struct spi_transfer *xfer = &st->offload_xfer; 1166 struct device *dev = &st->spi->dev; 1167 const struct iio_scan_type *scan_type; 1168 int oversampling_ratio; 1169 int ret; 1170 1171 scan_type = iio_get_current_scan_type(indio_dev, 1172 &indio_dev->channels[0]); 1173 if (IS_ERR(scan_type)) 1174 return PTR_ERR(scan_type); 1175 1176 if (st->chip_info->has_mux) { 1177 int index; 1178 1179 ret = iio_active_scan_mask_index(indio_dev); 1180 if (ret < 0) 1181 return ret; 1182 1183 index = ret; 1184 if (index == AD7380_SCAN_MASK_SEQ) { 1185 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 1186 AD7380_CONFIG1_SEQ); 1187 if (ret) 1188 return ret; 1189 1190 st->seq = true; 1191 } else { 1192 ret = ad7380_set_ch(st, index); 1193 if (ret) 1194 return ret; 1195 } 1196 } 1197 1198 ret = ad7380_get_osr(st, &oversampling_ratio); 1199 if (ret) 1200 return ret; 1201 1202 xfer->bits_per_word = scan_type->realbits; 1203 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1204 xfer->len = AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_channels; 1205 1206 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); 1207 st->offload_msg.offload = st->offload; 1208 1209 ret = spi_optimize_message(st->spi, &st->offload_msg); 1210 if (ret) { 1211 dev_err(dev, "failed to prepare offload msg, err: %d\n", 1212 ret); 1213 return ret; 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int ad7380_offload_buffer_postenable(struct iio_dev *indio_dev) 1220 { 1221 struct ad7380_state *st = iio_priv(indio_dev); 1222 struct spi_offload_trigger_config config = { 1223 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1224 .periodic = { 1225 .frequency_hz = st->offload_trigger_hz, 1226 }, 1227 }; 1228 int ret; 1229 1230 ret = ad7380_init_offload_msg(st, indio_dev); 1231 if (ret) 1232 return ret; 1233 1234 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config); 1235 if (ret) 1236 spi_unoptimize_message(&st->offload_msg); 1237 1238 return ret; 1239 } 1240 1241 static int ad7380_offload_buffer_predisable(struct iio_dev *indio_dev) 1242 { 1243 struct ad7380_state *st = iio_priv(indio_dev); 1244 int ret; 1245 1246 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1247 spi_unoptimize_message(&st->offload_msg); 1248 1249 if (st->seq) { 1250 ret = regmap_update_bits(st->regmap, 1251 AD7380_REG_ADDR_CONFIG1, 1252 AD7380_CONFIG1_SEQ, 1253 FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); 1254 if (ret) 1255 return ret; 1256 1257 st->seq = false; 1258 } 1259 1260 return 0; 1261 } 1262 1263 static const struct iio_buffer_setup_ops ad7380_offload_buffer_setup_ops = { 1264 .postenable = ad7380_offload_buffer_postenable, 1265 .predisable = ad7380_offload_buffer_predisable, 1266 }; 1267 1268 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) 1269 { 1270 struct ad7380_state *st = iio_priv(indio_dev); 1271 const struct iio_scan_type *scan_type; 1272 struct spi_message *msg = &st->normal_msg; 1273 int ret; 1274 1275 /* 1276 * Currently, we always read all channels at the same time. The scan_type 1277 * is the same for all channels, so we just pass the first channel. 1278 */ 1279 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1280 if (IS_ERR(scan_type)) 1281 return PTR_ERR(scan_type); 1282 1283 if (st->chip_info->has_mux) { 1284 unsigned int index; 1285 1286 /* 1287 * Depending on the requested scan_mask and current state, 1288 * we need to either change CH bit, or enable sequencer mode 1289 * to sample correct data. 1290 * Sequencer mode is enabled if active mask corresponds to all 1291 * IIO channels enabled. Otherwise, CH bit is set. 1292 */ 1293 ret = iio_active_scan_mask_index(indio_dev); 1294 if (ret < 0) 1295 return ret; 1296 1297 index = ret; 1298 if (index == AD7380_SCAN_MASK_SEQ) { 1299 ret = regmap_update_bits(st->regmap, 1300 AD7380_REG_ADDR_CONFIG1, 1301 AD7380_CONFIG1_SEQ, 1302 FIELD_PREP(AD7380_CONFIG1_SEQ, 1)); 1303 if (ret) 1304 return ret; 1305 msg = &st->seq_msg; 1306 st->seq = true; 1307 } else { 1308 ret = ad7380_set_ch(st, index); 1309 if (ret) 1310 return ret; 1311 } 1312 1313 } 1314 1315 ret = ad7380_update_xfers(st, scan_type); 1316 if (ret) 1317 return ret; 1318 1319 return spi_optimize_message(st->spi, msg); 1320 } 1321 1322 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev) 1323 { 1324 struct ad7380_state *st = iio_priv(indio_dev); 1325 struct spi_message *msg = &st->normal_msg; 1326 int ret; 1327 1328 if (st->seq) { 1329 ret = regmap_update_bits(st->regmap, 1330 AD7380_REG_ADDR_CONFIG1, 1331 AD7380_CONFIG1_SEQ, 1332 FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); 1333 if (ret) 1334 return ret; 1335 1336 msg = &st->seq_msg; 1337 st->seq = false; 1338 } 1339 1340 spi_unoptimize_message(msg); 1341 1342 return 0; 1343 } 1344 1345 static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = { 1346 .preenable = ad7380_triggered_buffer_preenable, 1347 .postdisable = ad7380_triggered_buffer_postdisable, 1348 }; 1349 1350 static irqreturn_t ad7380_trigger_handler(int irq, void *p) 1351 { 1352 struct iio_poll_func *pf = p; 1353 struct iio_dev *indio_dev = pf->indio_dev; 1354 struct ad7380_state *st = iio_priv(indio_dev); 1355 struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg; 1356 int ret; 1357 1358 ret = spi_sync(st->spi, msg); 1359 if (ret) 1360 goto out; 1361 1362 iio_push_to_buffers_with_ts(indio_dev, &st->scan_data, sizeof(st->scan_data), 1363 pf->timestamp); 1364 1365 out: 1366 iio_trigger_notify_done(indio_dev->trig); 1367 1368 return IRQ_HANDLED; 1369 } 1370 1371 static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index, 1372 const struct iio_scan_type *scan_type, int *val) 1373 { 1374 unsigned int index = scan_index; 1375 int ret; 1376 1377 if (st->chip_info->has_mux) { 1378 unsigned int ch = 0; 1379 1380 if (index >= st->chip_info->num_simult_channels) { 1381 index -= st->chip_info->num_simult_channels; 1382 ch = 1; 1383 } 1384 1385 ret = ad7380_set_ch(st, ch); 1386 if (ret) 1387 return ret; 1388 } 1389 1390 ret = ad7380_update_xfers(st, scan_type); 1391 if (ret) 1392 return ret; 1393 1394 ret = spi_sync(st->spi, &st->normal_msg); 1395 if (ret < 0) 1396 return ret; 1397 1398 if (scan_type->realbits > 16) { 1399 if (scan_type->sign == 's') 1400 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index), 1401 scan_type->realbits - 1); 1402 else 1403 *val = *(u32 *)(st->scan_data + 4 * index) & 1404 GENMASK(scan_type->realbits - 1, 0); 1405 } else { 1406 if (scan_type->sign == 's') 1407 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index), 1408 scan_type->realbits - 1); 1409 else 1410 *val = *(u16 *)(st->scan_data + 2 * index) & 1411 GENMASK(scan_type->realbits - 1, 0); 1412 } 1413 1414 return IIO_VAL_INT; 1415 } 1416 1417 static int ad7380_read_raw(struct iio_dev *indio_dev, 1418 struct iio_chan_spec const *chan, 1419 int *val, int *val2, long info) 1420 { 1421 struct ad7380_state *st = iio_priv(indio_dev); 1422 const struct iio_scan_type *scan_type; 1423 int ret; 1424 1425 scan_type = iio_get_current_scan_type(indio_dev, chan); 1426 1427 if (IS_ERR(scan_type)) 1428 return PTR_ERR(scan_type); 1429 1430 switch (info) { 1431 case IIO_CHAN_INFO_RAW: 1432 if (!iio_device_claim_direct(indio_dev)) 1433 return -EBUSY; 1434 1435 ret = ad7380_read_direct(st, chan->scan_index, 1436 scan_type, val); 1437 1438 iio_device_release_direct(indio_dev); 1439 1440 return ret; 1441 case IIO_CHAN_INFO_SCALE: 1442 /* 1443 * According to the datasheet, the LSB size is: 1444 * * (2 × VREF) / 2^N, for differential chips 1445 * * VREF / 2^N, for pseudo-differential chips 1446 * where N is the ADC resolution (i.e realbits) 1447 * 1448 * The gain is stored as a fraction of 1000 and, as we need to 1449 * divide vref_mv by the gain, we invert the gain/1000 fraction. 1450 */ 1451 if (st->chip_info->has_hardware_gain) 1452 *val = mult_frac(st->vref_mv, MILLI, 1453 st->gain_milli[chan->scan_index]); 1454 else 1455 *val = st->vref_mv; 1456 *val2 = scan_type->realbits - chan->differential; 1457 1458 return IIO_VAL_FRACTIONAL_LOG2; 1459 case IIO_CHAN_INFO_OFFSET: 1460 /* 1461 * According to IIO ABI, offset is applied before scale, 1462 * so offset is: vcm_mv / scale 1463 */ 1464 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits) 1465 / st->vref_mv; 1466 1467 return IIO_VAL_INT; 1468 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1469 if (!iio_device_claim_direct(indio_dev)) 1470 return -EBUSY; 1471 1472 ret = ad7380_get_osr(st, val); 1473 1474 iio_device_release_direct(indio_dev); 1475 1476 if (ret) 1477 return ret; 1478 1479 return IIO_VAL_INT; 1480 case IIO_CHAN_INFO_SAMP_FREQ: 1481 *val = st->offload_trigger_hz; 1482 return IIO_VAL_INT; 1483 default: 1484 return -EINVAL; 1485 } 1486 } 1487 1488 static int ad7380_read_avail(struct iio_dev *indio_dev, 1489 struct iio_chan_spec const *chan, 1490 const int **vals, int *type, int *length, 1491 long mask) 1492 { 1493 struct ad7380_state *st = iio_priv(indio_dev); 1494 1495 switch (mask) { 1496 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1497 *vals = ad7380_oversampling_ratios; 1498 *length = ARRAY_SIZE(ad7380_oversampling_ratios); 1499 *type = IIO_VAL_INT; 1500 1501 return IIO_AVAIL_LIST; 1502 case IIO_CHAN_INFO_SAMP_FREQ: 1503 *vals = st->sample_freq_range; 1504 *type = IIO_VAL_INT; 1505 return IIO_AVAIL_RANGE; 1506 default: 1507 return -EINVAL; 1508 } 1509 } 1510 1511 /** 1512 * ad7380_osr_to_regval - convert ratio to OSR register value 1513 * @ratio: ratio to check 1514 * 1515 * Check if ratio is present in the list of available ratios and return the 1516 * corresponding value that needs to be written to the register to select that 1517 * ratio. 1518 * 1519 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match 1520 */ 1521 static int ad7380_osr_to_regval(int ratio) 1522 { 1523 int i; 1524 1525 for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) { 1526 if (ratio == ad7380_oversampling_ratios[i]) 1527 return i; 1528 } 1529 1530 return -EINVAL; 1531 } 1532 1533 static int ad7380_set_oversampling_ratio(struct ad7380_state *st, int val) 1534 { 1535 int ret, osr, boost; 1536 1537 osr = ad7380_osr_to_regval(val); 1538 if (osr < 0) 1539 return osr; 1540 1541 /* always enable resolution boost when oversampling is enabled */ 1542 boost = osr > 0 ? 1 : 0; 1543 1544 ret = regmap_update_bits(st->regmap, 1545 AD7380_REG_ADDR_CONFIG1, 1546 AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES, 1547 FIELD_PREP(AD7380_CONFIG1_OSR, osr) | 1548 FIELD_PREP(AD7380_CONFIG1_RES, boost)); 1549 1550 if (ret) 1551 return ret; 1552 1553 st->resolution_boost_enabled = boost; 1554 1555 /* 1556 * Perform a soft reset. This will flush the oversampling 1557 * block and FIFO but will maintain the content of the 1558 * configurable registers. 1559 */ 1560 ret = regmap_update_bits(st->regmap, 1561 AD7380_REG_ADDR_CONFIG2, 1562 AD7380_CONFIG2_RESET, 1563 FIELD_PREP(AD7380_CONFIG2_RESET, 1564 AD7380_CONFIG2_RESET_SOFT)); 1565 return ret; 1566 } 1567 static int ad7380_write_raw(struct iio_dev *indio_dev, 1568 struct iio_chan_spec const *chan, int val, 1569 int val2, long mask) 1570 { 1571 struct ad7380_state *st = iio_priv(indio_dev); 1572 int ret; 1573 1574 switch (mask) { 1575 case IIO_CHAN_INFO_SAMP_FREQ: 1576 if (val < 1) 1577 return -EINVAL; 1578 return ad7380_set_sample_freq(st, val); 1579 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1580 if (!iio_device_claim_direct(indio_dev)) 1581 return -EBUSY; 1582 1583 ret = ad7380_set_oversampling_ratio(st, val); 1584 1585 iio_device_release_direct(indio_dev); 1586 1587 return ret; 1588 default: 1589 return -EINVAL; 1590 } 1591 } 1592 1593 static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev, 1594 const struct iio_chan_spec *chan) 1595 { 1596 struct ad7380_state *st = iio_priv(indio_dev); 1597 1598 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST 1599 : AD7380_SCAN_TYPE_NORMAL; 1600 } 1601 1602 static int ad7380_read_event_config(struct iio_dev *indio_dev, 1603 const struct iio_chan_spec *chan, 1604 enum iio_event_type type, 1605 enum iio_event_direction dir) 1606 { 1607 struct ad7380_state *st = iio_priv(indio_dev); 1608 int tmp, ret; 1609 1610 if (!iio_device_claim_direct(indio_dev)) 1611 return -EBUSY; 1612 1613 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); 1614 1615 iio_device_release_direct(indio_dev); 1616 1617 if (ret) 1618 return ret; 1619 1620 return FIELD_GET(AD7380_CONFIG1_ALERTEN, tmp); 1621 } 1622 1623 static int ad7380_write_event_config(struct iio_dev *indio_dev, 1624 const struct iio_chan_spec *chan, 1625 enum iio_event_type type, 1626 enum iio_event_direction dir, 1627 bool state) 1628 { 1629 struct ad7380_state *st = iio_priv(indio_dev); 1630 int ret; 1631 1632 if (!iio_device_claim_direct(indio_dev)) 1633 return -EBUSY; 1634 1635 ret = regmap_update_bits(st->regmap, 1636 AD7380_REG_ADDR_CONFIG1, 1637 AD7380_CONFIG1_ALERTEN, 1638 FIELD_PREP(AD7380_CONFIG1_ALERTEN, state)); 1639 1640 iio_device_release_direct(indio_dev); 1641 1642 return ret; 1643 } 1644 1645 static int ad7380_get_alert_th(struct iio_dev *indio_dev, 1646 const struct iio_chan_spec *chan, 1647 enum iio_event_direction dir, 1648 int *val) 1649 { 1650 struct ad7380_state *st = iio_priv(indio_dev); 1651 const struct iio_scan_type *scan_type; 1652 int ret, tmp, shift; 1653 1654 scan_type = iio_get_current_scan_type(indio_dev, chan); 1655 if (IS_ERR(scan_type)) 1656 return PTR_ERR(scan_type); 1657 1658 /* 1659 * The register value is 12-bits and is compared to the most significant 1660 * bits of raw value, therefore a shift is required to convert this to 1661 * the same scale as the raw value. 1662 */ 1663 shift = scan_type->realbits - 12; 1664 1665 switch (dir) { 1666 case IIO_EV_DIR_RISING: 1667 ret = regmap_read(st->regmap, 1668 AD7380_REG_ADDR_ALERT_HIGH_TH, 1669 &tmp); 1670 if (ret) 1671 return ret; 1672 1673 *val = FIELD_GET(AD7380_ALERT_HIGH_TH, tmp) << shift; 1674 return IIO_VAL_INT; 1675 case IIO_EV_DIR_FALLING: 1676 ret = regmap_read(st->regmap, 1677 AD7380_REG_ADDR_ALERT_LOW_TH, 1678 &tmp); 1679 if (ret) 1680 return ret; 1681 1682 *val = FIELD_GET(AD7380_ALERT_LOW_TH, tmp) << shift; 1683 return IIO_VAL_INT; 1684 default: 1685 return -EINVAL; 1686 } 1687 } 1688 1689 static int ad7380_read_event_value(struct iio_dev *indio_dev, 1690 const struct iio_chan_spec *chan, 1691 enum iio_event_type type, 1692 enum iio_event_direction dir, 1693 enum iio_event_info info, 1694 int *val, int *val2) 1695 { 1696 int ret; 1697 1698 switch (info) { 1699 case IIO_EV_INFO_VALUE: 1700 if (!iio_device_claim_direct(indio_dev)) 1701 return -EBUSY; 1702 1703 ret = ad7380_get_alert_th(indio_dev, chan, dir, val); 1704 1705 iio_device_release_direct(indio_dev); 1706 return ret; 1707 default: 1708 return -EINVAL; 1709 } 1710 } 1711 1712 static int ad7380_set_alert_th(struct iio_dev *indio_dev, 1713 const struct iio_chan_spec *chan, 1714 enum iio_event_direction dir, 1715 int val) 1716 { 1717 struct ad7380_state *st = iio_priv(indio_dev); 1718 const struct iio_scan_type *scan_type; 1719 u16 th; 1720 1721 /* 1722 * According to the datasheet, 1723 * AD7380_REG_ADDR_ALERT_HIGH_TH[11:0] are the 12 MSB of the 1724 * 16-bits internal alert high register. LSB are set to 0xf. 1725 * AD7380_REG_ADDR_ALERT_LOW_TH[11:0] are the 12 MSB of the 1726 * 16 bits internal alert low register. LSB are set to 0x0. 1727 * 1728 * When alert is enabled the conversion from the adc is compared 1729 * immediately to the alert high/low thresholds, before any 1730 * oversampling. This means that the thresholds are the same for 1731 * normal mode and oversampling mode. 1732 */ 1733 1734 /* Extract the 12 MSB of val */ 1735 scan_type = iio_get_current_scan_type(indio_dev, chan); 1736 if (IS_ERR(scan_type)) 1737 return PTR_ERR(scan_type); 1738 1739 th = val >> (scan_type->realbits - 12); 1740 1741 switch (dir) { 1742 case IIO_EV_DIR_RISING: 1743 return regmap_write(st->regmap, 1744 AD7380_REG_ADDR_ALERT_HIGH_TH, 1745 th); 1746 case IIO_EV_DIR_FALLING: 1747 return regmap_write(st->regmap, 1748 AD7380_REG_ADDR_ALERT_LOW_TH, 1749 th); 1750 default: 1751 return -EINVAL; 1752 } 1753 } 1754 1755 static int ad7380_write_event_value(struct iio_dev *indio_dev, 1756 const struct iio_chan_spec *chan, 1757 enum iio_event_type type, 1758 enum iio_event_direction dir, 1759 enum iio_event_info info, 1760 int val, int val2) 1761 { 1762 int ret; 1763 1764 switch (info) { 1765 case IIO_EV_INFO_VALUE: 1766 if (!iio_device_claim_direct(indio_dev)) 1767 return -EBUSY; 1768 1769 ret = ad7380_set_alert_th(indio_dev, chan, dir, val); 1770 1771 iio_device_release_direct(indio_dev); 1772 return ret; 1773 default: 1774 return -EINVAL; 1775 } 1776 } 1777 1778 static const struct iio_info ad7380_info = { 1779 .read_raw = &ad7380_read_raw, 1780 .read_avail = &ad7380_read_avail, 1781 .write_raw = &ad7380_write_raw, 1782 .get_current_scan_type = &ad7380_get_current_scan_type, 1783 .debugfs_reg_access = &ad7380_debugfs_reg_access, 1784 .read_event_config = &ad7380_read_event_config, 1785 .write_event_config = &ad7380_write_event_config, 1786 .read_event_value = &ad7380_read_event_value, 1787 .write_event_value = &ad7380_write_event_value, 1788 }; 1789 1790 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) 1791 { 1792 int ret; 1793 1794 /* perform hard reset */ 1795 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 1796 AD7380_CONFIG2_RESET, 1797 FIELD_PREP(AD7380_CONFIG2_RESET, 1798 AD7380_CONFIG2_RESET_HARD)); 1799 if (ret < 0) 1800 return ret; 1801 1802 if (external_ref_en) { 1803 /* select external reference voltage */ 1804 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 1805 AD7380_CONFIG1_REFSEL); 1806 if (ret < 0) 1807 return ret; 1808 } 1809 1810 /* This is the default value after reset. */ 1811 st->ch = 0; 1812 st->seq = false; 1813 1814 /* SPI 1-wire mode */ 1815 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 1816 AD7380_CONFIG2_SDO, 1817 FIELD_PREP(AD7380_CONFIG2_SDO, 1818 AD7380_NUM_SDO_LINES)); 1819 } 1820 1821 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, 1822 struct ad7380_state *st) 1823 { 1824 struct spi_device *spi = st->spi; 1825 struct device *dev = &spi->dev; 1826 struct dma_chan *rx_dma; 1827 int sample_rate, ret; 1828 1829 indio_dev->setup_ops = &ad7380_offload_buffer_setup_ops; 1830 indio_dev->channels = st->chip_info->offload_channels; 1831 /* Just removing the timestamp channel. */ 1832 indio_dev->num_channels--; 1833 1834 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1835 SPI_OFFLOAD_TRIGGER_PERIODIC); 1836 if (IS_ERR(st->offload_trigger)) 1837 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1838 "failed to get offload trigger\n"); 1839 1840 sample_rate = st->chip_info->max_conversion_rate_hz * 1841 AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; 1842 1843 st->sample_freq_range[0] = 1; /* min */ 1844 st->sample_freq_range[1] = 1; /* step */ 1845 st->sample_freq_range[2] = sample_rate; /* max */ 1846 1847 /* 1848 * Starting with a quite low frequency, to allow oversampling x32, 1849 * user is then reponsible to adjust the frequency for the specific case. 1850 */ 1851 ret = ad7380_set_sample_freq(st, sample_rate / 32); 1852 if (ret) 1853 return ret; 1854 1855 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1856 if (IS_ERR(rx_dma)) 1857 return dev_err_probe(dev, PTR_ERR(rx_dma), 1858 "failed to get offload RX DMA\n"); 1859 1860 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, 1861 rx_dma, IIO_BUFFER_DIRECTION_IN); 1862 if (ret) 1863 return dev_err_probe(dev, ret, "cannot setup dma buffer\n"); 1864 1865 return 0; 1866 } 1867 1868 static int ad7380_probe(struct spi_device *spi) 1869 { 1870 struct device *dev = &spi->dev; 1871 struct iio_dev *indio_dev; 1872 struct ad7380_state *st; 1873 bool external_ref_en; 1874 int ret, i; 1875 1876 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1877 if (!indio_dev) 1878 return -ENOMEM; 1879 1880 st = iio_priv(indio_dev); 1881 st->spi = spi; 1882 st->chip_info = spi_get_device_match_data(spi); 1883 if (!st->chip_info) 1884 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 1885 1886 ret = devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, 1887 st->chip_info->supplies); 1888 1889 if (ret) 1890 return dev_err_probe(dev, ret, 1891 "Failed to enable power supplies\n"); 1892 fsleep(T_POWERUP_US); 1893 1894 if (st->chip_info->internal_ref_only) { 1895 /* 1896 * ADAQ chips use fixed internal reference but still 1897 * require a specific reference supply to power it. 1898 * "refin" is already enabled with other power supplies 1899 * in bulk_get_enable(). 1900 */ 1901 1902 st->vref_mv = st->chip_info->internal_ref_mv; 1903 1904 /* these chips don't have a register bit for this */ 1905 external_ref_en = false; 1906 } else if (st->chip_info->external_ref_only) { 1907 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 1908 if (ret < 0) 1909 return dev_err_probe(dev, ret, 1910 "Failed to get refin regulator\n"); 1911 1912 st->vref_mv = ret / 1000; 1913 1914 /* these chips don't have a register bit for this */ 1915 external_ref_en = false; 1916 } else { 1917 /* 1918 * If there is no REFIO supply, then it means that we are using 1919 * the internal reference, otherwise REFIO is reference voltage. 1920 */ 1921 ret = devm_regulator_get_enable_read_voltage(dev, "refio"); 1922 if (ret < 0 && ret != -ENODEV) 1923 return dev_err_probe(dev, ret, 1924 "Failed to get refio regulator\n"); 1925 1926 external_ref_en = ret != -ENODEV; 1927 st->vref_mv = external_ref_en ? ret / 1000 1928 : st->chip_info->internal_ref_mv; 1929 } 1930 1931 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) 1932 return dev_err_probe(dev, -EINVAL, 1933 "invalid number of VCM supplies\n"); 1934 1935 /* 1936 * pseudo-differential chips have common mode supplies for the negative 1937 * input pin. 1938 */ 1939 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) { 1940 const char *vcm = st->chip_info->vcm_supplies[i]; 1941 1942 ret = devm_regulator_get_enable_read_voltage(dev, vcm); 1943 if (ret < 0) 1944 return dev_err_probe(dev, ret, 1945 "Failed to get %s regulator\n", 1946 vcm); 1947 1948 st->vcm_mv[i] = ret / 1000; 1949 } 1950 1951 for (i = 0; i < MAX_NUM_CHANNELS; i++) 1952 st->gain_milli[i] = AD7380_DEFAULT_GAIN_MILLI; 1953 1954 if (st->chip_info->has_hardware_gain) { 1955 device_for_each_child_node_scoped(dev, node) { 1956 unsigned int channel, gain; 1957 int gain_idx; 1958 1959 ret = fwnode_property_read_u32(node, "reg", &channel); 1960 if (ret) 1961 return dev_err_probe(dev, ret, 1962 "Failed to read reg property\n"); 1963 1964 if (channel >= st->chip_info->num_channels - 1) 1965 return dev_err_probe(dev, -EINVAL, 1966 "Invalid channel number %i\n", 1967 channel); 1968 1969 ret = fwnode_property_read_u32(node, "adi,gain-milli", 1970 &gain); 1971 if (ret && ret != -EINVAL) 1972 return dev_err_probe(dev, ret, 1973 "Failed to read gain for channel %i\n", 1974 channel); 1975 if (ret != -EINVAL) { 1976 /* 1977 * Match gain value from dt to one of supported 1978 * gains 1979 */ 1980 gain_idx = find_closest(gain, ad7380_gains, 1981 ARRAY_SIZE(ad7380_gains)); 1982 st->gain_milli[channel] = ad7380_gains[gain_idx]; 1983 } 1984 } 1985 } 1986 1987 st->regmap = devm_regmap_init(dev, NULL, st, &ad7380_regmap_config); 1988 if (IS_ERR(st->regmap)) 1989 return dev_err_probe(dev, PTR_ERR(st->regmap), 1990 "failed to allocate register map\n"); 1991 1992 /* 1993 * Setting up xfer structures for both normal and sequence mode. These 1994 * struct are used for both direct read and triggered buffer. Additional 1995 * fields will be set up in ad7380_update_xfers() based on the current 1996 * state of the driver at the time of the read. 1997 */ 1998 1999 /* 2000 * In normal mode a read is composed of two steps: 2001 * - first, toggle CS (no data xfer) to trigger a conversion 2002 * - then, read data 2003 */ 2004 st->normal_xfer[0].cs_change = 1; 2005 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2006 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2007 st->normal_xfer[1].rx_buf = st->scan_data; 2008 2009 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, 2010 ARRAY_SIZE(st->normal_xfer)); 2011 /* 2012 * In sequencer mode a read is composed of four steps: 2013 * - CS toggle (no data xfer) to get the right point in the sequence 2014 * - CS toggle (no data xfer) to trigger a conversion of AinX0 and 2015 * acquisition of AinX1 2016 * - 2 data reads, to read AinX0 and AinX1 2017 */ 2018 st->seq_xfer[0].cs_change = 1; 2019 st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2020 st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2021 st->seq_xfer[1].cs_change = 1; 2022 st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2023 st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2024 2025 st->seq_xfer[2].rx_buf = st->scan_data; 2026 st->seq_xfer[2].cs_change = 1; 2027 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2028 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2029 2030 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, 2031 ARRAY_SIZE(st->seq_xfer)); 2032 2033 indio_dev->channels = st->chip_info->channels; 2034 indio_dev->num_channels = st->chip_info->num_channels; 2035 indio_dev->name = st->chip_info->name; 2036 indio_dev->info = &ad7380_info; 2037 indio_dev->modes = INDIO_DIRECT_MODE; 2038 indio_dev->available_scan_masks = st->chip_info->available_scan_masks; 2039 2040 st->offload = devm_spi_offload_get(dev, spi, &ad7380_offload_config); 2041 ret = PTR_ERR_OR_ZERO(st->offload); 2042 if (ret && ret != -ENODEV) 2043 return dev_err_probe(dev, ret, "failed to get offload\n"); 2044 2045 /* If no SPI offload, fall back to low speed usage. */ 2046 if (ret == -ENODEV) { 2047 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 2048 iio_pollfunc_store_time, 2049 ad7380_trigger_handler, 2050 &ad7380_buffer_setup_ops); 2051 if (ret) 2052 return ret; 2053 } else { 2054 ret = ad7380_probe_spi_offload(indio_dev, st); 2055 if (ret) 2056 return ret; 2057 } 2058 2059 ret = ad7380_init(st, external_ref_en); 2060 if (ret) 2061 return ret; 2062 2063 return devm_iio_device_register(dev, indio_dev); 2064 } 2065 2066 static const struct of_device_id ad7380_of_match_table[] = { 2067 { .compatible = "adi,ad7380", .data = &ad7380_chip_info }, 2068 { .compatible = "adi,ad7381", .data = &ad7381_chip_info }, 2069 { .compatible = "adi,ad7383", .data = &ad7383_chip_info }, 2070 { .compatible = "adi,ad7384", .data = &ad7384_chip_info }, 2071 { .compatible = "adi,ad7386", .data = &ad7386_chip_info }, 2072 { .compatible = "adi,ad7387", .data = &ad7387_chip_info }, 2073 { .compatible = "adi,ad7388", .data = &ad7388_chip_info }, 2074 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info }, 2075 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info }, 2076 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info }, 2077 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info }, 2078 { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info }, 2079 { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info }, 2080 { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info }, 2081 { .compatible = "adi,ad7389-4", .data = &ad7389_4_chip_info }, 2082 { .compatible = "adi,adaq4370-4", .data = &adaq4370_4_chip_info }, 2083 { .compatible = "adi,adaq4380-4", .data = &adaq4380_4_chip_info }, 2084 { .compatible = "adi,adaq4381-4", .data = &adaq4381_4_chip_info }, 2085 { } 2086 }; 2087 2088 static const struct spi_device_id ad7380_id_table[] = { 2089 { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, 2090 { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, 2091 { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, 2092 { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, 2093 { "ad7386", (kernel_ulong_t)&ad7386_chip_info }, 2094 { "ad7387", (kernel_ulong_t)&ad7387_chip_info }, 2095 { "ad7388", (kernel_ulong_t)&ad7388_chip_info }, 2096 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, 2097 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, 2098 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, 2099 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, 2100 { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info }, 2101 { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info }, 2102 { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info }, 2103 { "ad7389-4", (kernel_ulong_t)&ad7389_4_chip_info }, 2104 { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info }, 2105 { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info }, 2106 { "adaq4381-4", (kernel_ulong_t)&adaq4381_4_chip_info }, 2107 { } 2108 }; 2109 MODULE_DEVICE_TABLE(spi, ad7380_id_table); 2110 2111 static struct spi_driver ad7380_driver = { 2112 .driver = { 2113 .name = "ad7380", 2114 .of_match_table = ad7380_of_match_table, 2115 }, 2116 .probe = ad7380_probe, 2117 .id_table = ad7380_id_table, 2118 }; 2119 module_spi_driver(ad7380_driver); 2120 2121 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 2122 MODULE_DESCRIPTION("Analog Devices AD738x ADC driver"); 2123 MODULE_LICENSE("GPL"); 2124 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 2125