1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD738x Simultaneous Sampling SAR ADCs 4 * 5 * Copyright 2017 Analog Devices Inc. 6 * Copyright 2024 BayLibre, SAS 7 * 8 * Datasheets of supported parts: 9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf 10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf 11 * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-7388.pdf 12 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf 13 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf 14 * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf 15 * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387-4-7388-4.pdf 16 * ad7389-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7389-4.pdf 17 * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4370-4.pdf 18 * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4380-4.pdf 19 * adaq4381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4381-4.pdf 20 * 21 * HDL ad738x_fmc: https://analogdevicesinc.github.io/hdl/projects/ad738x_fmc/index.html 22 * 23 */ 24 25 #include <linux/align.h> 26 #include <linux/bitfield.h> 27 #include <linux/bitops.h> 28 #include <linux/cleanup.h> 29 #include <linux/device.h> 30 #include <linux/err.h> 31 #include <linux/kernel.h> 32 #include <linux/math.h> 33 #include <linux/module.h> 34 #include <linux/regmap.h> 35 #include <linux/regulator/consumer.h> 36 #include <linux/slab.h> 37 #include <linux/spi/offload/consumer.h> 38 #include <linux/spi/spi.h> 39 #include <linux/units.h> 40 #include <linux/util_macros.h> 41 42 #include <linux/iio/buffer.h> 43 #include <linux/iio/buffer-dmaengine.h> 44 #include <linux/iio/events.h> 45 #include <linux/iio/iio.h> 46 #include <linux/iio/trigger_consumer.h> 47 #include <linux/iio/triggered_buffer.h> 48 49 #define MAX_NUM_CHANNELS 8 50 /* 2.5V internal reference voltage */ 51 #define AD7380_INTERNAL_REF_MV 2500 52 /* 3.3V internal reference voltage for ADAQ */ 53 #define ADAQ4380_INTERNAL_REF_MV 3300 54 55 /* reading and writing registers is more reliable at lower than max speed */ 56 #define AD7380_REG_WR_SPEED_HZ 10000000 57 58 #define AD7380_REG_WR BIT(15) 59 #define AD7380_REG_REGADDR GENMASK(14, 12) 60 #define AD7380_REG_DATA GENMASK(11, 0) 61 62 #define AD7380_REG_ADDR_NOP 0x0 63 #define AD7380_REG_ADDR_CONFIG1 0x1 64 #define AD7380_REG_ADDR_CONFIG2 0x2 65 #define AD7380_REG_ADDR_ALERT 0x3 66 #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 67 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 68 69 #define AD7380_CONFIG1_CH BIT(11) 70 #define AD7380_CONFIG1_SEQ BIT(10) 71 #define AD7380_CONFIG1_OS_MODE BIT(9) 72 #define AD7380_CONFIG1_OSR GENMASK(8, 6) 73 #define AD7380_CONFIG1_CRC_W BIT(5) 74 #define AD7380_CONFIG1_CRC_R BIT(4) 75 #define AD7380_CONFIG1_ALERTEN BIT(3) 76 #define AD7380_CONFIG1_RES BIT(2) 77 #define AD7380_CONFIG1_REFSEL BIT(1) 78 #define AD7380_CONFIG1_PMODE BIT(0) 79 80 #define AD7380_CONFIG2_SDO2 GENMASK(9, 8) 81 #define AD7380_CONFIG2_SDO BIT(8) 82 #define AD7380_CONFIG2_RESET GENMASK(7, 0) 83 84 #define AD7380_CONFIG2_RESET_SOFT 0x3C 85 #define AD7380_CONFIG2_RESET_HARD 0xFF 86 87 #define AD7380_ALERT_LOW_TH GENMASK(11, 0) 88 #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) 89 90 #define T_CONVERT_NS 190 /* conversion time */ 91 #define T_CONVERT_0_NS 10 /* 1st conversion start time (oversampling) */ 92 #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ 93 #define T_POWERUP_US 5000 /* Power up */ 94 95 /* 96 * AD738x support several SDO lines to increase throughput, but driver currently 97 * supports only 1 SDO line (standard SPI transaction) 98 */ 99 #define AD7380_NUM_SDO_LINES 1 100 #define AD7380_DEFAULT_GAIN_MILLI 1000 101 102 /* 103 * Using SPI offload, storagebits is always 32, so can't be used to compute struct 104 * spi_transfer.len. Using realbits instead. 105 */ 106 #define AD7380_SPI_BYTES(scan_type) ((scan_type)->realbits > 16 ? 4 : 2) 107 108 struct ad7380_timing_specs { 109 const unsigned int t_csh_ns; /* CS minimum high time */ 110 }; 111 112 struct ad7380_chip_info { 113 const char *name; 114 const struct iio_chan_spec *channels; 115 const struct iio_chan_spec *offload_channels; 116 unsigned int num_channels; 117 unsigned int num_simult_channels; 118 bool has_hardware_gain; 119 bool has_mux; 120 const char * const *supplies; 121 unsigned int num_supplies; 122 bool external_ref_only; 123 bool internal_ref_only; 124 unsigned int internal_ref_mv; 125 const char * const *vcm_supplies; 126 unsigned int num_vcm_supplies; 127 const unsigned long *available_scan_masks; 128 const struct ad7380_timing_specs *timing_specs; 129 u32 max_conversion_rate_hz; 130 }; 131 132 static const struct iio_event_spec ad7380_events[] = { 133 { 134 .type = IIO_EV_TYPE_THRESH, 135 .dir = IIO_EV_DIR_RISING, 136 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE), 137 }, 138 { 139 .type = IIO_EV_TYPE_THRESH, 140 .dir = IIO_EV_DIR_FALLING, 141 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE), 142 }, 143 { 144 .type = IIO_EV_TYPE_THRESH, 145 .dir = IIO_EV_DIR_EITHER, 146 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 147 }, 148 }; 149 150 enum { 151 AD7380_SCAN_TYPE_NORMAL, 152 AD7380_SCAN_TYPE_RESOLUTION_BOOST, 153 }; 154 155 /* Extended scan types for 12-bit unsigned chips. */ 156 static const struct iio_scan_type ad7380_scan_type_12_u[] = { 157 [AD7380_SCAN_TYPE_NORMAL] = { 158 .sign = 'u', 159 .realbits = 12, 160 .storagebits = 16, 161 .endianness = IIO_CPU, 162 }, 163 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 164 .sign = 'u', 165 .realbits = 14, 166 .storagebits = 16, 167 .endianness = IIO_CPU, 168 }, 169 }; 170 171 /* Extended scan types for 14-bit signed chips. */ 172 static const struct iio_scan_type ad7380_scan_type_14_s[] = { 173 [AD7380_SCAN_TYPE_NORMAL] = { 174 .sign = 's', 175 .realbits = 14, 176 .storagebits = 16, 177 .endianness = IIO_CPU, 178 }, 179 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 180 .sign = 's', 181 .realbits = 16, 182 .storagebits = 16, 183 .endianness = IIO_CPU, 184 }, 185 }; 186 187 /* Extended scan types for 14-bit unsigned chips. */ 188 static const struct iio_scan_type ad7380_scan_type_14_u[] = { 189 [AD7380_SCAN_TYPE_NORMAL] = { 190 .sign = 'u', 191 .realbits = 14, 192 .storagebits = 16, 193 .endianness = IIO_CPU, 194 }, 195 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 196 .sign = 'u', 197 .realbits = 16, 198 .storagebits = 16, 199 .endianness = IIO_CPU, 200 }, 201 }; 202 203 /* Extended scan types for 16-bit signed_chips. */ 204 static const struct iio_scan_type ad7380_scan_type_16_s[] = { 205 [AD7380_SCAN_TYPE_NORMAL] = { 206 .sign = 's', 207 .realbits = 16, 208 .storagebits = 16, 209 .endianness = IIO_CPU, 210 }, 211 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 212 .sign = 's', 213 .realbits = 18, 214 .storagebits = 32, 215 .endianness = IIO_CPU, 216 }, 217 }; 218 219 /* Extended scan types for 16-bit unsigned chips. */ 220 static const struct iio_scan_type ad7380_scan_type_16_u[] = { 221 [AD7380_SCAN_TYPE_NORMAL] = { 222 .sign = 'u', 223 .realbits = 16, 224 .storagebits = 16, 225 .endianness = IIO_CPU, 226 }, 227 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 228 .sign = 'u', 229 .realbits = 18, 230 .storagebits = 32, 231 .endianness = IIO_CPU, 232 }, 233 }; 234 235 /* 236 * Defining here scan types for offload mode, since with current available HDL 237 * only a value of 32 for storagebits is supported. 238 */ 239 240 /* Extended scan types for 12-bit unsigned chips, offload support. */ 241 static const struct iio_scan_type ad7380_scan_type_12_u_offload[] = { 242 [AD7380_SCAN_TYPE_NORMAL] = { 243 .sign = 'u', 244 .realbits = 12, 245 .storagebits = 32, 246 .endianness = IIO_CPU, 247 }, 248 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 249 .sign = 'u', 250 .realbits = 14, 251 .storagebits = 32, 252 .endianness = IIO_CPU, 253 }, 254 }; 255 256 /* Extended scan types for 14-bit signed chips, offload support. */ 257 static const struct iio_scan_type ad7380_scan_type_14_s_offload[] = { 258 [AD7380_SCAN_TYPE_NORMAL] = { 259 .sign = 's', 260 .realbits = 14, 261 .storagebits = 32, 262 .endianness = IIO_CPU, 263 }, 264 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 265 .sign = 's', 266 .realbits = 16, 267 .storagebits = 32, 268 .endianness = IIO_CPU, 269 }, 270 }; 271 272 /* Extended scan types for 14-bit unsigned chips, offload support. */ 273 static const struct iio_scan_type ad7380_scan_type_14_u_offload[] = { 274 [AD7380_SCAN_TYPE_NORMAL] = { 275 .sign = 'u', 276 .realbits = 14, 277 .storagebits = 32, 278 .endianness = IIO_CPU, 279 }, 280 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 281 .sign = 'u', 282 .realbits = 16, 283 .storagebits = 32, 284 .endianness = IIO_CPU, 285 }, 286 }; 287 288 /* Extended scan types for 16-bit signed_chips, offload support. */ 289 static const struct iio_scan_type ad7380_scan_type_16_s_offload[] = { 290 [AD7380_SCAN_TYPE_NORMAL] = { 291 .sign = 's', 292 .realbits = 16, 293 .storagebits = 32, 294 .endianness = IIO_CPU, 295 }, 296 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 297 .sign = 's', 298 .realbits = 18, 299 .storagebits = 32, 300 .endianness = IIO_CPU, 301 }, 302 }; 303 304 /* Extended scan types for 16-bit unsigned chips, offload support. */ 305 static const struct iio_scan_type ad7380_scan_type_16_u_offload[] = { 306 [AD7380_SCAN_TYPE_NORMAL] = { 307 .sign = 'u', 308 .realbits = 16, 309 .storagebits = 32, 310 .endianness = IIO_CPU, 311 }, 312 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 313 .sign = 'u', 314 .realbits = 18, 315 .storagebits = 32, 316 .endianness = IIO_CPU, 317 }, 318 }; 319 320 #define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \ 321 .type = IIO_VOLTAGE, \ 322 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 323 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 324 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 325 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ 326 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 327 .info_mask_shared_by_type_available = \ 328 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 329 .indexed = 1, \ 330 .differential = (diff), \ 331 .channel = (diff) ? (2 * (index)) : (index), \ 332 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 333 .scan_index = (index), \ 334 .has_ext_scan_type = 1, \ 335 .ext_scan_type = ad7380_scan_type_##bits##_##sign, \ 336 .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ 337 .event_spec = ad7380_events, \ 338 .num_event_specs = ARRAY_SIZE(ad7380_events), \ 339 } 340 341 #define _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, gain) { \ 342 .type = IIO_VOLTAGE, \ 343 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 344 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 345 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 346 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ 347 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ 348 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 349 .info_mask_shared_by_type_available = \ 350 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ 351 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 352 .indexed = 1, \ 353 .differential = (diff), \ 354 .channel = (diff) ? (2 * (index)) : (index), \ 355 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 356 .scan_index = (index), \ 357 .has_ext_scan_type = 1, \ 358 .ext_scan_type = ad7380_scan_type_##bits##_##sign##_offload, \ 359 .num_ext_scan_type = \ 360 ARRAY_SIZE(ad7380_scan_type_##bits##_##sign##_offload), \ 361 .event_spec = ad7380_events, \ 362 .num_event_specs = ARRAY_SIZE(ad7380_events), \ 363 } 364 365 /* 366 * Notes on the offload channels: 367 * - There is no soft timestamp since everything is done in hardware. 368 * - There is a sampling frequency attribute added. This controls the SPI 369 * offload trigger. 370 * - The storagebits value depends on the SPI offload provider. Currently there 371 * is only one supported provider, namely the ADI PULSAR ADC HDL project, 372 * which always uses 32-bit words for data values, even for <= 16-bit ADCs. 373 * So the value is just hardcoded to 32 for now. 374 */ 375 376 #define AD7380_CHANNEL(index, bits, diff, sign) \ 377 _AD7380_CHANNEL(index, bits, diff, sign, false) 378 379 #define ADAQ4380_CHANNEL(index, bits, diff, sign) \ 380 _AD7380_CHANNEL(index, bits, diff, sign, true) 381 382 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ 383 static const struct iio_chan_spec name[] = { \ 384 AD7380_CHANNEL(0, bits, diff, sign), \ 385 AD7380_CHANNEL(1, bits, diff, sign), \ 386 IIO_CHAN_SOFT_TIMESTAMP(2), \ 387 } 388 389 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \ 390 static const struct iio_chan_spec name[] = { \ 391 AD7380_CHANNEL(0, bits, diff, sign), \ 392 AD7380_CHANNEL(1, bits, diff, sign), \ 393 AD7380_CHANNEL(2, bits, diff, sign), \ 394 AD7380_CHANNEL(3, bits, diff, sign), \ 395 IIO_CHAN_SOFT_TIMESTAMP(4), \ 396 } 397 398 #define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \ 399 static const struct iio_chan_spec name[] = { \ 400 ADAQ4380_CHANNEL(0, bits, diff, sign), \ 401 ADAQ4380_CHANNEL(1, bits, diff, sign), \ 402 ADAQ4380_CHANNEL(2, bits, diff, sign), \ 403 ADAQ4380_CHANNEL(3, bits, diff, sign), \ 404 IIO_CHAN_SOFT_TIMESTAMP(4), \ 405 } 406 407 #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ 408 static const struct iio_chan_spec name[] = { \ 409 AD7380_CHANNEL(0, bits, diff, sign), \ 410 AD7380_CHANNEL(1, bits, diff, sign), \ 411 AD7380_CHANNEL(2, bits, diff, sign), \ 412 AD7380_CHANNEL(3, bits, diff, sign), \ 413 AD7380_CHANNEL(4, bits, diff, sign), \ 414 AD7380_CHANNEL(5, bits, diff, sign), \ 415 AD7380_CHANNEL(6, bits, diff, sign), \ 416 AD7380_CHANNEL(7, bits, diff, sign), \ 417 IIO_CHAN_SOFT_TIMESTAMP(8), \ 418 } 419 420 #define AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ 421 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, false) 422 423 #define ADAQ4380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ 424 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, true) 425 426 #define DEFINE_AD7380_2_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 427 static const struct iio_chan_spec name[] = { \ 428 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 429 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 430 } 431 432 #define DEFINE_AD7380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 433 static const struct iio_chan_spec name[] = { \ 434 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 435 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 436 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 437 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 438 } 439 440 #define DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 441 static const struct iio_chan_spec name[] = { \ 442 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 443 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 444 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 445 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 446 } 447 448 #define DEFINE_AD7380_8_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 449 static const struct iio_chan_spec name[] = { \ 450 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 451 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 452 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 453 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 454 AD7380_OFFLOAD_CHANNEL(4, bits, diff, sign), \ 455 AD7380_OFFLOAD_CHANNEL(5, bits, diff, sign), \ 456 AD7380_OFFLOAD_CHANNEL(6, bits, diff, sign), \ 457 AD7380_OFFLOAD_CHANNEL(7, bits, diff, sign), \ 458 } 459 460 /* fully differential */ 461 DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); 462 DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); 463 DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); 464 DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); 465 DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s); 466 DEFINE_ADAQ4380_4_CHANNEL(adaq4381_4_channels, 14, 1, s); 467 /* pseudo differential */ 468 DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); 469 DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); 470 DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s); 471 DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s); 472 473 /* Single ended */ 474 DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u); 475 DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u); 476 DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u); 477 DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u); 478 DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u); 479 DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u); 480 481 /* offload channels */ 482 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7380_offload_channels, 16, 1, s); 483 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7381_offload_channels, 14, 1, s); 484 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7380_4_offload_channels, 16, 1, s); 485 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7381_4_offload_channels, 14, 1, s); 486 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4380_4_offload_channels, 16, 1, s); 487 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4381_4_offload_channels, 14, 1, s); 488 489 /* pseudo differential */ 490 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7383_offload_channels, 16, 0, s); 491 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7384_offload_channels, 14, 0, s); 492 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7383_4_offload_channels, 16, 0, s); 493 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7384_4_offload_channels, 14, 0, s); 494 495 /* Single ended */ 496 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7386_offload_channels, 16, 0, u); 497 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7387_offload_channels, 14, 0, u); 498 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7388_offload_channels, 12, 0, u); 499 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7386_4_offload_channels, 16, 0, u); 500 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7387_4_offload_channels, 14, 0, u); 501 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7388_4_offload_channels, 12, 0, u); 502 503 static const char * const ad7380_supplies[] = { 504 "vcc", "vlogic", 505 }; 506 507 static const char * const adaq4380_supplies[] = { 508 "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin", 509 }; 510 511 static const char * const ad7380_2_channel_vcm_supplies[] = { 512 "aina", "ainb", 513 }; 514 515 static const char * const ad7380_4_channel_vcm_supplies[] = { 516 "aina", "ainb", "ainc", "aind", 517 }; 518 519 /* Since this is simultaneous sampling, we don't allow individual channels. */ 520 static const unsigned long ad7380_2_channel_scan_masks[] = { 521 GENMASK(1, 0), 522 0 523 }; 524 525 static const unsigned long ad7380_4_channel_scan_masks[] = { 526 GENMASK(3, 0), 527 0 528 }; 529 530 /* 531 * Single ended parts have a 2:1 multiplexer in front of each ADC. 532 * 533 * From an IIO point of view, all inputs are exported, i.e ad7386/7/8 534 * export 4 channels and ad7386-4/7-4/8-4 export 8 channels. 535 * 536 * Inputs AinX0 of multiplexers correspond to the first half of IIO channels 537 * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or 538 * 4-7). Example for AD7386/7/8 (2 channels parts): 539 * 540 * IIO | AD7386/7/8 541 * | +---------------------------- 542 * | | _____ ______ 543 * | | | | | | 544 * voltage0 | AinA0 --|--->| | | | 545 * | | | mux |----->| ADCA |--- 546 * voltage2 | AinA1 --|--->| | | | 547 * | | |_____| |_____ | 548 * | | _____ ______ 549 * | | | | | | 550 * voltage1 | AinB0 --|--->| | | | 551 * | | | mux |----->| ADCB |--- 552 * voltage3 | AinB1 --|--->| | | | 553 * | | |_____| |______| 554 * | | 555 * | +---------------------------- 556 * 557 * Since this is simultaneous sampling for AinX0 OR AinX1 we have two separate 558 * scan masks. 559 * When sequencer mode is enabled, chip automatically cycles through 560 * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all 561 * channels, at the cost of an extra read, thus dividing the maximum rate by 562 * two. 563 */ 564 enum { 565 AD7380_SCAN_MASK_CH_0, 566 AD7380_SCAN_MASK_CH_1, 567 AD7380_SCAN_MASK_SEQ, 568 }; 569 570 static const unsigned long ad7380_2x2_channel_scan_masks[] = { 571 [AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0), 572 [AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2), 573 [AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0), 574 0 575 }; 576 577 static const unsigned long ad7380_2x4_channel_scan_masks[] = { 578 [AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0), 579 [AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4), 580 [AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0), 581 0 582 }; 583 584 static const struct ad7380_timing_specs ad7380_timing = { 585 .t_csh_ns = 10, 586 }; 587 588 static const struct ad7380_timing_specs ad7380_4_timing = { 589 .t_csh_ns = 20, 590 }; 591 592 /* 593 * Available oversampling ratios. The indices correspond with the bit value 594 * expected by the chip. The available ratios depend on the averaging mode, 595 * only normal averaging is supported for now. 596 */ 597 static const int ad7380_oversampling_ratios[] = { 598 1, 2, 4, 8, 16, 32, 599 }; 600 601 /* Gains stored as fractions of 1000 so they can be expressed by integers. */ 602 static const int ad7380_gains[] = { 603 300, 600, 1000, 1600, 604 }; 605 606 static const struct ad7380_chip_info ad7380_chip_info = { 607 .name = "ad7380", 608 .channels = ad7380_channels, 609 .offload_channels = ad7380_offload_channels, 610 .num_channels = ARRAY_SIZE(ad7380_channels), 611 .num_simult_channels = 2, 612 .supplies = ad7380_supplies, 613 .num_supplies = ARRAY_SIZE(ad7380_supplies), 614 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 615 .available_scan_masks = ad7380_2_channel_scan_masks, 616 .timing_specs = &ad7380_timing, 617 .max_conversion_rate_hz = 4 * MEGA, 618 }; 619 620 static const struct ad7380_chip_info ad7381_chip_info = { 621 .name = "ad7381", 622 .channels = ad7381_channels, 623 .offload_channels = ad7381_offload_channels, 624 .num_channels = ARRAY_SIZE(ad7381_channels), 625 .num_simult_channels = 2, 626 .supplies = ad7380_supplies, 627 .num_supplies = ARRAY_SIZE(ad7380_supplies), 628 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 629 .available_scan_masks = ad7380_2_channel_scan_masks, 630 .timing_specs = &ad7380_timing, 631 .max_conversion_rate_hz = 4 * MEGA, 632 }; 633 634 static const struct ad7380_chip_info ad7383_chip_info = { 635 .name = "ad7383", 636 .channels = ad7383_channels, 637 .offload_channels = ad7383_offload_channels, 638 .num_channels = ARRAY_SIZE(ad7383_channels), 639 .num_simult_channels = 2, 640 .supplies = ad7380_supplies, 641 .num_supplies = ARRAY_SIZE(ad7380_supplies), 642 .vcm_supplies = ad7380_2_channel_vcm_supplies, 643 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 644 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 645 .available_scan_masks = ad7380_2_channel_scan_masks, 646 .timing_specs = &ad7380_timing, 647 .max_conversion_rate_hz = 4 * MEGA, 648 }; 649 650 static const struct ad7380_chip_info ad7384_chip_info = { 651 .name = "ad7384", 652 .channels = ad7384_channels, 653 .offload_channels = ad7384_offload_channels, 654 .num_channels = ARRAY_SIZE(ad7384_channels), 655 .num_simult_channels = 2, 656 .supplies = ad7380_supplies, 657 .num_supplies = ARRAY_SIZE(ad7380_supplies), 658 .vcm_supplies = ad7380_2_channel_vcm_supplies, 659 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 660 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 661 .available_scan_masks = ad7380_2_channel_scan_masks, 662 .timing_specs = &ad7380_timing, 663 .max_conversion_rate_hz = 4 * MEGA, 664 }; 665 666 static const struct ad7380_chip_info ad7386_chip_info = { 667 .name = "ad7386", 668 .channels = ad7386_channels, 669 .offload_channels = ad7386_offload_channels, 670 .num_channels = ARRAY_SIZE(ad7386_channels), 671 .num_simult_channels = 2, 672 .supplies = ad7380_supplies, 673 .num_supplies = ARRAY_SIZE(ad7380_supplies), 674 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 675 .has_mux = true, 676 .available_scan_masks = ad7380_2x2_channel_scan_masks, 677 .timing_specs = &ad7380_timing, 678 .max_conversion_rate_hz = 4 * MEGA, 679 }; 680 681 static const struct ad7380_chip_info ad7387_chip_info = { 682 .name = "ad7387", 683 .channels = ad7387_channels, 684 .offload_channels = ad7387_offload_channels, 685 .num_channels = ARRAY_SIZE(ad7387_channels), 686 .num_simult_channels = 2, 687 .supplies = ad7380_supplies, 688 .num_supplies = ARRAY_SIZE(ad7380_supplies), 689 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 690 .has_mux = true, 691 .available_scan_masks = ad7380_2x2_channel_scan_masks, 692 .timing_specs = &ad7380_timing, 693 .max_conversion_rate_hz = 4 * MEGA, 694 }; 695 696 static const struct ad7380_chip_info ad7388_chip_info = { 697 .name = "ad7388", 698 .channels = ad7388_channels, 699 .offload_channels = ad7388_offload_channels, 700 .num_channels = ARRAY_SIZE(ad7388_channels), 701 .num_simult_channels = 2, 702 .supplies = ad7380_supplies, 703 .num_supplies = ARRAY_SIZE(ad7380_supplies), 704 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 705 .has_mux = true, 706 .available_scan_masks = ad7380_2x2_channel_scan_masks, 707 .timing_specs = &ad7380_timing, 708 .max_conversion_rate_hz = 4 * MEGA, 709 }; 710 711 static const struct ad7380_chip_info ad7380_4_chip_info = { 712 .name = "ad7380-4", 713 .channels = ad7380_4_channels, 714 .offload_channels = ad7380_4_offload_channels, 715 .num_channels = ARRAY_SIZE(ad7380_4_channels), 716 .num_simult_channels = 4, 717 .supplies = ad7380_supplies, 718 .num_supplies = ARRAY_SIZE(ad7380_supplies), 719 .external_ref_only = true, 720 .available_scan_masks = ad7380_4_channel_scan_masks, 721 .timing_specs = &ad7380_4_timing, 722 .max_conversion_rate_hz = 4 * MEGA, 723 }; 724 725 static const struct ad7380_chip_info ad7381_4_chip_info = { 726 .name = "ad7381-4", 727 .channels = ad7381_4_channels, 728 .offload_channels = ad7381_4_offload_channels, 729 .num_channels = ARRAY_SIZE(ad7381_4_channels), 730 .num_simult_channels = 4, 731 .supplies = ad7380_supplies, 732 .num_supplies = ARRAY_SIZE(ad7380_supplies), 733 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 734 .available_scan_masks = ad7380_4_channel_scan_masks, 735 .timing_specs = &ad7380_4_timing, 736 .max_conversion_rate_hz = 4 * MEGA, 737 }; 738 739 static const struct ad7380_chip_info ad7383_4_chip_info = { 740 .name = "ad7383-4", 741 .channels = ad7383_4_channels, 742 .offload_channels = ad7383_4_offload_channels, 743 .num_channels = ARRAY_SIZE(ad7383_4_channels), 744 .num_simult_channels = 4, 745 .supplies = ad7380_supplies, 746 .num_supplies = ARRAY_SIZE(ad7380_supplies), 747 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 748 .vcm_supplies = ad7380_4_channel_vcm_supplies, 749 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 750 .available_scan_masks = ad7380_4_channel_scan_masks, 751 .timing_specs = &ad7380_4_timing, 752 .max_conversion_rate_hz = 4 * MEGA, 753 }; 754 755 static const struct ad7380_chip_info ad7384_4_chip_info = { 756 .name = "ad7384-4", 757 .channels = ad7384_4_channels, 758 .offload_channels = ad7384_4_offload_channels, 759 .num_channels = ARRAY_SIZE(ad7384_4_channels), 760 .num_simult_channels = 4, 761 .supplies = ad7380_supplies, 762 .num_supplies = ARRAY_SIZE(ad7380_supplies), 763 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 764 .vcm_supplies = ad7380_4_channel_vcm_supplies, 765 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 766 .available_scan_masks = ad7380_4_channel_scan_masks, 767 .timing_specs = &ad7380_4_timing, 768 .max_conversion_rate_hz = 4 * MEGA, 769 }; 770 771 static const struct ad7380_chip_info ad7386_4_chip_info = { 772 .name = "ad7386-4", 773 .channels = ad7386_4_channels, 774 .offload_channels = ad7386_4_offload_channels, 775 .num_channels = ARRAY_SIZE(ad7386_4_channels), 776 .num_simult_channels = 4, 777 .supplies = ad7380_supplies, 778 .num_supplies = ARRAY_SIZE(ad7380_supplies), 779 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 780 .has_mux = true, 781 .available_scan_masks = ad7380_2x4_channel_scan_masks, 782 .timing_specs = &ad7380_4_timing, 783 .max_conversion_rate_hz = 4 * MEGA, 784 }; 785 786 static const struct ad7380_chip_info ad7387_4_chip_info = { 787 .name = "ad7387-4", 788 .channels = ad7387_4_channels, 789 .offload_channels = ad7387_4_offload_channels, 790 .num_channels = ARRAY_SIZE(ad7387_4_channels), 791 .num_simult_channels = 4, 792 .supplies = ad7380_supplies, 793 .num_supplies = ARRAY_SIZE(ad7380_supplies), 794 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 795 .has_mux = true, 796 .available_scan_masks = ad7380_2x4_channel_scan_masks, 797 .timing_specs = &ad7380_4_timing, 798 .max_conversion_rate_hz = 4 * MEGA, 799 }; 800 801 static const struct ad7380_chip_info ad7388_4_chip_info = { 802 .name = "ad7388-4", 803 .channels = ad7388_4_channels, 804 .offload_channels = ad7388_4_offload_channels, 805 .num_channels = ARRAY_SIZE(ad7388_4_channels), 806 .num_simult_channels = 4, 807 .supplies = ad7380_supplies, 808 .num_supplies = ARRAY_SIZE(ad7380_supplies), 809 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 810 .has_mux = true, 811 .available_scan_masks = ad7380_2x4_channel_scan_masks, 812 .timing_specs = &ad7380_4_timing, 813 .max_conversion_rate_hz = 4 * MEGA, 814 }; 815 816 static const struct ad7380_chip_info ad7389_4_chip_info = { 817 .name = "ad7389-4", 818 .channels = ad7380_4_channels, 819 .offload_channels = ad7380_4_offload_channels, 820 .num_channels = ARRAY_SIZE(ad7380_4_channels), 821 .num_simult_channels = 4, 822 .supplies = ad7380_supplies, 823 .num_supplies = ARRAY_SIZE(ad7380_supplies), 824 .internal_ref_only = true, 825 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 826 .available_scan_masks = ad7380_4_channel_scan_masks, 827 .timing_specs = &ad7380_4_timing, 828 .max_conversion_rate_hz = 4 * MEGA, 829 }; 830 831 static const struct ad7380_chip_info adaq4370_4_chip_info = { 832 .name = "adaq4370-4", 833 .channels = adaq4380_4_channels, 834 .offload_channels = adaq4380_4_offload_channels, 835 .num_channels = ARRAY_SIZE(adaq4380_4_channels), 836 .num_simult_channels = 4, 837 .supplies = adaq4380_supplies, 838 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 839 .internal_ref_only = true, 840 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 841 .has_hardware_gain = true, 842 .available_scan_masks = ad7380_4_channel_scan_masks, 843 .timing_specs = &ad7380_4_timing, 844 .max_conversion_rate_hz = 2 * MEGA, 845 }; 846 847 static const struct ad7380_chip_info adaq4380_4_chip_info = { 848 .name = "adaq4380-4", 849 .channels = adaq4380_4_channels, 850 .offload_channels = adaq4380_4_offload_channels, 851 .num_channels = ARRAY_SIZE(adaq4380_4_channels), 852 .num_simult_channels = 4, 853 .supplies = adaq4380_supplies, 854 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 855 .internal_ref_only = true, 856 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 857 .has_hardware_gain = true, 858 .available_scan_masks = ad7380_4_channel_scan_masks, 859 .timing_specs = &ad7380_4_timing, 860 .max_conversion_rate_hz = 4 * MEGA, 861 }; 862 863 static const struct ad7380_chip_info adaq4381_4_chip_info = { 864 .name = "adaq4381-4", 865 .channels = adaq4381_4_channels, 866 .offload_channels = adaq4381_4_offload_channels, 867 .num_channels = ARRAY_SIZE(adaq4381_4_channels), 868 .num_simult_channels = 4, 869 .supplies = adaq4380_supplies, 870 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 871 .internal_ref_only = true, 872 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 873 .has_hardware_gain = true, 874 .available_scan_masks = ad7380_4_channel_scan_masks, 875 .timing_specs = &ad7380_4_timing, 876 }; 877 878 static const struct spi_offload_config ad7380_offload_config = { 879 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 880 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 881 }; 882 883 struct ad7380_state { 884 const struct ad7380_chip_info *chip_info; 885 struct spi_device *spi; 886 struct regmap *regmap; 887 bool resolution_boost_enabled; 888 unsigned int ch; 889 bool seq; 890 unsigned int vref_mv; 891 unsigned int vcm_mv[MAX_NUM_CHANNELS]; 892 unsigned int gain_milli[MAX_NUM_CHANNELS]; 893 /* xfers, message an buffer for reading sample data */ 894 struct spi_transfer normal_xfer[2]; 895 struct spi_message normal_msg; 896 struct spi_transfer seq_xfer[4]; 897 struct spi_message seq_msg; 898 struct spi_transfer offload_xfer; 899 struct spi_message offload_msg; 900 struct spi_offload *offload; 901 struct spi_offload_trigger *offload_trigger; 902 unsigned long offload_trigger_hz; 903 904 int sample_freq_range[3]; 905 /* 906 * DMA (thus cache coherency maintenance) requires the transfer buffers 907 * to live in their own cache lines. 908 * 909 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and 910 * one 64-bit aligned 64-bit timestamp. 911 */ 912 IIO_DECLARE_DMA_BUFFER_WITH_TS(u8, scan_data, MAX_NUM_CHANNELS * sizeof(u32)); 913 /* buffers for reading/writing registers */ 914 u16 tx; 915 u16 rx; 916 }; 917 918 static int ad7380_regmap_reg_write(void *context, unsigned int reg, 919 unsigned int val) 920 { 921 struct ad7380_state *st = context; 922 struct spi_transfer xfer = { 923 .speed_hz = AD7380_REG_WR_SPEED_HZ, 924 .bits_per_word = 16, 925 .len = 2, 926 .tx_buf = &st->tx, 927 }; 928 929 st->tx = FIELD_PREP(AD7380_REG_WR, 1) | 930 FIELD_PREP(AD7380_REG_REGADDR, reg) | 931 FIELD_PREP(AD7380_REG_DATA, val); 932 933 return spi_sync_transfer(st->spi, &xfer, 1); 934 } 935 936 static int ad7380_regmap_reg_read(void *context, unsigned int reg, 937 unsigned int *val) 938 { 939 struct ad7380_state *st = context; 940 struct spi_transfer xfers[] = { 941 { 942 .speed_hz = AD7380_REG_WR_SPEED_HZ, 943 .bits_per_word = 16, 944 .len = 2, 945 .tx_buf = &st->tx, 946 .cs_change = 1, 947 .cs_change_delay = { 948 .value = st->chip_info->timing_specs->t_csh_ns, 949 .unit = SPI_DELAY_UNIT_NSECS, 950 }, 951 }, { 952 .speed_hz = AD7380_REG_WR_SPEED_HZ, 953 .bits_per_word = 16, 954 .len = 2, 955 .rx_buf = &st->rx, 956 }, 957 }; 958 int ret; 959 960 st->tx = FIELD_PREP(AD7380_REG_WR, 0) | 961 FIELD_PREP(AD7380_REG_REGADDR, reg) | 962 FIELD_PREP(AD7380_REG_DATA, 0); 963 964 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 965 if (ret < 0) 966 return ret; 967 968 *val = FIELD_GET(AD7380_REG_DATA, st->rx); 969 970 return 0; 971 } 972 973 static const struct reg_default ad7380_reg_defaults[] = { 974 { AD7380_REG_ADDR_ALERT_LOW_TH, 0x800 }, 975 { AD7380_REG_ADDR_ALERT_HIGH_TH, 0x7FF }, 976 }; 977 978 static const struct regmap_range ad7380_volatile_reg_ranges[] = { 979 regmap_reg_range(AD7380_REG_ADDR_CONFIG2, AD7380_REG_ADDR_ALERT), 980 }; 981 982 static const struct regmap_access_table ad7380_volatile_regs = { 983 .yes_ranges = ad7380_volatile_reg_ranges, 984 .n_yes_ranges = ARRAY_SIZE(ad7380_volatile_reg_ranges), 985 }; 986 987 static const struct regmap_config ad7380_regmap_config = { 988 .reg_bits = 3, 989 .val_bits = 12, 990 .reg_read = ad7380_regmap_reg_read, 991 .reg_write = ad7380_regmap_reg_write, 992 .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH, 993 .can_sleep = true, 994 .reg_defaults = ad7380_reg_defaults, 995 .num_reg_defaults = ARRAY_SIZE(ad7380_reg_defaults), 996 .volatile_table = &ad7380_volatile_regs, 997 .cache_type = REGCACHE_MAPLE, 998 }; 999 1000 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, 1001 u32 writeval, u32 *readval) 1002 { 1003 struct ad7380_state *st = iio_priv(indio_dev); 1004 int ret; 1005 1006 if (!iio_device_claim_direct(indio_dev)) 1007 return -EBUSY; 1008 1009 if (readval) 1010 ret = regmap_read(st->regmap, reg, readval); 1011 else 1012 ret = regmap_write(st->regmap, reg, writeval); 1013 1014 iio_device_release_direct(indio_dev); 1015 1016 return ret; 1017 } 1018 1019 /** 1020 * ad7380_regval_to_osr - convert OSR register value to ratio 1021 * @regval: register value to check 1022 * 1023 * Returns: the ratio corresponding to the OSR register. If regval is not in 1024 * bound, return 1 (oversampling disabled) 1025 * 1026 */ 1027 static int ad7380_regval_to_osr(unsigned int regval) 1028 { 1029 if (regval >= ARRAY_SIZE(ad7380_oversampling_ratios)) 1030 return 1; 1031 1032 return ad7380_oversampling_ratios[regval]; 1033 } 1034 1035 static int ad7380_get_osr(struct ad7380_state *st, int *val) 1036 { 1037 u32 tmp; 1038 int ret; 1039 1040 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); 1041 if (ret) 1042 return ret; 1043 1044 *val = ad7380_regval_to_osr(FIELD_GET(AD7380_CONFIG1_OSR, tmp)); 1045 1046 return 0; 1047 } 1048 1049 /* 1050 * When switching channel, the ADC require an additional settling time. 1051 * According to the datasheet, data is value on the third CS low. We already 1052 * have an extra toggle before each read (either direct reads or buffered reads) 1053 * to sample correct data, so we just add a single CS toggle at the end of the 1054 * register write. 1055 */ 1056 static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch) 1057 { 1058 struct spi_transfer xfer = { 1059 .delay = { 1060 .value = T_CONVERT_NS, 1061 .unit = SPI_DELAY_UNIT_NSECS, 1062 } 1063 }; 1064 int oversampling_ratio, ret; 1065 1066 if (st->ch == ch) 1067 return 0; 1068 1069 ret = ad7380_get_osr(st, &oversampling_ratio); 1070 if (ret) 1071 return ret; 1072 1073 ret = regmap_update_bits(st->regmap, 1074 AD7380_REG_ADDR_CONFIG1, 1075 AD7380_CONFIG1_CH, 1076 FIELD_PREP(AD7380_CONFIG1_CH, ch)); 1077 1078 if (ret) 1079 return ret; 1080 1081 st->ch = ch; 1082 1083 if (oversampling_ratio > 1) 1084 xfer.delay.value = T_CONVERT_0_NS + 1085 T_CONVERT_X_NS * (oversampling_ratio - 1) * 1086 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; 1087 1088 return spi_sync_transfer(st->spi, &xfer, 1); 1089 } 1090 1091 /** 1092 * ad7380_update_xfers - update the SPI transfers base on the current scan type 1093 * @st: device instance specific state 1094 * @scan_type: current scan type 1095 */ 1096 static int ad7380_update_xfers(struct ad7380_state *st, 1097 const struct iio_scan_type *scan_type) 1098 { 1099 struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer; 1100 unsigned int t_convert = T_CONVERT_NS; 1101 int oversampling_ratio, ret; 1102 1103 /* 1104 * In the case of oversampling, conversion time is higher than in normal 1105 * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use 1106 * the maximum value for simplicity for now. 1107 */ 1108 ret = ad7380_get_osr(st, &oversampling_ratio); 1109 if (ret) 1110 return ret; 1111 1112 if (oversampling_ratio > 1) 1113 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS * 1114 (oversampling_ratio - 1) * 1115 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; 1116 1117 if (st->seq) { 1118 xfer[0].delay.value = xfer[1].delay.value = t_convert; 1119 xfer[0].delay.unit = xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS; 1120 xfer[2].bits_per_word = xfer[3].bits_per_word = 1121 scan_type->realbits; 1122 xfer[2].len = xfer[3].len = 1123 AD7380_SPI_BYTES(scan_type) * 1124 st->chip_info->num_simult_channels; 1125 xfer[3].rx_buf = xfer[2].rx_buf + xfer[2].len; 1126 /* Additional delay required here when oversampling is enabled */ 1127 if (oversampling_ratio > 1) 1128 xfer[2].delay.value = t_convert; 1129 else 1130 xfer[2].delay.value = 0; 1131 xfer[2].delay.unit = SPI_DELAY_UNIT_NSECS; 1132 } else { 1133 xfer[0].delay.value = t_convert; 1134 xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS; 1135 xfer[1].bits_per_word = scan_type->realbits; 1136 xfer[1].len = AD7380_SPI_BYTES(scan_type) * 1137 st->chip_info->num_simult_channels; 1138 } 1139 1140 return 0; 1141 } 1142 1143 static int ad7380_set_sample_freq(struct ad7380_state *st, int val) 1144 { 1145 struct spi_offload_trigger_config config = { 1146 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1147 .periodic = { 1148 .frequency_hz = val, 1149 }, 1150 }; 1151 int ret; 1152 1153 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 1154 if (ret) 1155 return ret; 1156 1157 st->offload_trigger_hz = config.periodic.frequency_hz; 1158 1159 return 0; 1160 } 1161 1162 static int ad7380_init_offload_msg(struct ad7380_state *st, 1163 struct iio_dev *indio_dev) 1164 { 1165 struct spi_transfer *xfer = &st->offload_xfer; 1166 struct device *dev = &st->spi->dev; 1167 const struct iio_scan_type *scan_type; 1168 int ret; 1169 1170 scan_type = iio_get_current_scan_type(indio_dev, 1171 &indio_dev->channels[0]); 1172 if (IS_ERR(scan_type)) 1173 return PTR_ERR(scan_type); 1174 1175 if (st->chip_info->has_mux) { 1176 int index; 1177 1178 ret = iio_active_scan_mask_index(indio_dev); 1179 if (ret < 0) 1180 return ret; 1181 1182 index = ret; 1183 if (index == AD7380_SCAN_MASK_SEQ) { 1184 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 1185 AD7380_CONFIG1_SEQ); 1186 if (ret) 1187 return ret; 1188 1189 st->seq = true; 1190 } else { 1191 ret = ad7380_set_ch(st, index); 1192 if (ret) 1193 return ret; 1194 } 1195 } 1196 1197 xfer->bits_per_word = scan_type->realbits; 1198 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1199 xfer->len = AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_channels; 1200 1201 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); 1202 st->offload_msg.offload = st->offload; 1203 1204 ret = spi_optimize_message(st->spi, &st->offload_msg); 1205 if (ret) { 1206 dev_err(dev, "failed to prepare offload msg, err: %d\n", 1207 ret); 1208 return ret; 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int ad7380_offload_buffer_postenable(struct iio_dev *indio_dev) 1215 { 1216 struct ad7380_state *st = iio_priv(indio_dev); 1217 struct spi_offload_trigger_config config = { 1218 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1219 .periodic = { 1220 .frequency_hz = st->offload_trigger_hz, 1221 }, 1222 }; 1223 int ret; 1224 1225 ret = ad7380_init_offload_msg(st, indio_dev); 1226 if (ret) 1227 return ret; 1228 1229 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config); 1230 if (ret) 1231 spi_unoptimize_message(&st->offload_msg); 1232 1233 return ret; 1234 } 1235 1236 static int ad7380_offload_buffer_predisable(struct iio_dev *indio_dev) 1237 { 1238 struct ad7380_state *st = iio_priv(indio_dev); 1239 int ret; 1240 1241 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1242 spi_unoptimize_message(&st->offload_msg); 1243 1244 if (st->seq) { 1245 ret = regmap_update_bits(st->regmap, 1246 AD7380_REG_ADDR_CONFIG1, 1247 AD7380_CONFIG1_SEQ, 1248 FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); 1249 if (ret) 1250 return ret; 1251 1252 st->seq = false; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static const struct iio_buffer_setup_ops ad7380_offload_buffer_setup_ops = { 1259 .postenable = ad7380_offload_buffer_postenable, 1260 .predisable = ad7380_offload_buffer_predisable, 1261 }; 1262 1263 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) 1264 { 1265 struct ad7380_state *st = iio_priv(indio_dev); 1266 const struct iio_scan_type *scan_type; 1267 struct spi_message *msg = &st->normal_msg; 1268 int ret; 1269 1270 /* 1271 * Currently, we always read all channels at the same time. The scan_type 1272 * is the same for all channels, so we just pass the first channel. 1273 */ 1274 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1275 if (IS_ERR(scan_type)) 1276 return PTR_ERR(scan_type); 1277 1278 if (st->chip_info->has_mux) { 1279 unsigned int index; 1280 1281 /* 1282 * Depending on the requested scan_mask and current state, 1283 * we need to either change CH bit, or enable sequencer mode 1284 * to sample correct data. 1285 * Sequencer mode is enabled if active mask corresponds to all 1286 * IIO channels enabled. Otherwise, CH bit is set. 1287 */ 1288 ret = iio_active_scan_mask_index(indio_dev); 1289 if (ret < 0) 1290 return ret; 1291 1292 index = ret; 1293 if (index == AD7380_SCAN_MASK_SEQ) { 1294 ret = regmap_update_bits(st->regmap, 1295 AD7380_REG_ADDR_CONFIG1, 1296 AD7380_CONFIG1_SEQ, 1297 FIELD_PREP(AD7380_CONFIG1_SEQ, 1)); 1298 if (ret) 1299 return ret; 1300 msg = &st->seq_msg; 1301 st->seq = true; 1302 } else { 1303 ret = ad7380_set_ch(st, index); 1304 if (ret) 1305 return ret; 1306 } 1307 1308 } 1309 1310 ret = ad7380_update_xfers(st, scan_type); 1311 if (ret) 1312 return ret; 1313 1314 return spi_optimize_message(st->spi, msg); 1315 } 1316 1317 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev) 1318 { 1319 struct ad7380_state *st = iio_priv(indio_dev); 1320 struct spi_message *msg = &st->normal_msg; 1321 int ret; 1322 1323 if (st->seq) { 1324 ret = regmap_update_bits(st->regmap, 1325 AD7380_REG_ADDR_CONFIG1, 1326 AD7380_CONFIG1_SEQ, 1327 FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); 1328 if (ret) 1329 return ret; 1330 1331 msg = &st->seq_msg; 1332 st->seq = false; 1333 } 1334 1335 spi_unoptimize_message(msg); 1336 1337 return 0; 1338 } 1339 1340 static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = { 1341 .preenable = ad7380_triggered_buffer_preenable, 1342 .postdisable = ad7380_triggered_buffer_postdisable, 1343 }; 1344 1345 static irqreturn_t ad7380_trigger_handler(int irq, void *p) 1346 { 1347 struct iio_poll_func *pf = p; 1348 struct iio_dev *indio_dev = pf->indio_dev; 1349 struct ad7380_state *st = iio_priv(indio_dev); 1350 struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg; 1351 int ret; 1352 1353 ret = spi_sync(st->spi, msg); 1354 if (ret) 1355 goto out; 1356 1357 iio_push_to_buffers_with_ts(indio_dev, &st->scan_data, sizeof(st->scan_data), 1358 pf->timestamp); 1359 1360 out: 1361 iio_trigger_notify_done(indio_dev->trig); 1362 1363 return IRQ_HANDLED; 1364 } 1365 1366 static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index, 1367 const struct iio_scan_type *scan_type, int *val) 1368 { 1369 unsigned int index = scan_index; 1370 int ret; 1371 1372 if (st->chip_info->has_mux) { 1373 unsigned int ch = 0; 1374 1375 if (index >= st->chip_info->num_simult_channels) { 1376 index -= st->chip_info->num_simult_channels; 1377 ch = 1; 1378 } 1379 1380 ret = ad7380_set_ch(st, ch); 1381 if (ret) 1382 return ret; 1383 } 1384 1385 ret = ad7380_update_xfers(st, scan_type); 1386 if (ret) 1387 return ret; 1388 1389 ret = spi_sync(st->spi, &st->normal_msg); 1390 if (ret < 0) 1391 return ret; 1392 1393 if (scan_type->realbits > 16) { 1394 if (scan_type->sign == 's') 1395 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index), 1396 scan_type->realbits - 1); 1397 else 1398 *val = *(u32 *)(st->scan_data + 4 * index) & 1399 GENMASK(scan_type->realbits - 1, 0); 1400 } else { 1401 if (scan_type->sign == 's') 1402 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index), 1403 scan_type->realbits - 1); 1404 else 1405 *val = *(u16 *)(st->scan_data + 2 * index) & 1406 GENMASK(scan_type->realbits - 1, 0); 1407 } 1408 1409 return IIO_VAL_INT; 1410 } 1411 1412 static int ad7380_read_raw(struct iio_dev *indio_dev, 1413 struct iio_chan_spec const *chan, 1414 int *val, int *val2, long info) 1415 { 1416 struct ad7380_state *st = iio_priv(indio_dev); 1417 const struct iio_scan_type *scan_type; 1418 int ret; 1419 1420 scan_type = iio_get_current_scan_type(indio_dev, chan); 1421 1422 if (IS_ERR(scan_type)) 1423 return PTR_ERR(scan_type); 1424 1425 switch (info) { 1426 case IIO_CHAN_INFO_RAW: 1427 if (!iio_device_claim_direct(indio_dev)) 1428 return -EBUSY; 1429 1430 ret = ad7380_read_direct(st, chan->scan_index, 1431 scan_type, val); 1432 1433 iio_device_release_direct(indio_dev); 1434 1435 return ret; 1436 case IIO_CHAN_INFO_SCALE: 1437 /* 1438 * According to the datasheet, the LSB size is: 1439 * * (2 × VREF) / 2^N, for differential chips 1440 * * VREF / 2^N, for pseudo-differential chips 1441 * where N is the ADC resolution (i.e realbits) 1442 * 1443 * The gain is stored as a fraction of 1000 and, as we need to 1444 * divide vref_mv by the gain, we invert the gain/1000 fraction. 1445 */ 1446 if (st->chip_info->has_hardware_gain) 1447 *val = mult_frac(st->vref_mv, MILLI, 1448 st->gain_milli[chan->scan_index]); 1449 else 1450 *val = st->vref_mv; 1451 *val2 = scan_type->realbits - chan->differential; 1452 1453 return IIO_VAL_FRACTIONAL_LOG2; 1454 case IIO_CHAN_INFO_OFFSET: 1455 /* 1456 * According to IIO ABI, offset is applied before scale, 1457 * so offset is: vcm_mv / scale 1458 */ 1459 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits) 1460 / st->vref_mv; 1461 1462 return IIO_VAL_INT; 1463 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1464 if (!iio_device_claim_direct(indio_dev)) 1465 return -EBUSY; 1466 1467 ret = ad7380_get_osr(st, val); 1468 1469 iio_device_release_direct(indio_dev); 1470 1471 if (ret) 1472 return ret; 1473 1474 return IIO_VAL_INT; 1475 case IIO_CHAN_INFO_SAMP_FREQ: 1476 *val = st->offload_trigger_hz; 1477 return IIO_VAL_INT; 1478 default: 1479 return -EINVAL; 1480 } 1481 } 1482 1483 static int ad7380_read_avail(struct iio_dev *indio_dev, 1484 struct iio_chan_spec const *chan, 1485 const int **vals, int *type, int *length, 1486 long mask) 1487 { 1488 struct ad7380_state *st = iio_priv(indio_dev); 1489 1490 switch (mask) { 1491 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1492 *vals = ad7380_oversampling_ratios; 1493 *length = ARRAY_SIZE(ad7380_oversampling_ratios); 1494 *type = IIO_VAL_INT; 1495 1496 return IIO_AVAIL_LIST; 1497 case IIO_CHAN_INFO_SAMP_FREQ: 1498 *vals = st->sample_freq_range; 1499 *type = IIO_VAL_INT; 1500 return IIO_AVAIL_RANGE; 1501 default: 1502 return -EINVAL; 1503 } 1504 } 1505 1506 /** 1507 * ad7380_osr_to_regval - convert ratio to OSR register value 1508 * @ratio: ratio to check 1509 * 1510 * Check if ratio is present in the list of available ratios and return the 1511 * corresponding value that needs to be written to the register to select that 1512 * ratio. 1513 * 1514 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match 1515 */ 1516 static int ad7380_osr_to_regval(int ratio) 1517 { 1518 int i; 1519 1520 for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) { 1521 if (ratio == ad7380_oversampling_ratios[i]) 1522 return i; 1523 } 1524 1525 return -EINVAL; 1526 } 1527 1528 static int ad7380_set_oversampling_ratio(struct ad7380_state *st, int val) 1529 { 1530 int ret, osr, boost; 1531 1532 osr = ad7380_osr_to_regval(val); 1533 if (osr < 0) 1534 return osr; 1535 1536 /* always enable resolution boost when oversampling is enabled */ 1537 boost = osr > 0 ? 1 : 0; 1538 1539 ret = regmap_update_bits(st->regmap, 1540 AD7380_REG_ADDR_CONFIG1, 1541 AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES, 1542 FIELD_PREP(AD7380_CONFIG1_OSR, osr) | 1543 FIELD_PREP(AD7380_CONFIG1_RES, boost)); 1544 1545 if (ret) 1546 return ret; 1547 1548 st->resolution_boost_enabled = boost; 1549 1550 /* 1551 * Perform a soft reset. This will flush the oversampling 1552 * block and FIFO but will maintain the content of the 1553 * configurable registers. 1554 */ 1555 ret = regmap_update_bits(st->regmap, 1556 AD7380_REG_ADDR_CONFIG2, 1557 AD7380_CONFIG2_RESET, 1558 FIELD_PREP(AD7380_CONFIG2_RESET, 1559 AD7380_CONFIG2_RESET_SOFT)); 1560 return ret; 1561 } 1562 static int ad7380_write_raw(struct iio_dev *indio_dev, 1563 struct iio_chan_spec const *chan, int val, 1564 int val2, long mask) 1565 { 1566 struct ad7380_state *st = iio_priv(indio_dev); 1567 int ret; 1568 1569 switch (mask) { 1570 case IIO_CHAN_INFO_SAMP_FREQ: 1571 if (val < 1) 1572 return -EINVAL; 1573 return ad7380_set_sample_freq(st, val); 1574 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1575 if (!iio_device_claim_direct(indio_dev)) 1576 return -EBUSY; 1577 1578 ret = ad7380_set_oversampling_ratio(st, val); 1579 1580 iio_device_release_direct(indio_dev); 1581 1582 return ret; 1583 default: 1584 return -EINVAL; 1585 } 1586 } 1587 1588 static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev, 1589 const struct iio_chan_spec *chan) 1590 { 1591 struct ad7380_state *st = iio_priv(indio_dev); 1592 1593 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST 1594 : AD7380_SCAN_TYPE_NORMAL; 1595 } 1596 1597 static int ad7380_read_event_config(struct iio_dev *indio_dev, 1598 const struct iio_chan_spec *chan, 1599 enum iio_event_type type, 1600 enum iio_event_direction dir) 1601 { 1602 struct ad7380_state *st = iio_priv(indio_dev); 1603 int tmp, ret; 1604 1605 if (!iio_device_claim_direct(indio_dev)) 1606 return -EBUSY; 1607 1608 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); 1609 1610 iio_device_release_direct(indio_dev); 1611 1612 if (ret) 1613 return ret; 1614 1615 return FIELD_GET(AD7380_CONFIG1_ALERTEN, tmp); 1616 } 1617 1618 static int ad7380_write_event_config(struct iio_dev *indio_dev, 1619 const struct iio_chan_spec *chan, 1620 enum iio_event_type type, 1621 enum iio_event_direction dir, 1622 bool state) 1623 { 1624 struct ad7380_state *st = iio_priv(indio_dev); 1625 int ret; 1626 1627 if (!iio_device_claim_direct(indio_dev)) 1628 return -EBUSY; 1629 1630 ret = regmap_update_bits(st->regmap, 1631 AD7380_REG_ADDR_CONFIG1, 1632 AD7380_CONFIG1_ALERTEN, 1633 FIELD_PREP(AD7380_CONFIG1_ALERTEN, state)); 1634 1635 iio_device_release_direct(indio_dev); 1636 1637 return ret; 1638 } 1639 1640 static int ad7380_get_alert_th(struct iio_dev *indio_dev, 1641 const struct iio_chan_spec *chan, 1642 enum iio_event_direction dir, 1643 int *val) 1644 { 1645 struct ad7380_state *st = iio_priv(indio_dev); 1646 const struct iio_scan_type *scan_type; 1647 int ret, tmp, shift; 1648 1649 scan_type = iio_get_current_scan_type(indio_dev, chan); 1650 if (IS_ERR(scan_type)) 1651 return PTR_ERR(scan_type); 1652 1653 /* 1654 * The register value is 12-bits and is compared to the most significant 1655 * bits of raw value, therefore a shift is required to convert this to 1656 * the same scale as the raw value. 1657 */ 1658 shift = scan_type->realbits - 12; 1659 1660 switch (dir) { 1661 case IIO_EV_DIR_RISING: 1662 ret = regmap_read(st->regmap, 1663 AD7380_REG_ADDR_ALERT_HIGH_TH, 1664 &tmp); 1665 if (ret) 1666 return ret; 1667 1668 *val = FIELD_GET(AD7380_ALERT_HIGH_TH, tmp) << shift; 1669 return IIO_VAL_INT; 1670 case IIO_EV_DIR_FALLING: 1671 ret = regmap_read(st->regmap, 1672 AD7380_REG_ADDR_ALERT_LOW_TH, 1673 &tmp); 1674 if (ret) 1675 return ret; 1676 1677 *val = FIELD_GET(AD7380_ALERT_LOW_TH, tmp) << shift; 1678 return IIO_VAL_INT; 1679 default: 1680 return -EINVAL; 1681 } 1682 } 1683 1684 static int ad7380_read_event_value(struct iio_dev *indio_dev, 1685 const struct iio_chan_spec *chan, 1686 enum iio_event_type type, 1687 enum iio_event_direction dir, 1688 enum iio_event_info info, 1689 int *val, int *val2) 1690 { 1691 int ret; 1692 1693 switch (info) { 1694 case IIO_EV_INFO_VALUE: 1695 if (!iio_device_claim_direct(indio_dev)) 1696 return -EBUSY; 1697 1698 ret = ad7380_get_alert_th(indio_dev, chan, dir, val); 1699 1700 iio_device_release_direct(indio_dev); 1701 return ret; 1702 default: 1703 return -EINVAL; 1704 } 1705 } 1706 1707 static int ad7380_set_alert_th(struct iio_dev *indio_dev, 1708 const struct iio_chan_spec *chan, 1709 enum iio_event_direction dir, 1710 int val) 1711 { 1712 struct ad7380_state *st = iio_priv(indio_dev); 1713 const struct iio_scan_type *scan_type; 1714 u16 th; 1715 1716 /* 1717 * According to the datasheet, 1718 * AD7380_REG_ADDR_ALERT_HIGH_TH[11:0] are the 12 MSB of the 1719 * 16-bits internal alert high register. LSB are set to 0xf. 1720 * AD7380_REG_ADDR_ALERT_LOW_TH[11:0] are the 12 MSB of the 1721 * 16 bits internal alert low register. LSB are set to 0x0. 1722 * 1723 * When alert is enabled the conversion from the adc is compared 1724 * immediately to the alert high/low thresholds, before any 1725 * oversampling. This means that the thresholds are the same for 1726 * normal mode and oversampling mode. 1727 */ 1728 1729 /* Extract the 12 MSB of val */ 1730 scan_type = iio_get_current_scan_type(indio_dev, chan); 1731 if (IS_ERR(scan_type)) 1732 return PTR_ERR(scan_type); 1733 1734 th = val >> (scan_type->realbits - 12); 1735 1736 switch (dir) { 1737 case IIO_EV_DIR_RISING: 1738 return regmap_write(st->regmap, 1739 AD7380_REG_ADDR_ALERT_HIGH_TH, 1740 th); 1741 case IIO_EV_DIR_FALLING: 1742 return regmap_write(st->regmap, 1743 AD7380_REG_ADDR_ALERT_LOW_TH, 1744 th); 1745 default: 1746 return -EINVAL; 1747 } 1748 } 1749 1750 static int ad7380_write_event_value(struct iio_dev *indio_dev, 1751 const struct iio_chan_spec *chan, 1752 enum iio_event_type type, 1753 enum iio_event_direction dir, 1754 enum iio_event_info info, 1755 int val, int val2) 1756 { 1757 int ret; 1758 1759 switch (info) { 1760 case IIO_EV_INFO_VALUE: 1761 if (!iio_device_claim_direct(indio_dev)) 1762 return -EBUSY; 1763 1764 ret = ad7380_set_alert_th(indio_dev, chan, dir, val); 1765 1766 iio_device_release_direct(indio_dev); 1767 return ret; 1768 default: 1769 return -EINVAL; 1770 } 1771 } 1772 1773 static const struct iio_info ad7380_info = { 1774 .read_raw = &ad7380_read_raw, 1775 .read_avail = &ad7380_read_avail, 1776 .write_raw = &ad7380_write_raw, 1777 .get_current_scan_type = &ad7380_get_current_scan_type, 1778 .debugfs_reg_access = &ad7380_debugfs_reg_access, 1779 .read_event_config = &ad7380_read_event_config, 1780 .write_event_config = &ad7380_write_event_config, 1781 .read_event_value = &ad7380_read_event_value, 1782 .write_event_value = &ad7380_write_event_value, 1783 }; 1784 1785 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) 1786 { 1787 int ret; 1788 1789 /* perform hard reset */ 1790 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 1791 AD7380_CONFIG2_RESET, 1792 FIELD_PREP(AD7380_CONFIG2_RESET, 1793 AD7380_CONFIG2_RESET_HARD)); 1794 if (ret < 0) 1795 return ret; 1796 1797 if (external_ref_en) { 1798 /* select external reference voltage */ 1799 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 1800 AD7380_CONFIG1_REFSEL); 1801 if (ret < 0) 1802 return ret; 1803 } 1804 1805 /* This is the default value after reset. */ 1806 st->ch = 0; 1807 st->seq = false; 1808 1809 /* SPI 1-wire mode */ 1810 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 1811 AD7380_CONFIG2_SDO, 1812 FIELD_PREP(AD7380_CONFIG2_SDO, 1813 AD7380_NUM_SDO_LINES)); 1814 } 1815 1816 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, 1817 struct ad7380_state *st) 1818 { 1819 struct spi_device *spi = st->spi; 1820 struct device *dev = &spi->dev; 1821 struct dma_chan *rx_dma; 1822 int sample_rate, ret; 1823 1824 indio_dev->setup_ops = &ad7380_offload_buffer_setup_ops; 1825 indio_dev->channels = st->chip_info->offload_channels; 1826 /* Just removing the timestamp channel. */ 1827 indio_dev->num_channels--; 1828 1829 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1830 SPI_OFFLOAD_TRIGGER_PERIODIC); 1831 if (IS_ERR(st->offload_trigger)) 1832 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1833 "failed to get offload trigger\n"); 1834 1835 sample_rate = st->chip_info->max_conversion_rate_hz * 1836 AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; 1837 1838 st->sample_freq_range[0] = 1; /* min */ 1839 st->sample_freq_range[1] = 1; /* step */ 1840 st->sample_freq_range[2] = sample_rate; /* max */ 1841 1842 /* 1843 * Starting with a quite low frequency, to allow oversampling x32, 1844 * user is then reponsible to adjust the frequency for the specific case. 1845 */ 1846 ret = ad7380_set_sample_freq(st, sample_rate / 32); 1847 if (ret) 1848 return ret; 1849 1850 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1851 if (IS_ERR(rx_dma)) 1852 return dev_err_probe(dev, PTR_ERR(rx_dma), 1853 "failed to get offload RX DMA\n"); 1854 1855 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, 1856 rx_dma, IIO_BUFFER_DIRECTION_IN); 1857 if (ret) 1858 return dev_err_probe(dev, ret, "cannot setup dma buffer\n"); 1859 1860 return 0; 1861 } 1862 1863 static int ad7380_probe(struct spi_device *spi) 1864 { 1865 struct device *dev = &spi->dev; 1866 struct iio_dev *indio_dev; 1867 struct ad7380_state *st; 1868 bool external_ref_en; 1869 int ret, i; 1870 1871 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1872 if (!indio_dev) 1873 return -ENOMEM; 1874 1875 st = iio_priv(indio_dev); 1876 st->spi = spi; 1877 st->chip_info = spi_get_device_match_data(spi); 1878 if (!st->chip_info) 1879 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 1880 1881 ret = devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, 1882 st->chip_info->supplies); 1883 1884 if (ret) 1885 return dev_err_probe(dev, ret, 1886 "Failed to enable power supplies\n"); 1887 fsleep(T_POWERUP_US); 1888 1889 if (st->chip_info->internal_ref_only) { 1890 /* 1891 * ADAQ chips use fixed internal reference but still 1892 * require a specific reference supply to power it. 1893 * "refin" is already enabled with other power supplies 1894 * in bulk_get_enable(). 1895 */ 1896 1897 st->vref_mv = st->chip_info->internal_ref_mv; 1898 1899 /* these chips don't have a register bit for this */ 1900 external_ref_en = false; 1901 } else if (st->chip_info->external_ref_only) { 1902 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 1903 if (ret < 0) 1904 return dev_err_probe(dev, ret, 1905 "Failed to get refin regulator\n"); 1906 1907 st->vref_mv = ret / 1000; 1908 1909 /* these chips don't have a register bit for this */ 1910 external_ref_en = false; 1911 } else { 1912 /* 1913 * If there is no REFIO supply, then it means that we are using 1914 * the internal reference, otherwise REFIO is reference voltage. 1915 */ 1916 ret = devm_regulator_get_enable_read_voltage(dev, "refio"); 1917 if (ret < 0 && ret != -ENODEV) 1918 return dev_err_probe(dev, ret, 1919 "Failed to get refio regulator\n"); 1920 1921 external_ref_en = ret != -ENODEV; 1922 st->vref_mv = external_ref_en ? ret / 1000 1923 : st->chip_info->internal_ref_mv; 1924 } 1925 1926 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) 1927 return dev_err_probe(dev, -EINVAL, 1928 "invalid number of VCM supplies\n"); 1929 1930 /* 1931 * pseudo-differential chips have common mode supplies for the negative 1932 * input pin. 1933 */ 1934 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) { 1935 const char *vcm = st->chip_info->vcm_supplies[i]; 1936 1937 ret = devm_regulator_get_enable_read_voltage(dev, vcm); 1938 if (ret < 0) 1939 return dev_err_probe(dev, ret, 1940 "Failed to get %s regulator\n", 1941 vcm); 1942 1943 st->vcm_mv[i] = ret / 1000; 1944 } 1945 1946 for (i = 0; i < MAX_NUM_CHANNELS; i++) 1947 st->gain_milli[i] = AD7380_DEFAULT_GAIN_MILLI; 1948 1949 if (st->chip_info->has_hardware_gain) { 1950 device_for_each_child_node_scoped(dev, node) { 1951 unsigned int channel; 1952 int gain_idx; 1953 u16 gain; 1954 1955 ret = fwnode_property_read_u32(node, "reg", &channel); 1956 if (ret) 1957 return dev_err_probe(dev, ret, 1958 "Failed to read reg property\n"); 1959 1960 if (channel >= st->chip_info->num_channels - 1) 1961 return dev_err_probe(dev, -EINVAL, 1962 "Invalid channel number %i\n", 1963 channel); 1964 1965 ret = fwnode_property_read_u16(node, "adi,gain-milli", 1966 &gain); 1967 if (ret && ret != -EINVAL) 1968 return dev_err_probe(dev, ret, 1969 "Failed to read gain for channel %i\n", 1970 channel); 1971 if (ret != -EINVAL) { 1972 /* 1973 * Match gain value from dt to one of supported 1974 * gains 1975 */ 1976 gain_idx = find_closest(gain, ad7380_gains, 1977 ARRAY_SIZE(ad7380_gains)); 1978 st->gain_milli[channel] = ad7380_gains[gain_idx]; 1979 } 1980 } 1981 } 1982 1983 st->regmap = devm_regmap_init(dev, NULL, st, &ad7380_regmap_config); 1984 if (IS_ERR(st->regmap)) 1985 return dev_err_probe(dev, PTR_ERR(st->regmap), 1986 "failed to allocate register map\n"); 1987 1988 /* 1989 * Setting up xfer structures for both normal and sequence mode. These 1990 * struct are used for both direct read and triggered buffer. Additional 1991 * fields will be set up in ad7380_update_xfers() based on the current 1992 * state of the driver at the time of the read. 1993 */ 1994 1995 /* 1996 * In normal mode a read is composed of two steps: 1997 * - first, toggle CS (no data xfer) to trigger a conversion 1998 * - then, read data 1999 */ 2000 st->normal_xfer[0].cs_change = 1; 2001 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2002 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2003 st->normal_xfer[1].rx_buf = st->scan_data; 2004 2005 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, 2006 ARRAY_SIZE(st->normal_xfer)); 2007 /* 2008 * In sequencer mode a read is composed of four steps: 2009 * - CS toggle (no data xfer) to get the right point in the sequence 2010 * - CS toggle (no data xfer) to trigger a conversion of AinX0 and 2011 * acquisition of AinX1 2012 * - 2 data reads, to read AinX0 and AinX1 2013 */ 2014 st->seq_xfer[0].cs_change = 1; 2015 st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2016 st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2017 st->seq_xfer[1].cs_change = 1; 2018 st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2019 st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2020 2021 st->seq_xfer[2].rx_buf = st->scan_data; 2022 st->seq_xfer[2].cs_change = 1; 2023 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2024 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2025 2026 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, 2027 ARRAY_SIZE(st->seq_xfer)); 2028 2029 indio_dev->channels = st->chip_info->channels; 2030 indio_dev->num_channels = st->chip_info->num_channels; 2031 indio_dev->name = st->chip_info->name; 2032 indio_dev->info = &ad7380_info; 2033 indio_dev->modes = INDIO_DIRECT_MODE; 2034 indio_dev->available_scan_masks = st->chip_info->available_scan_masks; 2035 2036 st->offload = devm_spi_offload_get(dev, spi, &ad7380_offload_config); 2037 ret = PTR_ERR_OR_ZERO(st->offload); 2038 if (ret && ret != -ENODEV) 2039 return dev_err_probe(dev, ret, "failed to get offload\n"); 2040 2041 /* If no SPI offload, fall back to low speed usage. */ 2042 if (ret == -ENODEV) { 2043 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 2044 iio_pollfunc_store_time, 2045 ad7380_trigger_handler, 2046 &ad7380_buffer_setup_ops); 2047 if (ret) 2048 return ret; 2049 } else { 2050 ret = ad7380_probe_spi_offload(indio_dev, st); 2051 if (ret) 2052 return ret; 2053 } 2054 2055 ret = ad7380_init(st, external_ref_en); 2056 if (ret) 2057 return ret; 2058 2059 return devm_iio_device_register(dev, indio_dev); 2060 } 2061 2062 static const struct of_device_id ad7380_of_match_table[] = { 2063 { .compatible = "adi,ad7380", .data = &ad7380_chip_info }, 2064 { .compatible = "adi,ad7381", .data = &ad7381_chip_info }, 2065 { .compatible = "adi,ad7383", .data = &ad7383_chip_info }, 2066 { .compatible = "adi,ad7384", .data = &ad7384_chip_info }, 2067 { .compatible = "adi,ad7386", .data = &ad7386_chip_info }, 2068 { .compatible = "adi,ad7387", .data = &ad7387_chip_info }, 2069 { .compatible = "adi,ad7388", .data = &ad7388_chip_info }, 2070 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info }, 2071 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info }, 2072 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info }, 2073 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info }, 2074 { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info }, 2075 { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info }, 2076 { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info }, 2077 { .compatible = "adi,ad7389-4", .data = &ad7389_4_chip_info }, 2078 { .compatible = "adi,adaq4370-4", .data = &adaq4370_4_chip_info }, 2079 { .compatible = "adi,adaq4380-4", .data = &adaq4380_4_chip_info }, 2080 { .compatible = "adi,adaq4381-4", .data = &adaq4381_4_chip_info }, 2081 { } 2082 }; 2083 2084 static const struct spi_device_id ad7380_id_table[] = { 2085 { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, 2086 { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, 2087 { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, 2088 { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, 2089 { "ad7386", (kernel_ulong_t)&ad7386_chip_info }, 2090 { "ad7387", (kernel_ulong_t)&ad7387_chip_info }, 2091 { "ad7388", (kernel_ulong_t)&ad7388_chip_info }, 2092 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, 2093 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, 2094 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, 2095 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, 2096 { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info }, 2097 { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info }, 2098 { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info }, 2099 { "ad7389-4", (kernel_ulong_t)&ad7389_4_chip_info }, 2100 { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info }, 2101 { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info }, 2102 { "adaq4381-4", (kernel_ulong_t)&adaq4381_4_chip_info }, 2103 { } 2104 }; 2105 MODULE_DEVICE_TABLE(spi, ad7380_id_table); 2106 2107 static struct spi_driver ad7380_driver = { 2108 .driver = { 2109 .name = "ad7380", 2110 .of_match_table = ad7380_of_match_table, 2111 }, 2112 .probe = ad7380_probe, 2113 .id_table = ad7380_id_table, 2114 }; 2115 module_spi_driver(ad7380_driver); 2116 2117 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 2118 MODULE_DESCRIPTION("Analog Devices AD738x ADC driver"); 2119 MODULE_LICENSE("GPL"); 2120 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 2121