1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD738x Simultaneous Sampling SAR ADCs 4 * 5 * Copyright 2017 Analog Devices Inc. 6 * Copyright 2024 BayLibre, SAS 7 * 8 * Datasheets of supported parts: 9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf 10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf 11 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf 12 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf 13 * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf 14 */ 15 16 #include <linux/align.h> 17 #include <linux/bitfield.h> 18 #include <linux/bitops.h> 19 #include <linux/cleanup.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/slab.h> 27 #include <linux/spi/spi.h> 28 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/iio.h> 31 #include <linux/iio/trigger_consumer.h> 32 #include <linux/iio/triggered_buffer.h> 33 34 #define MAX_NUM_CHANNELS 4 35 /* 2.5V internal reference voltage */ 36 #define AD7380_INTERNAL_REF_MV 2500 37 38 /* reading and writing registers is more reliable at lower than max speed */ 39 #define AD7380_REG_WR_SPEED_HZ 10000000 40 41 #define AD7380_REG_WR BIT(15) 42 #define AD7380_REG_REGADDR GENMASK(14, 12) 43 #define AD7380_REG_DATA GENMASK(11, 0) 44 45 #define AD7380_REG_ADDR_NOP 0x0 46 #define AD7380_REG_ADDR_CONFIG1 0x1 47 #define AD7380_REG_ADDR_CONFIG2 0x2 48 #define AD7380_REG_ADDR_ALERT 0x3 49 #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 50 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 51 52 #define AD7380_CONFIG1_OS_MODE BIT(9) 53 #define AD7380_CONFIG1_OSR GENMASK(8, 6) 54 #define AD7380_CONFIG1_CRC_W BIT(5) 55 #define AD7380_CONFIG1_CRC_R BIT(4) 56 #define AD7380_CONFIG1_ALERTEN BIT(3) 57 #define AD7380_CONFIG1_RES BIT(2) 58 #define AD7380_CONFIG1_REFSEL BIT(1) 59 #define AD7380_CONFIG1_PMODE BIT(0) 60 61 #define AD7380_CONFIG2_SDO2 GENMASK(9, 8) 62 #define AD7380_CONFIG2_SDO BIT(8) 63 #define AD7380_CONFIG2_RESET GENMASK(7, 0) 64 65 #define AD7380_CONFIG2_RESET_SOFT 0x3C 66 #define AD7380_CONFIG2_RESET_HARD 0xFF 67 68 #define AD7380_ALERT_LOW_TH GENMASK(11, 0) 69 #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) 70 71 #define T_CONVERT_NS 190 /* conversion time */ 72 #define T_CONVERT_0_NS 10 /* 1st conversion start time (oversampling) */ 73 #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ 74 75 struct ad7380_timing_specs { 76 const unsigned int t_csh_ns; /* CS minimum high time */ 77 }; 78 79 struct ad7380_chip_info { 80 const char *name; 81 const struct iio_chan_spec *channels; 82 unsigned int num_channels; 83 const char * const *vcm_supplies; 84 unsigned int num_vcm_supplies; 85 const unsigned long *available_scan_masks; 86 const struct ad7380_timing_specs *timing_specs; 87 }; 88 89 enum { 90 AD7380_SCAN_TYPE_NORMAL, 91 AD7380_SCAN_TYPE_RESOLUTION_BOOST, 92 }; 93 94 /* Extended scan types for 14-bit chips. */ 95 static const struct iio_scan_type ad7380_scan_type_14[] = { 96 [AD7380_SCAN_TYPE_NORMAL] = { 97 .sign = 's', 98 .realbits = 14, 99 .storagebits = 16, 100 .endianness = IIO_CPU 101 }, 102 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 103 .sign = 's', 104 .realbits = 16, 105 .storagebits = 16, 106 .endianness = IIO_CPU 107 }, 108 }; 109 110 /* Extended scan types for 16-bit chips. */ 111 static const struct iio_scan_type ad7380_scan_type_16[] = { 112 [AD7380_SCAN_TYPE_NORMAL] = { 113 .sign = 's', 114 .realbits = 16, 115 .storagebits = 16, 116 .endianness = IIO_CPU 117 }, 118 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 119 .sign = 's', 120 .realbits = 18, 121 .storagebits = 32, 122 .endianness = IIO_CPU 123 }, 124 }; 125 126 #define AD7380_CHANNEL(index, bits, diff) { \ 127 .type = IIO_VOLTAGE, \ 128 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 129 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 130 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 131 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 132 .info_mask_shared_by_type_available = \ 133 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 134 .indexed = 1, \ 135 .differential = (diff), \ 136 .channel = (diff) ? (2 * (index)) : (index), \ 137 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 138 .scan_index = (index), \ 139 .has_ext_scan_type = 1, \ 140 .ext_scan_type = ad7380_scan_type_##bits, \ 141 .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits),\ 142 } 143 144 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff) \ 145 static const struct iio_chan_spec name[] = { \ 146 AD7380_CHANNEL(0, bits, diff), \ 147 AD7380_CHANNEL(1, bits, diff), \ 148 IIO_CHAN_SOFT_TIMESTAMP(2), \ 149 } 150 151 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff) \ 152 static const struct iio_chan_spec name[] = { \ 153 AD7380_CHANNEL(0, bits, diff), \ 154 AD7380_CHANNEL(1, bits, diff), \ 155 AD7380_CHANNEL(2, bits, diff), \ 156 AD7380_CHANNEL(3, bits, diff), \ 157 IIO_CHAN_SOFT_TIMESTAMP(4), \ 158 } 159 160 /* fully differential */ 161 DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1); 162 DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1); 163 DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1); 164 DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1); 165 /* pseudo differential */ 166 DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0); 167 DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0); 168 DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0); 169 DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0); 170 171 static const char * const ad7380_2_channel_vcm_supplies[] = { 172 "aina", "ainb", 173 }; 174 175 static const char * const ad7380_4_channel_vcm_supplies[] = { 176 "aina", "ainb", "ainc", "aind", 177 }; 178 179 /* Since this is simultaneous sampling, we don't allow individual channels. */ 180 static const unsigned long ad7380_2_channel_scan_masks[] = { 181 GENMASK(1, 0), 182 0 183 }; 184 185 static const unsigned long ad7380_4_channel_scan_masks[] = { 186 GENMASK(3, 0), 187 0 188 }; 189 190 static const struct ad7380_timing_specs ad7380_timing = { 191 .t_csh_ns = 10, 192 }; 193 194 static const struct ad7380_timing_specs ad7380_4_timing = { 195 .t_csh_ns = 20, 196 }; 197 198 /* 199 * Available oversampling ratios. The indices correspond with the bit value 200 * expected by the chip. The available ratios depend on the averaging mode, 201 * only normal averaging is supported for now. 202 */ 203 static const int ad7380_oversampling_ratios[] = { 204 1, 2, 4, 8, 16, 32, 205 }; 206 207 static const struct ad7380_chip_info ad7380_chip_info = { 208 .name = "ad7380", 209 .channels = ad7380_channels, 210 .num_channels = ARRAY_SIZE(ad7380_channels), 211 .available_scan_masks = ad7380_2_channel_scan_masks, 212 .timing_specs = &ad7380_timing, 213 }; 214 215 static const struct ad7380_chip_info ad7381_chip_info = { 216 .name = "ad7381", 217 .channels = ad7381_channels, 218 .num_channels = ARRAY_SIZE(ad7381_channels), 219 .available_scan_masks = ad7380_2_channel_scan_masks, 220 .timing_specs = &ad7380_timing, 221 }; 222 223 static const struct ad7380_chip_info ad7383_chip_info = { 224 .name = "ad7383", 225 .channels = ad7383_channels, 226 .num_channels = ARRAY_SIZE(ad7383_channels), 227 .vcm_supplies = ad7380_2_channel_vcm_supplies, 228 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 229 .available_scan_masks = ad7380_2_channel_scan_masks, 230 .timing_specs = &ad7380_timing, 231 }; 232 233 static const struct ad7380_chip_info ad7384_chip_info = { 234 .name = "ad7384", 235 .channels = ad7384_channels, 236 .num_channels = ARRAY_SIZE(ad7384_channels), 237 .vcm_supplies = ad7380_2_channel_vcm_supplies, 238 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 239 .available_scan_masks = ad7380_2_channel_scan_masks, 240 .timing_specs = &ad7380_timing, 241 }; 242 243 static const struct ad7380_chip_info ad7380_4_chip_info = { 244 .name = "ad7380-4", 245 .channels = ad7380_4_channels, 246 .num_channels = ARRAY_SIZE(ad7380_4_channels), 247 .available_scan_masks = ad7380_4_channel_scan_masks, 248 .timing_specs = &ad7380_4_timing, 249 }; 250 251 static const struct ad7380_chip_info ad7381_4_chip_info = { 252 .name = "ad7381-4", 253 .channels = ad7381_4_channels, 254 .num_channels = ARRAY_SIZE(ad7381_4_channels), 255 .available_scan_masks = ad7380_4_channel_scan_masks, 256 .timing_specs = &ad7380_4_timing, 257 }; 258 259 static const struct ad7380_chip_info ad7383_4_chip_info = { 260 .name = "ad7383-4", 261 .channels = ad7383_4_channels, 262 .num_channels = ARRAY_SIZE(ad7383_4_channels), 263 .vcm_supplies = ad7380_4_channel_vcm_supplies, 264 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 265 .available_scan_masks = ad7380_4_channel_scan_masks, 266 .timing_specs = &ad7380_4_timing, 267 }; 268 269 static const struct ad7380_chip_info ad7384_4_chip_info = { 270 .name = "ad7384-4", 271 .channels = ad7384_4_channels, 272 .num_channels = ARRAY_SIZE(ad7384_4_channels), 273 .vcm_supplies = ad7380_4_channel_vcm_supplies, 274 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 275 .available_scan_masks = ad7380_4_channel_scan_masks, 276 .timing_specs = &ad7380_4_timing, 277 }; 278 279 struct ad7380_state { 280 const struct ad7380_chip_info *chip_info; 281 struct spi_device *spi; 282 struct regmap *regmap; 283 unsigned int oversampling_ratio; 284 bool resolution_boost_enabled; 285 unsigned int vref_mv; 286 unsigned int vcm_mv[MAX_NUM_CHANNELS]; 287 /* xfers, message an buffer for reading sample data */ 288 struct spi_transfer xfer[2]; 289 struct spi_message msg; 290 /* 291 * DMA (thus cache coherency maintenance) requires the transfer buffers 292 * to live in their own cache lines. 293 * 294 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and 295 * one 64-bit aligned 64-bit timestamp. 296 */ 297 u8 scan_data[ALIGN(MAX_NUM_CHANNELS * sizeof(u32), sizeof(s64)) 298 + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); 299 /* buffers for reading/writing registers */ 300 u16 tx; 301 u16 rx; 302 }; 303 304 static int ad7380_regmap_reg_write(void *context, unsigned int reg, 305 unsigned int val) 306 { 307 struct ad7380_state *st = context; 308 struct spi_transfer xfer = { 309 .speed_hz = AD7380_REG_WR_SPEED_HZ, 310 .bits_per_word = 16, 311 .len = 2, 312 .tx_buf = &st->tx, 313 }; 314 315 st->tx = FIELD_PREP(AD7380_REG_WR, 1) | 316 FIELD_PREP(AD7380_REG_REGADDR, reg) | 317 FIELD_PREP(AD7380_REG_DATA, val); 318 319 return spi_sync_transfer(st->spi, &xfer, 1); 320 } 321 322 static int ad7380_regmap_reg_read(void *context, unsigned int reg, 323 unsigned int *val) 324 { 325 struct ad7380_state *st = context; 326 struct spi_transfer xfers[] = { 327 { 328 .speed_hz = AD7380_REG_WR_SPEED_HZ, 329 .bits_per_word = 16, 330 .len = 2, 331 .tx_buf = &st->tx, 332 .cs_change = 1, 333 .cs_change_delay = { 334 .value = st->chip_info->timing_specs->t_csh_ns, 335 .unit = SPI_DELAY_UNIT_NSECS, 336 }, 337 }, { 338 .speed_hz = AD7380_REG_WR_SPEED_HZ, 339 .bits_per_word = 16, 340 .len = 2, 341 .rx_buf = &st->rx, 342 }, 343 }; 344 int ret; 345 346 st->tx = FIELD_PREP(AD7380_REG_WR, 0) | 347 FIELD_PREP(AD7380_REG_REGADDR, reg) | 348 FIELD_PREP(AD7380_REG_DATA, 0); 349 350 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 351 if (ret < 0) 352 return ret; 353 354 *val = FIELD_GET(AD7380_REG_DATA, st->rx); 355 356 return 0; 357 } 358 359 static const struct regmap_config ad7380_regmap_config = { 360 .reg_bits = 3, 361 .val_bits = 12, 362 .reg_read = ad7380_regmap_reg_read, 363 .reg_write = ad7380_regmap_reg_write, 364 .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH, 365 .can_sleep = true, 366 }; 367 368 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, 369 u32 writeval, u32 *readval) 370 { 371 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 372 struct ad7380_state *st = iio_priv(indio_dev); 373 374 if (readval) 375 return regmap_read(st->regmap, reg, readval); 376 else 377 return regmap_write(st->regmap, reg, writeval); 378 } 379 unreachable(); 380 } 381 382 /** 383 * ad7380_update_xfers - update the SPI transfers base on the current scan type 384 * @st: device instance specific state 385 * @scan_type: current scan type 386 */ 387 static void ad7380_update_xfers(struct ad7380_state *st, 388 const struct iio_scan_type *scan_type) 389 { 390 /* 391 * First xfer only triggers conversion and has to be long enough for 392 * all conversions to complete, which can be multiple conversion in the 393 * case of oversampling. Technically T_CONVERT_X_NS is lower for some 394 * chips, but we use the maximum value for simplicity for now. 395 */ 396 if (st->oversampling_ratio > 1) 397 st->xfer[0].delay.value = T_CONVERT_0_NS + T_CONVERT_X_NS * 398 (st->oversampling_ratio - 1); 399 else 400 st->xfer[0].delay.value = T_CONVERT_NS; 401 402 st->xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS; 403 404 /* 405 * Second xfer reads all channels. Data size depends on if resolution 406 * boost is enabled or not. 407 */ 408 st->xfer[1].bits_per_word = scan_type->realbits; 409 st->xfer[1].len = BITS_TO_BYTES(scan_type->storagebits) * 410 (st->chip_info->num_channels - 1); 411 } 412 413 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) 414 { 415 struct ad7380_state *st = iio_priv(indio_dev); 416 const struct iio_scan_type *scan_type; 417 418 /* 419 * Currently, we always read all channels at the same time. The scan_type 420 * is the same for all channels, so we just pass the first channel. 421 */ 422 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 423 if (IS_ERR(scan_type)) 424 return PTR_ERR(scan_type); 425 426 ad7380_update_xfers(st, scan_type); 427 428 return spi_optimize_message(st->spi, &st->msg); 429 } 430 431 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev) 432 { 433 struct ad7380_state *st = iio_priv(indio_dev); 434 435 spi_unoptimize_message(&st->msg); 436 437 return 0; 438 } 439 440 static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = { 441 .preenable = ad7380_triggered_buffer_preenable, 442 .postdisable = ad7380_triggered_buffer_postdisable, 443 }; 444 445 static irqreturn_t ad7380_trigger_handler(int irq, void *p) 446 { 447 struct iio_poll_func *pf = p; 448 struct iio_dev *indio_dev = pf->indio_dev; 449 struct ad7380_state *st = iio_priv(indio_dev); 450 int ret; 451 452 ret = spi_sync(st->spi, &st->msg); 453 if (ret) 454 goto out; 455 456 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data, 457 pf->timestamp); 458 459 out: 460 iio_trigger_notify_done(indio_dev->trig); 461 462 return IRQ_HANDLED; 463 } 464 465 static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index, 466 const struct iio_scan_type *scan_type, int *val) 467 { 468 int ret; 469 470 ad7380_update_xfers(st, scan_type); 471 472 ret = spi_sync(st->spi, &st->msg); 473 if (ret < 0) 474 return ret; 475 476 if (scan_type->storagebits > 16) 477 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * scan_index), 478 scan_type->realbits - 1); 479 else 480 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * scan_index), 481 scan_type->realbits - 1); 482 483 return IIO_VAL_INT; 484 } 485 486 static int ad7380_read_raw(struct iio_dev *indio_dev, 487 struct iio_chan_spec const *chan, 488 int *val, int *val2, long info) 489 { 490 struct ad7380_state *st = iio_priv(indio_dev); 491 const struct iio_scan_type *scan_type; 492 493 scan_type = iio_get_current_scan_type(indio_dev, chan); 494 495 if (IS_ERR(scan_type)) 496 return PTR_ERR(scan_type); 497 498 switch (info) { 499 case IIO_CHAN_INFO_RAW: 500 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 501 return ad7380_read_direct(st, chan->scan_index, 502 scan_type, val); 503 } 504 unreachable(); 505 case IIO_CHAN_INFO_SCALE: 506 /* 507 * According to the datasheet, the LSB size is: 508 * * (2 × VREF) / 2^N, for differential chips 509 * * VREF / 2^N, for pseudo-differential chips 510 * where N is the ADC resolution (i.e realbits) 511 */ 512 *val = st->vref_mv; 513 *val2 = scan_type->realbits - chan->differential; 514 515 return IIO_VAL_FRACTIONAL_LOG2; 516 case IIO_CHAN_INFO_OFFSET: 517 /* 518 * According to IIO ABI, offset is applied before scale, 519 * so offset is: vcm_mv / scale 520 */ 521 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits) 522 / st->vref_mv; 523 524 return IIO_VAL_INT; 525 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 526 *val = st->oversampling_ratio; 527 528 return IIO_VAL_INT; 529 default: 530 return -EINVAL; 531 } 532 } 533 534 static int ad7380_read_avail(struct iio_dev *indio_dev, 535 struct iio_chan_spec const *chan, 536 const int **vals, int *type, int *length, 537 long mask) 538 { 539 switch (mask) { 540 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 541 *vals = ad7380_oversampling_ratios; 542 *length = ARRAY_SIZE(ad7380_oversampling_ratios); 543 *type = IIO_VAL_INT; 544 545 return IIO_AVAIL_LIST; 546 default: 547 return -EINVAL; 548 } 549 } 550 551 /** 552 * ad7380_osr_to_regval - convert ratio to OSR register value 553 * @ratio: ratio to check 554 * 555 * Check if ratio is present in the list of available ratios and return the 556 * corresponding value that needs to be written to the register to select that 557 * ratio. 558 * 559 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match 560 */ 561 static int ad7380_osr_to_regval(int ratio) 562 { 563 int i; 564 565 for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) { 566 if (ratio == ad7380_oversampling_ratios[i]) 567 return i; 568 } 569 570 return -EINVAL; 571 } 572 573 static int ad7380_write_raw(struct iio_dev *indio_dev, 574 struct iio_chan_spec const *chan, int val, 575 int val2, long mask) 576 { 577 struct ad7380_state *st = iio_priv(indio_dev); 578 int ret, osr, boost; 579 580 switch (mask) { 581 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 582 osr = ad7380_osr_to_regval(val); 583 if (osr < 0) 584 return osr; 585 586 /* always enable resolution boost when oversampling is enabled */ 587 boost = osr > 0 ? 1 : 0; 588 589 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 590 ret = regmap_update_bits(st->regmap, 591 AD7380_REG_ADDR_CONFIG1, 592 AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES, 593 FIELD_PREP(AD7380_CONFIG1_OSR, osr) | 594 FIELD_PREP(AD7380_CONFIG1_RES, boost)); 595 596 if (ret) 597 return ret; 598 599 st->oversampling_ratio = val; 600 st->resolution_boost_enabled = boost; 601 602 /* 603 * Perform a soft reset. This will flush the oversampling 604 * block and FIFO but will maintain the content of the 605 * configurable registers. 606 */ 607 return regmap_update_bits(st->regmap, 608 AD7380_REG_ADDR_CONFIG2, 609 AD7380_CONFIG2_RESET, 610 FIELD_PREP(AD7380_CONFIG2_RESET, 611 AD7380_CONFIG2_RESET_SOFT)); 612 } 613 unreachable(); 614 default: 615 return -EINVAL; 616 } 617 } 618 619 static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev, 620 const struct iio_chan_spec *chan) 621 { 622 struct ad7380_state *st = iio_priv(indio_dev); 623 624 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST 625 : AD7380_SCAN_TYPE_NORMAL; 626 } 627 628 static const struct iio_info ad7380_info = { 629 .read_raw = &ad7380_read_raw, 630 .read_avail = &ad7380_read_avail, 631 .write_raw = &ad7380_write_raw, 632 .get_current_scan_type = &ad7380_get_current_scan_type, 633 .debugfs_reg_access = &ad7380_debugfs_reg_access, 634 }; 635 636 static int ad7380_init(struct ad7380_state *st, struct regulator *vref) 637 { 638 int ret; 639 640 /* perform hard reset */ 641 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 642 AD7380_CONFIG2_RESET, 643 FIELD_PREP(AD7380_CONFIG2_RESET, 644 AD7380_CONFIG2_RESET_HARD)); 645 if (ret < 0) 646 return ret; 647 648 /* select internal or external reference voltage */ 649 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 650 AD7380_CONFIG1_REFSEL, 651 FIELD_PREP(AD7380_CONFIG1_REFSEL, 652 vref ? 1 : 0)); 653 if (ret < 0) 654 return ret; 655 656 /* This is the default value after reset. */ 657 st->oversampling_ratio = 1; 658 659 /* SPI 1-wire mode */ 660 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 661 AD7380_CONFIG2_SDO, 662 FIELD_PREP(AD7380_CONFIG2_SDO, 1)); 663 } 664 665 static void ad7380_regulator_disable(void *p) 666 { 667 regulator_disable(p); 668 } 669 670 static int ad7380_probe(struct spi_device *spi) 671 { 672 struct iio_dev *indio_dev; 673 struct ad7380_state *st; 674 struct regulator *vref; 675 int ret, i; 676 677 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 678 if (!indio_dev) 679 return -ENOMEM; 680 681 st = iio_priv(indio_dev); 682 st->spi = spi; 683 st->chip_info = spi_get_device_match_data(spi); 684 if (!st->chip_info) 685 return dev_err_probe(&spi->dev, -EINVAL, "missing match data\n"); 686 687 vref = devm_regulator_get_optional(&spi->dev, "refio"); 688 if (IS_ERR(vref)) { 689 if (PTR_ERR(vref) != -ENODEV) 690 return dev_err_probe(&spi->dev, PTR_ERR(vref), 691 "Failed to get refio regulator\n"); 692 693 vref = NULL; 694 } 695 696 /* 697 * If there is no REFIO supply, then it means that we are using 698 * the internal 2.5V reference, otherwise REFIO is reference voltage. 699 */ 700 if (vref) { 701 ret = regulator_enable(vref); 702 if (ret) 703 return ret; 704 705 ret = devm_add_action_or_reset(&spi->dev, 706 ad7380_regulator_disable, vref); 707 if (ret) 708 return ret; 709 710 ret = regulator_get_voltage(vref); 711 if (ret < 0) 712 return ret; 713 714 st->vref_mv = ret / 1000; 715 } else { 716 st->vref_mv = AD7380_INTERNAL_REF_MV; 717 } 718 719 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) 720 return dev_err_probe(&spi->dev, -EINVAL, 721 "invalid number of VCM supplies\n"); 722 723 /* 724 * pseudo-differential chips have common mode supplies for the negative 725 * input pin. 726 */ 727 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) { 728 struct regulator *vcm; 729 730 vcm = devm_regulator_get(&spi->dev, 731 st->chip_info->vcm_supplies[i]); 732 if (IS_ERR(vcm)) 733 return dev_err_probe(&spi->dev, PTR_ERR(vcm), 734 "Failed to get %s regulator\n", 735 st->chip_info->vcm_supplies[i]); 736 737 ret = regulator_enable(vcm); 738 if (ret) 739 return ret; 740 741 ret = devm_add_action_or_reset(&spi->dev, 742 ad7380_regulator_disable, vcm); 743 if (ret) 744 return ret; 745 746 ret = regulator_get_voltage(vcm); 747 if (ret < 0) 748 return ret; 749 750 st->vcm_mv[i] = ret / 1000; 751 } 752 753 st->regmap = devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_config); 754 if (IS_ERR(st->regmap)) 755 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), 756 "failed to allocate register map\n"); 757 758 /* 759 * Setting up a low latency read for getting sample data. Used for both 760 * direct read an triggered buffer. Additional fields will be set up in 761 * ad7380_update_xfers() based on the current state of the driver at the 762 * time of the read. 763 */ 764 765 /* toggle CS (no data xfer) to trigger a conversion */ 766 st->xfer[0].cs_change = 1; 767 st->xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 768 st->xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 769 770 /* then do a second xfer to read the data */ 771 st->xfer[1].rx_buf = st->scan_data; 772 773 spi_message_init_with_transfers(&st->msg, st->xfer, ARRAY_SIZE(st->xfer)); 774 775 indio_dev->channels = st->chip_info->channels; 776 indio_dev->num_channels = st->chip_info->num_channels; 777 indio_dev->name = st->chip_info->name; 778 indio_dev->info = &ad7380_info; 779 indio_dev->modes = INDIO_DIRECT_MODE; 780 indio_dev->available_scan_masks = st->chip_info->available_scan_masks; 781 782 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 783 iio_pollfunc_store_time, 784 ad7380_trigger_handler, 785 &ad7380_buffer_setup_ops); 786 if (ret) 787 return ret; 788 789 ret = ad7380_init(st, vref); 790 if (ret) 791 return ret; 792 793 return devm_iio_device_register(&spi->dev, indio_dev); 794 } 795 796 static const struct of_device_id ad7380_of_match_table[] = { 797 { .compatible = "adi,ad7380", .data = &ad7380_chip_info }, 798 { .compatible = "adi,ad7381", .data = &ad7381_chip_info }, 799 { .compatible = "adi,ad7383", .data = &ad7383_chip_info }, 800 { .compatible = "adi,ad7384", .data = &ad7384_chip_info }, 801 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info }, 802 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info }, 803 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info }, 804 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info }, 805 { } 806 }; 807 808 static const struct spi_device_id ad7380_id_table[] = { 809 { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, 810 { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, 811 { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, 812 { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, 813 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, 814 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, 815 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, 816 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, 817 { } 818 }; 819 MODULE_DEVICE_TABLE(spi, ad7380_id_table); 820 821 static struct spi_driver ad7380_driver = { 822 .driver = { 823 .name = "ad7380", 824 .of_match_table = ad7380_of_match_table, 825 }, 826 .probe = ad7380_probe, 827 .id_table = ad7380_id_table, 828 }; 829 module_spi_driver(ad7380_driver); 830 831 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 832 MODULE_DESCRIPTION("Analog Devices AD738x ADC driver"); 833 MODULE_LICENSE("GPL"); 834