1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD738x Simultaneous Sampling SAR ADCs 4 * 5 * Copyright 2017 Analog Devices Inc. 6 * Copyright 2024 BayLibre, SAS 7 * 8 * Datasheets of supported parts: 9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf 10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf 11 * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-7388.pdf 12 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf 13 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf 14 * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf 15 * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387-4-7388-4.pdf 16 */ 17 18 #include <linux/align.h> 19 #include <linux/bitfield.h> 20 #include <linux/bitops.h> 21 #include <linux/cleanup.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/slab.h> 29 #include <linux/spi/spi.h> 30 31 #include <linux/iio/buffer.h> 32 #include <linux/iio/iio.h> 33 #include <linux/iio/trigger_consumer.h> 34 #include <linux/iio/triggered_buffer.h> 35 36 #define MAX_NUM_CHANNELS 8 37 /* 2.5V internal reference voltage */ 38 #define AD7380_INTERNAL_REF_MV 2500 39 40 /* reading and writing registers is more reliable at lower than max speed */ 41 #define AD7380_REG_WR_SPEED_HZ 10000000 42 43 #define AD7380_REG_WR BIT(15) 44 #define AD7380_REG_REGADDR GENMASK(14, 12) 45 #define AD7380_REG_DATA GENMASK(11, 0) 46 47 #define AD7380_REG_ADDR_NOP 0x0 48 #define AD7380_REG_ADDR_CONFIG1 0x1 49 #define AD7380_REG_ADDR_CONFIG2 0x2 50 #define AD7380_REG_ADDR_ALERT 0x3 51 #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 52 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 53 54 #define AD7380_CONFIG1_CH BIT(11) 55 #define AD7380_CONFIG1_SEQ BIT(10) 56 #define AD7380_CONFIG1_OS_MODE BIT(9) 57 #define AD7380_CONFIG1_OSR GENMASK(8, 6) 58 #define AD7380_CONFIG1_CRC_W BIT(5) 59 #define AD7380_CONFIG1_CRC_R BIT(4) 60 #define AD7380_CONFIG1_ALERTEN BIT(3) 61 #define AD7380_CONFIG1_RES BIT(2) 62 #define AD7380_CONFIG1_REFSEL BIT(1) 63 #define AD7380_CONFIG1_PMODE BIT(0) 64 65 #define AD7380_CONFIG2_SDO2 GENMASK(9, 8) 66 #define AD7380_CONFIG2_SDO BIT(8) 67 #define AD7380_CONFIG2_RESET GENMASK(7, 0) 68 69 #define AD7380_CONFIG2_RESET_SOFT 0x3C 70 #define AD7380_CONFIG2_RESET_HARD 0xFF 71 72 #define AD7380_ALERT_LOW_TH GENMASK(11, 0) 73 #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) 74 75 #define T_CONVERT_NS 190 /* conversion time */ 76 #define T_CONVERT_0_NS 10 /* 1st conversion start time (oversampling) */ 77 #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ 78 79 struct ad7380_timing_specs { 80 const unsigned int t_csh_ns; /* CS minimum high time */ 81 }; 82 83 struct ad7380_chip_info { 84 const char *name; 85 const struct iio_chan_spec *channels; 86 unsigned int num_channels; 87 unsigned int num_simult_channels; 88 bool has_mux; 89 const char * const *vcm_supplies; 90 unsigned int num_vcm_supplies; 91 const unsigned long *available_scan_masks; 92 const struct ad7380_timing_specs *timing_specs; 93 }; 94 95 enum { 96 AD7380_SCAN_TYPE_NORMAL, 97 AD7380_SCAN_TYPE_RESOLUTION_BOOST, 98 }; 99 100 /* Extended scan types for 12-bit unsigned chips. */ 101 static const struct iio_scan_type ad7380_scan_type_12_u[] = { 102 [AD7380_SCAN_TYPE_NORMAL] = { 103 .sign = 'u', 104 .realbits = 12, 105 .storagebits = 16, 106 .endianness = IIO_CPU, 107 }, 108 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 109 .sign = 'u', 110 .realbits = 14, 111 .storagebits = 16, 112 .endianness = IIO_CPU, 113 }, 114 }; 115 116 /* Extended scan types for 14-bit signed chips. */ 117 static const struct iio_scan_type ad7380_scan_type_14_s[] = { 118 [AD7380_SCAN_TYPE_NORMAL] = { 119 .sign = 's', 120 .realbits = 14, 121 .storagebits = 16, 122 .endianness = IIO_CPU, 123 }, 124 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 125 .sign = 's', 126 .realbits = 16, 127 .storagebits = 16, 128 .endianness = IIO_CPU, 129 }, 130 }; 131 132 /* Extended scan types for 14-bit unsigned chips. */ 133 static const struct iio_scan_type ad7380_scan_type_14_u[] = { 134 [AD7380_SCAN_TYPE_NORMAL] = { 135 .sign = 'u', 136 .realbits = 14, 137 .storagebits = 16, 138 .endianness = IIO_CPU, 139 }, 140 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 141 .sign = 'u', 142 .realbits = 16, 143 .storagebits = 16, 144 .endianness = IIO_CPU, 145 }, 146 }; 147 148 /* Extended scan types for 16-bit signed_chips. */ 149 static const struct iio_scan_type ad7380_scan_type_16_s[] = { 150 [AD7380_SCAN_TYPE_NORMAL] = { 151 .sign = 's', 152 .realbits = 16, 153 .storagebits = 16, 154 .endianness = IIO_CPU, 155 }, 156 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 157 .sign = 's', 158 .realbits = 18, 159 .storagebits = 32, 160 .endianness = IIO_CPU, 161 }, 162 }; 163 164 /* Extended scan types for 16-bit unsigned chips. */ 165 static const struct iio_scan_type ad7380_scan_type_16_u[] = { 166 [AD7380_SCAN_TYPE_NORMAL] = { 167 .sign = 'u', 168 .realbits = 16, 169 .storagebits = 16, 170 .endianness = IIO_CPU, 171 }, 172 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 173 .sign = 'u', 174 .realbits = 18, 175 .storagebits = 32, 176 .endianness = IIO_CPU, 177 }, 178 }; 179 180 #define AD7380_CHANNEL(index, bits, diff, sign) { \ 181 .type = IIO_VOLTAGE, \ 182 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 183 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 184 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 185 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 186 .info_mask_shared_by_type_available = \ 187 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 188 .indexed = 1, \ 189 .differential = (diff), \ 190 .channel = (diff) ? (2 * (index)) : (index), \ 191 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 192 .scan_index = (index), \ 193 .has_ext_scan_type = 1, \ 194 .ext_scan_type = ad7380_scan_type_##bits##_##sign, \ 195 .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ 196 } 197 198 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ 199 static const struct iio_chan_spec name[] = { \ 200 AD7380_CHANNEL(0, bits, diff, sign), \ 201 AD7380_CHANNEL(1, bits, diff, sign), \ 202 IIO_CHAN_SOFT_TIMESTAMP(2), \ 203 } 204 205 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \ 206 static const struct iio_chan_spec name[] = { \ 207 AD7380_CHANNEL(0, bits, diff, sign), \ 208 AD7380_CHANNEL(1, bits, diff, sign), \ 209 AD7380_CHANNEL(2, bits, diff, sign), \ 210 AD7380_CHANNEL(3, bits, diff, sign), \ 211 IIO_CHAN_SOFT_TIMESTAMP(4), \ 212 } 213 214 #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ 215 static const struct iio_chan_spec name[] = { \ 216 AD7380_CHANNEL(0, bits, diff, sign), \ 217 AD7380_CHANNEL(1, bits, diff, sign), \ 218 AD7380_CHANNEL(2, bits, diff, sign), \ 219 AD7380_CHANNEL(3, bits, diff, sign), \ 220 AD7380_CHANNEL(4, bits, diff, sign), \ 221 AD7380_CHANNEL(5, bits, diff, sign), \ 222 AD7380_CHANNEL(6, bits, diff, sign), \ 223 AD7380_CHANNEL(7, bits, diff, sign), \ 224 IIO_CHAN_SOFT_TIMESTAMP(8), \ 225 } 226 227 /* fully differential */ 228 DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); 229 DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); 230 DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); 231 DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); 232 /* pseudo differential */ 233 DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); 234 DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); 235 DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s); 236 DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s); 237 238 /* Single ended */ 239 DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u); 240 DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u); 241 DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u); 242 DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u); 243 DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u); 244 DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u); 245 246 static const char * const ad7380_2_channel_vcm_supplies[] = { 247 "aina", "ainb", 248 }; 249 250 static const char * const ad7380_4_channel_vcm_supplies[] = { 251 "aina", "ainb", "ainc", "aind", 252 }; 253 254 /* Since this is simultaneous sampling, we don't allow individual channels. */ 255 static const unsigned long ad7380_2_channel_scan_masks[] = { 256 GENMASK(1, 0), 257 0 258 }; 259 260 static const unsigned long ad7380_4_channel_scan_masks[] = { 261 GENMASK(3, 0), 262 0 263 }; 264 265 /* 266 * Single ended parts have a 2:1 multiplexer in front of each ADC. 267 * 268 * From an IIO point of view, all inputs are exported, i.e ad7386/7/8 269 * export 4 channels and ad7386-4/7-4/8-4 export 8 channels. 270 * 271 * Inputs AinX0 of multiplexers correspond to the first half of IIO channels 272 * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or 273 * 4-7). Example for AD7386/7/8 (2 channels parts): 274 * 275 * IIO | AD7386/7/8 276 * | +---------------------------- 277 * | | _____ ______ 278 * | | | | | | 279 * voltage0 | AinA0 --|--->| | | | 280 * | | | mux |----->| ADCA |--- 281 * voltage2 | AinA1 --|--->| | | | 282 * | | |_____| |_____ | 283 * | | _____ ______ 284 * | | | | | | 285 * voltage1 | AinB0 --|--->| | | | 286 * | | | mux |----->| ADCB |--- 287 * voltage3 | AinB1 --|--->| | | | 288 * | | |_____| |______| 289 * | | 290 * | +---------------------------- 291 * 292 * Since this is simultaneous sampling for AinX0 OR AinX1 we have two separate 293 * scan masks. 294 * When sequencer mode is enabled, chip automatically cycles through 295 * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all 296 * channels, at the cost of an extra read, thus dividing the maximum rate by 297 * two. 298 */ 299 enum { 300 AD7380_SCAN_MASK_CH_0, 301 AD7380_SCAN_MASK_CH_1, 302 AD7380_SCAN_MASK_SEQ, 303 }; 304 305 static const unsigned long ad7380_2x2_channel_scan_masks[] = { 306 [AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0), 307 [AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2), 308 [AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0), 309 0 310 }; 311 312 static const unsigned long ad7380_2x4_channel_scan_masks[] = { 313 [AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0), 314 [AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4), 315 [AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0), 316 0 317 }; 318 319 static const struct ad7380_timing_specs ad7380_timing = { 320 .t_csh_ns = 10, 321 }; 322 323 static const struct ad7380_timing_specs ad7380_4_timing = { 324 .t_csh_ns = 20, 325 }; 326 327 /* 328 * Available oversampling ratios. The indices correspond with the bit value 329 * expected by the chip. The available ratios depend on the averaging mode, 330 * only normal averaging is supported for now. 331 */ 332 static const int ad7380_oversampling_ratios[] = { 333 1, 2, 4, 8, 16, 32, 334 }; 335 336 static const struct ad7380_chip_info ad7380_chip_info = { 337 .name = "ad7380", 338 .channels = ad7380_channels, 339 .num_channels = ARRAY_SIZE(ad7380_channels), 340 .num_simult_channels = 2, 341 .available_scan_masks = ad7380_2_channel_scan_masks, 342 .timing_specs = &ad7380_timing, 343 }; 344 345 static const struct ad7380_chip_info ad7381_chip_info = { 346 .name = "ad7381", 347 .channels = ad7381_channels, 348 .num_channels = ARRAY_SIZE(ad7381_channels), 349 .num_simult_channels = 2, 350 .available_scan_masks = ad7380_2_channel_scan_masks, 351 .timing_specs = &ad7380_timing, 352 }; 353 354 static const struct ad7380_chip_info ad7383_chip_info = { 355 .name = "ad7383", 356 .channels = ad7383_channels, 357 .num_channels = ARRAY_SIZE(ad7383_channels), 358 .num_simult_channels = 2, 359 .vcm_supplies = ad7380_2_channel_vcm_supplies, 360 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 361 .available_scan_masks = ad7380_2_channel_scan_masks, 362 .timing_specs = &ad7380_timing, 363 }; 364 365 static const struct ad7380_chip_info ad7384_chip_info = { 366 .name = "ad7384", 367 .channels = ad7384_channels, 368 .num_channels = ARRAY_SIZE(ad7384_channels), 369 .num_simult_channels = 2, 370 .vcm_supplies = ad7380_2_channel_vcm_supplies, 371 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 372 .available_scan_masks = ad7380_2_channel_scan_masks, 373 .timing_specs = &ad7380_timing, 374 }; 375 376 static const struct ad7380_chip_info ad7386_chip_info = { 377 .name = "ad7386", 378 .channels = ad7386_channels, 379 .num_channels = ARRAY_SIZE(ad7386_channels), 380 .num_simult_channels = 2, 381 .has_mux = true, 382 .available_scan_masks = ad7380_2x2_channel_scan_masks, 383 .timing_specs = &ad7380_timing, 384 }; 385 386 static const struct ad7380_chip_info ad7387_chip_info = { 387 .name = "ad7387", 388 .channels = ad7387_channels, 389 .num_channels = ARRAY_SIZE(ad7387_channels), 390 .num_simult_channels = 2, 391 .has_mux = true, 392 .available_scan_masks = ad7380_2x2_channel_scan_masks, 393 .timing_specs = &ad7380_timing, 394 }; 395 396 static const struct ad7380_chip_info ad7388_chip_info = { 397 .name = "ad7388", 398 .channels = ad7388_channels, 399 .num_channels = ARRAY_SIZE(ad7388_channels), 400 .num_simult_channels = 2, 401 .has_mux = true, 402 .available_scan_masks = ad7380_2x2_channel_scan_masks, 403 .timing_specs = &ad7380_timing, 404 }; 405 406 static const struct ad7380_chip_info ad7380_4_chip_info = { 407 .name = "ad7380-4", 408 .channels = ad7380_4_channels, 409 .num_channels = ARRAY_SIZE(ad7380_4_channels), 410 .num_simult_channels = 4, 411 .available_scan_masks = ad7380_4_channel_scan_masks, 412 .timing_specs = &ad7380_4_timing, 413 }; 414 415 static const struct ad7380_chip_info ad7381_4_chip_info = { 416 .name = "ad7381-4", 417 .channels = ad7381_4_channels, 418 .num_channels = ARRAY_SIZE(ad7381_4_channels), 419 .num_simult_channels = 4, 420 .available_scan_masks = ad7380_4_channel_scan_masks, 421 .timing_specs = &ad7380_4_timing, 422 }; 423 424 static const struct ad7380_chip_info ad7383_4_chip_info = { 425 .name = "ad7383-4", 426 .channels = ad7383_4_channels, 427 .num_channels = ARRAY_SIZE(ad7383_4_channels), 428 .num_simult_channels = 4, 429 .vcm_supplies = ad7380_4_channel_vcm_supplies, 430 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 431 .available_scan_masks = ad7380_4_channel_scan_masks, 432 .timing_specs = &ad7380_4_timing, 433 }; 434 435 static const struct ad7380_chip_info ad7384_4_chip_info = { 436 .name = "ad7384-4", 437 .channels = ad7384_4_channels, 438 .num_channels = ARRAY_SIZE(ad7384_4_channels), 439 .num_simult_channels = 4, 440 .vcm_supplies = ad7380_4_channel_vcm_supplies, 441 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 442 .available_scan_masks = ad7380_4_channel_scan_masks, 443 .timing_specs = &ad7380_4_timing, 444 }; 445 446 static const struct ad7380_chip_info ad7386_4_chip_info = { 447 .name = "ad7386-4", 448 .channels = ad7386_4_channels, 449 .num_channels = ARRAY_SIZE(ad7386_4_channels), 450 .num_simult_channels = 4, 451 .has_mux = true, 452 .available_scan_masks = ad7380_2x4_channel_scan_masks, 453 .timing_specs = &ad7380_4_timing, 454 }; 455 456 static const struct ad7380_chip_info ad7387_4_chip_info = { 457 .name = "ad7387-4", 458 .channels = ad7387_4_channels, 459 .num_channels = ARRAY_SIZE(ad7387_4_channels), 460 .num_simult_channels = 4, 461 .has_mux = true, 462 .available_scan_masks = ad7380_2x4_channel_scan_masks, 463 .timing_specs = &ad7380_4_timing, 464 }; 465 466 static const struct ad7380_chip_info ad7388_4_chip_info = { 467 .name = "ad7388-4", 468 .channels = ad7388_4_channels, 469 .num_channels = ARRAY_SIZE(ad7388_4_channels), 470 .num_simult_channels = 4, 471 .has_mux = true, 472 .available_scan_masks = ad7380_2x4_channel_scan_masks, 473 .timing_specs = &ad7380_4_timing, 474 }; 475 476 struct ad7380_state { 477 const struct ad7380_chip_info *chip_info; 478 struct spi_device *spi; 479 struct regmap *regmap; 480 unsigned int oversampling_ratio; 481 bool resolution_boost_enabled; 482 unsigned int ch; 483 bool seq; 484 unsigned int vref_mv; 485 unsigned int vcm_mv[MAX_NUM_CHANNELS]; 486 /* xfers, message an buffer for reading sample data */ 487 struct spi_transfer normal_xfer[2]; 488 struct spi_message normal_msg; 489 struct spi_transfer seq_xfer[4]; 490 struct spi_message seq_msg; 491 /* 492 * DMA (thus cache coherency maintenance) requires the transfer buffers 493 * to live in their own cache lines. 494 * 495 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and 496 * one 64-bit aligned 64-bit timestamp. 497 */ 498 u8 scan_data[ALIGN(MAX_NUM_CHANNELS * sizeof(u32), sizeof(s64)) 499 + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); 500 /* buffers for reading/writing registers */ 501 u16 tx; 502 u16 rx; 503 }; 504 505 static int ad7380_regmap_reg_write(void *context, unsigned int reg, 506 unsigned int val) 507 { 508 struct ad7380_state *st = context; 509 struct spi_transfer xfer = { 510 .speed_hz = AD7380_REG_WR_SPEED_HZ, 511 .bits_per_word = 16, 512 .len = 2, 513 .tx_buf = &st->tx, 514 }; 515 516 st->tx = FIELD_PREP(AD7380_REG_WR, 1) | 517 FIELD_PREP(AD7380_REG_REGADDR, reg) | 518 FIELD_PREP(AD7380_REG_DATA, val); 519 520 return spi_sync_transfer(st->spi, &xfer, 1); 521 } 522 523 static int ad7380_regmap_reg_read(void *context, unsigned int reg, 524 unsigned int *val) 525 { 526 struct ad7380_state *st = context; 527 struct spi_transfer xfers[] = { 528 { 529 .speed_hz = AD7380_REG_WR_SPEED_HZ, 530 .bits_per_word = 16, 531 .len = 2, 532 .tx_buf = &st->tx, 533 .cs_change = 1, 534 .cs_change_delay = { 535 .value = st->chip_info->timing_specs->t_csh_ns, 536 .unit = SPI_DELAY_UNIT_NSECS, 537 }, 538 }, { 539 .speed_hz = AD7380_REG_WR_SPEED_HZ, 540 .bits_per_word = 16, 541 .len = 2, 542 .rx_buf = &st->rx, 543 }, 544 }; 545 int ret; 546 547 st->tx = FIELD_PREP(AD7380_REG_WR, 0) | 548 FIELD_PREP(AD7380_REG_REGADDR, reg) | 549 FIELD_PREP(AD7380_REG_DATA, 0); 550 551 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 552 if (ret < 0) 553 return ret; 554 555 *val = FIELD_GET(AD7380_REG_DATA, st->rx); 556 557 return 0; 558 } 559 560 static const struct regmap_config ad7380_regmap_config = { 561 .reg_bits = 3, 562 .val_bits = 12, 563 .reg_read = ad7380_regmap_reg_read, 564 .reg_write = ad7380_regmap_reg_write, 565 .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH, 566 .can_sleep = true, 567 }; 568 569 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, 570 u32 writeval, u32 *readval) 571 { 572 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 573 struct ad7380_state *st = iio_priv(indio_dev); 574 575 if (readval) 576 return regmap_read(st->regmap, reg, readval); 577 else 578 return regmap_write(st->regmap, reg, writeval); 579 } 580 unreachable(); 581 } 582 583 /* 584 * When switching channel, the ADC require an additional settling time. 585 * According to the datasheet, data is value on the third CS low. We already 586 * have an extra toggle before each read (either direct reads or buffered reads) 587 * to sample correct data, so we just add a single CS toggle at the end of the 588 * register write. 589 */ 590 static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch) 591 { 592 struct spi_transfer xfer = { 593 .delay = { 594 .value = T_CONVERT_NS, 595 .unit = SPI_DELAY_UNIT_NSECS, 596 } 597 }; 598 int ret; 599 600 if (st->ch == ch) 601 return 0; 602 603 ret = regmap_update_bits(st->regmap, 604 AD7380_REG_ADDR_CONFIG1, 605 AD7380_CONFIG1_CH, 606 FIELD_PREP(AD7380_CONFIG1_CH, ch)); 607 608 if (ret) 609 return ret; 610 611 st->ch = ch; 612 613 if (st->oversampling_ratio > 1) 614 xfer.delay.value = T_CONVERT_0_NS + 615 T_CONVERT_X_NS * (st->oversampling_ratio - 1); 616 617 return spi_sync_transfer(st->spi, &xfer, 1); 618 } 619 620 /** 621 * ad7380_update_xfers - update the SPI transfers base on the current scan type 622 * @st: device instance specific state 623 * @scan_type: current scan type 624 */ 625 static void ad7380_update_xfers(struct ad7380_state *st, 626 const struct iio_scan_type *scan_type) 627 { 628 struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer; 629 unsigned int t_convert = T_CONVERT_NS; 630 631 /* 632 * In the case of oversampling, conversion time is higher than in normal 633 * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use 634 * the maximum value for simplicity for now. 635 */ 636 if (st->oversampling_ratio > 1) 637 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS * 638 (st->oversampling_ratio - 1); 639 640 if (st->seq) { 641 xfer[0].delay.value = xfer[1].delay.value = t_convert; 642 xfer[0].delay.unit = xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS; 643 xfer[2].bits_per_word = xfer[3].bits_per_word = 644 scan_type->realbits; 645 xfer[2].len = xfer[3].len = 646 BITS_TO_BYTES(scan_type->storagebits) * 647 st->chip_info->num_simult_channels; 648 xfer[3].rx_buf = xfer[2].rx_buf + xfer[2].len; 649 /* Additional delay required here when oversampling is enabled */ 650 if (st->oversampling_ratio > 1) 651 xfer[2].delay.value = t_convert; 652 else 653 xfer[2].delay.value = 0; 654 xfer[2].delay.unit = SPI_DELAY_UNIT_NSECS; 655 } else { 656 xfer[0].delay.value = t_convert; 657 xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS; 658 xfer[1].bits_per_word = scan_type->realbits; 659 xfer[1].len = BITS_TO_BYTES(scan_type->storagebits) * 660 st->chip_info->num_simult_channels; 661 } 662 } 663 664 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) 665 { 666 struct ad7380_state *st = iio_priv(indio_dev); 667 const struct iio_scan_type *scan_type; 668 struct spi_message *msg = &st->normal_msg; 669 670 /* 671 * Currently, we always read all channels at the same time. The scan_type 672 * is the same for all channels, so we just pass the first channel. 673 */ 674 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 675 if (IS_ERR(scan_type)) 676 return PTR_ERR(scan_type); 677 678 if (st->chip_info->has_mux) { 679 unsigned int index; 680 int ret; 681 682 /* 683 * Depending on the requested scan_mask and current state, 684 * we need to either change CH bit, or enable sequencer mode 685 * to sample correct data. 686 * Sequencer mode is enabled if active mask corresponds to all 687 * IIO channels enabled. Otherwise, CH bit is set. 688 */ 689 ret = iio_active_scan_mask_index(indio_dev); 690 if (ret < 0) 691 return ret; 692 693 index = ret; 694 if (index == AD7380_SCAN_MASK_SEQ) { 695 ret = regmap_update_bits(st->regmap, 696 AD7380_REG_ADDR_CONFIG1, 697 AD7380_CONFIG1_SEQ, 698 FIELD_PREP(AD7380_CONFIG1_SEQ, 1)); 699 if (ret) 700 return ret; 701 msg = &st->seq_msg; 702 st->seq = true; 703 } else { 704 ret = ad7380_set_ch(st, index); 705 if (ret) 706 return ret; 707 } 708 709 } 710 711 ad7380_update_xfers(st, scan_type); 712 713 return spi_optimize_message(st->spi, msg); 714 } 715 716 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev) 717 { 718 struct ad7380_state *st = iio_priv(indio_dev); 719 struct spi_message *msg = &st->normal_msg; 720 int ret; 721 722 if (st->seq) { 723 ret = regmap_update_bits(st->regmap, 724 AD7380_REG_ADDR_CONFIG1, 725 AD7380_CONFIG1_SEQ, 726 FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); 727 if (ret) 728 return ret; 729 730 msg = &st->seq_msg; 731 st->seq = false; 732 } 733 734 spi_unoptimize_message(msg); 735 736 return 0; 737 } 738 739 static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = { 740 .preenable = ad7380_triggered_buffer_preenable, 741 .postdisable = ad7380_triggered_buffer_postdisable, 742 }; 743 744 static irqreturn_t ad7380_trigger_handler(int irq, void *p) 745 { 746 struct iio_poll_func *pf = p; 747 struct iio_dev *indio_dev = pf->indio_dev; 748 struct ad7380_state *st = iio_priv(indio_dev); 749 struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg; 750 int ret; 751 752 ret = spi_sync(st->spi, msg); 753 if (ret) 754 goto out; 755 756 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data, 757 pf->timestamp); 758 759 out: 760 iio_trigger_notify_done(indio_dev->trig); 761 762 return IRQ_HANDLED; 763 } 764 765 static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index, 766 const struct iio_scan_type *scan_type, int *val) 767 { 768 unsigned int index = scan_index; 769 int ret; 770 771 if (st->chip_info->has_mux) { 772 unsigned int ch = 0; 773 774 if (index >= st->chip_info->num_simult_channels) { 775 index -= st->chip_info->num_simult_channels; 776 ch = 1; 777 } 778 779 ret = ad7380_set_ch(st, ch); 780 if (ret) 781 return ret; 782 } 783 784 ad7380_update_xfers(st, scan_type); 785 786 ret = spi_sync(st->spi, &st->normal_msg); 787 if (ret < 0) 788 return ret; 789 790 if (scan_type->storagebits > 16) { 791 if (scan_type->sign == 's') 792 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index), 793 scan_type->realbits - 1); 794 else 795 *val = *(u32 *)(st->scan_data + 4 * index) & 796 GENMASK(scan_type->realbits - 1, 0); 797 } else { 798 if (scan_type->sign == 's') 799 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index), 800 scan_type->realbits - 1); 801 else 802 *val = *(u16 *)(st->scan_data + 2 * index) & 803 GENMASK(scan_type->realbits - 1, 0); 804 } 805 806 return IIO_VAL_INT; 807 } 808 809 static int ad7380_read_raw(struct iio_dev *indio_dev, 810 struct iio_chan_spec const *chan, 811 int *val, int *val2, long info) 812 { 813 struct ad7380_state *st = iio_priv(indio_dev); 814 const struct iio_scan_type *scan_type; 815 816 scan_type = iio_get_current_scan_type(indio_dev, chan); 817 818 if (IS_ERR(scan_type)) 819 return PTR_ERR(scan_type); 820 821 switch (info) { 822 case IIO_CHAN_INFO_RAW: 823 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 824 return ad7380_read_direct(st, chan->scan_index, 825 scan_type, val); 826 } 827 unreachable(); 828 case IIO_CHAN_INFO_SCALE: 829 /* 830 * According to the datasheet, the LSB size is: 831 * * (2 × VREF) / 2^N, for differential chips 832 * * VREF / 2^N, for pseudo-differential chips 833 * where N is the ADC resolution (i.e realbits) 834 */ 835 *val = st->vref_mv; 836 *val2 = scan_type->realbits - chan->differential; 837 838 return IIO_VAL_FRACTIONAL_LOG2; 839 case IIO_CHAN_INFO_OFFSET: 840 /* 841 * According to IIO ABI, offset is applied before scale, 842 * so offset is: vcm_mv / scale 843 */ 844 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits) 845 / st->vref_mv; 846 847 return IIO_VAL_INT; 848 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 849 *val = st->oversampling_ratio; 850 851 return IIO_VAL_INT; 852 default: 853 return -EINVAL; 854 } 855 } 856 857 static int ad7380_read_avail(struct iio_dev *indio_dev, 858 struct iio_chan_spec const *chan, 859 const int **vals, int *type, int *length, 860 long mask) 861 { 862 switch (mask) { 863 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 864 *vals = ad7380_oversampling_ratios; 865 *length = ARRAY_SIZE(ad7380_oversampling_ratios); 866 *type = IIO_VAL_INT; 867 868 return IIO_AVAIL_LIST; 869 default: 870 return -EINVAL; 871 } 872 } 873 874 /** 875 * ad7380_osr_to_regval - convert ratio to OSR register value 876 * @ratio: ratio to check 877 * 878 * Check if ratio is present in the list of available ratios and return the 879 * corresponding value that needs to be written to the register to select that 880 * ratio. 881 * 882 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match 883 */ 884 static int ad7380_osr_to_regval(int ratio) 885 { 886 int i; 887 888 for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) { 889 if (ratio == ad7380_oversampling_ratios[i]) 890 return i; 891 } 892 893 return -EINVAL; 894 } 895 896 static int ad7380_write_raw(struct iio_dev *indio_dev, 897 struct iio_chan_spec const *chan, int val, 898 int val2, long mask) 899 { 900 struct ad7380_state *st = iio_priv(indio_dev); 901 int ret, osr, boost; 902 903 switch (mask) { 904 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 905 osr = ad7380_osr_to_regval(val); 906 if (osr < 0) 907 return osr; 908 909 /* always enable resolution boost when oversampling is enabled */ 910 boost = osr > 0 ? 1 : 0; 911 912 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 913 ret = regmap_update_bits(st->regmap, 914 AD7380_REG_ADDR_CONFIG1, 915 AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES, 916 FIELD_PREP(AD7380_CONFIG1_OSR, osr) | 917 FIELD_PREP(AD7380_CONFIG1_RES, boost)); 918 919 if (ret) 920 return ret; 921 922 st->oversampling_ratio = val; 923 st->resolution_boost_enabled = boost; 924 925 /* 926 * Perform a soft reset. This will flush the oversampling 927 * block and FIFO but will maintain the content of the 928 * configurable registers. 929 */ 930 return regmap_update_bits(st->regmap, 931 AD7380_REG_ADDR_CONFIG2, 932 AD7380_CONFIG2_RESET, 933 FIELD_PREP(AD7380_CONFIG2_RESET, 934 AD7380_CONFIG2_RESET_SOFT)); 935 } 936 unreachable(); 937 default: 938 return -EINVAL; 939 } 940 } 941 942 static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev, 943 const struct iio_chan_spec *chan) 944 { 945 struct ad7380_state *st = iio_priv(indio_dev); 946 947 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST 948 : AD7380_SCAN_TYPE_NORMAL; 949 } 950 951 static const struct iio_info ad7380_info = { 952 .read_raw = &ad7380_read_raw, 953 .read_avail = &ad7380_read_avail, 954 .write_raw = &ad7380_write_raw, 955 .get_current_scan_type = &ad7380_get_current_scan_type, 956 .debugfs_reg_access = &ad7380_debugfs_reg_access, 957 }; 958 959 static int ad7380_init(struct ad7380_state *st, struct regulator *vref) 960 { 961 int ret; 962 963 /* perform hard reset */ 964 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 965 AD7380_CONFIG2_RESET, 966 FIELD_PREP(AD7380_CONFIG2_RESET, 967 AD7380_CONFIG2_RESET_HARD)); 968 if (ret < 0) 969 return ret; 970 971 /* select internal or external reference voltage */ 972 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 973 AD7380_CONFIG1_REFSEL, 974 FIELD_PREP(AD7380_CONFIG1_REFSEL, 975 vref ? 1 : 0)); 976 if (ret < 0) 977 return ret; 978 979 /* This is the default value after reset. */ 980 st->oversampling_ratio = 1; 981 st->ch = 0; 982 st->seq = false; 983 984 /* SPI 1-wire mode */ 985 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 986 AD7380_CONFIG2_SDO, 987 FIELD_PREP(AD7380_CONFIG2_SDO, 1)); 988 } 989 990 static void ad7380_regulator_disable(void *p) 991 { 992 regulator_disable(p); 993 } 994 995 static int ad7380_probe(struct spi_device *spi) 996 { 997 struct iio_dev *indio_dev; 998 struct ad7380_state *st; 999 struct regulator *vref; 1000 int ret, i; 1001 1002 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1003 if (!indio_dev) 1004 return -ENOMEM; 1005 1006 st = iio_priv(indio_dev); 1007 st->spi = spi; 1008 st->chip_info = spi_get_device_match_data(spi); 1009 if (!st->chip_info) 1010 return dev_err_probe(&spi->dev, -EINVAL, "missing match data\n"); 1011 1012 vref = devm_regulator_get_optional(&spi->dev, "refio"); 1013 if (IS_ERR(vref)) { 1014 if (PTR_ERR(vref) != -ENODEV) 1015 return dev_err_probe(&spi->dev, PTR_ERR(vref), 1016 "Failed to get refio regulator\n"); 1017 1018 vref = NULL; 1019 } 1020 1021 /* 1022 * If there is no REFIO supply, then it means that we are using 1023 * the internal 2.5V reference, otherwise REFIO is reference voltage. 1024 */ 1025 if (vref) { 1026 ret = regulator_enable(vref); 1027 if (ret) 1028 return ret; 1029 1030 ret = devm_add_action_or_reset(&spi->dev, 1031 ad7380_regulator_disable, vref); 1032 if (ret) 1033 return ret; 1034 1035 ret = regulator_get_voltage(vref); 1036 if (ret < 0) 1037 return ret; 1038 1039 st->vref_mv = ret / 1000; 1040 } else { 1041 st->vref_mv = AD7380_INTERNAL_REF_MV; 1042 } 1043 1044 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) 1045 return dev_err_probe(&spi->dev, -EINVAL, 1046 "invalid number of VCM supplies\n"); 1047 1048 /* 1049 * pseudo-differential chips have common mode supplies for the negative 1050 * input pin. 1051 */ 1052 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) { 1053 struct regulator *vcm; 1054 1055 vcm = devm_regulator_get(&spi->dev, 1056 st->chip_info->vcm_supplies[i]); 1057 if (IS_ERR(vcm)) 1058 return dev_err_probe(&spi->dev, PTR_ERR(vcm), 1059 "Failed to get %s regulator\n", 1060 st->chip_info->vcm_supplies[i]); 1061 1062 ret = regulator_enable(vcm); 1063 if (ret) 1064 return ret; 1065 1066 ret = devm_add_action_or_reset(&spi->dev, 1067 ad7380_regulator_disable, vcm); 1068 if (ret) 1069 return ret; 1070 1071 ret = regulator_get_voltage(vcm); 1072 if (ret < 0) 1073 return ret; 1074 1075 st->vcm_mv[i] = ret / 1000; 1076 } 1077 1078 st->regmap = devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_config); 1079 if (IS_ERR(st->regmap)) 1080 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), 1081 "failed to allocate register map\n"); 1082 1083 /* 1084 * Setting up xfer structures for both normal and sequence mode. These 1085 * struct are used for both direct read and triggered buffer. Additional 1086 * fields will be set up in ad7380_update_xfers() based on the current 1087 * state of the driver at the time of the read. 1088 */ 1089 1090 /* 1091 * In normal mode a read is composed of two steps: 1092 * - first, toggle CS (no data xfer) to trigger a conversion 1093 * - then, read data 1094 */ 1095 st->normal_xfer[0].cs_change = 1; 1096 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 1097 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 1098 st->normal_xfer[1].rx_buf = st->scan_data; 1099 1100 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, 1101 ARRAY_SIZE(st->normal_xfer)); 1102 /* 1103 * In sequencer mode a read is composed of four steps: 1104 * - CS toggle (no data xfer) to get the right point in the sequence 1105 * - CS toggle (no data xfer) to trigger a conversion of AinX0 and 1106 * acquisition of AinX1 1107 * - 2 data reads, to read AinX0 and AinX1 1108 */ 1109 st->seq_xfer[0].cs_change = 1; 1110 st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 1111 st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 1112 st->seq_xfer[1].cs_change = 1; 1113 st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 1114 st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 1115 1116 st->seq_xfer[2].rx_buf = st->scan_data; 1117 st->seq_xfer[2].cs_change = 1; 1118 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 1119 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 1120 1121 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, 1122 ARRAY_SIZE(st->seq_xfer)); 1123 1124 indio_dev->channels = st->chip_info->channels; 1125 indio_dev->num_channels = st->chip_info->num_channels; 1126 indio_dev->name = st->chip_info->name; 1127 indio_dev->info = &ad7380_info; 1128 indio_dev->modes = INDIO_DIRECT_MODE; 1129 indio_dev->available_scan_masks = st->chip_info->available_scan_masks; 1130 1131 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 1132 iio_pollfunc_store_time, 1133 ad7380_trigger_handler, 1134 &ad7380_buffer_setup_ops); 1135 if (ret) 1136 return ret; 1137 1138 ret = ad7380_init(st, vref); 1139 if (ret) 1140 return ret; 1141 1142 return devm_iio_device_register(&spi->dev, indio_dev); 1143 } 1144 1145 static const struct of_device_id ad7380_of_match_table[] = { 1146 { .compatible = "adi,ad7380", .data = &ad7380_chip_info }, 1147 { .compatible = "adi,ad7381", .data = &ad7381_chip_info }, 1148 { .compatible = "adi,ad7383", .data = &ad7383_chip_info }, 1149 { .compatible = "adi,ad7384", .data = &ad7384_chip_info }, 1150 { .compatible = "adi,ad7386", .data = &ad7386_chip_info }, 1151 { .compatible = "adi,ad7387", .data = &ad7387_chip_info }, 1152 { .compatible = "adi,ad7388", .data = &ad7388_chip_info }, 1153 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info }, 1154 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info }, 1155 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info }, 1156 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info }, 1157 { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info }, 1158 { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info }, 1159 { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info }, 1160 { } 1161 }; 1162 1163 static const struct spi_device_id ad7380_id_table[] = { 1164 { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, 1165 { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, 1166 { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, 1167 { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, 1168 { "ad7386", (kernel_ulong_t)&ad7386_chip_info }, 1169 { "ad7387", (kernel_ulong_t)&ad7387_chip_info }, 1170 { "ad7388", (kernel_ulong_t)&ad7388_chip_info }, 1171 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, 1172 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, 1173 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, 1174 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, 1175 { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info }, 1176 { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info }, 1177 { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info }, 1178 { } 1179 }; 1180 MODULE_DEVICE_TABLE(spi, ad7380_id_table); 1181 1182 static struct spi_driver ad7380_driver = { 1183 .driver = { 1184 .name = "ad7380", 1185 .of_match_table = ad7380_of_match_table, 1186 }, 1187 .probe = ad7380_probe, 1188 .id_table = ad7380_id_table, 1189 }; 1190 module_spi_driver(ad7380_driver); 1191 1192 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1193 MODULE_DESCRIPTION("Analog Devices AD738x ADC driver"); 1194 MODULE_LICENSE("GPL"); 1195