1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD738x Simultaneous Sampling SAR ADCs 4 * 5 * Copyright 2017 Analog Devices Inc. 6 * Copyright 2024 BayLibre, SAS 7 * 8 * Datasheets of supported parts: 9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf 10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf 11 * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-7388.pdf 12 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf 13 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf 14 * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf 15 * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387-4-7388-4.pdf 16 * ad7389-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7389-4.pdf 17 * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4370-4.pdf 18 * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4380-4.pdf 19 * adaq4381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4381-4.pdf 20 * 21 * HDL ad738x_fmc: https://analogdevicesinc.github.io/hdl/projects/ad738x_fmc/index.html 22 * 23 */ 24 25 #include <linux/align.h> 26 #include <linux/bitfield.h> 27 #include <linux/bitops.h> 28 #include <linux/cleanup.h> 29 #include <linux/device.h> 30 #include <linux/err.h> 31 #include <linux/kernel.h> 32 #include <linux/math.h> 33 #include <linux/module.h> 34 #include <linux/regmap.h> 35 #include <linux/regulator/consumer.h> 36 #include <linux/slab.h> 37 #include <linux/spi/offload/consumer.h> 38 #include <linux/spi/spi.h> 39 #include <linux/units.h> 40 #include <linux/util_macros.h> 41 42 #include <linux/iio/buffer.h> 43 #include <linux/iio/buffer-dmaengine.h> 44 #include <linux/iio/events.h> 45 #include <linux/iio/iio.h> 46 #include <linux/iio/trigger_consumer.h> 47 #include <linux/iio/triggered_buffer.h> 48 49 #define MAX_NUM_CHANNELS 8 50 /* 2.5V internal reference voltage */ 51 #define AD7380_INTERNAL_REF_MV 2500 52 /* 3.3V internal reference voltage for ADAQ */ 53 #define ADAQ4380_INTERNAL_REF_MV 3300 54 55 /* reading and writing registers is more reliable at lower than max speed */ 56 #define AD7380_REG_WR_SPEED_HZ 10000000 57 58 #define AD7380_REG_WR BIT(15) 59 #define AD7380_REG_REGADDR GENMASK(14, 12) 60 #define AD7380_REG_DATA GENMASK(11, 0) 61 62 #define AD7380_REG_ADDR_NOP 0x0 63 #define AD7380_REG_ADDR_CONFIG1 0x1 64 #define AD7380_REG_ADDR_CONFIG2 0x2 65 #define AD7380_REG_ADDR_ALERT 0x3 66 #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 67 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 68 69 #define AD7380_CONFIG1_CH BIT(11) 70 #define AD7380_CONFIG1_SEQ BIT(10) 71 #define AD7380_CONFIG1_OS_MODE BIT(9) 72 #define AD7380_CONFIG1_OSR GENMASK(8, 6) 73 #define AD7380_CONFIG1_CRC_W BIT(5) 74 #define AD7380_CONFIG1_CRC_R BIT(4) 75 #define AD7380_CONFIG1_ALERTEN BIT(3) 76 #define AD7380_CONFIG1_RES BIT(2) 77 #define AD7380_CONFIG1_REFSEL BIT(1) 78 #define AD7380_CONFIG1_PMODE BIT(0) 79 80 #define AD7380_CONFIG2_SDO GENMASK(9, 8) 81 #define AD7380_CONFIG2_RESET GENMASK(7, 0) 82 83 #define AD7380_CONFIG2_RESET_SOFT 0x3C 84 #define AD7380_CONFIG2_RESET_HARD 0xFF 85 86 #define AD7380_ALERT_LOW_TH GENMASK(11, 0) 87 #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) 88 89 #define T_CONVERT_NS 190 /* conversion time */ 90 #define T_CONVERT_0_NS 10 /* 1st conversion start time (oversampling) */ 91 #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ 92 #define T_POWERUP_US 5000 /* Power up */ 93 94 #define AD7380_DEFAULT_GAIN_MILLI 1000 95 96 /* 97 * Using SPI offload, storagebits is always 32, so can't be used to compute struct 98 * spi_transfer.len. Using realbits instead. 99 */ 100 #define AD7380_SPI_BYTES(scan_type) ((scan_type)->realbits > 16 ? 4 : 2) 101 102 struct ad7380_timing_specs { 103 const unsigned int t_csh_ns; /* CS minimum high time */ 104 }; 105 106 struct ad7380_chip_info { 107 const char *name; 108 const struct iio_chan_spec *channels; 109 const struct iio_chan_spec *offload_channels; 110 unsigned int num_channels; 111 unsigned int num_simult_channels; 112 bool has_hardware_gain; 113 bool has_mux; 114 const char * const *supplies; 115 unsigned int num_supplies; 116 bool external_ref_only; 117 bool internal_ref_only; 118 unsigned int internal_ref_mv; 119 const char * const *vcm_supplies; 120 unsigned int num_vcm_supplies; 121 const unsigned long *available_scan_masks; 122 const struct ad7380_timing_specs *timing_specs; 123 u32 max_conversion_rate_hz; 124 }; 125 126 static const struct iio_event_spec ad7380_events[] = { 127 { 128 .type = IIO_EV_TYPE_THRESH, 129 .dir = IIO_EV_DIR_RISING, 130 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE), 131 }, 132 { 133 .type = IIO_EV_TYPE_THRESH, 134 .dir = IIO_EV_DIR_FALLING, 135 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE), 136 }, 137 { 138 .type = IIO_EV_TYPE_THRESH, 139 .dir = IIO_EV_DIR_EITHER, 140 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 141 }, 142 }; 143 144 enum { 145 AD7380_SCAN_TYPE_NORMAL, 146 AD7380_SCAN_TYPE_RESOLUTION_BOOST, 147 }; 148 149 /* Extended scan types for 12-bit unsigned chips. */ 150 static const struct iio_scan_type ad7380_scan_type_12_u[] = { 151 [AD7380_SCAN_TYPE_NORMAL] = { 152 .sign = 'u', 153 .realbits = 12, 154 .storagebits = 16, 155 .endianness = IIO_CPU, 156 }, 157 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 158 .sign = 'u', 159 .realbits = 14, 160 .storagebits = 16, 161 .endianness = IIO_CPU, 162 }, 163 }; 164 165 /* Extended scan types for 14-bit signed chips. */ 166 static const struct iio_scan_type ad7380_scan_type_14_s[] = { 167 [AD7380_SCAN_TYPE_NORMAL] = { 168 .sign = 's', 169 .realbits = 14, 170 .storagebits = 16, 171 .endianness = IIO_CPU, 172 }, 173 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 174 .sign = 's', 175 .realbits = 16, 176 .storagebits = 16, 177 .endianness = IIO_CPU, 178 }, 179 }; 180 181 /* Extended scan types for 14-bit unsigned chips. */ 182 static const struct iio_scan_type ad7380_scan_type_14_u[] = { 183 [AD7380_SCAN_TYPE_NORMAL] = { 184 .sign = 'u', 185 .realbits = 14, 186 .storagebits = 16, 187 .endianness = IIO_CPU, 188 }, 189 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 190 .sign = 'u', 191 .realbits = 16, 192 .storagebits = 16, 193 .endianness = IIO_CPU, 194 }, 195 }; 196 197 /* Extended scan types for 16-bit signed_chips. */ 198 static const struct iio_scan_type ad7380_scan_type_16_s[] = { 199 [AD7380_SCAN_TYPE_NORMAL] = { 200 .sign = 's', 201 .realbits = 16, 202 .storagebits = 16, 203 .endianness = IIO_CPU, 204 }, 205 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 206 .sign = 's', 207 .realbits = 18, 208 .storagebits = 32, 209 .endianness = IIO_CPU, 210 }, 211 }; 212 213 /* Extended scan types for 16-bit unsigned chips. */ 214 static const struct iio_scan_type ad7380_scan_type_16_u[] = { 215 [AD7380_SCAN_TYPE_NORMAL] = { 216 .sign = 'u', 217 .realbits = 16, 218 .storagebits = 16, 219 .endianness = IIO_CPU, 220 }, 221 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 222 .sign = 'u', 223 .realbits = 18, 224 .storagebits = 32, 225 .endianness = IIO_CPU, 226 }, 227 }; 228 229 /* 230 * Defining here scan types for offload mode, since with current available HDL 231 * only a value of 32 for storagebits is supported. 232 */ 233 234 /* Extended scan types for 12-bit unsigned chips, offload support. */ 235 static const struct iio_scan_type ad7380_scan_type_12_u_offload[] = { 236 [AD7380_SCAN_TYPE_NORMAL] = { 237 .sign = 'u', 238 .realbits = 12, 239 .storagebits = 32, 240 .endianness = IIO_CPU, 241 }, 242 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 243 .sign = 'u', 244 .realbits = 14, 245 .storagebits = 32, 246 .endianness = IIO_CPU, 247 }, 248 }; 249 250 /* Extended scan types for 14-bit signed chips, offload support. */ 251 static const struct iio_scan_type ad7380_scan_type_14_s_offload[] = { 252 [AD7380_SCAN_TYPE_NORMAL] = { 253 .sign = 's', 254 .realbits = 14, 255 .storagebits = 32, 256 .endianness = IIO_CPU, 257 }, 258 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 259 .sign = 's', 260 .realbits = 16, 261 .storagebits = 32, 262 .endianness = IIO_CPU, 263 }, 264 }; 265 266 /* Extended scan types for 14-bit unsigned chips, offload support. */ 267 static const struct iio_scan_type ad7380_scan_type_14_u_offload[] = { 268 [AD7380_SCAN_TYPE_NORMAL] = { 269 .sign = 'u', 270 .realbits = 14, 271 .storagebits = 32, 272 .endianness = IIO_CPU, 273 }, 274 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 275 .sign = 'u', 276 .realbits = 16, 277 .storagebits = 32, 278 .endianness = IIO_CPU, 279 }, 280 }; 281 282 /* Extended scan types for 16-bit signed_chips, offload support. */ 283 static const struct iio_scan_type ad7380_scan_type_16_s_offload[] = { 284 [AD7380_SCAN_TYPE_NORMAL] = { 285 .sign = 's', 286 .realbits = 16, 287 .storagebits = 32, 288 .endianness = IIO_CPU, 289 }, 290 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 291 .sign = 's', 292 .realbits = 18, 293 .storagebits = 32, 294 .endianness = IIO_CPU, 295 }, 296 }; 297 298 /* Extended scan types for 16-bit unsigned chips, offload support. */ 299 static const struct iio_scan_type ad7380_scan_type_16_u_offload[] = { 300 [AD7380_SCAN_TYPE_NORMAL] = { 301 .sign = 'u', 302 .realbits = 16, 303 .storagebits = 32, 304 .endianness = IIO_CPU, 305 }, 306 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = { 307 .sign = 'u', 308 .realbits = 18, 309 .storagebits = 32, 310 .endianness = IIO_CPU, 311 }, 312 }; 313 314 #define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \ 315 .type = IIO_VOLTAGE, \ 316 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 317 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 318 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 319 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ 320 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 321 .info_mask_shared_by_type_available = \ 322 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 323 .indexed = 1, \ 324 .differential = (diff), \ 325 .channel = (diff) ? (2 * (index)) : (index), \ 326 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 327 .scan_index = (index), \ 328 .has_ext_scan_type = 1, \ 329 .ext_scan_type = ad7380_scan_type_##bits##_##sign, \ 330 .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \ 331 .event_spec = ad7380_events, \ 332 .num_event_specs = ARRAY_SIZE(ad7380_events), \ 333 } 334 335 #define _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, gain) { \ 336 .type = IIO_VOLTAGE, \ 337 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 338 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 339 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ 340 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \ 341 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ 342 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 343 .info_mask_shared_by_type_available = \ 344 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ 345 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 346 .indexed = 1, \ 347 .differential = (diff), \ 348 .channel = (diff) ? (2 * (index)) : (index), \ 349 .channel2 = (diff) ? (2 * (index) + 1) : 0, \ 350 .scan_index = (index), \ 351 .has_ext_scan_type = 1, \ 352 .ext_scan_type = ad7380_scan_type_##bits##_##sign##_offload, \ 353 .num_ext_scan_type = \ 354 ARRAY_SIZE(ad7380_scan_type_##bits##_##sign##_offload), \ 355 .event_spec = ad7380_events, \ 356 .num_event_specs = ARRAY_SIZE(ad7380_events), \ 357 } 358 359 /* 360 * Notes on the offload channels: 361 * - There is no soft timestamp since everything is done in hardware. 362 * - There is a sampling frequency attribute added. This controls the SPI 363 * offload trigger. 364 * - The storagebits value depends on the SPI offload provider. Currently there 365 * is only one supported provider, namely the ADI PULSAR ADC HDL project, 366 * which always uses 32-bit words for data values, even for <= 16-bit ADCs. 367 * So the value is just hardcoded to 32 for now. 368 */ 369 370 #define AD7380_CHANNEL(index, bits, diff, sign) \ 371 _AD7380_CHANNEL(index, bits, diff, sign, false) 372 373 #define ADAQ4380_CHANNEL(index, bits, diff, sign) \ 374 _AD7380_CHANNEL(index, bits, diff, sign, true) 375 376 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ 377 static const struct iio_chan_spec name[] = { \ 378 AD7380_CHANNEL(0, bits, diff, sign), \ 379 AD7380_CHANNEL(1, bits, diff, sign), \ 380 IIO_CHAN_SOFT_TIMESTAMP(2), \ 381 } 382 383 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \ 384 static const struct iio_chan_spec name[] = { \ 385 AD7380_CHANNEL(0, bits, diff, sign), \ 386 AD7380_CHANNEL(1, bits, diff, sign), \ 387 AD7380_CHANNEL(2, bits, diff, sign), \ 388 AD7380_CHANNEL(3, bits, diff, sign), \ 389 IIO_CHAN_SOFT_TIMESTAMP(4), \ 390 } 391 392 #define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \ 393 static const struct iio_chan_spec name[] = { \ 394 ADAQ4380_CHANNEL(0, bits, diff, sign), \ 395 ADAQ4380_CHANNEL(1, bits, diff, sign), \ 396 ADAQ4380_CHANNEL(2, bits, diff, sign), \ 397 ADAQ4380_CHANNEL(3, bits, diff, sign), \ 398 IIO_CHAN_SOFT_TIMESTAMP(4), \ 399 } 400 401 #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ 402 static const struct iio_chan_spec name[] = { \ 403 AD7380_CHANNEL(0, bits, diff, sign), \ 404 AD7380_CHANNEL(1, bits, diff, sign), \ 405 AD7380_CHANNEL(2, bits, diff, sign), \ 406 AD7380_CHANNEL(3, bits, diff, sign), \ 407 AD7380_CHANNEL(4, bits, diff, sign), \ 408 AD7380_CHANNEL(5, bits, diff, sign), \ 409 AD7380_CHANNEL(6, bits, diff, sign), \ 410 AD7380_CHANNEL(7, bits, diff, sign), \ 411 IIO_CHAN_SOFT_TIMESTAMP(8), \ 412 } 413 414 #define AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ 415 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, false) 416 417 #define ADAQ4380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ 418 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, true) 419 420 #define DEFINE_AD7380_2_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 421 static const struct iio_chan_spec name[] = { \ 422 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 423 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 424 } 425 426 #define DEFINE_AD7380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 427 static const struct iio_chan_spec name[] = { \ 428 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 429 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 430 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 431 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 432 } 433 434 #define DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 435 static const struct iio_chan_spec name[] = { \ 436 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 437 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 438 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 439 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 440 } 441 442 #define DEFINE_AD7380_8_OFFLOAD_CHANNEL(name, bits, diff, sign) \ 443 static const struct iio_chan_spec name[] = { \ 444 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \ 445 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \ 446 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \ 447 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \ 448 AD7380_OFFLOAD_CHANNEL(4, bits, diff, sign), \ 449 AD7380_OFFLOAD_CHANNEL(5, bits, diff, sign), \ 450 AD7380_OFFLOAD_CHANNEL(6, bits, diff, sign), \ 451 AD7380_OFFLOAD_CHANNEL(7, bits, diff, sign), \ 452 } 453 454 /* fully differential */ 455 DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s); 456 DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s); 457 DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s); 458 DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s); 459 DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s); 460 DEFINE_ADAQ4380_4_CHANNEL(adaq4381_4_channels, 14, 1, s); 461 /* pseudo differential */ 462 DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s); 463 DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s); 464 DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s); 465 DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s); 466 467 /* Single ended */ 468 DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u); 469 DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u); 470 DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u); 471 DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u); 472 DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u); 473 DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u); 474 475 /* offload channels */ 476 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7380_offload_channels, 16, 1, s); 477 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7381_offload_channels, 14, 1, s); 478 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7380_4_offload_channels, 16, 1, s); 479 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7381_4_offload_channels, 14, 1, s); 480 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4380_4_offload_channels, 16, 1, s); 481 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4381_4_offload_channels, 14, 1, s); 482 483 /* pseudo differential */ 484 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7383_offload_channels, 16, 0, s); 485 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7384_offload_channels, 14, 0, s); 486 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7383_4_offload_channels, 16, 0, s); 487 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7384_4_offload_channels, 14, 0, s); 488 489 /* Single ended */ 490 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7386_offload_channels, 16, 0, u); 491 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7387_offload_channels, 14, 0, u); 492 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7388_offload_channels, 12, 0, u); 493 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7386_4_offload_channels, 16, 0, u); 494 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7387_4_offload_channels, 14, 0, u); 495 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7388_4_offload_channels, 12, 0, u); 496 497 static const char * const ad7380_supplies[] = { 498 "vcc", "vlogic", 499 }; 500 501 static const char * const adaq4380_supplies[] = { 502 "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin", 503 }; 504 505 static const char * const ad7380_2_channel_vcm_supplies[] = { 506 "aina", "ainb", 507 }; 508 509 static const char * const ad7380_4_channel_vcm_supplies[] = { 510 "aina", "ainb", "ainc", "aind", 511 }; 512 513 /* Since this is simultaneous sampling, we don't allow individual channels. */ 514 static const unsigned long ad7380_2_channel_scan_masks[] = { 515 GENMASK(1, 0), 516 0 517 }; 518 519 static const unsigned long ad7380_4_channel_scan_masks[] = { 520 GENMASK(3, 0), 521 0 522 }; 523 524 /* 525 * Single ended parts have a 2:1 multiplexer in front of each ADC. 526 * 527 * From an IIO point of view, all inputs are exported, i.e ad7386/7/8 528 * export 4 channels and ad7386-4/7-4/8-4 export 8 channels. 529 * 530 * Inputs AinX0 of multiplexers correspond to the first half of IIO channels 531 * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or 532 * 4-7). Example for AD7386/7/8 (2 channels parts): 533 * 534 * IIO | AD7386/7/8 535 * | +---------------------------- 536 * | | _____ ______ 537 * | | | | | | 538 * voltage0 | AinA0 --|--->| | | | 539 * | | | mux |----->| ADCA |--- 540 * voltage2 | AinA1 --|--->| | | | 541 * | | |_____| |_____ | 542 * | | _____ ______ 543 * | | | | | | 544 * voltage1 | AinB0 --|--->| | | | 545 * | | | mux |----->| ADCB |--- 546 * voltage3 | AinB1 --|--->| | | | 547 * | | |_____| |______| 548 * | | 549 * | +---------------------------- 550 * 551 * Since this is simultaneous sampling for AinX0 OR AinX1 we have two separate 552 * scan masks. 553 * When sequencer mode is enabled, chip automatically cycles through 554 * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all 555 * channels, at the cost of an extra read, thus dividing the maximum rate by 556 * two. 557 */ 558 enum { 559 AD7380_SCAN_MASK_CH_0, 560 AD7380_SCAN_MASK_CH_1, 561 AD7380_SCAN_MASK_SEQ, 562 }; 563 564 static const unsigned long ad7380_2x2_channel_scan_masks[] = { 565 [AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0), 566 [AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2), 567 [AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0), 568 0 569 }; 570 571 static const unsigned long ad7380_2x4_channel_scan_masks[] = { 572 [AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0), 573 [AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4), 574 [AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0), 575 0 576 }; 577 578 static const struct ad7380_timing_specs ad7380_timing = { 579 .t_csh_ns = 10, 580 }; 581 582 static const struct ad7380_timing_specs ad7380_4_timing = { 583 .t_csh_ns = 20, 584 }; 585 586 /* 587 * Available oversampling ratios. The indices correspond with the bit value 588 * expected by the chip. The available ratios depend on the averaging mode, 589 * only normal averaging is supported for now. 590 */ 591 static const int ad7380_oversampling_ratios[] = { 592 1, 2, 4, 8, 16, 32, 593 }; 594 595 /* Gains stored as fractions of 1000 so they can be expressed by integers. */ 596 static const int ad7380_gains[] = { 597 300, 600, 1000, 1600, 598 }; 599 600 static const struct ad7380_chip_info ad7380_chip_info = { 601 .name = "ad7380", 602 .channels = ad7380_channels, 603 .offload_channels = ad7380_offload_channels, 604 .num_channels = ARRAY_SIZE(ad7380_channels), 605 .num_simult_channels = 2, 606 .supplies = ad7380_supplies, 607 .num_supplies = ARRAY_SIZE(ad7380_supplies), 608 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 609 .available_scan_masks = ad7380_2_channel_scan_masks, 610 .timing_specs = &ad7380_timing, 611 .max_conversion_rate_hz = 4 * MEGA, 612 }; 613 614 static const struct ad7380_chip_info ad7381_chip_info = { 615 .name = "ad7381", 616 .channels = ad7381_channels, 617 .offload_channels = ad7381_offload_channels, 618 .num_channels = ARRAY_SIZE(ad7381_channels), 619 .num_simult_channels = 2, 620 .supplies = ad7380_supplies, 621 .num_supplies = ARRAY_SIZE(ad7380_supplies), 622 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 623 .available_scan_masks = ad7380_2_channel_scan_masks, 624 .timing_specs = &ad7380_timing, 625 .max_conversion_rate_hz = 4 * MEGA, 626 }; 627 628 static const struct ad7380_chip_info ad7383_chip_info = { 629 .name = "ad7383", 630 .channels = ad7383_channels, 631 .offload_channels = ad7383_offload_channels, 632 .num_channels = ARRAY_SIZE(ad7383_channels), 633 .num_simult_channels = 2, 634 .supplies = ad7380_supplies, 635 .num_supplies = ARRAY_SIZE(ad7380_supplies), 636 .vcm_supplies = ad7380_2_channel_vcm_supplies, 637 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 638 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 639 .available_scan_masks = ad7380_2_channel_scan_masks, 640 .timing_specs = &ad7380_timing, 641 .max_conversion_rate_hz = 4 * MEGA, 642 }; 643 644 static const struct ad7380_chip_info ad7384_chip_info = { 645 .name = "ad7384", 646 .channels = ad7384_channels, 647 .offload_channels = ad7384_offload_channels, 648 .num_channels = ARRAY_SIZE(ad7384_channels), 649 .num_simult_channels = 2, 650 .supplies = ad7380_supplies, 651 .num_supplies = ARRAY_SIZE(ad7380_supplies), 652 .vcm_supplies = ad7380_2_channel_vcm_supplies, 653 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies), 654 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 655 .available_scan_masks = ad7380_2_channel_scan_masks, 656 .timing_specs = &ad7380_timing, 657 .max_conversion_rate_hz = 4 * MEGA, 658 }; 659 660 static const struct ad7380_chip_info ad7386_chip_info = { 661 .name = "ad7386", 662 .channels = ad7386_channels, 663 .offload_channels = ad7386_offload_channels, 664 .num_channels = ARRAY_SIZE(ad7386_channels), 665 .num_simult_channels = 2, 666 .supplies = ad7380_supplies, 667 .num_supplies = ARRAY_SIZE(ad7380_supplies), 668 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 669 .has_mux = true, 670 .available_scan_masks = ad7380_2x2_channel_scan_masks, 671 .timing_specs = &ad7380_timing, 672 .max_conversion_rate_hz = 4 * MEGA, 673 }; 674 675 static const struct ad7380_chip_info ad7387_chip_info = { 676 .name = "ad7387", 677 .channels = ad7387_channels, 678 .offload_channels = ad7387_offload_channels, 679 .num_channels = ARRAY_SIZE(ad7387_channels), 680 .num_simult_channels = 2, 681 .supplies = ad7380_supplies, 682 .num_supplies = ARRAY_SIZE(ad7380_supplies), 683 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 684 .has_mux = true, 685 .available_scan_masks = ad7380_2x2_channel_scan_masks, 686 .timing_specs = &ad7380_timing, 687 .max_conversion_rate_hz = 4 * MEGA, 688 }; 689 690 static const struct ad7380_chip_info ad7388_chip_info = { 691 .name = "ad7388", 692 .channels = ad7388_channels, 693 .offload_channels = ad7388_offload_channels, 694 .num_channels = ARRAY_SIZE(ad7388_channels), 695 .num_simult_channels = 2, 696 .supplies = ad7380_supplies, 697 .num_supplies = ARRAY_SIZE(ad7380_supplies), 698 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 699 .has_mux = true, 700 .available_scan_masks = ad7380_2x2_channel_scan_masks, 701 .timing_specs = &ad7380_timing, 702 .max_conversion_rate_hz = 4 * MEGA, 703 }; 704 705 static const struct ad7380_chip_info ad7380_4_chip_info = { 706 .name = "ad7380-4", 707 .channels = ad7380_4_channels, 708 .offload_channels = ad7380_4_offload_channels, 709 .num_channels = ARRAY_SIZE(ad7380_4_channels), 710 .num_simult_channels = 4, 711 .supplies = ad7380_supplies, 712 .num_supplies = ARRAY_SIZE(ad7380_supplies), 713 .external_ref_only = true, 714 .available_scan_masks = ad7380_4_channel_scan_masks, 715 .timing_specs = &ad7380_4_timing, 716 .max_conversion_rate_hz = 4 * MEGA, 717 }; 718 719 static const struct ad7380_chip_info ad7381_4_chip_info = { 720 .name = "ad7381-4", 721 .channels = ad7381_4_channels, 722 .offload_channels = ad7381_4_offload_channels, 723 .num_channels = ARRAY_SIZE(ad7381_4_channels), 724 .num_simult_channels = 4, 725 .supplies = ad7380_supplies, 726 .num_supplies = ARRAY_SIZE(ad7380_supplies), 727 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 728 .available_scan_masks = ad7380_4_channel_scan_masks, 729 .timing_specs = &ad7380_4_timing, 730 .max_conversion_rate_hz = 4 * MEGA, 731 }; 732 733 static const struct ad7380_chip_info ad7383_4_chip_info = { 734 .name = "ad7383-4", 735 .channels = ad7383_4_channels, 736 .offload_channels = ad7383_4_offload_channels, 737 .num_channels = ARRAY_SIZE(ad7383_4_channels), 738 .num_simult_channels = 4, 739 .supplies = ad7380_supplies, 740 .num_supplies = ARRAY_SIZE(ad7380_supplies), 741 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 742 .vcm_supplies = ad7380_4_channel_vcm_supplies, 743 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 744 .available_scan_masks = ad7380_4_channel_scan_masks, 745 .timing_specs = &ad7380_4_timing, 746 .max_conversion_rate_hz = 4 * MEGA, 747 }; 748 749 static const struct ad7380_chip_info ad7384_4_chip_info = { 750 .name = "ad7384-4", 751 .channels = ad7384_4_channels, 752 .offload_channels = ad7384_4_offload_channels, 753 .num_channels = ARRAY_SIZE(ad7384_4_channels), 754 .num_simult_channels = 4, 755 .supplies = ad7380_supplies, 756 .num_supplies = ARRAY_SIZE(ad7380_supplies), 757 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 758 .vcm_supplies = ad7380_4_channel_vcm_supplies, 759 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies), 760 .available_scan_masks = ad7380_4_channel_scan_masks, 761 .timing_specs = &ad7380_4_timing, 762 .max_conversion_rate_hz = 4 * MEGA, 763 }; 764 765 static const struct ad7380_chip_info ad7386_4_chip_info = { 766 .name = "ad7386-4", 767 .channels = ad7386_4_channels, 768 .offload_channels = ad7386_4_offload_channels, 769 .num_channels = ARRAY_SIZE(ad7386_4_channels), 770 .num_simult_channels = 4, 771 .supplies = ad7380_supplies, 772 .num_supplies = ARRAY_SIZE(ad7380_supplies), 773 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 774 .has_mux = true, 775 .available_scan_masks = ad7380_2x4_channel_scan_masks, 776 .timing_specs = &ad7380_4_timing, 777 .max_conversion_rate_hz = 4 * MEGA, 778 }; 779 780 static const struct ad7380_chip_info ad7387_4_chip_info = { 781 .name = "ad7387-4", 782 .channels = ad7387_4_channels, 783 .offload_channels = ad7387_4_offload_channels, 784 .num_channels = ARRAY_SIZE(ad7387_4_channels), 785 .num_simult_channels = 4, 786 .supplies = ad7380_supplies, 787 .num_supplies = ARRAY_SIZE(ad7380_supplies), 788 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 789 .has_mux = true, 790 .available_scan_masks = ad7380_2x4_channel_scan_masks, 791 .timing_specs = &ad7380_4_timing, 792 .max_conversion_rate_hz = 4 * MEGA, 793 }; 794 795 static const struct ad7380_chip_info ad7388_4_chip_info = { 796 .name = "ad7388-4", 797 .channels = ad7388_4_channels, 798 .offload_channels = ad7388_4_offload_channels, 799 .num_channels = ARRAY_SIZE(ad7388_4_channels), 800 .num_simult_channels = 4, 801 .supplies = ad7380_supplies, 802 .num_supplies = ARRAY_SIZE(ad7380_supplies), 803 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 804 .has_mux = true, 805 .available_scan_masks = ad7380_2x4_channel_scan_masks, 806 .timing_specs = &ad7380_4_timing, 807 .max_conversion_rate_hz = 4 * MEGA, 808 }; 809 810 static const struct ad7380_chip_info ad7389_4_chip_info = { 811 .name = "ad7389-4", 812 .channels = ad7380_4_channels, 813 .offload_channels = ad7380_4_offload_channels, 814 .num_channels = ARRAY_SIZE(ad7380_4_channels), 815 .num_simult_channels = 4, 816 .supplies = ad7380_supplies, 817 .num_supplies = ARRAY_SIZE(ad7380_supplies), 818 .internal_ref_only = true, 819 .internal_ref_mv = AD7380_INTERNAL_REF_MV, 820 .available_scan_masks = ad7380_4_channel_scan_masks, 821 .timing_specs = &ad7380_4_timing, 822 .max_conversion_rate_hz = 4 * MEGA, 823 }; 824 825 static const struct ad7380_chip_info adaq4370_4_chip_info = { 826 .name = "adaq4370-4", 827 .channels = adaq4380_4_channels, 828 .offload_channels = adaq4380_4_offload_channels, 829 .num_channels = ARRAY_SIZE(adaq4380_4_channels), 830 .num_simult_channels = 4, 831 .supplies = adaq4380_supplies, 832 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 833 .internal_ref_only = true, 834 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 835 .has_hardware_gain = true, 836 .available_scan_masks = ad7380_4_channel_scan_masks, 837 .timing_specs = &ad7380_4_timing, 838 .max_conversion_rate_hz = 2 * MEGA, 839 }; 840 841 static const struct ad7380_chip_info adaq4380_4_chip_info = { 842 .name = "adaq4380-4", 843 .channels = adaq4380_4_channels, 844 .offload_channels = adaq4380_4_offload_channels, 845 .num_channels = ARRAY_SIZE(adaq4380_4_channels), 846 .num_simult_channels = 4, 847 .supplies = adaq4380_supplies, 848 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 849 .internal_ref_only = true, 850 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 851 .has_hardware_gain = true, 852 .available_scan_masks = ad7380_4_channel_scan_masks, 853 .timing_specs = &ad7380_4_timing, 854 .max_conversion_rate_hz = 4 * MEGA, 855 }; 856 857 static const struct ad7380_chip_info adaq4381_4_chip_info = { 858 .name = "adaq4381-4", 859 .channels = adaq4381_4_channels, 860 .offload_channels = adaq4381_4_offload_channels, 861 .num_channels = ARRAY_SIZE(adaq4381_4_channels), 862 .num_simult_channels = 4, 863 .supplies = adaq4380_supplies, 864 .num_supplies = ARRAY_SIZE(adaq4380_supplies), 865 .internal_ref_only = true, 866 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV, 867 .has_hardware_gain = true, 868 .available_scan_masks = ad7380_4_channel_scan_masks, 869 .timing_specs = &ad7380_4_timing, 870 .max_conversion_rate_hz = 4 * MEGA, 871 }; 872 873 static const struct spi_offload_config ad7380_offload_config = { 874 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 875 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 876 }; 877 878 struct ad7380_state { 879 const struct ad7380_chip_info *chip_info; 880 struct spi_device *spi; 881 struct regmap *regmap; 882 bool resolution_boost_enabled; 883 unsigned int ch; 884 bool seq; 885 /* How many SDO lines are wired up. */ 886 u8 num_sdo_lines; 887 unsigned int vref_mv; 888 unsigned int vcm_mv[MAX_NUM_CHANNELS]; 889 unsigned int gain_milli[MAX_NUM_CHANNELS]; 890 /* xfers, message an buffer for reading sample data */ 891 struct spi_transfer normal_xfer[2]; 892 struct spi_message normal_msg; 893 struct spi_transfer seq_xfer[4]; 894 struct spi_message seq_msg; 895 struct spi_transfer offload_xfer; 896 struct spi_message offload_msg; 897 struct spi_offload *offload; 898 struct spi_offload_trigger *offload_trigger; 899 unsigned long offload_trigger_hz; 900 901 int sample_freq_range[3]; 902 /* 903 * DMA (thus cache coherency maintenance) requires the transfer buffers 904 * to live in their own cache lines. 905 * 906 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and 907 * one 64-bit aligned 64-bit timestamp. 908 */ 909 IIO_DECLARE_DMA_BUFFER_WITH_TS(u8, scan_data, MAX_NUM_CHANNELS * sizeof(u32)); 910 /* buffers for reading/writing registers */ 911 u16 tx; 912 u16 rx; 913 }; 914 915 static int ad7380_regmap_reg_write(void *context, unsigned int reg, 916 unsigned int val) 917 { 918 struct ad7380_state *st = context; 919 struct spi_transfer xfer = { 920 .speed_hz = AD7380_REG_WR_SPEED_HZ, 921 .bits_per_word = 16, 922 .len = 2, 923 .tx_buf = &st->tx, 924 }; 925 926 st->tx = FIELD_PREP(AD7380_REG_WR, 1) | 927 FIELD_PREP(AD7380_REG_REGADDR, reg) | 928 FIELD_PREP(AD7380_REG_DATA, val); 929 930 return spi_sync_transfer(st->spi, &xfer, 1); 931 } 932 933 static int ad7380_regmap_reg_read(void *context, unsigned int reg, 934 unsigned int *val) 935 { 936 struct ad7380_state *st = context; 937 struct spi_transfer xfers[] = { 938 { 939 .speed_hz = AD7380_REG_WR_SPEED_HZ, 940 .bits_per_word = 16, 941 .len = 2, 942 .tx_buf = &st->tx, 943 .cs_change = 1, 944 .cs_change_delay = { 945 .value = st->chip_info->timing_specs->t_csh_ns, 946 .unit = SPI_DELAY_UNIT_NSECS, 947 }, 948 }, { 949 .speed_hz = AD7380_REG_WR_SPEED_HZ, 950 .bits_per_word = 16, 951 .len = 2, 952 .rx_buf = &st->rx, 953 }, 954 }; 955 int ret; 956 957 st->tx = FIELD_PREP(AD7380_REG_WR, 0) | 958 FIELD_PREP(AD7380_REG_REGADDR, reg) | 959 FIELD_PREP(AD7380_REG_DATA, 0); 960 961 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 962 if (ret < 0) 963 return ret; 964 965 *val = FIELD_GET(AD7380_REG_DATA, st->rx); 966 967 return 0; 968 } 969 970 static const struct reg_default ad7380_reg_defaults[] = { 971 { AD7380_REG_ADDR_ALERT_LOW_TH, 0x800 }, 972 { AD7380_REG_ADDR_ALERT_HIGH_TH, 0x7FF }, 973 }; 974 975 static const struct regmap_range ad7380_volatile_reg_ranges[] = { 976 regmap_reg_range(AD7380_REG_ADDR_CONFIG2, AD7380_REG_ADDR_ALERT), 977 }; 978 979 static const struct regmap_access_table ad7380_volatile_regs = { 980 .yes_ranges = ad7380_volatile_reg_ranges, 981 .n_yes_ranges = ARRAY_SIZE(ad7380_volatile_reg_ranges), 982 }; 983 984 static const struct regmap_config ad7380_regmap_config = { 985 .reg_bits = 3, 986 .val_bits = 12, 987 .reg_read = ad7380_regmap_reg_read, 988 .reg_write = ad7380_regmap_reg_write, 989 .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH, 990 .can_sleep = true, 991 .reg_defaults = ad7380_reg_defaults, 992 .num_reg_defaults = ARRAY_SIZE(ad7380_reg_defaults), 993 .volatile_table = &ad7380_volatile_regs, 994 .cache_type = REGCACHE_MAPLE, 995 }; 996 997 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, 998 u32 writeval, u32 *readval) 999 { 1000 struct ad7380_state *st = iio_priv(indio_dev); 1001 int ret; 1002 1003 if (!iio_device_claim_direct(indio_dev)) 1004 return -EBUSY; 1005 1006 if (readval) 1007 ret = regmap_read(st->regmap, reg, readval); 1008 else 1009 ret = regmap_write(st->regmap, reg, writeval); 1010 1011 iio_device_release_direct(indio_dev); 1012 1013 return ret; 1014 } 1015 1016 /** 1017 * ad7380_regval_to_osr - convert OSR register value to ratio 1018 * @regval: register value to check 1019 * 1020 * Returns: the ratio corresponding to the OSR register. If regval is not in 1021 * bound, return 1 (oversampling disabled) 1022 * 1023 */ 1024 static int ad7380_regval_to_osr(unsigned int regval) 1025 { 1026 if (regval >= ARRAY_SIZE(ad7380_oversampling_ratios)) 1027 return 1; 1028 1029 return ad7380_oversampling_ratios[regval]; 1030 } 1031 1032 static int ad7380_get_osr(struct ad7380_state *st, int *val) 1033 { 1034 u32 tmp; 1035 int ret; 1036 1037 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); 1038 if (ret) 1039 return ret; 1040 1041 *val = ad7380_regval_to_osr(FIELD_GET(AD7380_CONFIG1_OSR, tmp)); 1042 1043 return 0; 1044 } 1045 1046 /* 1047 * When switching channel, the ADC require an additional settling time. 1048 * According to the datasheet, data is value on the third CS low. We already 1049 * have an extra toggle before each read (either direct reads or buffered reads) 1050 * to sample correct data, so we just add a single CS toggle at the end of the 1051 * register write. 1052 */ 1053 static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch) 1054 { 1055 struct spi_transfer xfer = { 1056 .delay = { 1057 .value = T_CONVERT_NS, 1058 .unit = SPI_DELAY_UNIT_NSECS, 1059 } 1060 }; 1061 int oversampling_ratio, ret; 1062 1063 if (st->ch == ch) 1064 return 0; 1065 1066 ret = ad7380_get_osr(st, &oversampling_ratio); 1067 if (ret) 1068 return ret; 1069 1070 ret = regmap_update_bits(st->regmap, 1071 AD7380_REG_ADDR_CONFIG1, 1072 AD7380_CONFIG1_CH, 1073 FIELD_PREP(AD7380_CONFIG1_CH, ch)); 1074 1075 if (ret) 1076 return ret; 1077 1078 st->ch = ch; 1079 1080 if (oversampling_ratio > 1) 1081 xfer.delay.value = T_CONVERT_0_NS + 1082 T_CONVERT_X_NS * (oversampling_ratio - 1) * 1083 st->chip_info->num_simult_channels / st->num_sdo_lines; 1084 1085 return spi_sync_transfer(st->spi, &xfer, 1); 1086 } 1087 1088 /** 1089 * ad7380_update_xfers - update the SPI transfers base on the current scan type 1090 * @st: device instance specific state 1091 * @scan_type: current scan type 1092 */ 1093 static int ad7380_update_xfers(struct ad7380_state *st, 1094 const struct iio_scan_type *scan_type) 1095 { 1096 struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer; 1097 unsigned int t_convert = T_CONVERT_NS; 1098 int oversampling_ratio, ret; 1099 1100 /* 1101 * In the case of oversampling, conversion time is higher than in normal 1102 * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use 1103 * the maximum value for simplicity for now. 1104 */ 1105 ret = ad7380_get_osr(st, &oversampling_ratio); 1106 if (ret) 1107 return ret; 1108 1109 if (oversampling_ratio > 1) 1110 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS * 1111 (oversampling_ratio - 1) * 1112 st->chip_info->num_simult_channels / st->num_sdo_lines; 1113 1114 if (st->seq) { 1115 xfer[0].delay.value = xfer[1].delay.value = t_convert; 1116 xfer[0].delay.unit = xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS; 1117 xfer[2].bits_per_word = xfer[3].bits_per_word = 1118 scan_type->realbits; 1119 xfer[2].len = xfer[3].len = 1120 AD7380_SPI_BYTES(scan_type) * 1121 st->chip_info->num_simult_channels; 1122 xfer[3].rx_buf = xfer[2].rx_buf + xfer[2].len; 1123 /* Additional delay required here when oversampling is enabled */ 1124 if (oversampling_ratio > 1) 1125 xfer[2].delay.value = t_convert; 1126 else 1127 xfer[2].delay.value = 0; 1128 xfer[2].delay.unit = SPI_DELAY_UNIT_NSECS; 1129 } else { 1130 xfer[0].delay.value = t_convert; 1131 xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS; 1132 xfer[1].bits_per_word = scan_type->realbits; 1133 xfer[1].len = AD7380_SPI_BYTES(scan_type) * 1134 st->chip_info->num_simult_channels; 1135 } 1136 1137 return 0; 1138 } 1139 1140 static int ad7380_set_sample_freq(struct ad7380_state *st, int val) 1141 { 1142 struct spi_offload_trigger_config config = { 1143 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1144 .periodic = { 1145 .frequency_hz = val, 1146 }, 1147 }; 1148 int ret; 1149 1150 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 1151 if (ret) 1152 return ret; 1153 1154 st->offload_trigger_hz = config.periodic.frequency_hz; 1155 1156 return 0; 1157 } 1158 1159 static int ad7380_init_offload_msg(struct ad7380_state *st, 1160 struct iio_dev *indio_dev) 1161 { 1162 struct spi_transfer *xfer = &st->offload_xfer; 1163 struct device *dev = &st->spi->dev; 1164 const struct iio_scan_type *scan_type; 1165 int ret; 1166 1167 scan_type = iio_get_current_scan_type(indio_dev, 1168 &indio_dev->channels[0]); 1169 if (IS_ERR(scan_type)) 1170 return PTR_ERR(scan_type); 1171 1172 if (st->chip_info->has_mux) { 1173 int index; 1174 1175 ret = iio_active_scan_mask_index(indio_dev); 1176 if (ret < 0) 1177 return ret; 1178 1179 index = ret; 1180 if (index == AD7380_SCAN_MASK_SEQ) { 1181 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 1182 AD7380_CONFIG1_SEQ); 1183 if (ret) 1184 return ret; 1185 1186 st->seq = true; 1187 } else { 1188 ret = ad7380_set_ch(st, index); 1189 if (ret) 1190 return ret; 1191 } 1192 } 1193 1194 xfer->bits_per_word = scan_type->realbits; 1195 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1196 xfer->len = AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_channels; 1197 if (st->num_sdo_lines > 1) 1198 xfer->multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 1199 1200 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); 1201 st->offload_msg.offload = st->offload; 1202 1203 ret = spi_optimize_message(st->spi, &st->offload_msg); 1204 if (ret) { 1205 dev_err(dev, "failed to prepare offload msg, err: %d\n", 1206 ret); 1207 return ret; 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int ad7380_offload_buffer_postenable(struct iio_dev *indio_dev) 1214 { 1215 struct ad7380_state *st = iio_priv(indio_dev); 1216 struct spi_offload_trigger_config config = { 1217 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1218 .periodic = { 1219 .frequency_hz = st->offload_trigger_hz, 1220 }, 1221 }; 1222 int ret; 1223 1224 ret = ad7380_init_offload_msg(st, indio_dev); 1225 if (ret) 1226 return ret; 1227 1228 /* 1229 * When the sequencer is required to read all channels, we need to 1230 * trigger twice per sample period in order to read one complete set 1231 * of samples. 1232 */ 1233 if (st->seq) 1234 config.periodic.frequency_hz *= 2; 1235 1236 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config); 1237 if (ret) 1238 spi_unoptimize_message(&st->offload_msg); 1239 1240 return ret; 1241 } 1242 1243 static int ad7380_offload_buffer_predisable(struct iio_dev *indio_dev) 1244 { 1245 struct ad7380_state *st = iio_priv(indio_dev); 1246 int ret; 1247 1248 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1249 spi_unoptimize_message(&st->offload_msg); 1250 1251 if (st->seq) { 1252 ret = regmap_update_bits(st->regmap, 1253 AD7380_REG_ADDR_CONFIG1, 1254 AD7380_CONFIG1_SEQ, 1255 FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); 1256 if (ret) 1257 return ret; 1258 1259 st->seq = false; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static const struct iio_buffer_setup_ops ad7380_offload_buffer_setup_ops = { 1266 .postenable = ad7380_offload_buffer_postenable, 1267 .predisable = ad7380_offload_buffer_predisable, 1268 }; 1269 1270 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev) 1271 { 1272 struct ad7380_state *st = iio_priv(indio_dev); 1273 const struct iio_scan_type *scan_type; 1274 struct spi_message *msg = &st->normal_msg; 1275 int ret; 1276 1277 /* 1278 * Currently, we always read all channels at the same time. The scan_type 1279 * is the same for all channels, so we just pass the first channel. 1280 */ 1281 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1282 if (IS_ERR(scan_type)) 1283 return PTR_ERR(scan_type); 1284 1285 if (st->chip_info->has_mux) { 1286 unsigned int index; 1287 1288 /* 1289 * Depending on the requested scan_mask and current state, 1290 * we need to either change CH bit, or enable sequencer mode 1291 * to sample correct data. 1292 * Sequencer mode is enabled if active mask corresponds to all 1293 * IIO channels enabled. Otherwise, CH bit is set. 1294 */ 1295 ret = iio_active_scan_mask_index(indio_dev); 1296 if (ret < 0) 1297 return ret; 1298 1299 index = ret; 1300 if (index == AD7380_SCAN_MASK_SEQ) { 1301 ret = regmap_update_bits(st->regmap, 1302 AD7380_REG_ADDR_CONFIG1, 1303 AD7380_CONFIG1_SEQ, 1304 FIELD_PREP(AD7380_CONFIG1_SEQ, 1)); 1305 if (ret) 1306 return ret; 1307 msg = &st->seq_msg; 1308 st->seq = true; 1309 } else { 1310 ret = ad7380_set_ch(st, index); 1311 if (ret) 1312 return ret; 1313 } 1314 1315 } 1316 1317 ret = ad7380_update_xfers(st, scan_type); 1318 if (ret) 1319 return ret; 1320 1321 return spi_optimize_message(st->spi, msg); 1322 } 1323 1324 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev) 1325 { 1326 struct ad7380_state *st = iio_priv(indio_dev); 1327 struct spi_message *msg = &st->normal_msg; 1328 int ret; 1329 1330 if (st->seq) { 1331 ret = regmap_update_bits(st->regmap, 1332 AD7380_REG_ADDR_CONFIG1, 1333 AD7380_CONFIG1_SEQ, 1334 FIELD_PREP(AD7380_CONFIG1_SEQ, 0)); 1335 if (ret) 1336 return ret; 1337 1338 msg = &st->seq_msg; 1339 st->seq = false; 1340 } 1341 1342 spi_unoptimize_message(msg); 1343 1344 return 0; 1345 } 1346 1347 static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = { 1348 .preenable = ad7380_triggered_buffer_preenable, 1349 .postdisable = ad7380_triggered_buffer_postdisable, 1350 }; 1351 1352 static irqreturn_t ad7380_trigger_handler(int irq, void *p) 1353 { 1354 struct iio_poll_func *pf = p; 1355 struct iio_dev *indio_dev = pf->indio_dev; 1356 struct ad7380_state *st = iio_priv(indio_dev); 1357 struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg; 1358 int ret; 1359 1360 ret = spi_sync(st->spi, msg); 1361 if (ret) 1362 goto out; 1363 1364 iio_push_to_buffers_with_ts(indio_dev, &st->scan_data, sizeof(st->scan_data), 1365 pf->timestamp); 1366 1367 out: 1368 iio_trigger_notify_done(indio_dev->trig); 1369 1370 return IRQ_HANDLED; 1371 } 1372 1373 static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index, 1374 const struct iio_scan_type *scan_type, int *val) 1375 { 1376 unsigned int index = scan_index; 1377 int ret; 1378 1379 if (st->chip_info->has_mux) { 1380 unsigned int ch = 0; 1381 1382 if (index >= st->chip_info->num_simult_channels) { 1383 index -= st->chip_info->num_simult_channels; 1384 ch = 1; 1385 } 1386 1387 ret = ad7380_set_ch(st, ch); 1388 if (ret) 1389 return ret; 1390 } 1391 1392 ret = ad7380_update_xfers(st, scan_type); 1393 if (ret) 1394 return ret; 1395 1396 ret = spi_sync(st->spi, &st->normal_msg); 1397 if (ret < 0) 1398 return ret; 1399 1400 if (scan_type->realbits > 16) { 1401 if (scan_type->sign == 's') 1402 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index), 1403 scan_type->realbits - 1); 1404 else 1405 *val = *(u32 *)(st->scan_data + 4 * index) & 1406 GENMASK(scan_type->realbits - 1, 0); 1407 } else { 1408 if (scan_type->sign == 's') 1409 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index), 1410 scan_type->realbits - 1); 1411 else 1412 *val = *(u16 *)(st->scan_data + 2 * index) & 1413 GENMASK(scan_type->realbits - 1, 0); 1414 } 1415 1416 return IIO_VAL_INT; 1417 } 1418 1419 static int ad7380_read_raw(struct iio_dev *indio_dev, 1420 struct iio_chan_spec const *chan, 1421 int *val, int *val2, long info) 1422 { 1423 struct ad7380_state *st = iio_priv(indio_dev); 1424 const struct iio_scan_type *scan_type; 1425 int ret; 1426 1427 scan_type = iio_get_current_scan_type(indio_dev, chan); 1428 1429 if (IS_ERR(scan_type)) 1430 return PTR_ERR(scan_type); 1431 1432 switch (info) { 1433 case IIO_CHAN_INFO_RAW: 1434 if (!iio_device_claim_direct(indio_dev)) 1435 return -EBUSY; 1436 1437 ret = ad7380_read_direct(st, chan->scan_index, 1438 scan_type, val); 1439 1440 iio_device_release_direct(indio_dev); 1441 1442 return ret; 1443 case IIO_CHAN_INFO_SCALE: 1444 /* 1445 * According to the datasheet, the LSB size is: 1446 * * (2 × VREF) / 2^N, for differential chips 1447 * * VREF / 2^N, for pseudo-differential chips 1448 * where N is the ADC resolution (i.e realbits) 1449 * 1450 * The gain is stored as a fraction of 1000 and, as we need to 1451 * divide vref_mv by the gain, we invert the gain/1000 fraction. 1452 */ 1453 if (st->chip_info->has_hardware_gain) 1454 *val = mult_frac(st->vref_mv, MILLI, 1455 st->gain_milli[chan->scan_index]); 1456 else 1457 *val = st->vref_mv; 1458 *val2 = scan_type->realbits - chan->differential; 1459 1460 return IIO_VAL_FRACTIONAL_LOG2; 1461 case IIO_CHAN_INFO_OFFSET: 1462 /* 1463 * According to IIO ABI, offset is applied before scale, 1464 * so offset is: vcm_mv / scale 1465 */ 1466 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits) 1467 / st->vref_mv; 1468 1469 return IIO_VAL_INT; 1470 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1471 if (!iio_device_claim_direct(indio_dev)) 1472 return -EBUSY; 1473 1474 ret = ad7380_get_osr(st, val); 1475 1476 iio_device_release_direct(indio_dev); 1477 1478 if (ret) 1479 return ret; 1480 1481 return IIO_VAL_INT; 1482 case IIO_CHAN_INFO_SAMP_FREQ: 1483 *val = st->offload_trigger_hz; 1484 return IIO_VAL_INT; 1485 default: 1486 return -EINVAL; 1487 } 1488 } 1489 1490 static int ad7380_read_avail(struct iio_dev *indio_dev, 1491 struct iio_chan_spec const *chan, 1492 const int **vals, int *type, int *length, 1493 long mask) 1494 { 1495 struct ad7380_state *st = iio_priv(indio_dev); 1496 1497 switch (mask) { 1498 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1499 *vals = ad7380_oversampling_ratios; 1500 *length = ARRAY_SIZE(ad7380_oversampling_ratios); 1501 *type = IIO_VAL_INT; 1502 1503 return IIO_AVAIL_LIST; 1504 case IIO_CHAN_INFO_SAMP_FREQ: 1505 *vals = st->sample_freq_range; 1506 *type = IIO_VAL_INT; 1507 return IIO_AVAIL_RANGE; 1508 default: 1509 return -EINVAL; 1510 } 1511 } 1512 1513 /** 1514 * ad7380_osr_to_regval - convert ratio to OSR register value 1515 * @ratio: ratio to check 1516 * 1517 * Check if ratio is present in the list of available ratios and return the 1518 * corresponding value that needs to be written to the register to select that 1519 * ratio. 1520 * 1521 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match 1522 */ 1523 static int ad7380_osr_to_regval(int ratio) 1524 { 1525 int i; 1526 1527 for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) { 1528 if (ratio == ad7380_oversampling_ratios[i]) 1529 return i; 1530 } 1531 1532 return -EINVAL; 1533 } 1534 1535 static int ad7380_set_oversampling_ratio(struct ad7380_state *st, int val) 1536 { 1537 int ret, osr, boost; 1538 1539 osr = ad7380_osr_to_regval(val); 1540 if (osr < 0) 1541 return osr; 1542 1543 /* always enable resolution boost when oversampling is enabled */ 1544 boost = osr > 0 ? 1 : 0; 1545 1546 ret = regmap_update_bits(st->regmap, 1547 AD7380_REG_ADDR_CONFIG1, 1548 AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES, 1549 FIELD_PREP(AD7380_CONFIG1_OSR, osr) | 1550 FIELD_PREP(AD7380_CONFIG1_RES, boost)); 1551 1552 if (ret) 1553 return ret; 1554 1555 st->resolution_boost_enabled = boost; 1556 1557 /* 1558 * Perform a soft reset. This will flush the oversampling 1559 * block and FIFO but will maintain the content of the 1560 * configurable registers. 1561 */ 1562 ret = regmap_update_bits(st->regmap, 1563 AD7380_REG_ADDR_CONFIG2, 1564 AD7380_CONFIG2_RESET, 1565 FIELD_PREP(AD7380_CONFIG2_RESET, 1566 AD7380_CONFIG2_RESET_SOFT)); 1567 return ret; 1568 } 1569 static int ad7380_write_raw(struct iio_dev *indio_dev, 1570 struct iio_chan_spec const *chan, int val, 1571 int val2, long mask) 1572 { 1573 struct ad7380_state *st = iio_priv(indio_dev); 1574 int ret; 1575 1576 switch (mask) { 1577 case IIO_CHAN_INFO_SAMP_FREQ: 1578 if (val < 1) 1579 return -EINVAL; 1580 return ad7380_set_sample_freq(st, val); 1581 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1582 if (!iio_device_claim_direct(indio_dev)) 1583 return -EBUSY; 1584 1585 ret = ad7380_set_oversampling_ratio(st, val); 1586 1587 iio_device_release_direct(indio_dev); 1588 1589 return ret; 1590 default: 1591 return -EINVAL; 1592 } 1593 } 1594 1595 static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev, 1596 const struct iio_chan_spec *chan) 1597 { 1598 struct ad7380_state *st = iio_priv(indio_dev); 1599 1600 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST 1601 : AD7380_SCAN_TYPE_NORMAL; 1602 } 1603 1604 static int ad7380_read_event_config(struct iio_dev *indio_dev, 1605 const struct iio_chan_spec *chan, 1606 enum iio_event_type type, 1607 enum iio_event_direction dir) 1608 { 1609 struct ad7380_state *st = iio_priv(indio_dev); 1610 int tmp, ret; 1611 1612 if (!iio_device_claim_direct(indio_dev)) 1613 return -EBUSY; 1614 1615 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); 1616 1617 iio_device_release_direct(indio_dev); 1618 1619 if (ret) 1620 return ret; 1621 1622 return FIELD_GET(AD7380_CONFIG1_ALERTEN, tmp); 1623 } 1624 1625 static int ad7380_write_event_config(struct iio_dev *indio_dev, 1626 const struct iio_chan_spec *chan, 1627 enum iio_event_type type, 1628 enum iio_event_direction dir, 1629 bool state) 1630 { 1631 struct ad7380_state *st = iio_priv(indio_dev); 1632 int ret; 1633 1634 if (!iio_device_claim_direct(indio_dev)) 1635 return -EBUSY; 1636 1637 ret = regmap_update_bits(st->regmap, 1638 AD7380_REG_ADDR_CONFIG1, 1639 AD7380_CONFIG1_ALERTEN, 1640 FIELD_PREP(AD7380_CONFIG1_ALERTEN, state)); 1641 1642 iio_device_release_direct(indio_dev); 1643 1644 return ret; 1645 } 1646 1647 static int ad7380_get_alert_th(struct iio_dev *indio_dev, 1648 const struct iio_chan_spec *chan, 1649 enum iio_event_direction dir, 1650 int *val) 1651 { 1652 struct ad7380_state *st = iio_priv(indio_dev); 1653 const struct iio_scan_type *scan_type; 1654 int ret, tmp, shift; 1655 1656 scan_type = iio_get_current_scan_type(indio_dev, chan); 1657 if (IS_ERR(scan_type)) 1658 return PTR_ERR(scan_type); 1659 1660 /* 1661 * The register value is 12-bits and is compared to the most significant 1662 * bits of raw value, therefore a shift is required to convert this to 1663 * the same scale as the raw value. 1664 */ 1665 shift = scan_type->realbits - 12; 1666 1667 switch (dir) { 1668 case IIO_EV_DIR_RISING: 1669 ret = regmap_read(st->regmap, 1670 AD7380_REG_ADDR_ALERT_HIGH_TH, 1671 &tmp); 1672 if (ret) 1673 return ret; 1674 1675 *val = FIELD_GET(AD7380_ALERT_HIGH_TH, tmp) << shift; 1676 return IIO_VAL_INT; 1677 case IIO_EV_DIR_FALLING: 1678 ret = regmap_read(st->regmap, 1679 AD7380_REG_ADDR_ALERT_LOW_TH, 1680 &tmp); 1681 if (ret) 1682 return ret; 1683 1684 *val = FIELD_GET(AD7380_ALERT_LOW_TH, tmp) << shift; 1685 return IIO_VAL_INT; 1686 default: 1687 return -EINVAL; 1688 } 1689 } 1690 1691 static int ad7380_read_event_value(struct iio_dev *indio_dev, 1692 const struct iio_chan_spec *chan, 1693 enum iio_event_type type, 1694 enum iio_event_direction dir, 1695 enum iio_event_info info, 1696 int *val, int *val2) 1697 { 1698 int ret; 1699 1700 switch (info) { 1701 case IIO_EV_INFO_VALUE: 1702 if (!iio_device_claim_direct(indio_dev)) 1703 return -EBUSY; 1704 1705 ret = ad7380_get_alert_th(indio_dev, chan, dir, val); 1706 1707 iio_device_release_direct(indio_dev); 1708 return ret; 1709 default: 1710 return -EINVAL; 1711 } 1712 } 1713 1714 static int ad7380_set_alert_th(struct iio_dev *indio_dev, 1715 const struct iio_chan_spec *chan, 1716 enum iio_event_direction dir, 1717 int val) 1718 { 1719 struct ad7380_state *st = iio_priv(indio_dev); 1720 const struct iio_scan_type *scan_type; 1721 u16 th; 1722 1723 /* 1724 * According to the datasheet, 1725 * AD7380_REG_ADDR_ALERT_HIGH_TH[11:0] are the 12 MSB of the 1726 * 16-bits internal alert high register. LSB are set to 0xf. 1727 * AD7380_REG_ADDR_ALERT_LOW_TH[11:0] are the 12 MSB of the 1728 * 16 bits internal alert low register. LSB are set to 0x0. 1729 * 1730 * When alert is enabled the conversion from the adc is compared 1731 * immediately to the alert high/low thresholds, before any 1732 * oversampling. This means that the thresholds are the same for 1733 * normal mode and oversampling mode. 1734 */ 1735 1736 /* Extract the 12 MSB of val */ 1737 scan_type = iio_get_current_scan_type(indio_dev, chan); 1738 if (IS_ERR(scan_type)) 1739 return PTR_ERR(scan_type); 1740 1741 th = val >> (scan_type->realbits - 12); 1742 1743 switch (dir) { 1744 case IIO_EV_DIR_RISING: 1745 return regmap_write(st->regmap, 1746 AD7380_REG_ADDR_ALERT_HIGH_TH, 1747 th); 1748 case IIO_EV_DIR_FALLING: 1749 return regmap_write(st->regmap, 1750 AD7380_REG_ADDR_ALERT_LOW_TH, 1751 th); 1752 default: 1753 return -EINVAL; 1754 } 1755 } 1756 1757 static int ad7380_write_event_value(struct iio_dev *indio_dev, 1758 const struct iio_chan_spec *chan, 1759 enum iio_event_type type, 1760 enum iio_event_direction dir, 1761 enum iio_event_info info, 1762 int val, int val2) 1763 { 1764 int ret; 1765 1766 switch (info) { 1767 case IIO_EV_INFO_VALUE: 1768 if (!iio_device_claim_direct(indio_dev)) 1769 return -EBUSY; 1770 1771 ret = ad7380_set_alert_th(indio_dev, chan, dir, val); 1772 1773 iio_device_release_direct(indio_dev); 1774 return ret; 1775 default: 1776 return -EINVAL; 1777 } 1778 } 1779 1780 static const struct iio_info ad7380_info = { 1781 .read_raw = &ad7380_read_raw, 1782 .read_avail = &ad7380_read_avail, 1783 .write_raw = &ad7380_write_raw, 1784 .get_current_scan_type = &ad7380_get_current_scan_type, 1785 .debugfs_reg_access = &ad7380_debugfs_reg_access, 1786 .read_event_config = &ad7380_read_event_config, 1787 .write_event_config = &ad7380_write_event_config, 1788 .read_event_value = &ad7380_read_event_value, 1789 .write_event_value = &ad7380_write_event_value, 1790 }; 1791 1792 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) 1793 { 1794 u32 sdo; 1795 int ret; 1796 1797 /* perform hard reset */ 1798 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 1799 AD7380_CONFIG2_RESET, 1800 FIELD_PREP(AD7380_CONFIG2_RESET, 1801 AD7380_CONFIG2_RESET_HARD)); 1802 if (ret < 0) 1803 return ret; 1804 1805 if (external_ref_en) { 1806 /* select external reference voltage */ 1807 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, 1808 AD7380_CONFIG1_REFSEL); 1809 if (ret < 0) 1810 return ret; 1811 } 1812 1813 /* This is the default value after reset. */ 1814 st->ch = 0; 1815 st->seq = false; 1816 1817 /* SDO field has an irregular mapping. */ 1818 switch (st->num_sdo_lines) { 1819 case 1: 1820 sdo = 1; 1821 break; 1822 case 2: 1823 sdo = 0; 1824 break; 1825 case 4: 1826 sdo = 2; 1827 break; 1828 default: 1829 return -EINVAL; 1830 } 1831 1832 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 1833 AD7380_CONFIG2_SDO, 1834 FIELD_PREP(AD7380_CONFIG2_SDO, sdo)); 1835 } 1836 1837 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, 1838 struct ad7380_state *st) 1839 { 1840 struct spi_device *spi = st->spi; 1841 struct device *dev = &spi->dev; 1842 struct dma_chan *rx_dma; 1843 int sample_rate, ret; 1844 1845 indio_dev->setup_ops = &ad7380_offload_buffer_setup_ops; 1846 indio_dev->channels = st->chip_info->offload_channels; 1847 /* Just removing the timestamp channel. */ 1848 indio_dev->num_channels--; 1849 1850 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1851 SPI_OFFLOAD_TRIGGER_PERIODIC); 1852 if (IS_ERR(st->offload_trigger)) 1853 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1854 "failed to get offload trigger\n"); 1855 1856 sample_rate = st->chip_info->max_conversion_rate_hz * 1857 st->num_sdo_lines / st->chip_info->num_simult_channels; 1858 1859 st->sample_freq_range[0] = 1; /* min */ 1860 st->sample_freq_range[1] = 1; /* step */ 1861 st->sample_freq_range[2] = sample_rate; /* max */ 1862 1863 /* 1864 * Starting with a quite low frequency, to allow oversampling x32, 1865 * user is then responsible to adjust the frequency for the specific case. 1866 */ 1867 ret = ad7380_set_sample_freq(st, sample_rate / 32); 1868 if (ret) 1869 return ret; 1870 1871 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1872 if (IS_ERR(rx_dma)) 1873 return dev_err_probe(dev, PTR_ERR(rx_dma), 1874 "failed to get offload RX DMA\n"); 1875 1876 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, 1877 rx_dma, IIO_BUFFER_DIRECTION_IN); 1878 if (ret) 1879 return dev_err_probe(dev, ret, "cannot setup dma buffer\n"); 1880 1881 return 0; 1882 } 1883 1884 static int ad7380_probe(struct spi_device *spi) 1885 { 1886 struct device *dev = &spi->dev; 1887 struct iio_dev *indio_dev; 1888 struct ad7380_state *st; 1889 bool external_ref_en; 1890 int ret, i; 1891 1892 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1893 if (!indio_dev) 1894 return -ENOMEM; 1895 1896 st = iio_priv(indio_dev); 1897 st->spi = spi; 1898 st->chip_info = spi_get_device_match_data(spi); 1899 if (!st->chip_info) 1900 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 1901 1902 st->num_sdo_lines = spi->num_rx_lanes; 1903 1904 if (st->num_sdo_lines < 1 || st->num_sdo_lines > st->chip_info->num_simult_channels) 1905 return dev_err_probe(dev, -EINVAL, 1906 "invalid number of SDO lines (%d)\n", 1907 st->num_sdo_lines); 1908 1909 ret = devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, 1910 st->chip_info->supplies); 1911 1912 if (ret) 1913 return dev_err_probe(dev, ret, 1914 "Failed to enable power supplies\n"); 1915 fsleep(T_POWERUP_US); 1916 1917 if (st->chip_info->internal_ref_only) { 1918 /* 1919 * ADAQ chips use fixed internal reference but still 1920 * require a specific reference supply to power it. 1921 * "refin" is already enabled with other power supplies 1922 * in bulk_get_enable(). 1923 */ 1924 1925 st->vref_mv = st->chip_info->internal_ref_mv; 1926 1927 /* these chips don't have a register bit for this */ 1928 external_ref_en = false; 1929 } else if (st->chip_info->external_ref_only) { 1930 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 1931 if (ret < 0) 1932 return dev_err_probe(dev, ret, 1933 "Failed to get refin regulator\n"); 1934 1935 st->vref_mv = ret / 1000; 1936 1937 /* these chips don't have a register bit for this */ 1938 external_ref_en = false; 1939 } else { 1940 /* 1941 * If there is no REFIO supply, then it means that we are using 1942 * the internal reference, otherwise REFIO is reference voltage. 1943 */ 1944 ret = devm_regulator_get_enable_read_voltage(dev, "refio"); 1945 if (ret < 0 && ret != -ENODEV) 1946 return dev_err_probe(dev, ret, 1947 "Failed to get refio regulator\n"); 1948 1949 external_ref_en = ret != -ENODEV; 1950 st->vref_mv = external_ref_en ? ret / 1000 1951 : st->chip_info->internal_ref_mv; 1952 } 1953 1954 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) 1955 return dev_err_probe(dev, -EINVAL, 1956 "invalid number of VCM supplies\n"); 1957 1958 /* 1959 * pseudo-differential chips have common mode supplies for the negative 1960 * input pin. 1961 */ 1962 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) { 1963 const char *vcm = st->chip_info->vcm_supplies[i]; 1964 1965 ret = devm_regulator_get_enable_read_voltage(dev, vcm); 1966 if (ret < 0) 1967 return dev_err_probe(dev, ret, 1968 "Failed to get %s regulator\n", 1969 vcm); 1970 1971 st->vcm_mv[i] = ret / 1000; 1972 } 1973 1974 for (i = 0; i < MAX_NUM_CHANNELS; i++) 1975 st->gain_milli[i] = AD7380_DEFAULT_GAIN_MILLI; 1976 1977 if (st->chip_info->has_hardware_gain) { 1978 device_for_each_child_node_scoped(dev, node) { 1979 unsigned int channel; 1980 int gain_idx; 1981 u16 gain; 1982 1983 ret = fwnode_property_read_u32(node, "reg", &channel); 1984 if (ret) 1985 return dev_err_probe(dev, ret, 1986 "Failed to read reg property\n"); 1987 1988 if (channel >= st->chip_info->num_channels - 1) 1989 return dev_err_probe(dev, -EINVAL, 1990 "Invalid channel number %i\n", 1991 channel); 1992 1993 ret = fwnode_property_read_u16(node, "adi,gain-milli", 1994 &gain); 1995 if (ret && ret != -EINVAL) 1996 return dev_err_probe(dev, ret, 1997 "Failed to read gain for channel %i\n", 1998 channel); 1999 if (ret != -EINVAL) { 2000 /* 2001 * Match gain value from dt to one of supported 2002 * gains 2003 */ 2004 gain_idx = find_closest(gain, ad7380_gains, 2005 ARRAY_SIZE(ad7380_gains)); 2006 st->gain_milli[channel] = ad7380_gains[gain_idx]; 2007 } 2008 } 2009 } 2010 2011 st->regmap = devm_regmap_init(dev, NULL, st, &ad7380_regmap_config); 2012 if (IS_ERR(st->regmap)) 2013 return dev_err_probe(dev, PTR_ERR(st->regmap), 2014 "failed to allocate register map\n"); 2015 2016 /* 2017 * Setting up xfer structures for both normal and sequence mode. These 2018 * struct are used for both direct read and triggered buffer. Additional 2019 * fields will be set up in ad7380_update_xfers() based on the current 2020 * state of the driver at the time of the read. 2021 */ 2022 2023 /* 2024 * In normal mode a read is composed of two steps: 2025 * - first, toggle CS (no data xfer) to trigger a conversion 2026 * - then, read data 2027 */ 2028 st->normal_xfer[0].cs_change = 1; 2029 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2030 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2031 st->normal_xfer[1].rx_buf = st->scan_data; 2032 if (st->num_sdo_lines > 1) 2033 st->normal_xfer[1].multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 2034 2035 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, 2036 ARRAY_SIZE(st->normal_xfer)); 2037 /* 2038 * In sequencer mode a read is composed of four steps: 2039 * - CS toggle (no data xfer) to get the right point in the sequence 2040 * - CS toggle (no data xfer) to trigger a conversion of AinX0 and 2041 * acquisition of AinX1 2042 * - 2 data reads, to read AinX0 and AinX1 2043 */ 2044 st->seq_xfer[0].cs_change = 1; 2045 st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2046 st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2047 st->seq_xfer[1].cs_change = 1; 2048 st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2049 st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2050 2051 st->seq_xfer[2].rx_buf = st->scan_data; 2052 st->seq_xfer[2].cs_change = 1; 2053 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2054 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2055 if (st->num_sdo_lines > 1) { 2056 st->seq_xfer[2].multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 2057 st->seq_xfer[3].multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 2058 } 2059 2060 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, 2061 ARRAY_SIZE(st->seq_xfer)); 2062 2063 indio_dev->channels = st->chip_info->channels; 2064 indio_dev->num_channels = st->chip_info->num_channels; 2065 indio_dev->name = st->chip_info->name; 2066 indio_dev->info = &ad7380_info; 2067 indio_dev->modes = INDIO_DIRECT_MODE; 2068 indio_dev->available_scan_masks = st->chip_info->available_scan_masks; 2069 2070 st->offload = devm_spi_offload_get(dev, spi, &ad7380_offload_config); 2071 ret = PTR_ERR_OR_ZERO(st->offload); 2072 if (ret && ret != -ENODEV) 2073 return dev_err_probe(dev, ret, "failed to get offload\n"); 2074 2075 /* If no SPI offload, fall back to low speed usage. */ 2076 if (ret == -ENODEV) { 2077 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 2078 iio_pollfunc_store_time, 2079 ad7380_trigger_handler, 2080 &ad7380_buffer_setup_ops); 2081 if (ret) 2082 return ret; 2083 } else { 2084 ret = ad7380_probe_spi_offload(indio_dev, st); 2085 if (ret) 2086 return ret; 2087 } 2088 2089 ret = ad7380_init(st, external_ref_en); 2090 if (ret) 2091 return ret; 2092 2093 return devm_iio_device_register(dev, indio_dev); 2094 } 2095 2096 static const struct of_device_id ad7380_of_match_table[] = { 2097 { .compatible = "adi,ad7380", .data = &ad7380_chip_info }, 2098 { .compatible = "adi,ad7381", .data = &ad7381_chip_info }, 2099 { .compatible = "adi,ad7383", .data = &ad7383_chip_info }, 2100 { .compatible = "adi,ad7384", .data = &ad7384_chip_info }, 2101 { .compatible = "adi,ad7386", .data = &ad7386_chip_info }, 2102 { .compatible = "adi,ad7387", .data = &ad7387_chip_info }, 2103 { .compatible = "adi,ad7388", .data = &ad7388_chip_info }, 2104 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info }, 2105 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info }, 2106 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info }, 2107 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info }, 2108 { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info }, 2109 { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info }, 2110 { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info }, 2111 { .compatible = "adi,ad7389-4", .data = &ad7389_4_chip_info }, 2112 { .compatible = "adi,adaq4370-4", .data = &adaq4370_4_chip_info }, 2113 { .compatible = "adi,adaq4380-4", .data = &adaq4380_4_chip_info }, 2114 { .compatible = "adi,adaq4381-4", .data = &adaq4381_4_chip_info }, 2115 { } 2116 }; 2117 2118 static const struct spi_device_id ad7380_id_table[] = { 2119 { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, 2120 { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, 2121 { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, 2122 { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, 2123 { "ad7386", (kernel_ulong_t)&ad7386_chip_info }, 2124 { "ad7387", (kernel_ulong_t)&ad7387_chip_info }, 2125 { "ad7388", (kernel_ulong_t)&ad7388_chip_info }, 2126 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, 2127 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, 2128 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, 2129 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, 2130 { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info }, 2131 { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info }, 2132 { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info }, 2133 { "ad7389-4", (kernel_ulong_t)&ad7389_4_chip_info }, 2134 { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info }, 2135 { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info }, 2136 { "adaq4381-4", (kernel_ulong_t)&adaq4381_4_chip_info }, 2137 { } 2138 }; 2139 MODULE_DEVICE_TABLE(spi, ad7380_id_table); 2140 2141 static struct spi_driver ad7380_driver = { 2142 .driver = { 2143 .name = "ad7380", 2144 .of_match_table = ad7380_of_match_table, 2145 }, 2146 .probe = ad7380_probe, 2147 .id_table = ad7380_id_table, 2148 }; 2149 module_spi_driver(ad7380_driver); 2150 2151 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 2152 MODULE_DESCRIPTION("Analog Devices AD738x ADC driver"); 2153 MODULE_LICENSE("GPL"); 2154 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 2155