xref: /linux/drivers/iio/adc/ad7292.c (revision 06a130e42a5bfc84795464bff023bff4c16f58c5)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Analog Devices AD7292 SPI ADC driver
4  *
5  * Copyright 2019 Analog Devices Inc.
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/device.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/property.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/spi/spi.h>
15 
16 #include <linux/iio/iio.h>
17 
18 #define ADI_VENDOR_ID 0x0018
19 
20 #define AD7292_INTERNAL_REF_MV 1250
21 
22 /* AD7292 registers definition */
23 #define AD7292_REG_VENDOR_ID		0x00
24 #define AD7292_REG_CONF_BANK		0x05
25 #define AD7292_REG_CONV_COMM		0x0E
26 #define AD7292_REG_ADC_CH(x)		(0x10 + (x))
27 
28 /* AD7292 configuration bank subregisters definition */
29 #define AD7292_BANK_REG_VIN_RNG0	0x10
30 #define AD7292_BANK_REG_VIN_RNG1	0x11
31 #define AD7292_BANK_REG_SAMP_MODE	0x12
32 
33 #define AD7292_RD_FLAG_MSK(x)		(BIT(7) | ((x) & 0x3F))
34 
35 /* AD7292_REG_ADC_CONVERSION */
36 #define AD7292_ADC_DATA_MASK		GENMASK(15, 6)
37 #define AD7292_ADC_DATA(x)		FIELD_GET(AD7292_ADC_DATA_MASK, x)
38 
39 /* AD7292_CHANNEL_SAMPLING_MODE */
40 #define AD7292_CH_SAMP_MODE(reg, ch)	(((reg) >> 8) & BIT(ch))
41 
42 /* AD7292_CHANNEL_VIN_RANGE */
43 #define AD7292_CH_VIN_RANGE(reg, ch)	((reg) & BIT(ch))
44 
45 #define AD7292_VOLTAGE_CHAN(_chan)					\
46 {									\
47 	.type = IIO_VOLTAGE,						\
48 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
49 			      BIT(IIO_CHAN_INFO_SCALE),			\
50 	.indexed = 1,							\
51 	.channel = _chan,						\
52 }
53 
54 static const struct iio_chan_spec ad7292_channels[] = {
55 	AD7292_VOLTAGE_CHAN(0),
56 	AD7292_VOLTAGE_CHAN(1),
57 	AD7292_VOLTAGE_CHAN(2),
58 	AD7292_VOLTAGE_CHAN(3),
59 	AD7292_VOLTAGE_CHAN(4),
60 	AD7292_VOLTAGE_CHAN(5),
61 	AD7292_VOLTAGE_CHAN(6),
62 	AD7292_VOLTAGE_CHAN(7)
63 };
64 
65 static const struct iio_chan_spec ad7292_channels_diff[] = {
66 	{
67 		.type = IIO_VOLTAGE,
68 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
69 		.indexed = 1,
70 		.differential = 1,
71 		.channel = 0,
72 		.channel2 = 1,
73 	},
74 	AD7292_VOLTAGE_CHAN(2),
75 	AD7292_VOLTAGE_CHAN(3),
76 	AD7292_VOLTAGE_CHAN(4),
77 	AD7292_VOLTAGE_CHAN(5),
78 	AD7292_VOLTAGE_CHAN(6),
79 	AD7292_VOLTAGE_CHAN(7)
80 };
81 
82 struct ad7292_state {
83 	struct spi_device *spi;
84 	unsigned short vref_mv;
85 
86 	__be16 d16 __aligned(IIO_DMA_MINALIGN);
87 	u8 d8[2];
88 };
89 
90 static int ad7292_spi_reg_read(struct ad7292_state *st, unsigned int addr)
91 {
92 	int ret;
93 
94 	st->d8[0] = AD7292_RD_FLAG_MSK(addr);
95 
96 	ret = spi_write_then_read(st->spi, st->d8, 1, &st->d16, 2);
97 	if (ret < 0)
98 		return ret;
99 
100 	return be16_to_cpu(st->d16);
101 }
102 
103 static int ad7292_spi_subreg_read(struct ad7292_state *st, unsigned int addr,
104 				  unsigned int sub_addr, unsigned int len)
105 {
106 	unsigned int shift = 16 - (8 * len);
107 	int ret;
108 
109 	st->d8[0] = AD7292_RD_FLAG_MSK(addr);
110 	st->d8[1] = sub_addr;
111 
112 	ret = spi_write_then_read(st->spi, st->d8, 2, &st->d16, len);
113 	if (ret < 0)
114 		return ret;
115 
116 	return (be16_to_cpu(st->d16) >> shift);
117 }
118 
119 static int ad7292_single_conversion(struct ad7292_state *st,
120 				    unsigned int chan_addr)
121 {
122 	int ret;
123 
124 	struct spi_transfer t[] = {
125 		{
126 			.tx_buf = &st->d8,
127 			.len = 4,
128 			.delay = {
129 				.value = 6,
130 				.unit = SPI_DELAY_UNIT_USECS
131 			},
132 		}, {
133 			.rx_buf = &st->d16,
134 			.len = 2,
135 		},
136 	};
137 
138 	st->d8[0] = chan_addr;
139 	st->d8[1] = AD7292_RD_FLAG_MSK(AD7292_REG_CONV_COMM);
140 
141 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
142 
143 	if (ret < 0)
144 		return ret;
145 
146 	return be16_to_cpu(st->d16);
147 }
148 
149 static int ad7292_vin_range_multiplier(struct ad7292_state *st, int channel)
150 {
151 	int samp_mode, range0, range1, factor = 1;
152 
153 	/*
154 	 * Every AD7292 ADC channel may have its input range adjusted according
155 	 * to the settings at the ADC sampling mode and VIN range subregisters.
156 	 * For a given channel, the minimum input range is equal to Vref, and it
157 	 * may be increased by a multiplier factor of 2 or 4 according to the
158 	 * following rule:
159 	 * If channel is being sampled with respect to AGND:
160 	 *	factor = 4 if VIN range0 and VIN range1 equal 0
161 	 *	factor = 2 if only one of VIN ranges equal 1
162 	 *	factor = 1 if both VIN range0 and VIN range1 equal 1
163 	 * If channel is being sampled with respect to AVDD:
164 	 *	factor = 4 if VIN range0 and VIN range1 equal 0
165 	 *	Behavior is undefined if any of VIN range doesn't equal 0
166 	 */
167 
168 	samp_mode = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
169 					   AD7292_BANK_REG_SAMP_MODE, 2);
170 
171 	if (samp_mode < 0)
172 		return samp_mode;
173 
174 	range0 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
175 					AD7292_BANK_REG_VIN_RNG0, 2);
176 
177 	if (range0 < 0)
178 		return range0;
179 
180 	range1 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
181 					AD7292_BANK_REG_VIN_RNG1, 2);
182 
183 	if (range1 < 0)
184 		return range1;
185 
186 	if (AD7292_CH_SAMP_MODE(samp_mode, channel)) {
187 		/* Sampling with respect to AGND */
188 		if (!AD7292_CH_VIN_RANGE(range0, channel))
189 			factor *= 2;
190 
191 		if (!AD7292_CH_VIN_RANGE(range1, channel))
192 			factor *= 2;
193 
194 	} else {
195 		/* Sampling with respect to AVDD */
196 		if (AD7292_CH_VIN_RANGE(range0, channel) ||
197 		    AD7292_CH_VIN_RANGE(range1, channel))
198 			return -EPERM;
199 
200 		factor = 4;
201 	}
202 
203 	return factor;
204 }
205 
206 static int ad7292_read_raw(struct iio_dev *indio_dev,
207 			   const struct iio_chan_spec *chan,
208 			   int *val, int *val2, long info)
209 {
210 	struct ad7292_state *st = iio_priv(indio_dev);
211 	unsigned int ch_addr;
212 	int ret;
213 
214 	switch (info) {
215 	case IIO_CHAN_INFO_RAW:
216 		ch_addr = AD7292_REG_ADC_CH(chan->channel);
217 		ret = ad7292_single_conversion(st, ch_addr);
218 		if (ret < 0)
219 			return ret;
220 
221 		*val = AD7292_ADC_DATA(ret);
222 
223 		return IIO_VAL_INT;
224 	case IIO_CHAN_INFO_SCALE:
225 		/*
226 		 * To convert a raw value to standard units, the IIO defines
227 		 * this formula: Scaled value = (raw + offset) * scale.
228 		 * For the scale to be a correct multiplier for (raw + offset),
229 		 * it must be calculated as the input range divided by the
230 		 * number of possible distinct input values. Given the ADC data
231 		 * is 10 bit long, it may assume 2^10 distinct values.
232 		 * Hence, scale = range / 2^10. The IIO_VAL_FRACTIONAL_LOG2
233 		 * return type indicates to the IIO API to divide *val by 2 to
234 		 * the power of *val2 when returning from read_raw.
235 		 */
236 
237 		ret = ad7292_vin_range_multiplier(st, chan->channel);
238 		if (ret < 0)
239 			return ret;
240 
241 		*val = st->vref_mv * ret;
242 		*val2 = 10;
243 		return IIO_VAL_FRACTIONAL_LOG2;
244 	default:
245 		break;
246 	}
247 	return -EINVAL;
248 }
249 
250 static const struct iio_info ad7292_info = {
251 	.read_raw = ad7292_read_raw,
252 };
253 
254 static int ad7292_probe(struct spi_device *spi)
255 {
256 	struct ad7292_state *st;
257 	struct iio_dev *indio_dev;
258 	bool diff_channels = false;
259 	int ret;
260 
261 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
262 	if (!indio_dev)
263 		return -ENOMEM;
264 
265 	st = iio_priv(indio_dev);
266 	st->spi = spi;
267 
268 	ret = ad7292_spi_reg_read(st, AD7292_REG_VENDOR_ID);
269 	if (ret != ADI_VENDOR_ID) {
270 		dev_err(&spi->dev, "Wrong vendor id 0x%x\n", ret);
271 		return -EINVAL;
272 	}
273 
274 	ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vref");
275 	if (ret < 0 && ret != -ENODEV)
276 		return ret;
277 
278 	st->vref_mv = ret == -ENODEV ? AD7292_INTERNAL_REF_MV : ret / 1000;
279 
280 	indio_dev->name = spi_get_device_id(spi)->name;
281 	indio_dev->modes = INDIO_DIRECT_MODE;
282 	indio_dev->info = &ad7292_info;
283 
284 	device_for_each_child_node_scoped(&spi->dev, child) {
285 		diff_channels = fwnode_property_read_bool(child,
286 							  "diff-channels");
287 		if (diff_channels)
288 			break;
289 	}
290 
291 	if (diff_channels) {
292 		indio_dev->num_channels = ARRAY_SIZE(ad7292_channels_diff);
293 		indio_dev->channels = ad7292_channels_diff;
294 	} else {
295 		indio_dev->num_channels = ARRAY_SIZE(ad7292_channels);
296 		indio_dev->channels = ad7292_channels;
297 	}
298 
299 	return devm_iio_device_register(&spi->dev, indio_dev);
300 }
301 
302 static const struct spi_device_id ad7292_id_table[] = {
303 	{ "ad7292", 0 },
304 	{ }
305 };
306 MODULE_DEVICE_TABLE(spi, ad7292_id_table);
307 
308 static const struct of_device_id ad7292_of_match[] = {
309 	{ .compatible = "adi,ad7292" },
310 	{ }
311 };
312 MODULE_DEVICE_TABLE(of, ad7292_of_match);
313 
314 static struct spi_driver ad7292_driver = {
315 	.driver = {
316 		.name = "ad7292",
317 		.of_match_table = ad7292_of_match,
318 	},
319 	.probe = ad7292_probe,
320 	.id_table = ad7292_id_table,
321 };
322 module_spi_driver(ad7292_driver);
323 
324 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt1@gmail.com>");
325 MODULE_DESCRIPTION("Analog Devices AD7292 ADC driver");
326 MODULE_LICENSE("GPL v2");
327