1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver 4 * 5 * Copyright 2011-2015 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/kernel.h> 13 #include <linux/slab.h> 14 #include <linux/sysfs.h> 15 #include <linux/spi/spi.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/err.h> 18 #include <linux/sched.h> 19 #include <linux/delay.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/property.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/sysfs.h> 26 #include <linux/iio/buffer.h> 27 #include <linux/iio/trigger.h> 28 #include <linux/iio/trigger_consumer.h> 29 #include <linux/iio/triggered_buffer.h> 30 #include <linux/iio/adc/ad_sigma_delta.h> 31 32 /* Registers */ 33 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 34 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 35 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 36 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 37 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 38 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 39 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ 40 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ 41 /* (AD7792)/24-bit (AD7192)) */ 42 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ 43 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 44 45 /* Communications Register Bit Designations (AD7192_REG_COMM) */ 46 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 47 #define AD7192_COMM_WRITE 0 /* Write Operation */ 48 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 49 #define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */ 50 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 51 52 /* Status Register Bit Designations (AD7192_REG_STAT) */ 53 #define AD7192_STAT_RDY BIT(7) /* Ready */ 54 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ 55 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ 56 #define AD7192_STAT_PARITY BIT(4) /* Parity */ 57 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ 58 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ 59 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 60 61 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 62 #define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */ 63 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ 64 #define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */ 65 #define AD7192_MODE_AVG_MASK GENMASK(17, 16) 66 /* Fast Settling Filter Average Select Mask (AD7193 only) */ 67 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 68 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 69 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 70 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 71 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 72 /* Filter Update Rate Select Mask */ 73 #define AD7192_MODE_RATE_MASK GENMASK(9, 0) 74 75 /* Mode Register: AD7192_MODE_SEL options */ 76 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 77 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 78 #define AD7192_MODE_IDLE 2 /* Idle Mode */ 79 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 80 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 81 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 82 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 83 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 84 85 /* Mode Register: AD7192_MODE_CLKSRC options */ 86 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ 87 /* from MCLK1 to MCLK2 */ 88 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 89 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ 90 /* available at the MCLK2 pin */ 91 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ 92 /* at the MCLK2 pin */ 93 94 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 95 96 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 97 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */ 98 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 99 #define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */ 100 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 101 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 102 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 103 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 104 #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */ 105 106 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 107 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ 108 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ 109 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ 110 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ 111 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ 112 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ 113 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ 114 115 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */ 116 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */ 117 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */ 118 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */ 119 #define AD7193_CH_TEMP 0x100 /* Temp senseor */ 120 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */ 121 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */ 122 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */ 123 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */ 124 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */ 125 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */ 126 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */ 127 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */ 128 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ 129 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 130 131 /* ID Register Bit Designations (AD7192_REG_ID) */ 132 #define CHIPID_AD7190 0x4 133 #define CHIPID_AD7192 0x0 134 #define CHIPID_AD7193 0x2 135 #define CHIPID_AD7195 0x6 136 #define AD7192_ID_MASK GENMASK(3, 0) 137 138 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 139 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ 140 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ 141 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ 142 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ 143 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ 144 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ 145 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ 146 147 #define AD7192_EXT_FREQ_MHZ_MIN 2457600 148 #define AD7192_EXT_FREQ_MHZ_MAX 5120000 149 #define AD7192_INT_FREQ_MHZ 4915200 150 151 #define AD7192_NO_SYNC_FILTER 1 152 #define AD7192_SYNC3_FILTER 3 153 #define AD7192_SYNC4_FILTER 4 154 155 /* NOTE: 156 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 157 * In order to avoid contentions on the SPI bus, it's therefore necessary 158 * to use spi bus locking. 159 * 160 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 161 */ 162 163 enum { 164 AD7192_SYSCALIB_ZERO_SCALE, 165 AD7192_SYSCALIB_FULL_SCALE, 166 }; 167 168 enum { 169 ID_AD7190, 170 ID_AD7192, 171 ID_AD7193, 172 ID_AD7195, 173 }; 174 175 struct ad7192_chip_info { 176 unsigned int chip_id; 177 const char *name; 178 const struct iio_chan_spec *channels; 179 u8 num_channels; 180 const struct iio_info *info; 181 }; 182 183 struct ad7192_state { 184 const struct ad7192_chip_info *chip_info; 185 struct regulator *avdd; 186 struct regulator *vref; 187 struct clk *mclk; 188 u16 int_vref_mv; 189 u32 fclk; 190 u32 mode; 191 u32 conf; 192 u32 scale_avail[8][2]; 193 u32 oversampling_ratio_avail[4]; 194 u8 gpocon; 195 u8 clock_sel; 196 struct mutex lock; /* protect sensor state */ 197 u8 syscalib_mode[8]; 198 199 struct ad_sigma_delta sd; 200 }; 201 202 static const char * const ad7192_syscalib_modes[] = { 203 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale", 204 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale", 205 }; 206 207 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, 208 const struct iio_chan_spec *chan, 209 unsigned int mode) 210 { 211 struct ad7192_state *st = iio_priv(indio_dev); 212 213 st->syscalib_mode[chan->channel] = mode; 214 215 return 0; 216 } 217 218 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, 219 const struct iio_chan_spec *chan) 220 { 221 struct ad7192_state *st = iio_priv(indio_dev); 222 223 return st->syscalib_mode[chan->channel]; 224 } 225 226 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, 227 uintptr_t private, 228 const struct iio_chan_spec *chan, 229 const char *buf, size_t len) 230 { 231 struct ad7192_state *st = iio_priv(indio_dev); 232 bool sys_calib; 233 int ret, temp; 234 235 ret = kstrtobool(buf, &sys_calib); 236 if (ret) 237 return ret; 238 239 temp = st->syscalib_mode[chan->channel]; 240 if (sys_calib) { 241 if (temp == AD7192_SYSCALIB_ZERO_SCALE) 242 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, 243 chan->address); 244 else 245 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, 246 chan->address); 247 } 248 249 return ret ? ret : len; 250 } 251 252 static const struct iio_enum ad7192_syscalib_mode_enum = { 253 .items = ad7192_syscalib_modes, 254 .num_items = ARRAY_SIZE(ad7192_syscalib_modes), 255 .set = ad7192_set_syscalib_mode, 256 .get = ad7192_get_syscalib_mode 257 }; 258 259 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = { 260 { 261 .name = "sys_calibration", 262 .write = ad7192_write_syscalib, 263 .shared = IIO_SEPARATE, 264 }, 265 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 266 &ad7192_syscalib_mode_enum), 267 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 268 &ad7192_syscalib_mode_enum), 269 {} 270 }; 271 272 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) 273 { 274 return container_of(sd, struct ad7192_state, sd); 275 } 276 277 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 278 { 279 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 280 281 st->conf &= ~AD7192_CONF_CHAN_MASK; 282 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); 283 284 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 285 } 286 287 static int ad7192_set_mode(struct ad_sigma_delta *sd, 288 enum ad_sigma_delta_mode mode) 289 { 290 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 291 292 st->mode &= ~AD7192_MODE_SEL_MASK; 293 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); 294 295 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 296 } 297 298 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append) 299 { 300 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 301 unsigned int mode = st->mode; 302 int ret; 303 304 mode &= ~AD7192_MODE_STA_MASK; 305 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append); 306 307 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); 308 if (ret < 0) 309 return ret; 310 311 st->mode = mode; 312 313 return 0; 314 } 315 316 static int ad7192_disable_all(struct ad_sigma_delta *sd) 317 { 318 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 319 u32 conf = st->conf; 320 int ret; 321 322 conf &= ~AD7192_CONF_CHAN_MASK; 323 324 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 325 if (ret < 0) 326 return ret; 327 328 st->conf = conf; 329 330 return 0; 331 } 332 333 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { 334 .set_channel = ad7192_set_channel, 335 .append_status = ad7192_append_status, 336 .disable_all = ad7192_disable_all, 337 .set_mode = ad7192_set_mode, 338 .has_registers = true, 339 .addr_shift = 3, 340 .read_mask = BIT(6), 341 .status_ch_mask = GENMASK(3, 0), 342 .num_slots = 4, 343 .irq_flags = IRQF_TRIGGER_FALLING, 344 }; 345 346 static const struct ad_sd_calib_data ad7192_calib_arr[8] = { 347 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 348 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 349 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 350 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 351 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 352 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 353 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 354 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 355 }; 356 357 static int ad7192_calibrate_all(struct ad7192_state *st) 358 { 359 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, 360 ARRAY_SIZE(ad7192_calib_arr)); 361 } 362 363 static inline bool ad7192_valid_external_frequency(u32 freq) 364 { 365 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && 366 freq <= AD7192_EXT_FREQ_MHZ_MAX); 367 } 368 369 static int ad7192_clock_select(struct ad7192_state *st) 370 { 371 struct device *dev = &st->sd.spi->dev; 372 unsigned int clock_sel; 373 374 clock_sel = AD7192_CLK_INT; 375 376 /* use internal clock */ 377 if (!st->mclk) { 378 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) 379 clock_sel = AD7192_CLK_INT_CO; 380 } else { 381 if (device_property_read_bool(dev, "adi,clock-xtal")) 382 clock_sel = AD7192_CLK_EXT_MCLK1_2; 383 else 384 clock_sel = AD7192_CLK_EXT_MCLK2; 385 } 386 387 return clock_sel; 388 } 389 390 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) 391 { 392 struct ad7192_state *st = iio_priv(indio_dev); 393 bool rej60_en, refin2_en; 394 bool buf_en, bipolar, burnout_curr_en; 395 unsigned long long scale_uv; 396 int i, ret, id; 397 398 /* reset the serial interface */ 399 ret = ad_sd_reset(&st->sd, 48); 400 if (ret < 0) 401 return ret; 402 usleep_range(500, 1000); /* Wait for at least 500us */ 403 404 /* write/read test for device presence */ 405 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); 406 if (ret) 407 return ret; 408 409 id = FIELD_GET(AD7192_ID_MASK, id); 410 411 if (id != st->chip_info->chip_id) 412 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n", 413 id, st->chip_info->chip_id); 414 415 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | 416 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | 417 FIELD_PREP(AD7192_MODE_RATE_MASK, 480); 418 419 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); 420 421 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable"); 422 if (rej60_en) 423 st->mode |= AD7192_MODE_REJ60; 424 425 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable"); 426 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 427 st->conf |= AD7192_CONF_REFSEL; 428 429 st->conf &= ~AD7192_CONF_CHOP; 430 431 buf_en = device_property_read_bool(dev, "adi,buffer-enable"); 432 if (buf_en) 433 st->conf |= AD7192_CONF_BUF; 434 435 bipolar = device_property_read_bool(dev, "bipolar"); 436 if (!bipolar) 437 st->conf |= AD7192_CONF_UNIPOLAR; 438 439 burnout_curr_en = device_property_read_bool(dev, 440 "adi,burnout-currents-enable"); 441 if (burnout_curr_en && buf_en) { 442 st->conf |= AD7192_CONF_BURN; 443 } else if (burnout_curr_en) { 444 dev_warn(dev, 445 "Can't enable burnout currents: see CHOP or buffer\n"); 446 } 447 448 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 449 if (ret) 450 return ret; 451 452 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 453 if (ret) 454 return ret; 455 456 ret = ad7192_calibrate_all(st); 457 if (ret) 458 return ret; 459 460 /* Populate available ADC input ranges */ 461 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 462 scale_uv = ((u64)st->int_vref_mv * 100000000) 463 >> (indio_dev->channels[0].scan_type.realbits - 464 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); 465 scale_uv >>= i; 466 467 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 468 st->scale_avail[i][0] = scale_uv; 469 } 470 471 st->oversampling_ratio_avail[0] = 1; 472 st->oversampling_ratio_avail[1] = 2; 473 st->oversampling_ratio_avail[2] = 8; 474 st->oversampling_ratio_avail[3] = 16; 475 476 return 0; 477 } 478 479 static ssize_t ad7192_show_ac_excitation(struct device *dev, 480 struct device_attribute *attr, 481 char *buf) 482 { 483 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 484 struct ad7192_state *st = iio_priv(indio_dev); 485 486 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); 487 } 488 489 static ssize_t ad7192_show_bridge_switch(struct device *dev, 490 struct device_attribute *attr, 491 char *buf) 492 { 493 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 494 struct ad7192_state *st = iio_priv(indio_dev); 495 496 return sysfs_emit(buf, "%ld\n", 497 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); 498 } 499 500 static ssize_t ad7192_set(struct device *dev, 501 struct device_attribute *attr, 502 const char *buf, 503 size_t len) 504 { 505 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 506 struct ad7192_state *st = iio_priv(indio_dev); 507 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 508 int ret; 509 bool val; 510 511 ret = kstrtobool(buf, &val); 512 if (ret < 0) 513 return ret; 514 515 ret = iio_device_claim_direct_mode(indio_dev); 516 if (ret) 517 return ret; 518 519 switch ((u32)this_attr->address) { 520 case AD7192_REG_GPOCON: 521 if (val) 522 st->gpocon |= AD7192_GPOCON_BPDSW; 523 else 524 st->gpocon &= ~AD7192_GPOCON_BPDSW; 525 526 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 527 break; 528 case AD7192_REG_CONF: 529 if (val) 530 st->conf |= AD7192_CONF_ACX; 531 else 532 st->conf &= ~AD7192_CONF_ACX; 533 534 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 535 break; 536 default: 537 ret = -EINVAL; 538 } 539 540 iio_device_release_direct_mode(indio_dev); 541 542 return ret ? ret : len; 543 } 544 545 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) 546 { 547 u8 avg_factor_selected, oversampling_ratio; 548 549 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); 550 551 if (!avg_factor_selected && !chop_en) 552 return 1; 553 554 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; 555 556 if (sinc3_en) 557 return AD7192_SYNC3_FILTER + oversampling_ratio - 1; 558 559 return AD7192_SYNC4_FILTER + oversampling_ratio - 1; 560 } 561 562 static int ad7192_get_f_order(struct ad7192_state *st) 563 { 564 bool sinc3_en, chop_en; 565 566 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); 567 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); 568 569 return ad7192_compute_f_order(st, sinc3_en, chop_en); 570 } 571 572 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, 573 bool chop_en) 574 { 575 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en); 576 577 return DIV_ROUND_CLOSEST(st->fclk, 578 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 579 } 580 581 static int ad7192_get_f_adc(struct ad7192_state *st) 582 { 583 unsigned int f_order = ad7192_get_f_order(st); 584 585 return DIV_ROUND_CLOSEST(st->fclk, 586 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 587 } 588 589 static void ad7192_get_available_filter_freq(struct ad7192_state *st, 590 int *freq) 591 { 592 unsigned int fadc; 593 594 /* Formulas for filter at page 25 of the datasheet */ 595 fadc = ad7192_compute_f_adc(st, false, true); 596 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 597 598 fadc = ad7192_compute_f_adc(st, true, true); 599 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 600 601 fadc = ad7192_compute_f_adc(st, false, false); 602 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 603 604 fadc = ad7192_compute_f_adc(st, true, false); 605 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 606 } 607 608 static ssize_t ad7192_show_filter_avail(struct device *dev, 609 struct device_attribute *attr, 610 char *buf) 611 { 612 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 613 struct ad7192_state *st = iio_priv(indio_dev); 614 unsigned int freq_avail[4], i; 615 size_t len = 0; 616 617 ad7192_get_available_filter_freq(st, freq_avail); 618 619 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) 620 len += sysfs_emit_at(buf, len, "%d.%03d ", freq_avail[i] / 1000, 621 freq_avail[i] % 1000); 622 623 buf[len - 1] = '\n'; 624 625 return len; 626 } 627 628 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available, 629 0444, ad7192_show_filter_avail, NULL, 0); 630 631 static IIO_DEVICE_ATTR(bridge_switch_en, 0644, 632 ad7192_show_bridge_switch, ad7192_set, 633 AD7192_REG_GPOCON); 634 635 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 636 ad7192_show_ac_excitation, ad7192_set, 637 AD7192_REG_CONF); 638 639 static struct attribute *ad7192_attributes[] = { 640 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 641 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 642 NULL 643 }; 644 645 static const struct attribute_group ad7192_attribute_group = { 646 .attrs = ad7192_attributes, 647 }; 648 649 static struct attribute *ad7195_attributes[] = { 650 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 651 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 652 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 653 NULL 654 }; 655 656 static const struct attribute_group ad7195_attribute_group = { 657 .attrs = ad7195_attributes, 658 }; 659 660 static unsigned int ad7192_get_temp_scale(bool unipolar) 661 { 662 return unipolar ? 2815 * 2 : 2815; 663 } 664 665 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, 666 int val, int val2) 667 { 668 int freq_avail[4], i, ret, freq; 669 unsigned int diff_new, diff_old; 670 int idx = 0; 671 672 diff_old = U32_MAX; 673 freq = val * 1000 + val2; 674 675 ad7192_get_available_filter_freq(st, freq_avail); 676 677 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) { 678 diff_new = abs(freq - freq_avail[i]); 679 if (diff_new < diff_old) { 680 diff_old = diff_new; 681 idx = i; 682 } 683 } 684 685 switch (idx) { 686 case 0: 687 st->mode &= ~AD7192_MODE_SINC3; 688 689 st->conf |= AD7192_CONF_CHOP; 690 break; 691 case 1: 692 st->mode |= AD7192_MODE_SINC3; 693 694 st->conf |= AD7192_CONF_CHOP; 695 break; 696 case 2: 697 st->mode &= ~AD7192_MODE_SINC3; 698 699 st->conf &= ~AD7192_CONF_CHOP; 700 break; 701 case 3: 702 st->mode |= AD7192_MODE_SINC3; 703 704 st->conf &= ~AD7192_CONF_CHOP; 705 break; 706 } 707 708 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 709 if (ret < 0) 710 return ret; 711 712 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 713 } 714 715 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) 716 { 717 unsigned int fadc; 718 719 fadc = ad7192_get_f_adc(st); 720 721 if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) 722 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 723 if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) 724 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 725 else 726 return DIV_ROUND_CLOSEST(fadc * 230, 1024); 727 } 728 729 static int ad7192_read_raw(struct iio_dev *indio_dev, 730 struct iio_chan_spec const *chan, 731 int *val, 732 int *val2, 733 long m) 734 { 735 struct ad7192_state *st = iio_priv(indio_dev); 736 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); 737 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); 738 739 switch (m) { 740 case IIO_CHAN_INFO_RAW: 741 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 742 case IIO_CHAN_INFO_SCALE: 743 switch (chan->type) { 744 case IIO_VOLTAGE: 745 mutex_lock(&st->lock); 746 *val = st->scale_avail[gain][0]; 747 *val2 = st->scale_avail[gain][1]; 748 mutex_unlock(&st->lock); 749 return IIO_VAL_INT_PLUS_NANO; 750 case IIO_TEMP: 751 *val = 0; 752 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar); 753 return IIO_VAL_INT_PLUS_NANO; 754 default: 755 return -EINVAL; 756 } 757 case IIO_CHAN_INFO_OFFSET: 758 if (!unipolar) 759 *val = -(1 << (chan->scan_type.realbits - 1)); 760 else 761 *val = 0; 762 /* Kelvin to Celsius */ 763 if (chan->type == IIO_TEMP) 764 *val -= 273 * ad7192_get_temp_scale(unipolar); 765 return IIO_VAL_INT; 766 case IIO_CHAN_INFO_SAMP_FREQ: 767 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); 768 return IIO_VAL_INT; 769 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 770 *val = ad7192_get_3db_filter_freq(st); 771 *val2 = 1000; 772 return IIO_VAL_FRACTIONAL; 773 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 774 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; 775 return IIO_VAL_INT; 776 } 777 778 return -EINVAL; 779 } 780 781 static int ad7192_write_raw(struct iio_dev *indio_dev, 782 struct iio_chan_spec const *chan, 783 int val, 784 int val2, 785 long mask) 786 { 787 struct ad7192_state *st = iio_priv(indio_dev); 788 int ret, i, div; 789 unsigned int tmp; 790 791 ret = iio_device_claim_direct_mode(indio_dev); 792 if (ret) 793 return ret; 794 795 switch (mask) { 796 case IIO_CHAN_INFO_SCALE: 797 ret = -EINVAL; 798 mutex_lock(&st->lock); 799 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 800 if (val2 == st->scale_avail[i][1]) { 801 ret = 0; 802 tmp = st->conf; 803 st->conf &= ~AD7192_CONF_GAIN_MASK; 804 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); 805 if (tmp == st->conf) 806 break; 807 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 808 3, st->conf); 809 ad7192_calibrate_all(st); 810 break; 811 } 812 mutex_unlock(&st->lock); 813 break; 814 case IIO_CHAN_INFO_SAMP_FREQ: 815 if (!val) { 816 ret = -EINVAL; 817 break; 818 } 819 820 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); 821 if (div < 1 || div > 1023) { 822 ret = -EINVAL; 823 break; 824 } 825 826 st->mode &= ~AD7192_MODE_RATE_MASK; 827 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); 828 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 829 break; 830 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 831 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); 832 break; 833 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 834 ret = -EINVAL; 835 mutex_lock(&st->lock); 836 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) 837 if (val == st->oversampling_ratio_avail[i]) { 838 ret = 0; 839 tmp = st->mode; 840 st->mode &= ~AD7192_MODE_AVG_MASK; 841 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); 842 if (tmp == st->mode) 843 break; 844 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 845 3, st->mode); 846 break; 847 } 848 mutex_unlock(&st->lock); 849 break; 850 default: 851 ret = -EINVAL; 852 } 853 854 iio_device_release_direct_mode(indio_dev); 855 856 return ret; 857 } 858 859 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 860 struct iio_chan_spec const *chan, 861 long mask) 862 { 863 switch (mask) { 864 case IIO_CHAN_INFO_SCALE: 865 return IIO_VAL_INT_PLUS_NANO; 866 case IIO_CHAN_INFO_SAMP_FREQ: 867 return IIO_VAL_INT; 868 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 869 return IIO_VAL_INT_PLUS_MICRO; 870 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 871 return IIO_VAL_INT; 872 default: 873 return -EINVAL; 874 } 875 } 876 877 static int ad7192_read_avail(struct iio_dev *indio_dev, 878 struct iio_chan_spec const *chan, 879 const int **vals, int *type, int *length, 880 long mask) 881 { 882 struct ad7192_state *st = iio_priv(indio_dev); 883 884 switch (mask) { 885 case IIO_CHAN_INFO_SCALE: 886 *vals = (int *)st->scale_avail; 887 *type = IIO_VAL_INT_PLUS_NANO; 888 /* Values are stored in a 2D matrix */ 889 *length = ARRAY_SIZE(st->scale_avail) * 2; 890 891 return IIO_AVAIL_LIST; 892 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 893 *vals = (int *)st->oversampling_ratio_avail; 894 *type = IIO_VAL_INT; 895 *length = ARRAY_SIZE(st->oversampling_ratio_avail); 896 897 return IIO_AVAIL_LIST; 898 } 899 900 return -EINVAL; 901 } 902 903 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) 904 { 905 struct ad7192_state *st = iio_priv(indio_dev); 906 u32 conf = st->conf; 907 int ret; 908 int i; 909 910 conf &= ~AD7192_CONF_CHAN_MASK; 911 for_each_set_bit(i, scan_mask, 8) 912 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, i); 913 914 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 915 if (ret < 0) 916 return ret; 917 918 st->conf = conf; 919 920 return 0; 921 } 922 923 static const struct iio_info ad7192_info = { 924 .read_raw = ad7192_read_raw, 925 .write_raw = ad7192_write_raw, 926 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 927 .read_avail = ad7192_read_avail, 928 .attrs = &ad7192_attribute_group, 929 .validate_trigger = ad_sd_validate_trigger, 930 .update_scan_mode = ad7192_update_scan_mode, 931 }; 932 933 static const struct iio_info ad7195_info = { 934 .read_raw = ad7192_read_raw, 935 .write_raw = ad7192_write_raw, 936 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 937 .read_avail = ad7192_read_avail, 938 .attrs = &ad7195_attribute_group, 939 .validate_trigger = ad_sd_validate_trigger, 940 .update_scan_mode = ad7192_update_scan_mode, 941 }; 942 943 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \ 944 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \ 945 { \ 946 .type = (_type), \ 947 .differential = ((_channel2) == -1 ? 0 : 1), \ 948 .indexed = 1, \ 949 .channel = (_channel1), \ 950 .channel2 = (_channel2), \ 951 .address = (_address), \ 952 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 953 BIT(IIO_CHAN_INFO_OFFSET), \ 954 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 955 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 956 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 957 (_mask_all), \ 958 .info_mask_shared_by_type_available = (_mask_type_av), \ 959 .info_mask_shared_by_all_available = (_mask_all_av), \ 960 .ext_info = (_ext_info), \ 961 .scan_index = (_si), \ 962 .scan_type = { \ 963 .sign = 'u', \ 964 .realbits = 24, \ 965 .storagebits = 32, \ 966 .endianness = IIO_BE, \ 967 }, \ 968 } 969 970 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 971 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \ 972 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 973 974 #define AD719x_CHANNEL(_si, _channel1, _address) \ 975 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \ 976 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 977 978 #define AD719x_TEMP_CHANNEL(_si, _address) \ 979 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL) 980 981 #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 982 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \ 983 IIO_VOLTAGE, \ 984 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 985 BIT(IIO_CHAN_INFO_SCALE), \ 986 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 987 ad7192_calibsys_ext_info) 988 989 #define AD7193_CHANNEL(_si, _channel1, _address) \ 990 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address) 991 992 static const struct iio_chan_spec ad7192_channels[] = { 993 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), 994 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M), 995 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP), 996 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M), 997 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1), 998 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2), 999 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3), 1000 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4), 1001 IIO_CHAN_SOFT_TIMESTAMP(8), 1002 }; 1003 1004 static const struct iio_chan_spec ad7193_channels[] = { 1005 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 1006 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 1007 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 1008 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 1009 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 1010 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M), 1011 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1), 1012 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2), 1013 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3), 1014 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4), 1015 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5), 1016 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6), 1017 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7), 1018 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8), 1019 IIO_CHAN_SOFT_TIMESTAMP(14), 1020 }; 1021 1022 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 1023 [ID_AD7190] = { 1024 .chip_id = CHIPID_AD7190, 1025 .name = "ad7190", 1026 .channels = ad7192_channels, 1027 .num_channels = ARRAY_SIZE(ad7192_channels), 1028 .info = &ad7192_info, 1029 }, 1030 [ID_AD7192] = { 1031 .chip_id = CHIPID_AD7192, 1032 .name = "ad7192", 1033 .channels = ad7192_channels, 1034 .num_channels = ARRAY_SIZE(ad7192_channels), 1035 .info = &ad7192_info, 1036 }, 1037 [ID_AD7193] = { 1038 .chip_id = CHIPID_AD7193, 1039 .name = "ad7193", 1040 .channels = ad7193_channels, 1041 .num_channels = ARRAY_SIZE(ad7193_channels), 1042 .info = &ad7192_info, 1043 }, 1044 [ID_AD7195] = { 1045 .chip_id = CHIPID_AD7195, 1046 .name = "ad7195", 1047 .channels = ad7192_channels, 1048 .num_channels = ARRAY_SIZE(ad7192_channels), 1049 .info = &ad7195_info, 1050 }, 1051 }; 1052 1053 static void ad7192_reg_disable(void *reg) 1054 { 1055 regulator_disable(reg); 1056 } 1057 1058 static int ad7192_probe(struct spi_device *spi) 1059 { 1060 struct ad7192_state *st; 1061 struct iio_dev *indio_dev; 1062 int ret; 1063 1064 if (!spi->irq) { 1065 dev_err(&spi->dev, "no IRQ?\n"); 1066 return -ENODEV; 1067 } 1068 1069 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1070 if (!indio_dev) 1071 return -ENOMEM; 1072 1073 st = iio_priv(indio_dev); 1074 1075 mutex_init(&st->lock); 1076 1077 st->avdd = devm_regulator_get(&spi->dev, "avdd"); 1078 if (IS_ERR(st->avdd)) 1079 return PTR_ERR(st->avdd); 1080 1081 ret = regulator_enable(st->avdd); 1082 if (ret) { 1083 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); 1084 return ret; 1085 } 1086 1087 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); 1088 if (ret) 1089 return ret; 1090 1091 ret = devm_regulator_get_enable(&spi->dev, "dvdd"); 1092 if (ret) 1093 return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n"); 1094 1095 st->vref = devm_regulator_get_optional(&spi->dev, "vref"); 1096 if (IS_ERR(st->vref)) { 1097 if (PTR_ERR(st->vref) != -ENODEV) 1098 return PTR_ERR(st->vref); 1099 1100 ret = regulator_get_voltage(st->avdd); 1101 if (ret < 0) 1102 return dev_err_probe(&spi->dev, ret, 1103 "Device tree error, AVdd voltage undefined\n"); 1104 } else { 1105 ret = regulator_enable(st->vref); 1106 if (ret) { 1107 dev_err(&spi->dev, "Failed to enable specified Vref supply\n"); 1108 return ret; 1109 } 1110 1111 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->vref); 1112 if (ret) 1113 return ret; 1114 1115 ret = regulator_get_voltage(st->vref); 1116 if (ret < 0) 1117 return dev_err_probe(&spi->dev, ret, 1118 "Device tree error, Vref voltage undefined\n"); 1119 } 1120 st->int_vref_mv = ret / 1000; 1121 1122 st->chip_info = spi_get_device_match_data(spi); 1123 indio_dev->name = st->chip_info->name; 1124 indio_dev->modes = INDIO_DIRECT_MODE; 1125 indio_dev->channels = st->chip_info->channels; 1126 indio_dev->num_channels = st->chip_info->num_channels; 1127 indio_dev->info = st->chip_info->info; 1128 1129 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); 1130 if (ret) 1131 return ret; 1132 1133 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 1134 if (ret) 1135 return ret; 1136 1137 st->fclk = AD7192_INT_FREQ_MHZ; 1138 1139 st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk"); 1140 if (IS_ERR(st->mclk)) 1141 return PTR_ERR(st->mclk); 1142 1143 st->clock_sel = ad7192_clock_select(st); 1144 1145 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || 1146 st->clock_sel == AD7192_CLK_EXT_MCLK2) { 1147 st->fclk = clk_get_rate(st->mclk); 1148 if (!ad7192_valid_external_frequency(st->fclk)) { 1149 dev_err(&spi->dev, 1150 "External clock frequency out of bounds\n"); 1151 return -EINVAL; 1152 } 1153 } 1154 1155 ret = ad7192_setup(indio_dev, &spi->dev); 1156 if (ret) 1157 return ret; 1158 1159 return devm_iio_device_register(&spi->dev, indio_dev); 1160 } 1161 1162 static const struct of_device_id ad7192_of_match[] = { 1163 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 1164 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 1165 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 1166 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 1167 {} 1168 }; 1169 MODULE_DEVICE_TABLE(of, ad7192_of_match); 1170 1171 static const struct spi_device_id ad7192_ids[] = { 1172 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] }, 1173 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] }, 1174 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] }, 1175 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] }, 1176 {} 1177 }; 1178 MODULE_DEVICE_TABLE(spi, ad7192_ids); 1179 1180 static struct spi_driver ad7192_driver = { 1181 .driver = { 1182 .name = "ad7192", 1183 .of_match_table = ad7192_of_match, 1184 }, 1185 .probe = ad7192_probe, 1186 .id_table = ad7192_ids, 1187 }; 1188 module_spi_driver(ad7192_driver); 1189 1190 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1191 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC"); 1192 MODULE_LICENSE("GPL v2"); 1193 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1194