xref: /linux/drivers/iio/adc/ad7192.c (revision 4b132aacb0768ac1e652cf517097ea6f237214b9)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * AD7192 and similar SPI ADC driver
4  *
5  * Copyright 2011-2015 Analog Devices Inc.
6  */
7 
8 #include <linux/interrupt.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/sysfs.h>
15 #include <linux/spi/spi.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/err.h>
18 #include <linux/sched.h>
19 #include <linux/delay.h>
20 #include <linux/module.h>
21 #include <linux/mod_devicetable.h>
22 #include <linux/property.h>
23 #include <linux/units.h>
24 
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/adc/ad_sigma_delta.h>
32 
33 /* Registers */
34 #define AD7192_REG_COMM		0 /* Communications Register (WO, 8-bit) */
35 #define AD7192_REG_STAT		0 /* Status Register	     (RO, 8-bit) */
36 #define AD7192_REG_MODE		1 /* Mode Register	     (RW, 24-bit */
37 #define AD7192_REG_CONF		2 /* Configuration Register  (RW, 24-bit) */
38 #define AD7192_REG_DATA		3 /* Data Register	     (RO, 24/32-bit) */
39 #define AD7192_REG_ID		4 /* ID Register	     (RO, 8-bit) */
40 #define AD7192_REG_GPOCON	5 /* GPOCON Register	     (RO, 8-bit) */
41 #define AD7192_REG_OFFSET	6 /* Offset Register	     (RW, 16-bit */
42 				  /* (AD7792)/24-bit (AD7192)) */
43 #define AD7192_REG_FULLSALE	7 /* Full-Scale Register */
44 				  /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
45 
46 /* Communications Register Bit Designations (AD7192_REG_COMM) */
47 #define AD7192_COMM_WEN		BIT(7) /* Write Enable */
48 #define AD7192_COMM_WRITE	0 /* Write Operation */
49 #define AD7192_COMM_READ	BIT(6) /* Read Operation */
50 #define AD7192_COMM_ADDR_MASK	GENMASK(5, 3) /* Register Address Mask */
51 #define AD7192_COMM_CREAD	BIT(2) /* Continuous Read of Data Register */
52 
53 /* Status Register Bit Designations (AD7192_REG_STAT) */
54 #define AD7192_STAT_RDY		BIT(7) /* Ready */
55 #define AD7192_STAT_ERR		BIT(6) /* Error (Overrange, Underrange) */
56 #define AD7192_STAT_NOREF	BIT(5) /* Error no external reference */
57 #define AD7192_STAT_PARITY	BIT(4) /* Parity */
58 #define AD7192_STAT_CH3		BIT(2) /* Channel 3 */
59 #define AD7192_STAT_CH2		BIT(1) /* Channel 2 */
60 #define AD7192_STAT_CH1		BIT(0) /* Channel 1 */
61 
62 /* Mode Register Bit Designations (AD7192_REG_MODE) */
63 #define AD7192_MODE_SEL_MASK	GENMASK(23, 21) /* Operation Mode Select Mask */
64 #define AD7192_MODE_STA_MASK	BIT(20) /* Status Register transmission Mask */
65 #define AD7192_MODE_CLKSRC_MASK	GENMASK(19, 18) /* Clock Source Select Mask */
66 #define AD7192_MODE_AVG_MASK	GENMASK(17, 16)
67 		  /* Fast Settling Filter Average Select Mask (AD7193 only) */
68 #define AD7192_MODE_SINC3	BIT(15) /* SINC3 Filter Select */
69 #define AD7192_MODE_ENPAR	BIT(13) /* Parity Enable */
70 #define AD7192_MODE_CLKDIV	BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
71 #define AD7192_MODE_SCYCLE	BIT(11) /* Single cycle conversion */
72 #define AD7192_MODE_REJ60	BIT(10) /* 50/60Hz notch filter */
73 				  /* Filter Update Rate Select Mask */
74 #define AD7192_MODE_RATE_MASK	GENMASK(9, 0)
75 
76 /* Mode Register: AD7192_MODE_SEL options */
77 #define AD7192_MODE_CONT		0 /* Continuous Conversion Mode */
78 #define AD7192_MODE_SINGLE		1 /* Single Conversion Mode */
79 #define AD7192_MODE_IDLE		2 /* Idle Mode */
80 #define AD7192_MODE_PWRDN		3 /* Power-Down Mode */
81 #define AD7192_MODE_CAL_INT_ZERO	4 /* Internal Zero-Scale Calibration */
82 #define AD7192_MODE_CAL_INT_FULL	5 /* Internal Full-Scale Calibration */
83 #define AD7192_MODE_CAL_SYS_ZERO	6 /* System Zero-Scale Calibration */
84 #define AD7192_MODE_CAL_SYS_FULL	7 /* System Full-Scale Calibration */
85 
86 /* Mode Register: AD7192_MODE_CLKSRC options */
87 #define AD7192_CLK_EXT_MCLK1_2		0 /* External 4.92 MHz Clock connected*/
88 					  /* from MCLK1 to MCLK2 */
89 #define AD7192_CLK_EXT_MCLK2		1 /* External Clock applied to MCLK2 */
90 #define AD7192_CLK_INT			2 /* Internal 4.92 MHz Clock not */
91 					  /* available at the MCLK2 pin */
92 #define AD7192_CLK_INT_CO		3 /* Internal 4.92 MHz Clock available*/
93 					  /* at the MCLK2 pin */
94 
95 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
96 
97 #define AD7192_CONF_CHOP	BIT(23) /* CHOP enable */
98 #define AD7192_CONF_ACX		BIT(22) /* AC excitation enable(AD7195 only) */
99 #define AD7192_CONF_REFSEL	BIT(20) /* REFIN1/REFIN2 Reference Select */
100 #define AD7192_CONF_CHAN_MASK	GENMASK(18, 8) /* Channel select mask */
101 #define AD7192_CONF_BURN	BIT(7) /* Burnout current enable */
102 #define AD7192_CONF_REFDET	BIT(6) /* Reference detect enable */
103 #define AD7192_CONF_BUF		BIT(4) /* Buffered Mode Enable */
104 #define AD7192_CONF_UNIPOLAR	BIT(3) /* Unipolar/Bipolar Enable */
105 #define AD7192_CONF_GAIN_MASK	GENMASK(2, 0) /* Gain Select */
106 
107 #define AD7192_CH_AIN1P_AIN2M	BIT(0) /* AIN1(+) - AIN2(-) */
108 #define AD7192_CH_AIN3P_AIN4M	BIT(1) /* AIN3(+) - AIN4(-) */
109 #define AD7192_CH_TEMP		BIT(2) /* Temp Sensor */
110 #define AD7192_CH_AIN2P_AIN2M	BIT(3) /* AIN2(+) - AIN2(-) */
111 #define AD7192_CH_AIN1		BIT(4) /* AIN1 - AINCOM */
112 #define AD7192_CH_AIN2		BIT(5) /* AIN2 - AINCOM */
113 #define AD7192_CH_AIN3		BIT(6) /* AIN3 - AINCOM */
114 #define AD7192_CH_AIN4		BIT(7) /* AIN4 - AINCOM */
115 
116 #define AD7193_CH_AIN1P_AIN2M	0x001  /* AIN1(+) - AIN2(-) */
117 #define AD7193_CH_AIN3P_AIN4M	0x002  /* AIN3(+) - AIN4(-) */
118 #define AD7193_CH_AIN5P_AIN6M	0x004  /* AIN5(+) - AIN6(-) */
119 #define AD7193_CH_AIN7P_AIN8M	0x008  /* AIN7(+) - AIN8(-) */
120 #define AD7193_CH_TEMP		0x100 /* Temp senseor */
121 #define AD7193_CH_AIN2P_AIN2M	0x200 /* AIN2(+) - AIN2(-) */
122 #define AD7193_CH_AIN1		0x401 /* AIN1 - AINCOM */
123 #define AD7193_CH_AIN2		0x402 /* AIN2 - AINCOM */
124 #define AD7193_CH_AIN3		0x404 /* AIN3 - AINCOM */
125 #define AD7193_CH_AIN4		0x408 /* AIN4 - AINCOM */
126 #define AD7193_CH_AIN5		0x410 /* AIN5 - AINCOM */
127 #define AD7193_CH_AIN6		0x420 /* AIN6 - AINCOM */
128 #define AD7193_CH_AIN7		0x440 /* AIN7 - AINCOM */
129 #define AD7193_CH_AIN8		0x480 /* AIN7 - AINCOM */
130 #define AD7193_CH_AINCOM	0x600 /* AINCOM - AINCOM */
131 
132 #define AD7194_CH_POS(x)	(((x) - 1) << 4)
133 #define AD7194_CH_NEG(x)	((x) - 1)
134 
135 /* 10th bit corresponds to CON18(Pseudo) */
136 #define AD7194_CH(p)		(BIT(10) | AD7194_CH_POS(p))
137 
138 #define AD7194_DIFF_CH(p, n)	(AD7194_CH_POS(p) | AD7194_CH_NEG(n))
139 #define AD7194_CH_TEMP		0x100
140 #define AD7194_CH_BASE_NR	2
141 #define AD7194_CH_AIN_START	1
142 #define AD7194_CH_AIN_NR	16
143 #define AD7194_CH_MAX_NR	272
144 
145 /* ID Register Bit Designations (AD7192_REG_ID) */
146 #define CHIPID_AD7190		0x4
147 #define CHIPID_AD7192		0x0
148 #define CHIPID_AD7193		0x2
149 #define CHIPID_AD7194		0x3
150 #define CHIPID_AD7195		0x6
151 #define AD7192_ID_MASK		GENMASK(3, 0)
152 
153 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
154 #define AD7192_GPOCON_BPDSW	BIT(6) /* Bridge power-down switch enable */
155 #define AD7192_GPOCON_GP32EN	BIT(5) /* Digital Output P3 and P2 enable */
156 #define AD7192_GPOCON_GP10EN	BIT(4) /* Digital Output P1 and P0 enable */
157 #define AD7192_GPOCON_P3DAT	BIT(3) /* P3 state */
158 #define AD7192_GPOCON_P2DAT	BIT(2) /* P2 state */
159 #define AD7192_GPOCON_P1DAT	BIT(1) /* P1 state */
160 #define AD7192_GPOCON_P0DAT	BIT(0) /* P0 state */
161 
162 #define AD7192_EXT_FREQ_MHZ_MIN	2457600
163 #define AD7192_EXT_FREQ_MHZ_MAX	5120000
164 #define AD7192_INT_FREQ_MHZ	4915200
165 
166 #define AD7192_NO_SYNC_FILTER	1
167 #define AD7192_SYNC3_FILTER	3
168 #define AD7192_SYNC4_FILTER	4
169 
170 /* NOTE:
171  * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
172  * In order to avoid contentions on the SPI bus, it's therefore necessary
173  * to use spi bus locking.
174  *
175  * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
176  */
177 
178 enum {
179 	AD7192_SYSCALIB_ZERO_SCALE,
180 	AD7192_SYSCALIB_FULL_SCALE,
181 };
182 
183 enum {
184 	ID_AD7190,
185 	ID_AD7192,
186 	ID_AD7193,
187 	ID_AD7194,
188 	ID_AD7195,
189 };
190 
191 struct ad7192_chip_info {
192 	unsigned int			chip_id;
193 	const char			*name;
194 	const struct iio_chan_spec	*channels;
195 	u8				num_channels;
196 	const struct ad_sigma_delta_info	*sigma_delta_info;
197 	const struct iio_info		*info;
198 	int (*parse_channels)(struct iio_dev *indio_dev);
199 };
200 
201 struct ad7192_state {
202 	const struct ad7192_chip_info	*chip_info;
203 	struct clk			*mclk;
204 	u16				int_vref_mv;
205 	u32				aincom_mv;
206 	u32				fclk;
207 	u32				mode;
208 	u32				conf;
209 	u32				scale_avail[8][2];
210 	u32				filter_freq_avail[4][2];
211 	u32				oversampling_ratio_avail[4];
212 	u8				gpocon;
213 	u8				clock_sel;
214 	struct mutex			lock;	/* protect sensor state */
215 	u8				syscalib_mode[8];
216 
217 	struct ad_sigma_delta		sd;
218 };
219 
220 static const char * const ad7192_syscalib_modes[] = {
221 	[AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
222 	[AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
223 };
224 
225 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
226 				    const struct iio_chan_spec *chan,
227 				    unsigned int mode)
228 {
229 	struct ad7192_state *st = iio_priv(indio_dev);
230 
231 	st->syscalib_mode[chan->channel] = mode;
232 
233 	return 0;
234 }
235 
236 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
237 				    const struct iio_chan_spec *chan)
238 {
239 	struct ad7192_state *st = iio_priv(indio_dev);
240 
241 	return st->syscalib_mode[chan->channel];
242 }
243 
244 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
245 				     uintptr_t private,
246 				     const struct iio_chan_spec *chan,
247 				     const char *buf, size_t len)
248 {
249 	struct ad7192_state *st = iio_priv(indio_dev);
250 	bool sys_calib;
251 	int ret, temp;
252 
253 	ret = kstrtobool(buf, &sys_calib);
254 	if (ret)
255 		return ret;
256 
257 	temp = st->syscalib_mode[chan->channel];
258 	if (sys_calib) {
259 		if (temp == AD7192_SYSCALIB_ZERO_SCALE)
260 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
261 					      chan->address);
262 		else
263 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
264 					      chan->address);
265 	}
266 
267 	return ret ? ret : len;
268 }
269 
270 static const struct iio_enum ad7192_syscalib_mode_enum = {
271 	.items = ad7192_syscalib_modes,
272 	.num_items = ARRAY_SIZE(ad7192_syscalib_modes),
273 	.set = ad7192_set_syscalib_mode,
274 	.get = ad7192_get_syscalib_mode
275 };
276 
277 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
278 	{
279 		.name = "sys_calibration",
280 		.write = ad7192_write_syscalib,
281 		.shared = IIO_SEPARATE,
282 	},
283 	IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
284 		 &ad7192_syscalib_mode_enum),
285 	IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
286 			   &ad7192_syscalib_mode_enum),
287 	{}
288 };
289 
290 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
291 {
292 	return container_of(sd, struct ad7192_state, sd);
293 }
294 
295 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
296 {
297 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
298 
299 	st->conf &= ~AD7192_CONF_CHAN_MASK;
300 	st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);
301 
302 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
303 }
304 
305 static int ad7192_set_mode(struct ad_sigma_delta *sd,
306 			   enum ad_sigma_delta_mode mode)
307 {
308 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
309 
310 	st->mode &= ~AD7192_MODE_SEL_MASK;
311 	st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);
312 
313 	return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
314 }
315 
316 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
317 {
318 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
319 	unsigned int mode = st->mode;
320 	int ret;
321 
322 	mode &= ~AD7192_MODE_STA_MASK;
323 	mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append);
324 
325 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
326 	if (ret < 0)
327 		return ret;
328 
329 	st->mode = mode;
330 
331 	return 0;
332 }
333 
334 static int ad7192_disable_all(struct ad_sigma_delta *sd)
335 {
336 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
337 	u32 conf = st->conf;
338 	int ret;
339 
340 	conf &= ~AD7192_CONF_CHAN_MASK;
341 
342 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
343 	if (ret < 0)
344 		return ret;
345 
346 	st->conf = conf;
347 
348 	return 0;
349 }
350 
351 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
352 	.set_channel = ad7192_set_channel,
353 	.append_status = ad7192_append_status,
354 	.disable_all = ad7192_disable_all,
355 	.set_mode = ad7192_set_mode,
356 	.has_registers = true,
357 	.addr_shift = 3,
358 	.read_mask = BIT(6),
359 	.status_ch_mask = GENMASK(3, 0),
360 	.num_slots = 4,
361 	.irq_flags = IRQF_TRIGGER_FALLING,
362 };
363 
364 static const struct ad_sigma_delta_info ad7194_sigma_delta_info = {
365 	.set_channel = ad7192_set_channel,
366 	.append_status = ad7192_append_status,
367 	.disable_all = ad7192_disable_all,
368 	.set_mode = ad7192_set_mode,
369 	.has_registers = true,
370 	.addr_shift = 3,
371 	.read_mask = BIT(6),
372 	.status_ch_mask = GENMASK(3, 0),
373 	.irq_flags = IRQF_TRIGGER_FALLING,
374 };
375 
376 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
377 	{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
378 	{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
379 	{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
380 	{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
381 	{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
382 	{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
383 	{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
384 	{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
385 };
386 
387 static int ad7192_calibrate_all(struct ad7192_state *st)
388 {
389 	return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
390 				   ARRAY_SIZE(ad7192_calib_arr));
391 }
392 
393 static inline bool ad7192_valid_external_frequency(u32 freq)
394 {
395 	return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
396 		freq <= AD7192_EXT_FREQ_MHZ_MAX);
397 }
398 
399 static int ad7192_clock_select(struct ad7192_state *st)
400 {
401 	struct device *dev = &st->sd.spi->dev;
402 	unsigned int clock_sel;
403 
404 	clock_sel = AD7192_CLK_INT;
405 
406 	/* use internal clock */
407 	if (!st->mclk) {
408 		if (device_property_read_bool(dev, "adi,int-clock-output-enable"))
409 			clock_sel = AD7192_CLK_INT_CO;
410 	} else {
411 		if (device_property_read_bool(dev, "adi,clock-xtal"))
412 			clock_sel = AD7192_CLK_EXT_MCLK1_2;
413 		else
414 			clock_sel = AD7192_CLK_EXT_MCLK2;
415 	}
416 
417 	return clock_sel;
418 }
419 
420 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev)
421 {
422 	struct ad7192_state *st = iio_priv(indio_dev);
423 	bool rej60_en, refin2_en;
424 	bool buf_en, bipolar, burnout_curr_en;
425 	unsigned long long scale_uv;
426 	int i, ret, id;
427 
428 	/* reset the serial interface */
429 	ret = ad_sd_reset(&st->sd, 48);
430 	if (ret < 0)
431 		return ret;
432 	usleep_range(500, 1000); /* Wait for at least 500us */
433 
434 	/* write/read test for device presence */
435 	ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
436 	if (ret)
437 		return ret;
438 
439 	id = FIELD_GET(AD7192_ID_MASK, id);
440 
441 	if (id != st->chip_info->chip_id)
442 		dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n",
443 			 id, st->chip_info->chip_id);
444 
445 	st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |
446 		FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |
447 		FIELD_PREP(AD7192_MODE_RATE_MASK, 480);
448 
449 	st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);
450 
451 	rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable");
452 	if (rej60_en)
453 		st->mode |= AD7192_MODE_REJ60;
454 
455 	refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable");
456 	if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
457 		st->conf |= AD7192_CONF_REFSEL;
458 
459 	st->conf &= ~AD7192_CONF_CHOP;
460 
461 	buf_en = device_property_read_bool(dev, "adi,buffer-enable");
462 	if (buf_en)
463 		st->conf |= AD7192_CONF_BUF;
464 
465 	bipolar = device_property_read_bool(dev, "bipolar");
466 	if (!bipolar)
467 		st->conf |= AD7192_CONF_UNIPOLAR;
468 
469 	burnout_curr_en = device_property_read_bool(dev,
470 						    "adi,burnout-currents-enable");
471 	if (burnout_curr_en && buf_en) {
472 		st->conf |= AD7192_CONF_BURN;
473 	} else if (burnout_curr_en) {
474 		dev_warn(dev,
475 			 "Can't enable burnout currents: see CHOP or buffer\n");
476 	}
477 
478 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
479 	if (ret)
480 		return ret;
481 
482 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
483 	if (ret)
484 		return ret;
485 
486 	ret = ad7192_calibrate_all(st);
487 	if (ret)
488 		return ret;
489 
490 	/* Populate available ADC input ranges */
491 	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
492 		scale_uv = ((u64)st->int_vref_mv * 100000000)
493 			>> (indio_dev->channels[0].scan_type.realbits -
494 			!FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));
495 		scale_uv >>= i;
496 
497 		st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
498 		st->scale_avail[i][0] = scale_uv;
499 	}
500 
501 	st->oversampling_ratio_avail[0] = 1;
502 	st->oversampling_ratio_avail[1] = 2;
503 	st->oversampling_ratio_avail[2] = 8;
504 	st->oversampling_ratio_avail[3] = 16;
505 
506 	st->filter_freq_avail[0][0] = 600;
507 	st->filter_freq_avail[1][0] = 800;
508 	st->filter_freq_avail[2][0] = 2300;
509 	st->filter_freq_avail[3][0] = 2720;
510 
511 	st->filter_freq_avail[0][1] = 1000;
512 	st->filter_freq_avail[1][1] = 1000;
513 	st->filter_freq_avail[2][1] = 1000;
514 	st->filter_freq_avail[3][1] = 1000;
515 
516 	return 0;
517 }
518 
519 static ssize_t ad7192_show_ac_excitation(struct device *dev,
520 					 struct device_attribute *attr,
521 					 char *buf)
522 {
523 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
524 	struct ad7192_state *st = iio_priv(indio_dev);
525 
526 	return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));
527 }
528 
529 static ssize_t ad7192_show_bridge_switch(struct device *dev,
530 					 struct device_attribute *attr,
531 					 char *buf)
532 {
533 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
534 	struct ad7192_state *st = iio_priv(indio_dev);
535 
536 	return sysfs_emit(buf, "%ld\n",
537 			  FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));
538 }
539 
540 static ssize_t ad7192_set(struct device *dev,
541 			  struct device_attribute *attr,
542 			  const char *buf,
543 			  size_t len)
544 {
545 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
546 	struct ad7192_state *st = iio_priv(indio_dev);
547 	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
548 	int ret;
549 	bool val;
550 
551 	ret = kstrtobool(buf, &val);
552 	if (ret < 0)
553 		return ret;
554 
555 	ret = iio_device_claim_direct_mode(indio_dev);
556 	if (ret)
557 		return ret;
558 
559 	switch ((u32)this_attr->address) {
560 	case AD7192_REG_GPOCON:
561 		if (val)
562 			st->gpocon |= AD7192_GPOCON_BPDSW;
563 		else
564 			st->gpocon &= ~AD7192_GPOCON_BPDSW;
565 
566 		ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
567 		break;
568 	case AD7192_REG_CONF:
569 		if (val)
570 			st->conf |= AD7192_CONF_ACX;
571 		else
572 			st->conf &= ~AD7192_CONF_ACX;
573 
574 		ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
575 		break;
576 	default:
577 		ret = -EINVAL;
578 	}
579 
580 	iio_device_release_direct_mode(indio_dev);
581 
582 	return ret ? ret : len;
583 }
584 
585 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en)
586 {
587 	u8 avg_factor_selected, oversampling_ratio;
588 
589 	avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);
590 
591 	if (!avg_factor_selected && !chop_en)
592 		return 1;
593 
594 	oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];
595 
596 	if (sinc3_en)
597 		return AD7192_SYNC3_FILTER + oversampling_ratio - 1;
598 
599 	return AD7192_SYNC4_FILTER + oversampling_ratio - 1;
600 }
601 
602 static int ad7192_get_f_order(struct ad7192_state *st)
603 {
604 	bool sinc3_en, chop_en;
605 
606 	sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);
607 	chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);
608 
609 	return ad7192_compute_f_order(st, sinc3_en, chop_en);
610 }
611 
612 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en,
613 				bool chop_en)
614 {
615 	unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en);
616 
617 	return DIV_ROUND_CLOSEST(st->fclk,
618 				 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
619 }
620 
621 static int ad7192_get_f_adc(struct ad7192_state *st)
622 {
623 	unsigned int f_order = ad7192_get_f_order(st);
624 
625 	return DIV_ROUND_CLOSEST(st->fclk,
626 				 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
627 }
628 
629 static void ad7192_update_filter_freq_avail(struct ad7192_state *st)
630 {
631 	unsigned int fadc;
632 
633 	/* Formulas for filter at page 25 of the datasheet */
634 	fadc = ad7192_compute_f_adc(st, false, true);
635 	st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
636 
637 	fadc = ad7192_compute_f_adc(st, true, true);
638 	st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
639 
640 	fadc = ad7192_compute_f_adc(st, false, false);
641 	st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
642 
643 	fadc = ad7192_compute_f_adc(st, true, false);
644 	st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
645 }
646 
647 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
648 		       ad7192_show_bridge_switch, ad7192_set,
649 		       AD7192_REG_GPOCON);
650 
651 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
652 		       ad7192_show_ac_excitation, ad7192_set,
653 		       AD7192_REG_CONF);
654 
655 static struct attribute *ad7192_attributes[] = {
656 	&iio_dev_attr_bridge_switch_en.dev_attr.attr,
657 	NULL
658 };
659 
660 static const struct attribute_group ad7192_attribute_group = {
661 	.attrs = ad7192_attributes,
662 };
663 
664 static struct attribute *ad7195_attributes[] = {
665 	&iio_dev_attr_bridge_switch_en.dev_attr.attr,
666 	&iio_dev_attr_ac_excitation_en.dev_attr.attr,
667 	NULL
668 };
669 
670 static const struct attribute_group ad7195_attribute_group = {
671 	.attrs = ad7195_attributes,
672 };
673 
674 static unsigned int ad7192_get_temp_scale(bool unipolar)
675 {
676 	return unipolar ? 2815 * 2 : 2815;
677 }
678 
679 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
680 				      int val, int val2)
681 {
682 	int i, ret, freq;
683 	unsigned int diff_new, diff_old;
684 	int idx = 0;
685 
686 	diff_old = U32_MAX;
687 	freq = val * 1000 + val2;
688 
689 	for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) {
690 		diff_new = abs(freq - st->filter_freq_avail[i][0]);
691 		if (diff_new < diff_old) {
692 			diff_old = diff_new;
693 			idx = i;
694 		}
695 	}
696 
697 	switch (idx) {
698 	case 0:
699 		st->mode &= ~AD7192_MODE_SINC3;
700 
701 		st->conf |= AD7192_CONF_CHOP;
702 		break;
703 	case 1:
704 		st->mode |= AD7192_MODE_SINC3;
705 
706 		st->conf |= AD7192_CONF_CHOP;
707 		break;
708 	case 2:
709 		st->mode &= ~AD7192_MODE_SINC3;
710 
711 		st->conf &= ~AD7192_CONF_CHOP;
712 		break;
713 	case 3:
714 		st->mode |= AD7192_MODE_SINC3;
715 
716 		st->conf &= ~AD7192_CONF_CHOP;
717 		break;
718 	}
719 
720 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
721 	if (ret < 0)
722 		return ret;
723 
724 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
725 }
726 
727 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
728 {
729 	unsigned int fadc;
730 
731 	fadc = ad7192_get_f_adc(st);
732 
733 	if (FIELD_GET(AD7192_CONF_CHOP, st->conf))
734 		return DIV_ROUND_CLOSEST(fadc * 240, 1024);
735 	if (FIELD_GET(AD7192_MODE_SINC3, st->mode))
736 		return DIV_ROUND_CLOSEST(fadc * 272, 1024);
737 	else
738 		return DIV_ROUND_CLOSEST(fadc * 230, 1024);
739 }
740 
741 static int ad7192_read_raw(struct iio_dev *indio_dev,
742 			   struct iio_chan_spec const *chan,
743 			   int *val,
744 			   int *val2,
745 			   long m)
746 {
747 	struct ad7192_state *st = iio_priv(indio_dev);
748 	bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);
749 	u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);
750 
751 	switch (m) {
752 	case IIO_CHAN_INFO_RAW:
753 		return ad_sigma_delta_single_conversion(indio_dev, chan, val);
754 	case IIO_CHAN_INFO_SCALE:
755 		switch (chan->type) {
756 		case IIO_VOLTAGE:
757 			mutex_lock(&st->lock);
758 			*val = st->scale_avail[gain][0];
759 			*val2 = st->scale_avail[gain][1];
760 			mutex_unlock(&st->lock);
761 			return IIO_VAL_INT_PLUS_NANO;
762 		case IIO_TEMP:
763 			*val = 0;
764 			*val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
765 			return IIO_VAL_INT_PLUS_NANO;
766 		default:
767 			return -EINVAL;
768 		}
769 	case IIO_CHAN_INFO_OFFSET:
770 		if (!unipolar)
771 			*val = -(1 << (chan->scan_type.realbits - 1));
772 		else
773 			*val = 0;
774 
775 		switch (chan->type) {
776 		case IIO_VOLTAGE:
777 			/*
778 			 * Only applies to pseudo-differential inputs.
779 			 * AINCOM voltage has to be converted to "raw" units.
780 			 */
781 			if (st->aincom_mv && !chan->differential)
782 				*val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO,
783 							      st->scale_avail[gain][1]);
784 			return IIO_VAL_INT;
785 		/* Kelvin to Celsius */
786 		case IIO_TEMP:
787 			*val -= 273 * ad7192_get_temp_scale(unipolar);
788 			return IIO_VAL_INT;
789 		default:
790 			return -EINVAL;
791 		}
792 	case IIO_CHAN_INFO_SAMP_FREQ:
793 		*val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024);
794 		return IIO_VAL_INT;
795 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
796 		*val = ad7192_get_3db_filter_freq(st);
797 		*val2 = 1000;
798 		return IIO_VAL_FRACTIONAL;
799 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
800 		*val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];
801 		return IIO_VAL_INT;
802 	}
803 
804 	return -EINVAL;
805 }
806 
807 static int ad7192_write_raw(struct iio_dev *indio_dev,
808 			    struct iio_chan_spec const *chan,
809 			    int val,
810 			    int val2,
811 			    long mask)
812 {
813 	struct ad7192_state *st = iio_priv(indio_dev);
814 	int ret, i, div;
815 	unsigned int tmp;
816 
817 	ret = iio_device_claim_direct_mode(indio_dev);
818 	if (ret)
819 		return ret;
820 
821 	mutex_lock(&st->lock);
822 
823 	switch (mask) {
824 	case IIO_CHAN_INFO_SCALE:
825 		ret = -EINVAL;
826 		for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
827 			if (val2 == st->scale_avail[i][1]) {
828 				ret = 0;
829 				tmp = st->conf;
830 				st->conf &= ~AD7192_CONF_GAIN_MASK;
831 				st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);
832 				if (tmp == st->conf)
833 					break;
834 				ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
835 						3, st->conf);
836 				ad7192_calibrate_all(st);
837 				break;
838 			}
839 		break;
840 	case IIO_CHAN_INFO_SAMP_FREQ:
841 		if (!val) {
842 			ret = -EINVAL;
843 			break;
844 		}
845 
846 		div = st->fclk / (val * ad7192_get_f_order(st) * 1024);
847 		if (div < 1 || div > 1023) {
848 			ret = -EINVAL;
849 			break;
850 		}
851 
852 		st->mode &= ~AD7192_MODE_RATE_MASK;
853 		st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);
854 		ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
855 		ad7192_update_filter_freq_avail(st);
856 		break;
857 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
858 		ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
859 		break;
860 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
861 		ret = -EINVAL;
862 		for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++)
863 			if (val == st->oversampling_ratio_avail[i]) {
864 				ret = 0;
865 				tmp = st->mode;
866 				st->mode &= ~AD7192_MODE_AVG_MASK;
867 				st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);
868 				if (tmp == st->mode)
869 					break;
870 				ad_sd_write_reg(&st->sd, AD7192_REG_MODE,
871 						3, st->mode);
872 				break;
873 			}
874 		ad7192_update_filter_freq_avail(st);
875 		break;
876 	default:
877 		ret = -EINVAL;
878 	}
879 
880 	mutex_unlock(&st->lock);
881 
882 	iio_device_release_direct_mode(indio_dev);
883 
884 	return ret;
885 }
886 
887 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
888 				    struct iio_chan_spec const *chan,
889 				    long mask)
890 {
891 	switch (mask) {
892 	case IIO_CHAN_INFO_SCALE:
893 		return IIO_VAL_INT_PLUS_NANO;
894 	case IIO_CHAN_INFO_SAMP_FREQ:
895 		return IIO_VAL_INT;
896 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
897 		return IIO_VAL_INT_PLUS_MICRO;
898 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
899 		return IIO_VAL_INT;
900 	default:
901 		return -EINVAL;
902 	}
903 }
904 
905 static int ad7192_read_avail(struct iio_dev *indio_dev,
906 			     struct iio_chan_spec const *chan,
907 			     const int **vals, int *type, int *length,
908 			     long mask)
909 {
910 	struct ad7192_state *st = iio_priv(indio_dev);
911 
912 	switch (mask) {
913 	case IIO_CHAN_INFO_SCALE:
914 		*vals = (int *)st->scale_avail;
915 		*type = IIO_VAL_INT_PLUS_NANO;
916 		/* Values are stored in a 2D matrix  */
917 		*length = ARRAY_SIZE(st->scale_avail) * 2;
918 
919 		return IIO_AVAIL_LIST;
920 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
921 		*vals = (int *)st->filter_freq_avail;
922 		*type = IIO_VAL_FRACTIONAL;
923 		*length = ARRAY_SIZE(st->filter_freq_avail) * 2;
924 
925 		return IIO_AVAIL_LIST;
926 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
927 		*vals = (int *)st->oversampling_ratio_avail;
928 		*type = IIO_VAL_INT;
929 		*length = ARRAY_SIZE(st->oversampling_ratio_avail);
930 
931 		return IIO_AVAIL_LIST;
932 	}
933 
934 	return -EINVAL;
935 }
936 
937 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
938 {
939 	struct ad7192_state *st = iio_priv(indio_dev);
940 	u32 conf = st->conf;
941 	int ret;
942 	int i;
943 
944 	conf &= ~AD7192_CONF_CHAN_MASK;
945 	for_each_set_bit(i, scan_mask, 8)
946 		conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, i);
947 
948 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
949 	if (ret < 0)
950 		return ret;
951 
952 	st->conf = conf;
953 
954 	return 0;
955 }
956 
957 static const struct iio_info ad7192_info = {
958 	.read_raw = ad7192_read_raw,
959 	.write_raw = ad7192_write_raw,
960 	.write_raw_get_fmt = ad7192_write_raw_get_fmt,
961 	.read_avail = ad7192_read_avail,
962 	.attrs = &ad7192_attribute_group,
963 	.validate_trigger = ad_sd_validate_trigger,
964 	.update_scan_mode = ad7192_update_scan_mode,
965 };
966 
967 static const struct iio_info ad7194_info = {
968 	.read_raw = ad7192_read_raw,
969 	.write_raw = ad7192_write_raw,
970 	.write_raw_get_fmt = ad7192_write_raw_get_fmt,
971 	.read_avail = ad7192_read_avail,
972 	.validate_trigger = ad_sd_validate_trigger,
973 };
974 
975 static const struct iio_info ad7195_info = {
976 	.read_raw = ad7192_read_raw,
977 	.write_raw = ad7192_write_raw,
978 	.write_raw_get_fmt = ad7192_write_raw_get_fmt,
979 	.read_avail = ad7192_read_avail,
980 	.attrs = &ad7195_attribute_group,
981 	.validate_trigger = ad_sd_validate_trigger,
982 	.update_scan_mode = ad7192_update_scan_mode,
983 };
984 
985 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \
986 	_mask_all, _mask_type_av, _mask_all_av, _ext_info) \
987 	{ \
988 		.type = (_type), \
989 		.differential = ((_channel2) == -1 ? 0 : 1), \
990 		.indexed = 1, \
991 		.channel = (_channel1), \
992 		.channel2 = (_channel2), \
993 		.address = (_address), \
994 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
995 			BIT(IIO_CHAN_INFO_OFFSET), \
996 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
997 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
998 			BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
999 			(_mask_all), \
1000 		.info_mask_shared_by_type_available = (_mask_type_av), \
1001 		.info_mask_shared_by_all_available = \
1002 			BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1003 			(_mask_all_av), \
1004 		.ext_info = (_ext_info), \
1005 		.scan_index = (_si), \
1006 		.scan_type = { \
1007 			.sign = 'u', \
1008 			.realbits = 24, \
1009 			.storagebits = 32, \
1010 			.endianness = IIO_BE, \
1011 		}, \
1012 	}
1013 
1014 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1015 	__AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \
1016 		BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1017 
1018 #define AD719x_CHANNEL(_si, _channel1, _address) \
1019 	__AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1020 		BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1021 
1022 #define AD719x_TEMP_CHANNEL(_si, _address) \
1023 	__AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1024 
1025 #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1026 	__AD719x_CHANNEL(_si, _channel1, _channel2, _address, \
1027 		IIO_VOLTAGE, \
1028 		BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1029 		BIT(IIO_CHAN_INFO_SCALE), \
1030 		BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1031 		ad7192_calibsys_ext_info)
1032 
1033 #define AD7193_CHANNEL(_si, _channel1, _address) \
1034 	AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1035 
1036 static const struct iio_chan_spec ad7192_channels[] = {
1037 	AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
1038 	AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
1039 	AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
1040 	AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
1041 	AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
1042 	AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
1043 	AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
1044 	AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
1045 	IIO_CHAN_SOFT_TIMESTAMP(8),
1046 };
1047 
1048 static const struct iio_chan_spec ad7193_channels[] = {
1049 	AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1050 	AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1051 	AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
1052 	AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
1053 	AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
1054 	AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
1055 	AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1056 	AD7193_CHANNEL(7, 2, AD7193_CH_AIN2),
1057 	AD7193_CHANNEL(8, 3, AD7193_CH_AIN3),
1058 	AD7193_CHANNEL(9, 4, AD7193_CH_AIN4),
1059 	AD7193_CHANNEL(10, 5, AD7193_CH_AIN5),
1060 	AD7193_CHANNEL(11, 6, AD7193_CH_AIN6),
1061 	AD7193_CHANNEL(12, 7, AD7193_CH_AIN7),
1062 	AD7193_CHANNEL(13, 8, AD7193_CH_AIN8),
1063 	IIO_CHAN_SOFT_TIMESTAMP(14),
1064 };
1065 
1066 static bool ad7194_validate_ain_channel(struct device *dev, u32 ain)
1067 {
1068 	return in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR);
1069 }
1070 
1071 static int ad7194_parse_channels(struct iio_dev *indio_dev)
1072 {
1073 	struct device *dev = indio_dev->dev.parent;
1074 	struct iio_chan_spec *ad7194_channels;
1075 	const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0);
1076 	const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0);
1077 	const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0);
1078 	const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0);
1079 	unsigned int num_channels, index = 0;
1080 	u32 ain[2];
1081 	int ret;
1082 
1083 	num_channels = device_get_child_node_count(dev);
1084 	if (num_channels > AD7194_CH_MAX_NR)
1085 		return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",
1086 				     num_channels);
1087 
1088 	num_channels += AD7194_CH_BASE_NR;
1089 
1090 	ad7194_channels = devm_kcalloc(dev, num_channels,
1091 				       sizeof(*ad7194_channels), GFP_KERNEL);
1092 	if (!ad7194_channels)
1093 		return -ENOMEM;
1094 
1095 	indio_dev->channels = ad7194_channels;
1096 	indio_dev->num_channels = num_channels;
1097 
1098 	device_for_each_child_node_scoped(dev, child) {
1099 		ret = fwnode_property_read_u32_array(child, "diff-channels",
1100 						     ain, ARRAY_SIZE(ain));
1101 		if (ret == 0) {
1102 			if (!ad7194_validate_ain_channel(dev, ain[0]))
1103 				return dev_err_probe(dev, -EINVAL,
1104 						     "Invalid AIN channel: %u\n",
1105 						     ain[0]);
1106 
1107 			if (!ad7194_validate_ain_channel(dev, ain[1]))
1108 				return dev_err_probe(dev, -EINVAL,
1109 						     "Invalid AIN channel: %u\n",
1110 						     ain[1]);
1111 
1112 			*ad7194_channels = ad7194_chan_diff;
1113 			ad7194_channels->scan_index = index++;
1114 			ad7194_channels->channel = ain[0];
1115 			ad7194_channels->channel2 = ain[1];
1116 			ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]);
1117 		} else {
1118 			ret = fwnode_property_read_u32(child, "single-channel",
1119 						       &ain[0]);
1120 			if (ret)
1121 				return dev_err_probe(dev, ret,
1122 						     "Missing channel property\n");
1123 
1124 			if (!ad7194_validate_ain_channel(dev, ain[0]))
1125 				return dev_err_probe(dev, -EINVAL,
1126 						     "Invalid AIN channel: %u\n",
1127 						     ain[0]);
1128 
1129 			*ad7194_channels = ad7194_chan;
1130 			ad7194_channels->scan_index = index++;
1131 			ad7194_channels->channel = ain[0];
1132 			ad7194_channels->address = AD7194_CH(ain[0]);
1133 		}
1134 		ad7194_channels++;
1135 	}
1136 
1137 	*ad7194_channels = ad7194_chan_temp;
1138 	ad7194_channels->scan_index = index++;
1139 	ad7194_channels->address = AD7194_CH_TEMP;
1140 	ad7194_channels++;
1141 
1142 	*ad7194_channels = ad7194_chan_timestamp;
1143 	ad7194_channels->scan_index = index;
1144 
1145 	return 0;
1146 }
1147 
1148 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
1149 	[ID_AD7190] = {
1150 		.chip_id = CHIPID_AD7190,
1151 		.name = "ad7190",
1152 		.channels = ad7192_channels,
1153 		.num_channels = ARRAY_SIZE(ad7192_channels),
1154 		.sigma_delta_info = &ad7192_sigma_delta_info,
1155 		.info = &ad7192_info,
1156 	},
1157 	[ID_AD7192] = {
1158 		.chip_id = CHIPID_AD7192,
1159 		.name = "ad7192",
1160 		.channels = ad7192_channels,
1161 		.num_channels = ARRAY_SIZE(ad7192_channels),
1162 		.sigma_delta_info = &ad7192_sigma_delta_info,
1163 		.info = &ad7192_info,
1164 	},
1165 	[ID_AD7193] = {
1166 		.chip_id = CHIPID_AD7193,
1167 		.name = "ad7193",
1168 		.channels = ad7193_channels,
1169 		.num_channels = ARRAY_SIZE(ad7193_channels),
1170 		.sigma_delta_info = &ad7192_sigma_delta_info,
1171 		.info = &ad7192_info,
1172 	},
1173 	[ID_AD7194] = {
1174 		.chip_id = CHIPID_AD7194,
1175 		.name = "ad7194",
1176 		.info = &ad7194_info,
1177 		.sigma_delta_info = &ad7194_sigma_delta_info,
1178 		.parse_channels = ad7194_parse_channels,
1179 	},
1180 	[ID_AD7195] = {
1181 		.chip_id = CHIPID_AD7195,
1182 		.name = "ad7195",
1183 		.channels = ad7192_channels,
1184 		.num_channels = ARRAY_SIZE(ad7192_channels),
1185 		.sigma_delta_info = &ad7192_sigma_delta_info,
1186 		.info = &ad7195_info,
1187 	},
1188 };
1189 
1190 static int ad7192_probe(struct spi_device *spi)
1191 {
1192 	struct device *dev = &spi->dev;
1193 	struct ad7192_state *st;
1194 	struct iio_dev *indio_dev;
1195 	int ret, avdd_mv;
1196 
1197 	if (!spi->irq)
1198 		return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n");
1199 
1200 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1201 	if (!indio_dev)
1202 		return -ENOMEM;
1203 
1204 	st = iio_priv(indio_dev);
1205 
1206 	mutex_init(&st->lock);
1207 
1208 	/*
1209 	 * Regulator aincom is optional to maintain compatibility with older DT.
1210 	 * Newer firmware should provide a zero volt fixed supply if wired to
1211 	 * ground.
1212 	 */
1213 	ret = devm_regulator_get_enable_read_voltage(dev, "aincom");
1214 	if (ret < 0 && ret != -ENODEV)
1215 		return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n");
1216 
1217 	st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI;
1218 
1219 	/* AVDD can optionally be used as reference voltage */
1220 	ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
1221 	if (ret == -ENODEV || ret == -EINVAL) {
1222 		int ret2;
1223 
1224 		/*
1225 		 * We get -EINVAL if avdd is a supply with unknown voltage. We
1226 		 * still need to enable it since it is also a power supply.
1227 		 */
1228 		ret2 = devm_regulator_get_enable(dev, "avdd");
1229 		if (ret2)
1230 			return dev_err_probe(dev, ret2,
1231 					     "Failed to enable AVDD supply\n");
1232 	} else if (ret < 0) {
1233 		return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n");
1234 	}
1235 
1236 	avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI;
1237 
1238 	ret = devm_regulator_get_enable(dev, "dvdd");
1239 	if (ret)
1240 		return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n");
1241 
1242 	/*
1243 	 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable.
1244 	 * If this supply is not present, fall back to AVDD as reference.
1245 	 */
1246 	ret = devm_regulator_get_enable_read_voltage(dev, "vref");
1247 	if (ret == -ENODEV) {
1248 		if (avdd_mv == 0)
1249 			return dev_err_probe(dev, -ENODEV,
1250 					     "No reference voltage available\n");
1251 	} else if (ret < 0) {
1252 		return ret;
1253 	}
1254 
1255 	st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI;
1256 
1257 	st->chip_info = spi_get_device_match_data(spi);
1258 	indio_dev->name = st->chip_info->name;
1259 	indio_dev->modes = INDIO_DIRECT_MODE;
1260 	indio_dev->info = st->chip_info->info;
1261 	if (st->chip_info->parse_channels) {
1262 		ret = st->chip_info->parse_channels(indio_dev);
1263 		if (ret)
1264 			return ret;
1265 	} else {
1266 		indio_dev->channels = st->chip_info->channels;
1267 		indio_dev->num_channels = st->chip_info->num_channels;
1268 	}
1269 
1270 	ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info);
1271 	if (ret)
1272 		return ret;
1273 
1274 	ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1275 	if (ret)
1276 		return ret;
1277 
1278 	st->fclk = AD7192_INT_FREQ_MHZ;
1279 
1280 	st->mclk = devm_clk_get_optional_enabled(dev, "mclk");
1281 	if (IS_ERR(st->mclk))
1282 		return PTR_ERR(st->mclk);
1283 
1284 	st->clock_sel = ad7192_clock_select(st);
1285 
1286 	if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1287 	    st->clock_sel == AD7192_CLK_EXT_MCLK2) {
1288 		st->fclk = clk_get_rate(st->mclk);
1289 		if (!ad7192_valid_external_frequency(st->fclk))
1290 			return dev_err_probe(dev, -EINVAL,
1291 					     "External clock frequency out of bounds\n");
1292 	}
1293 
1294 	ret = ad7192_setup(indio_dev, dev);
1295 	if (ret)
1296 		return ret;
1297 
1298 	return devm_iio_device_register(dev, indio_dev);
1299 }
1300 
1301 static const struct of_device_id ad7192_of_match[] = {
1302 	{ .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1303 	{ .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1304 	{ .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1305 	{ .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] },
1306 	{ .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1307 	{}
1308 };
1309 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1310 
1311 static const struct spi_device_id ad7192_ids[] = {
1312 	{ "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1313 	{ "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1314 	{ "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1315 	{ "ad7194", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] },
1316 	{ "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1317 	{}
1318 };
1319 MODULE_DEVICE_TABLE(spi, ad7192_ids);
1320 
1321 static struct spi_driver ad7192_driver = {
1322 	.driver = {
1323 		.name	= "ad7192",
1324 		.of_match_table = ad7192_of_match,
1325 	},
1326 	.probe		= ad7192_probe,
1327 	.id_table	= ad7192_ids,
1328 };
1329 module_spi_driver(ad7192_driver);
1330 
1331 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1332 MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC");
1333 MODULE_LICENSE("GPL v2");
1334 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1335