1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7192 and similar SPI ADC driver 4 * 5 * Copyright 2011-2015 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/bitfield.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/sysfs.h> 17 #include <linux/spi/spi.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/err.h> 20 #include <linux/sched.h> 21 #include <linux/delay.h> 22 #include <linux/module.h> 23 #include <linux/property.h> 24 #include <linux/units.h> 25 26 #include <linux/iio/iio.h> 27 #include <linux/iio/sysfs.h> 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/trigger.h> 30 #include <linux/iio/trigger_consumer.h> 31 #include <linux/iio/triggered_buffer.h> 32 #include <linux/iio/adc/ad_sigma_delta.h> 33 34 /* Registers */ 35 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 36 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 37 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 38 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 39 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 40 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 41 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RW, 8-bit) */ 42 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ 43 /* (AD7792)/24-bit (AD7192)) */ 44 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ 45 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 46 47 /* Communications Register Bit Designations (AD7192_REG_COMM) */ 48 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 49 #define AD7192_COMM_WRITE 0 /* Write Operation */ 50 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 51 #define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */ 52 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 53 54 /* Status Register Bit Designations (AD7192_REG_STAT) */ 55 #define AD7192_STAT_RDY BIT(7) /* Ready */ 56 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ 57 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ 58 #define AD7192_STAT_PARITY BIT(4) /* Parity */ 59 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ 60 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ 61 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 62 63 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 64 #define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */ 65 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ 66 #define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */ 67 #define AD7192_MODE_AVG_MASK GENMASK(17, 16) 68 /* Fast Settling Filter Average Select Mask (AD7193 only) */ 69 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 70 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 71 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 72 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 73 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 74 /* Filter Update Rate Select Mask */ 75 #define AD7192_MODE_RATE_MASK GENMASK(9, 0) 76 77 /* Mode Register: AD7192_MODE_SEL options */ 78 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 79 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 80 #define AD7192_MODE_IDLE 2 /* Idle Mode */ 81 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 82 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 83 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 84 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 85 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 86 87 /* Mode Register: AD7192_MODE_CLKSRC options */ 88 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ 89 /* from MCLK1 to MCLK2 */ 90 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 91 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ 92 /* available at the MCLK2 pin */ 93 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ 94 /* at the MCLK2 pin */ 95 96 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 97 98 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 99 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */ 100 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 101 #define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */ 102 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 103 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 104 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 105 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 106 #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */ 107 108 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 109 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ 110 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ 111 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ 112 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ 113 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ 114 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ 115 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ 116 117 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */ 118 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */ 119 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */ 120 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */ 121 #define AD7193_CH_TEMP 0x100 /* Temp senseor */ 122 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */ 123 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */ 124 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */ 125 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */ 126 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */ 127 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */ 128 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */ 129 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */ 130 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ 131 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 132 133 #define AD7194_CH_POS(x) (((x) - 1) << 4) 134 #define AD7194_CH_NEG(x) ((x) - 1) 135 136 /* 10th bit corresponds to CON18(Pseudo) */ 137 #define AD7194_CH(p) (BIT(10) | AD7194_CH_POS(p)) 138 139 #define AD7194_DIFF_CH(p, n) (AD7194_CH_POS(p) | AD7194_CH_NEG(n)) 140 #define AD7194_CH_TEMP 0x100 141 #define AD7194_CH_BASE_NR 2 142 #define AD7194_CH_AIN_START 1 143 #define AD7194_CH_AIN_NR 16 144 #define AD7194_CH_MAX_NR 272 145 146 /* ID Register Bit Designations (AD7192_REG_ID) */ 147 #define CHIPID_AD7190 0x4 148 #define CHIPID_AD7192 0x0 149 #define CHIPID_AD7193 0x2 150 #define CHIPID_AD7194 0x3 151 #define CHIPID_AD7195 0x6 152 #define AD7192_ID_MASK GENMASK(3, 0) 153 154 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 155 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ 156 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ 157 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ 158 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ 159 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ 160 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ 161 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ 162 163 #define AD7192_EXT_FREQ_MHZ_MIN 2457600 164 #define AD7192_EXT_FREQ_MHZ_MAX 5120000 165 #define AD7192_INT_FREQ_MHZ 4915200 166 167 #define AD7192_NO_SYNC_FILTER 1 168 #define AD7192_SYNC3_FILTER 3 169 #define AD7192_SYNC4_FILTER 4 170 171 /* NOTE: 172 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 173 * In order to avoid contentions on the SPI bus, it's therefore necessary 174 * to use spi bus locking. 175 * 176 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 177 */ 178 179 enum { 180 AD7192_SYSCALIB_ZERO_SCALE, 181 AD7192_SYSCALIB_FULL_SCALE, 182 }; 183 184 enum { 185 ID_AD7190, 186 ID_AD7192, 187 ID_AD7193, 188 ID_AD7194, 189 ID_AD7195, 190 }; 191 192 struct ad7192_chip_info { 193 unsigned int chip_id; 194 const char *name; 195 const struct iio_chan_spec *channels; 196 u8 num_channels; 197 const struct ad_sigma_delta_info *sigma_delta_info; 198 const struct iio_info *info; 199 int (*parse_channels)(struct iio_dev *indio_dev); 200 }; 201 202 struct ad7192_state { 203 const struct ad7192_chip_info *chip_info; 204 struct clk *mclk; 205 struct clk_hw int_clk_hw; 206 u16 int_vref_mv; 207 u32 aincom_mv; 208 u32 fclk; 209 u32 mode; 210 u32 conf; 211 u32 scale_avail[8][2]; 212 u32 filter_freq_avail[4][2]; 213 u32 oversampling_ratio_avail[4]; 214 u8 gpocon; 215 u8 clock_sel; 216 struct mutex lock; /* protect sensor state */ 217 u8 syscalib_mode[8]; 218 219 struct ad_sigma_delta sd; 220 }; 221 222 static const char * const ad7192_syscalib_modes[] = { 223 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale", 224 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale", 225 }; 226 227 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, 228 const struct iio_chan_spec *chan, 229 unsigned int mode) 230 { 231 struct ad7192_state *st = iio_priv(indio_dev); 232 233 st->syscalib_mode[chan->channel] = mode; 234 235 return 0; 236 } 237 238 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, 239 const struct iio_chan_spec *chan) 240 { 241 struct ad7192_state *st = iio_priv(indio_dev); 242 243 return st->syscalib_mode[chan->channel]; 244 } 245 246 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, 247 uintptr_t private, 248 const struct iio_chan_spec *chan, 249 const char *buf, size_t len) 250 { 251 struct ad7192_state *st = iio_priv(indio_dev); 252 bool sys_calib; 253 int ret, temp; 254 255 ret = kstrtobool(buf, &sys_calib); 256 if (ret) 257 return ret; 258 259 if (!iio_device_claim_direct(indio_dev)) 260 return -EBUSY; 261 262 temp = st->syscalib_mode[chan->channel]; 263 if (sys_calib) { 264 if (temp == AD7192_SYSCALIB_ZERO_SCALE) 265 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, 266 chan->address); 267 else 268 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, 269 chan->address); 270 } 271 272 iio_device_release_direct(indio_dev); 273 274 return ret ? ret : len; 275 } 276 277 static const struct iio_enum ad7192_syscalib_mode_enum = { 278 .items = ad7192_syscalib_modes, 279 .num_items = ARRAY_SIZE(ad7192_syscalib_modes), 280 .set = ad7192_set_syscalib_mode, 281 .get = ad7192_get_syscalib_mode 282 }; 283 284 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = { 285 { 286 .name = "sys_calibration", 287 .write = ad7192_write_syscalib, 288 .shared = IIO_SEPARATE, 289 }, 290 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 291 &ad7192_syscalib_mode_enum), 292 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 293 &ad7192_syscalib_mode_enum), 294 { } 295 }; 296 297 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) 298 { 299 return container_of(sd, struct ad7192_state, sd); 300 } 301 302 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 303 { 304 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 305 306 st->conf &= ~AD7192_CONF_CHAN_MASK; 307 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); 308 309 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 310 } 311 312 static int ad7192_set_mode(struct ad_sigma_delta *sd, 313 enum ad_sigma_delta_mode mode) 314 { 315 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 316 317 st->mode &= ~AD7192_MODE_SEL_MASK; 318 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); 319 320 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 321 } 322 323 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append) 324 { 325 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 326 unsigned int mode = st->mode; 327 int ret; 328 329 mode &= ~AD7192_MODE_STA_MASK; 330 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append); 331 332 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); 333 if (ret < 0) 334 return ret; 335 336 st->mode = mode; 337 338 return 0; 339 } 340 341 static int ad7192_disable_all(struct ad_sigma_delta *sd) 342 { 343 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 344 u32 conf = st->conf; 345 int ret; 346 347 conf &= ~AD7192_CONF_CHAN_MASK; 348 349 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 350 if (ret < 0) 351 return ret; 352 353 st->conf = conf; 354 355 return 0; 356 } 357 358 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { 359 .set_channel = ad7192_set_channel, 360 .append_status = ad7192_append_status, 361 .disable_all = ad7192_disable_all, 362 .set_mode = ad7192_set_mode, 363 .has_registers = true, 364 .addr_shift = 3, 365 .read_mask = BIT(6), 366 .status_ch_mask = GENMASK(3, 0), 367 .num_slots = 4, 368 .irq_flags = IRQF_TRIGGER_FALLING, 369 .num_resetclks = 40, 370 }; 371 372 static const struct ad_sigma_delta_info ad7194_sigma_delta_info = { 373 .set_channel = ad7192_set_channel, 374 .append_status = ad7192_append_status, 375 .disable_all = ad7192_disable_all, 376 .set_mode = ad7192_set_mode, 377 .has_registers = true, 378 .addr_shift = 3, 379 .read_mask = BIT(6), 380 .status_ch_mask = GENMASK(3, 0), 381 .irq_flags = IRQF_TRIGGER_FALLING, 382 .num_resetclks = 40, 383 }; 384 385 static const struct ad_sd_calib_data ad7192_calib_arr[8] = { 386 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 387 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 388 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 389 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 390 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 391 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 392 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 393 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 394 }; 395 396 static int ad7192_calibrate_all(struct ad7192_state *st) 397 { 398 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, 399 ARRAY_SIZE(ad7192_calib_arr)); 400 } 401 402 static inline bool ad7192_valid_external_frequency(u32 freq) 403 { 404 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && 405 freq <= AD7192_EXT_FREQ_MHZ_MAX); 406 } 407 408 /* 409 * Position 0 of ad7192_clock_names, xtal, corresponds to clock source 410 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to 411 * AD7192_CLK_EXT_MCLK2 412 */ 413 static const char *const ad7192_clock_names[] = { 414 "xtal", 415 "mclk" 416 }; 417 418 static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) 419 { 420 return container_of(hw, struct ad7192_state, int_clk_hw); 421 } 422 423 static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, 424 unsigned long parent_rate) 425 { 426 return AD7192_INT_FREQ_MHZ; 427 } 428 429 static int ad7192_clk_output_is_enabled(struct clk_hw *hw) 430 { 431 struct ad7192_state *st = clk_hw_to_ad7192(hw); 432 433 return st->clock_sel == AD7192_CLK_INT_CO; 434 } 435 436 static int ad7192_clk_prepare(struct clk_hw *hw) 437 { 438 struct ad7192_state *st = clk_hw_to_ad7192(hw); 439 int ret; 440 441 st->mode &= ~AD7192_MODE_CLKSRC_MASK; 442 st->mode |= AD7192_CLK_INT_CO; 443 444 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 445 if (ret) 446 return ret; 447 448 st->clock_sel = AD7192_CLK_INT_CO; 449 450 return 0; 451 } 452 453 static void ad7192_clk_unprepare(struct clk_hw *hw) 454 { 455 struct ad7192_state *st = clk_hw_to_ad7192(hw); 456 int ret; 457 458 st->mode &= ~AD7192_MODE_CLKSRC_MASK; 459 st->mode |= AD7192_CLK_INT; 460 461 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 462 if (ret) 463 return; 464 465 st->clock_sel = AD7192_CLK_INT; 466 } 467 468 static const struct clk_ops ad7192_int_clk_ops = { 469 .recalc_rate = ad7192_clk_recalc_rate, 470 .is_enabled = ad7192_clk_output_is_enabled, 471 .prepare = ad7192_clk_prepare, 472 .unprepare = ad7192_clk_unprepare, 473 }; 474 475 static int ad7192_register_clk_provider(struct ad7192_state *st) 476 { 477 struct device *dev = &st->sd.spi->dev; 478 struct clk_init_data init = {}; 479 int ret; 480 481 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 482 return 0; 483 484 if (!device_property_present(dev, "#clock-cells")) 485 return 0; 486 487 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", 488 fwnode_get_name(dev_fwnode(dev))); 489 if (!init.name) 490 return -ENOMEM; 491 492 init.ops = &ad7192_int_clk_ops; 493 494 st->int_clk_hw.init = &init; 495 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 496 if (ret) 497 return ret; 498 499 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 500 &st->int_clk_hw); 501 } 502 503 static int ad7192_clock_setup(struct ad7192_state *st) 504 { 505 struct device *dev = &st->sd.spi->dev; 506 int ret; 507 508 /* 509 * The following two if branches are kept for backward compatibility but 510 * the use of the two devicetree properties is highly discouraged. Clock 511 * configuration should be done according to the bindings. 512 */ 513 514 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) { 515 st->clock_sel = AD7192_CLK_INT_CO; 516 st->fclk = AD7192_INT_FREQ_MHZ; 517 dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n"); 518 return 0; 519 } 520 521 if (device_property_read_bool(dev, "adi,clock-xtal")) { 522 st->clock_sel = AD7192_CLK_EXT_MCLK1_2; 523 st->mclk = devm_clk_get_enabled(dev, "mclk"); 524 if (IS_ERR(st->mclk)) 525 return dev_err_probe(dev, PTR_ERR(st->mclk), 526 "Failed to get mclk\n"); 527 528 st->fclk = clk_get_rate(st->mclk); 529 if (!ad7192_valid_external_frequency(st->fclk)) 530 return dev_err_probe(dev, -EINVAL, 531 "External clock frequency out of bounds\n"); 532 533 dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n"); 534 return 0; 535 } 536 537 ret = device_property_match_property_string(dev, "clock-names", 538 ad7192_clock_names, 539 ARRAY_SIZE(ad7192_clock_names)); 540 if (ret < 0) { 541 st->clock_sel = AD7192_CLK_INT; 542 st->fclk = AD7192_INT_FREQ_MHZ; 543 544 ret = ad7192_register_clk_provider(st); 545 if (ret) 546 return dev_err_probe(dev, ret, 547 "Failed to register clock provider\n"); 548 return 0; 549 } 550 551 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; 552 553 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); 554 if (IS_ERR(st->mclk)) 555 return dev_err_probe(dev, PTR_ERR(st->mclk), 556 "Failed to get clock source\n"); 557 558 st->fclk = clk_get_rate(st->mclk); 559 if (!ad7192_valid_external_frequency(st->fclk)) 560 return dev_err_probe(dev, -EINVAL, 561 "External clock frequency out of bounds\n"); 562 563 return 0; 564 } 565 566 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) 567 { 568 struct ad7192_state *st = iio_priv(indio_dev); 569 bool rej60_en, refin2_en; 570 bool buf_en, bipolar, burnout_curr_en; 571 unsigned long long scale_uv; 572 int i, ret, id; 573 574 /* reset the serial interface */ 575 ret = ad_sd_reset(&st->sd); 576 if (ret < 0) 577 return ret; 578 579 /* 580 * Per AD7192 datasheet (Rev. A, page 34, RESET section), allow 581 * 500 us after a reset before accessing on-chip registers. 582 */ 583 fsleep(500); 584 585 /* write/read test for device presence */ 586 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); 587 if (ret) 588 return ret; 589 590 id = FIELD_GET(AD7192_ID_MASK, id); 591 592 if (id != st->chip_info->chip_id) 593 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n", 594 id, st->chip_info->chip_id); 595 596 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | 597 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | 598 FIELD_PREP(AD7192_MODE_RATE_MASK, 480); 599 600 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); 601 602 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable"); 603 if (rej60_en) 604 st->mode |= AD7192_MODE_REJ60; 605 606 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable"); 607 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 608 st->conf |= AD7192_CONF_REFSEL; 609 610 st->conf &= ~AD7192_CONF_CHOP; 611 612 buf_en = device_property_read_bool(dev, "adi,buffer-enable"); 613 if (buf_en) 614 st->conf |= AD7192_CONF_BUF; 615 616 bipolar = device_property_read_bool(dev, "bipolar"); 617 if (!bipolar) 618 st->conf |= AD7192_CONF_UNIPOLAR; 619 620 burnout_curr_en = device_property_read_bool(dev, 621 "adi,burnout-currents-enable"); 622 if (burnout_curr_en && buf_en) { 623 st->conf |= AD7192_CONF_BURN; 624 } else if (burnout_curr_en) { 625 dev_warn(dev, 626 "Can't enable burnout currents: see CHOP or buffer\n"); 627 } 628 629 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 630 if (ret) 631 return ret; 632 633 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 634 if (ret) 635 return ret; 636 637 ret = ad7192_calibrate_all(st); 638 if (ret) 639 return ret; 640 641 /* Populate available ADC input ranges */ 642 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 643 scale_uv = ((u64)st->int_vref_mv * 100000000) 644 >> (indio_dev->channels[0].scan_type.realbits - 645 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); 646 scale_uv >>= i; 647 648 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 649 st->scale_avail[i][0] = scale_uv; 650 } 651 652 st->oversampling_ratio_avail[0] = 1; 653 st->oversampling_ratio_avail[1] = 2; 654 st->oversampling_ratio_avail[2] = 8; 655 st->oversampling_ratio_avail[3] = 16; 656 657 st->filter_freq_avail[0][0] = 600; 658 st->filter_freq_avail[1][0] = 800; 659 st->filter_freq_avail[2][0] = 2300; 660 st->filter_freq_avail[3][0] = 2720; 661 662 st->filter_freq_avail[0][1] = 1000; 663 st->filter_freq_avail[1][1] = 1000; 664 st->filter_freq_avail[2][1] = 1000; 665 st->filter_freq_avail[3][1] = 1000; 666 667 return 0; 668 } 669 670 static ssize_t ad7192_show_ac_excitation(struct device *dev, 671 struct device_attribute *attr, 672 char *buf) 673 { 674 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 675 struct ad7192_state *st = iio_priv(indio_dev); 676 677 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); 678 } 679 680 static ssize_t ad7192_show_bridge_switch(struct device *dev, 681 struct device_attribute *attr, 682 char *buf) 683 { 684 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 685 struct ad7192_state *st = iio_priv(indio_dev); 686 687 return sysfs_emit(buf, "%ld\n", 688 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); 689 } 690 691 static ssize_t ad7192_set(struct device *dev, 692 struct device_attribute *attr, 693 const char *buf, 694 size_t len) 695 { 696 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 697 struct ad7192_state *st = iio_priv(indio_dev); 698 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 699 int ret; 700 bool val; 701 702 ret = kstrtobool(buf, &val); 703 if (ret < 0) 704 return ret; 705 706 if (!iio_device_claim_direct(indio_dev)) 707 return -EBUSY; 708 709 switch ((u32)this_attr->address) { 710 case AD7192_REG_GPOCON: 711 if (val) 712 st->gpocon |= AD7192_GPOCON_BPDSW; 713 else 714 st->gpocon &= ~AD7192_GPOCON_BPDSW; 715 716 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 717 break; 718 case AD7192_REG_CONF: 719 if (val) 720 st->conf |= AD7192_CONF_ACX; 721 else 722 st->conf &= ~AD7192_CONF_ACX; 723 724 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 725 break; 726 default: 727 ret = -EINVAL; 728 } 729 730 iio_device_release_direct(indio_dev); 731 732 return ret ? ret : len; 733 } 734 735 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) 736 { 737 u8 avg_factor_selected, oversampling_ratio; 738 739 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); 740 741 if (!avg_factor_selected && !chop_en) 742 return 1; 743 744 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; 745 746 if (sinc3_en) 747 return AD7192_SYNC3_FILTER + oversampling_ratio - 1; 748 749 return AD7192_SYNC4_FILTER + oversampling_ratio - 1; 750 } 751 752 static int ad7192_get_f_order(struct ad7192_state *st) 753 { 754 bool sinc3_en, chop_en; 755 756 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); 757 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); 758 759 return ad7192_compute_f_order(st, sinc3_en, chop_en); 760 } 761 762 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, 763 bool chop_en) 764 { 765 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en); 766 767 return DIV_ROUND_CLOSEST(st->fclk, 768 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 769 } 770 771 static int ad7192_get_f_adc(struct ad7192_state *st) 772 { 773 unsigned int f_order = ad7192_get_f_order(st); 774 775 return DIV_ROUND_CLOSEST(st->fclk, 776 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); 777 } 778 779 static void ad7192_update_filter_freq_avail(struct ad7192_state *st) 780 { 781 unsigned int fadc; 782 783 /* Formulas for filter at page 25 of the datasheet */ 784 fadc = ad7192_compute_f_adc(st, false, true); 785 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 786 787 fadc = ad7192_compute_f_adc(st, true, true); 788 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 789 790 fadc = ad7192_compute_f_adc(st, false, false); 791 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 792 793 fadc = ad7192_compute_f_adc(st, true, false); 794 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 795 } 796 797 static IIO_DEVICE_ATTR(bridge_switch_en, 0644, 798 ad7192_show_bridge_switch, ad7192_set, 799 AD7192_REG_GPOCON); 800 801 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 802 ad7192_show_ac_excitation, ad7192_set, 803 AD7192_REG_CONF); 804 805 static struct attribute *ad7192_attributes[] = { 806 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 807 NULL 808 }; 809 810 static const struct attribute_group ad7192_attribute_group = { 811 .attrs = ad7192_attributes, 812 }; 813 814 static struct attribute *ad7195_attributes[] = { 815 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 816 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 817 NULL 818 }; 819 820 static const struct attribute_group ad7195_attribute_group = { 821 .attrs = ad7195_attributes, 822 }; 823 824 static unsigned int ad7192_get_temp_scale(bool unipolar) 825 { 826 return unipolar ? 2815 * 2 : 2815; 827 } 828 829 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, 830 int val, int val2) 831 { 832 int i, ret, freq; 833 unsigned int diff_new, diff_old; 834 int idx = 0; 835 836 diff_old = U32_MAX; 837 freq = val * 1000 + val2; 838 839 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) { 840 diff_new = abs(freq - st->filter_freq_avail[i][0]); 841 if (diff_new < diff_old) { 842 diff_old = diff_new; 843 idx = i; 844 } 845 } 846 847 switch (idx) { 848 case 0: 849 st->mode &= ~AD7192_MODE_SINC3; 850 851 st->conf |= AD7192_CONF_CHOP; 852 break; 853 case 1: 854 st->mode |= AD7192_MODE_SINC3; 855 856 st->conf |= AD7192_CONF_CHOP; 857 break; 858 case 2: 859 st->mode &= ~AD7192_MODE_SINC3; 860 861 st->conf &= ~AD7192_CONF_CHOP; 862 break; 863 case 3: 864 st->mode |= AD7192_MODE_SINC3; 865 866 st->conf &= ~AD7192_CONF_CHOP; 867 break; 868 } 869 870 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 871 if (ret < 0) 872 return ret; 873 874 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 875 } 876 877 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) 878 { 879 unsigned int fadc; 880 881 fadc = ad7192_get_f_adc(st); 882 883 if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) 884 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 885 if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) 886 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 887 else 888 return DIV_ROUND_CLOSEST(fadc * 230, 1024); 889 } 890 891 static int ad7192_read_raw(struct iio_dev *indio_dev, 892 struct iio_chan_spec const *chan, 893 int *val, 894 int *val2, 895 long m) 896 { 897 struct ad7192_state *st = iio_priv(indio_dev); 898 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); 899 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); 900 901 switch (m) { 902 case IIO_CHAN_INFO_RAW: 903 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 904 case IIO_CHAN_INFO_SCALE: 905 switch (chan->type) { 906 case IIO_VOLTAGE: 907 mutex_lock(&st->lock); 908 *val = st->scale_avail[gain][0]; 909 *val2 = st->scale_avail[gain][1]; 910 mutex_unlock(&st->lock); 911 return IIO_VAL_INT_PLUS_NANO; 912 case IIO_TEMP: 913 *val = 0; 914 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar); 915 return IIO_VAL_INT_PLUS_NANO; 916 default: 917 return -EINVAL; 918 } 919 case IIO_CHAN_INFO_OFFSET: 920 if (!unipolar) 921 *val = -(1 << (chan->scan_type.realbits - 1)); 922 else 923 *val = 0; 924 925 switch (chan->type) { 926 case IIO_VOLTAGE: 927 /* 928 * Only applies to pseudo-differential inputs. 929 * AINCOM voltage has to be converted to "raw" units. 930 */ 931 if (st->aincom_mv && !chan->differential) 932 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO, 933 st->scale_avail[gain][1]); 934 return IIO_VAL_INT; 935 /* Kelvin to Celsius */ 936 case IIO_TEMP: 937 *val -= 273 * ad7192_get_temp_scale(unipolar); 938 return IIO_VAL_INT; 939 default: 940 return -EINVAL; 941 } 942 case IIO_CHAN_INFO_SAMP_FREQ: 943 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); 944 return IIO_VAL_INT; 945 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 946 *val = ad7192_get_3db_filter_freq(st); 947 *val2 = 1000; 948 return IIO_VAL_FRACTIONAL; 949 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 950 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; 951 return IIO_VAL_INT; 952 } 953 954 return -EINVAL; 955 } 956 957 static int __ad7192_write_raw(struct iio_dev *indio_dev, 958 struct iio_chan_spec const *chan, 959 int val, 960 int val2, 961 long mask) 962 { 963 struct ad7192_state *st = iio_priv(indio_dev); 964 int i, div; 965 unsigned int tmp; 966 967 guard(mutex)(&st->lock); 968 969 switch (mask) { 970 case IIO_CHAN_INFO_SCALE: 971 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 972 if (val2 != st->scale_avail[i][1]) 973 continue; 974 975 tmp = st->conf; 976 st->conf &= ~AD7192_CONF_GAIN_MASK; 977 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); 978 if (tmp == st->conf) 979 return 0; 980 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 981 ad7192_calibrate_all(st); 982 return 0; 983 } 984 return -EINVAL; 985 case IIO_CHAN_INFO_SAMP_FREQ: 986 if (!val) 987 return -EINVAL; 988 989 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); 990 if (div < 1 || div > 1023) 991 return -EINVAL; 992 993 st->mode &= ~AD7192_MODE_RATE_MASK; 994 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); 995 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 996 ad7192_update_filter_freq_avail(st); 997 return 0; 998 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 999 return ad7192_set_3db_filter_freq(st, val, val2 / 1000); 1000 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1001 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) { 1002 if (val != st->oversampling_ratio_avail[i]) 1003 continue; 1004 1005 tmp = st->mode; 1006 st->mode &= ~AD7192_MODE_AVG_MASK; 1007 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); 1008 if (tmp == st->mode) 1009 return 0; 1010 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 1011 ad7192_update_filter_freq_avail(st); 1012 return 0; 1013 } 1014 return -EINVAL; 1015 default: 1016 return -EINVAL; 1017 } 1018 } 1019 1020 static int ad7192_write_raw(struct iio_dev *indio_dev, 1021 struct iio_chan_spec const *chan, 1022 int val, 1023 int val2, 1024 long mask) 1025 { 1026 int ret; 1027 1028 if (!iio_device_claim_direct(indio_dev)) 1029 return -EBUSY; 1030 1031 ret = __ad7192_write_raw(indio_dev, chan, val, val2, mask); 1032 1033 iio_device_release_direct(indio_dev); 1034 1035 return ret; 1036 } 1037 1038 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 1039 struct iio_chan_spec const *chan, 1040 long mask) 1041 { 1042 switch (mask) { 1043 case IIO_CHAN_INFO_SCALE: 1044 return IIO_VAL_INT_PLUS_NANO; 1045 case IIO_CHAN_INFO_SAMP_FREQ: 1046 return IIO_VAL_INT; 1047 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1048 return IIO_VAL_INT_PLUS_MICRO; 1049 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1050 return IIO_VAL_INT; 1051 default: 1052 return -EINVAL; 1053 } 1054 } 1055 1056 static int ad7192_read_avail(struct iio_dev *indio_dev, 1057 struct iio_chan_spec const *chan, 1058 const int **vals, int *type, int *length, 1059 long mask) 1060 { 1061 struct ad7192_state *st = iio_priv(indio_dev); 1062 1063 switch (mask) { 1064 case IIO_CHAN_INFO_SCALE: 1065 *vals = (int *)st->scale_avail; 1066 *type = IIO_VAL_INT_PLUS_NANO; 1067 /* Values are stored in a 2D matrix */ 1068 *length = ARRAY_SIZE(st->scale_avail) * 2; 1069 1070 return IIO_AVAIL_LIST; 1071 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1072 *vals = (int *)st->filter_freq_avail; 1073 *type = IIO_VAL_FRACTIONAL; 1074 *length = ARRAY_SIZE(st->filter_freq_avail) * 2; 1075 1076 return IIO_AVAIL_LIST; 1077 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1078 *vals = (int *)st->oversampling_ratio_avail; 1079 *type = IIO_VAL_INT; 1080 *length = ARRAY_SIZE(st->oversampling_ratio_avail); 1081 1082 return IIO_AVAIL_LIST; 1083 } 1084 1085 return -EINVAL; 1086 } 1087 1088 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) 1089 { 1090 struct ad7192_state *st = iio_priv(indio_dev); 1091 u32 conf = st->conf; 1092 int ret; 1093 int i; 1094 1095 conf &= ~AD7192_CONF_CHAN_MASK; 1096 for_each_set_bit(i, scan_mask, 8) 1097 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, BIT(i)); 1098 1099 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 1100 if (ret < 0) 1101 return ret; 1102 1103 st->conf = conf; 1104 1105 return 0; 1106 } 1107 1108 static const struct iio_info ad7192_info = { 1109 .read_raw = ad7192_read_raw, 1110 .write_raw = ad7192_write_raw, 1111 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 1112 .read_avail = ad7192_read_avail, 1113 .attrs = &ad7192_attribute_group, 1114 .validate_trigger = ad_sd_validate_trigger, 1115 .update_scan_mode = ad7192_update_scan_mode, 1116 }; 1117 1118 static const struct iio_info ad7194_info = { 1119 .read_raw = ad7192_read_raw, 1120 .write_raw = ad7192_write_raw, 1121 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 1122 .read_avail = ad7192_read_avail, 1123 .validate_trigger = ad_sd_validate_trigger, 1124 }; 1125 1126 static const struct iio_info ad7195_info = { 1127 .read_raw = ad7192_read_raw, 1128 .write_raw = ad7192_write_raw, 1129 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 1130 .read_avail = ad7192_read_avail, 1131 .attrs = &ad7195_attribute_group, 1132 .validate_trigger = ad_sd_validate_trigger, 1133 .update_scan_mode = ad7192_update_scan_mode, 1134 }; 1135 1136 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \ 1137 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \ 1138 { \ 1139 .type = (_type), \ 1140 .differential = ((_channel2) == -1 ? 0 : 1), \ 1141 .indexed = 1, \ 1142 .channel = (_channel1), \ 1143 .channel2 = (_channel2), \ 1144 .address = (_address), \ 1145 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1146 BIT(IIO_CHAN_INFO_OFFSET), \ 1147 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 1148 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1149 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 1150 (_mask_all), \ 1151 .info_mask_shared_by_type_available = (_mask_type_av), \ 1152 .info_mask_shared_by_all_available = \ 1153 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 1154 (_mask_all_av), \ 1155 .ext_info = (_ext_info), \ 1156 .scan_index = (_si), \ 1157 .scan_type = { \ 1158 .sign = 'u', \ 1159 .realbits = 24, \ 1160 .storagebits = 32, \ 1161 .endianness = IIO_BE, \ 1162 }, \ 1163 } 1164 1165 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 1166 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \ 1167 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 1168 1169 #define AD719x_CHANNEL(_si, _channel1, _address) \ 1170 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \ 1171 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info) 1172 1173 #define AD719x_TEMP_CHANNEL(_si, _address) \ 1174 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL) 1175 1176 #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 1177 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \ 1178 IIO_VOLTAGE, \ 1179 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1180 BIT(IIO_CHAN_INFO_SCALE), \ 1181 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1182 ad7192_calibsys_ext_info) 1183 1184 #define AD7193_CHANNEL(_si, _channel1, _address) \ 1185 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address) 1186 1187 static const struct iio_chan_spec ad7192_channels[] = { 1188 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), 1189 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M), 1190 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP), 1191 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M), 1192 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1), 1193 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2), 1194 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3), 1195 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4), 1196 IIO_CHAN_SOFT_TIMESTAMP(8), 1197 }; 1198 1199 static const struct iio_chan_spec ad7193_channels[] = { 1200 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 1201 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 1202 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 1203 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 1204 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 1205 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M), 1206 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1), 1207 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2), 1208 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3), 1209 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4), 1210 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5), 1211 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6), 1212 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7), 1213 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8), 1214 IIO_CHAN_SOFT_TIMESTAMP(14), 1215 }; 1216 1217 static bool ad7194_validate_ain_channel(struct device *dev, u32 ain) 1218 { 1219 return in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR); 1220 } 1221 1222 static int ad7194_parse_channels(struct iio_dev *indio_dev) 1223 { 1224 struct device *dev = indio_dev->dev.parent; 1225 struct iio_chan_spec *ad7194_channels; 1226 const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0); 1227 const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0); 1228 const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0); 1229 const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0); 1230 unsigned int num_channels, index = 0; 1231 u32 ain[2]; 1232 int ret; 1233 1234 num_channels = device_get_child_node_count(dev); 1235 if (num_channels > AD7194_CH_MAX_NR) 1236 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n", 1237 num_channels); 1238 1239 num_channels += AD7194_CH_BASE_NR; 1240 1241 ad7194_channels = devm_kcalloc(dev, num_channels, 1242 sizeof(*ad7194_channels), GFP_KERNEL); 1243 if (!ad7194_channels) 1244 return -ENOMEM; 1245 1246 indio_dev->channels = ad7194_channels; 1247 indio_dev->num_channels = num_channels; 1248 1249 device_for_each_child_node_scoped(dev, child) { 1250 ret = fwnode_property_read_u32_array(child, "diff-channels", 1251 ain, ARRAY_SIZE(ain)); 1252 if (ret == 0) { 1253 if (!ad7194_validate_ain_channel(dev, ain[0])) 1254 return dev_err_probe(dev, -EINVAL, 1255 "Invalid AIN channel: %u\n", 1256 ain[0]); 1257 1258 if (!ad7194_validate_ain_channel(dev, ain[1])) 1259 return dev_err_probe(dev, -EINVAL, 1260 "Invalid AIN channel: %u\n", 1261 ain[1]); 1262 1263 *ad7194_channels = ad7194_chan_diff; 1264 ad7194_channels->scan_index = index++; 1265 ad7194_channels->channel = ain[0]; 1266 ad7194_channels->channel2 = ain[1]; 1267 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]); 1268 } else { 1269 ret = fwnode_property_read_u32(child, "single-channel", 1270 &ain[0]); 1271 if (ret) 1272 return dev_err_probe(dev, ret, 1273 "Missing channel property\n"); 1274 1275 if (!ad7194_validate_ain_channel(dev, ain[0])) 1276 return dev_err_probe(dev, -EINVAL, 1277 "Invalid AIN channel: %u\n", 1278 ain[0]); 1279 1280 *ad7194_channels = ad7194_chan; 1281 ad7194_channels->scan_index = index++; 1282 ad7194_channels->channel = ain[0]; 1283 ad7194_channels->address = AD7194_CH(ain[0]); 1284 } 1285 ad7194_channels++; 1286 } 1287 1288 *ad7194_channels = ad7194_chan_temp; 1289 ad7194_channels->scan_index = index++; 1290 ad7194_channels->address = AD7194_CH_TEMP; 1291 ad7194_channels++; 1292 1293 *ad7194_channels = ad7194_chan_timestamp; 1294 ad7194_channels->scan_index = index; 1295 1296 return 0; 1297 } 1298 1299 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 1300 [ID_AD7190] = { 1301 .chip_id = CHIPID_AD7190, 1302 .name = "ad7190", 1303 .channels = ad7192_channels, 1304 .num_channels = ARRAY_SIZE(ad7192_channels), 1305 .sigma_delta_info = &ad7192_sigma_delta_info, 1306 .info = &ad7192_info, 1307 }, 1308 [ID_AD7192] = { 1309 .chip_id = CHIPID_AD7192, 1310 .name = "ad7192", 1311 .channels = ad7192_channels, 1312 .num_channels = ARRAY_SIZE(ad7192_channels), 1313 .sigma_delta_info = &ad7192_sigma_delta_info, 1314 .info = &ad7192_info, 1315 }, 1316 [ID_AD7193] = { 1317 .chip_id = CHIPID_AD7193, 1318 .name = "ad7193", 1319 .channels = ad7193_channels, 1320 .num_channels = ARRAY_SIZE(ad7193_channels), 1321 .sigma_delta_info = &ad7192_sigma_delta_info, 1322 .info = &ad7192_info, 1323 }, 1324 [ID_AD7194] = { 1325 .chip_id = CHIPID_AD7194, 1326 .name = "ad7194", 1327 .info = &ad7194_info, 1328 .sigma_delta_info = &ad7194_sigma_delta_info, 1329 .parse_channels = ad7194_parse_channels, 1330 }, 1331 [ID_AD7195] = { 1332 .chip_id = CHIPID_AD7195, 1333 .name = "ad7195", 1334 .channels = ad7192_channels, 1335 .num_channels = ARRAY_SIZE(ad7192_channels), 1336 .sigma_delta_info = &ad7192_sigma_delta_info, 1337 .info = &ad7195_info, 1338 }, 1339 }; 1340 1341 static int ad7192_probe(struct spi_device *spi) 1342 { 1343 struct device *dev = &spi->dev; 1344 struct ad7192_state *st; 1345 struct iio_dev *indio_dev; 1346 int ret, avdd_mv; 1347 1348 if (!spi->irq) 1349 return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n"); 1350 1351 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1352 if (!indio_dev) 1353 return -ENOMEM; 1354 1355 st = iio_priv(indio_dev); 1356 1357 mutex_init(&st->lock); 1358 1359 /* 1360 * Regulator aincom is optional to maintain compatibility with older DT. 1361 * Newer firmware should provide a zero volt fixed supply if wired to 1362 * ground. 1363 */ 1364 ret = devm_regulator_get_enable_read_voltage(dev, "aincom"); 1365 if (ret < 0 && ret != -ENODEV) 1366 return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n"); 1367 1368 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI; 1369 1370 /* AVDD can optionally be used as reference voltage */ 1371 ret = devm_regulator_get_enable_read_voltage(dev, "avdd"); 1372 if (ret == -ENODEV || ret == -EINVAL) { 1373 int ret2; 1374 1375 /* 1376 * We get -EINVAL if avdd is a supply with unknown voltage. We 1377 * still need to enable it since it is also a power supply. 1378 */ 1379 ret2 = devm_regulator_get_enable(dev, "avdd"); 1380 if (ret2) 1381 return dev_err_probe(dev, ret2, 1382 "Failed to enable AVDD supply\n"); 1383 } else if (ret < 0) { 1384 return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n"); 1385 } 1386 1387 avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI; 1388 1389 ret = devm_regulator_get_enable(dev, "dvdd"); 1390 if (ret) 1391 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n"); 1392 1393 /* 1394 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable. 1395 * If this supply is not present, fall back to AVDD as reference. 1396 */ 1397 ret = devm_regulator_get_enable_read_voltage(dev, "vref"); 1398 if (ret == -ENODEV) { 1399 if (avdd_mv == 0) 1400 return dev_err_probe(dev, -ENODEV, 1401 "No reference voltage available\n"); 1402 } else if (ret < 0) { 1403 return ret; 1404 } 1405 1406 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI; 1407 1408 st->chip_info = spi_get_device_match_data(spi); 1409 indio_dev->name = st->chip_info->name; 1410 indio_dev->modes = INDIO_DIRECT_MODE; 1411 indio_dev->info = st->chip_info->info; 1412 if (st->chip_info->parse_channels) { 1413 ret = st->chip_info->parse_channels(indio_dev); 1414 if (ret) 1415 return ret; 1416 } else { 1417 indio_dev->channels = st->chip_info->channels; 1418 indio_dev->num_channels = st->chip_info->num_channels; 1419 } 1420 1421 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info); 1422 if (ret) 1423 return ret; 1424 1425 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1426 if (ret) 1427 return ret; 1428 1429 ret = ad7192_clock_setup(st); 1430 if (ret) 1431 return ret; 1432 1433 ret = ad7192_setup(indio_dev, dev); 1434 if (ret) 1435 return ret; 1436 1437 return devm_iio_device_register(dev, indio_dev); 1438 } 1439 1440 static const struct of_device_id ad7192_of_match[] = { 1441 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 1442 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 1443 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 1444 { .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] }, 1445 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 1446 { } 1447 }; 1448 MODULE_DEVICE_TABLE(of, ad7192_of_match); 1449 1450 static const struct spi_device_id ad7192_ids[] = { 1451 { .name = "ad7190", .driver_data = (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] }, 1452 { .name = "ad7192", .driver_data = (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] }, 1453 { .name = "ad7193", .driver_data = (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] }, 1454 { .name = "ad7194", .driver_data = (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] }, 1455 { .name = "ad7195", .driver_data = (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] }, 1456 { } 1457 }; 1458 MODULE_DEVICE_TABLE(spi, ad7192_ids); 1459 1460 static struct spi_driver ad7192_driver = { 1461 .driver = { 1462 .name = "ad7192", 1463 .of_match_table = ad7192_of_match, 1464 }, 1465 .probe = ad7192_probe, 1466 .id_table = ad7192_ids, 1467 }; 1468 module_spi_driver(ad7192_driver); 1469 1470 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1471 MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC"); 1472 MODULE_LICENSE("GPL v2"); 1473 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1474