1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD7191 ADC driver 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/mutex.h> 16 #include <linux/property.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/spi/spi.h> 19 #include <linux/types.h> 20 #include <linux/units.h> 21 22 #include <linux/iio/adc/ad_sigma_delta.h> 23 #include <linux/iio/iio.h> 24 25 #define ad_sigma_delta_to_ad7191(sigmad) \ 26 container_of((sigmad), struct ad7191_state, sd) 27 28 #define AD7191_TEMP_CODES_PER_DEGREE 2815 29 30 #define AD7191_CHAN_MASK BIT(0) 31 #define AD7191_TEMP_MASK BIT(1) 32 33 enum ad7191_channel { 34 AD7191_CH_AIN1_AIN2, 35 AD7191_CH_AIN3_AIN4, 36 AD7191_CH_TEMP, 37 }; 38 39 /* 40 * NOTE: 41 * The AD7191 features a dual-use data out ready DOUT/RDY output. 42 * In order to avoid contentions on the SPI bus, it's therefore necessary 43 * to use SPI bus locking. 44 * 45 * The DOUT/RDY output must also be wired to an interrupt-capable GPIO. 46 * 47 * The SPI controller's chip select must be connected to the PDOWN pin 48 * of the ADC. When CS (PDOWN) is high, it powers down the device and 49 * resets the internal circuitry. 50 */ 51 52 struct ad7191_state { 53 struct ad_sigma_delta sd; 54 struct mutex lock; /* Protect device state */ 55 56 struct gpio_descs *odr_gpios; 57 struct gpio_descs *pga_gpios; 58 struct gpio_desc *temp_gpio; 59 struct gpio_desc *chan_gpio; 60 61 u16 int_vref_mv; 62 const u32 (*scale_avail)[2]; 63 size_t scale_avail_size; 64 u32 scale_index; 65 const u32 *samp_freq_avail; 66 size_t samp_freq_avail_size; 67 u32 samp_freq_index; 68 69 struct clk *mclk; 70 }; 71 72 static int ad7191_set_channel(struct ad_sigma_delta *sd, unsigned int address) 73 { 74 struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd); 75 u8 temp_gpio_val, chan_gpio_val; 76 77 if (!FIELD_FIT(AD7191_CHAN_MASK | AD7191_TEMP_MASK, address)) 78 return -EINVAL; 79 80 chan_gpio_val = FIELD_GET(AD7191_CHAN_MASK, address); 81 temp_gpio_val = FIELD_GET(AD7191_TEMP_MASK, address); 82 83 gpiod_set_value(st->chan_gpio, chan_gpio_val); 84 gpiod_set_value(st->temp_gpio, temp_gpio_val); 85 86 return 0; 87 } 88 89 static int ad7191_set_cs(struct ad_sigma_delta *sigma_delta, int assert) 90 { 91 struct spi_transfer t = { 92 .len = 0, 93 .cs_change = assert, 94 }; 95 struct spi_message m; 96 97 spi_message_init_with_transfers(&m, &t, 1); 98 99 return spi_sync_locked(sigma_delta->spi, &m); 100 } 101 102 static int ad7191_set_mode(struct ad_sigma_delta *sd, 103 enum ad_sigma_delta_mode mode) 104 { 105 struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd); 106 107 switch (mode) { 108 case AD_SD_MODE_CONTINUOUS: 109 case AD_SD_MODE_SINGLE: 110 return ad7191_set_cs(&st->sd, 1); 111 case AD_SD_MODE_IDLE: 112 return ad7191_set_cs(&st->sd, 0); 113 default: 114 return -EINVAL; 115 } 116 } 117 118 static const struct ad_sigma_delta_info ad7191_sigma_delta_info = { 119 .set_channel = ad7191_set_channel, 120 .set_mode = ad7191_set_mode, 121 .has_registers = false, 122 }; 123 124 static int ad7191_init_regulators(struct iio_dev *indio_dev) 125 { 126 struct ad7191_state *st = iio_priv(indio_dev); 127 struct device *dev = &st->sd.spi->dev; 128 int ret; 129 130 ret = devm_regulator_get_enable(dev, "avdd"); 131 if (ret) 132 return dev_err_probe(dev, ret, "Failed to enable specified AVdd supply\n"); 133 134 ret = devm_regulator_get_enable(dev, "dvdd"); 135 if (ret) 136 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n"); 137 138 ret = devm_regulator_get_enable_read_voltage(dev, "vref"); 139 if (ret < 0) 140 return dev_err_probe(dev, ret, "Failed to get Vref voltage\n"); 141 142 st->int_vref_mv = ret / 1000; 143 144 return 0; 145 } 146 147 static int ad7191_config_setup(struct iio_dev *indio_dev) 148 { 149 struct ad7191_state *st = iio_priv(indio_dev); 150 struct device *dev = &st->sd.spi->dev; 151 /* Sampling frequencies in Hz, see Table 5 */ 152 static const u32 samp_freq[4] = { 120, 60, 50, 10 }; 153 /* Gain options, see Table 7 */ 154 const u32 gain[4] = { 1, 8, 64, 128 }; 155 static u32 scale_buffer[4][2]; 156 int odr_value, odr_index = 0, pga_value, pga_index = 0, i, ret; 157 const char *propname; 158 u64 scale_uv; 159 160 st->samp_freq_index = 0; 161 st->scale_index = 0; 162 163 propname = "adi,odr-value"; 164 if (device_property_present(dev, propname)) { 165 ret = device_property_read_u32(dev, propname, &odr_value); 166 if (ret) 167 return dev_err_probe(dev, ret, "Failed to get %s.\n", propname); 168 169 for (i = 0; i < ARRAY_SIZE(samp_freq); i++) { 170 if (odr_value != samp_freq[i]) 171 continue; 172 odr_index = i; 173 break; 174 } 175 176 st->samp_freq_avail = &samp_freq[odr_index]; 177 st->samp_freq_avail_size = 1; 178 179 st->odr_gpios = NULL; 180 } else { 181 st->odr_gpios = devm_gpiod_get_array(dev, "odr", GPIOD_OUT_LOW); 182 if (IS_ERR(st->odr_gpios)) 183 return dev_err_probe(dev, PTR_ERR(st->odr_gpios), 184 "Failed to get odr gpios.\n"); 185 186 if (st->odr_gpios->ndescs != 2) 187 return dev_err_probe(dev, -EINVAL, "Expected 2 odr gpio pins.\n"); 188 189 st->samp_freq_avail = samp_freq; 190 st->samp_freq_avail_size = ARRAY_SIZE(samp_freq); 191 } 192 193 mutex_lock(&st->lock); 194 195 for (i = 0; i < ARRAY_SIZE(scale_buffer); i++) { 196 scale_uv = ((u64)st->int_vref_mv * NANO) >> 197 (indio_dev->channels[0].scan_type.realbits - 1); 198 do_div(scale_uv, gain[i]); 199 scale_buffer[i][1] = do_div(scale_uv, NANO); 200 scale_buffer[i][0] = scale_uv; 201 } 202 203 mutex_unlock(&st->lock); 204 205 propname = "adi,pga-value"; 206 if (device_property_present(dev, propname)) { 207 ret = device_property_read_u32(dev, propname, &pga_value); 208 if (ret) 209 return dev_err_probe(dev, ret, "Failed to get %s.\n", propname); 210 211 for (i = 0; i < ARRAY_SIZE(gain); i++) { 212 if (pga_value != gain[i]) 213 continue; 214 pga_index = i; 215 break; 216 } 217 218 st->scale_avail = &scale_buffer[pga_index]; 219 st->scale_avail_size = 1; 220 221 st->pga_gpios = NULL; 222 } else { 223 st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); 224 if (IS_ERR(st->pga_gpios)) 225 return dev_err_probe(dev, PTR_ERR(st->pga_gpios), 226 "Failed to get pga gpios.\n"); 227 228 if (st->pga_gpios->ndescs != 2) 229 return dev_err_probe(dev, -EINVAL, "Expected 2 pga gpio pins.\n"); 230 231 st->scale_avail = scale_buffer; 232 st->scale_avail_size = ARRAY_SIZE(scale_buffer); 233 } 234 235 st->temp_gpio = devm_gpiod_get(dev, "temp", GPIOD_OUT_LOW); 236 if (IS_ERR(st->temp_gpio)) 237 return dev_err_probe(dev, PTR_ERR(st->temp_gpio), 238 "Failed to get temp gpio.\n"); 239 240 st->chan_gpio = devm_gpiod_get(dev, "chan", GPIOD_OUT_LOW); 241 if (IS_ERR(st->chan_gpio)) 242 return dev_err_probe(dev, PTR_ERR(st->chan_gpio), 243 "Failed to get chan gpio.\n"); 244 245 return 0; 246 } 247 248 static int ad7191_clock_setup(struct ad7191_state *st) 249 { 250 struct device *dev = &st->sd.spi->dev; 251 252 st->mclk = devm_clk_get_optional_enabled(dev, "mclk"); 253 if (IS_ERR(st->mclk)) 254 return dev_err_probe(dev, PTR_ERR(st->mclk), 255 "Failed to get mclk.\n"); 256 257 return 0; 258 } 259 260 static int ad7191_setup(struct iio_dev *indio_dev) 261 { 262 struct ad7191_state *st = iio_priv(indio_dev); 263 int ret; 264 265 ret = ad7191_init_regulators(indio_dev); 266 if (ret) 267 return ret; 268 269 ret = ad7191_config_setup(indio_dev); 270 if (ret) 271 return ret; 272 273 return ad7191_clock_setup(st); 274 } 275 276 static int ad7191_read_raw(struct iio_dev *indio_dev, 277 struct iio_chan_spec const *chan, int *val, 278 int *val2, long m) 279 { 280 struct ad7191_state *st = iio_priv(indio_dev); 281 282 switch (m) { 283 case IIO_CHAN_INFO_RAW: 284 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 285 case IIO_CHAN_INFO_SCALE: 286 switch (chan->type) { 287 case IIO_VOLTAGE: { 288 guard(mutex)(&st->lock); 289 *val = st->scale_avail[st->scale_index][0]; 290 *val2 = st->scale_avail[st->scale_index][1]; 291 return IIO_VAL_INT_PLUS_NANO; 292 } 293 case IIO_TEMP: 294 *val = 0; 295 *val2 = NANO / AD7191_TEMP_CODES_PER_DEGREE; 296 return IIO_VAL_INT_PLUS_NANO; 297 default: 298 return -EINVAL; 299 } 300 case IIO_CHAN_INFO_OFFSET: 301 *val = -(1 << (chan->scan_type.realbits - 1)); 302 switch (chan->type) { 303 case IIO_VOLTAGE: 304 return IIO_VAL_INT; 305 case IIO_TEMP: 306 *val -= 273 * AD7191_TEMP_CODES_PER_DEGREE; 307 return IIO_VAL_INT; 308 default: 309 return -EINVAL; 310 } 311 case IIO_CHAN_INFO_SAMP_FREQ: 312 *val = st->samp_freq_avail[st->samp_freq_index]; 313 return IIO_VAL_INT; 314 default: 315 return -EINVAL; 316 } 317 } 318 319 static int ad7191_set_gain(struct ad7191_state *st, int gain_index) 320 { 321 DECLARE_BITMAP(bitmap, 2) = { }; 322 323 st->scale_index = gain_index; 324 325 bitmap_write(bitmap, gain_index, 0, 2); 326 327 return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); 328 } 329 330 static int ad7191_set_samp_freq(struct ad7191_state *st, int samp_freq_index) 331 { 332 DECLARE_BITMAP(bitmap, 2) = {}; 333 334 st->samp_freq_index = samp_freq_index; 335 336 bitmap_write(bitmap, samp_freq_index, 0, 2); 337 338 return gpiod_multi_set_value_cansleep(st->odr_gpios, bitmap); 339 } 340 341 static int __ad7191_write_raw(struct ad7191_state *st, 342 struct iio_chan_spec const *chan, 343 int val, int val2, long mask) 344 { 345 int i; 346 347 switch (mask) { 348 case IIO_CHAN_INFO_SCALE: { 349 if (!st->pga_gpios) 350 return -EPERM; 351 guard(mutex)(&st->lock); 352 for (i = 0; i < st->scale_avail_size; i++) { 353 if (val2 == st->scale_avail[i][1]) 354 return ad7191_set_gain(st, i); 355 } 356 return -EINVAL; 357 } 358 case IIO_CHAN_INFO_SAMP_FREQ: { 359 if (!st->odr_gpios) 360 return -EPERM; 361 guard(mutex)(&st->lock); 362 for (i = 0; i < st->samp_freq_avail_size; i++) { 363 if (val == st->samp_freq_avail[i]) 364 return ad7191_set_samp_freq(st, i); 365 } 366 return -EINVAL; 367 } 368 default: 369 return -EINVAL; 370 } 371 } 372 373 static int ad7191_write_raw(struct iio_dev *indio_dev, 374 struct iio_chan_spec const *chan, int val, int val2, 375 long mask) 376 { 377 struct ad7191_state *st = iio_priv(indio_dev); 378 int ret; 379 380 if (!iio_device_claim_direct(indio_dev)) 381 return -EBUSY; 382 383 ret = __ad7191_write_raw(st, chan, val, val2, mask); 384 385 iio_device_release_direct(indio_dev); 386 387 return ret; 388 } 389 390 static int ad7191_write_raw_get_fmt(struct iio_dev *indio_dev, 391 struct iio_chan_spec const *chan, long mask) 392 { 393 switch (mask) { 394 case IIO_CHAN_INFO_SCALE: 395 return IIO_VAL_INT_PLUS_NANO; 396 case IIO_CHAN_INFO_SAMP_FREQ: 397 return IIO_VAL_INT; 398 default: 399 return -EINVAL; 400 } 401 } 402 403 static int ad7191_read_avail(struct iio_dev *indio_dev, 404 struct iio_chan_spec const *chan, const int **vals, 405 int *type, int *length, long mask) 406 { 407 struct ad7191_state *st = iio_priv(indio_dev); 408 409 switch (mask) { 410 case IIO_CHAN_INFO_SCALE: 411 *vals = (int *)st->scale_avail; 412 *type = IIO_VAL_INT_PLUS_NANO; 413 *length = st->scale_avail_size * 2; 414 return IIO_AVAIL_LIST; 415 case IIO_CHAN_INFO_SAMP_FREQ: 416 *vals = (int *)st->samp_freq_avail; 417 *type = IIO_VAL_INT; 418 *length = st->samp_freq_avail_size; 419 return IIO_AVAIL_LIST; 420 } 421 422 return -EINVAL; 423 } 424 425 static const struct iio_info ad7191_info = { 426 .read_raw = ad7191_read_raw, 427 .write_raw = ad7191_write_raw, 428 .write_raw_get_fmt = ad7191_write_raw_get_fmt, 429 .read_avail = ad7191_read_avail, 430 .validate_trigger = ad_sd_validate_trigger, 431 }; 432 433 static const struct iio_chan_spec ad7191_channels[] = { 434 { 435 .type = IIO_TEMP, 436 .address = AD7191_CH_TEMP, 437 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 438 BIT(IIO_CHAN_INFO_OFFSET) | 439 BIT(IIO_CHAN_INFO_SAMP_FREQ), 440 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 441 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 442 .scan_type = { 443 .sign = 'u', 444 .realbits = 24, 445 .storagebits = 32, 446 .endianness = IIO_BE, 447 }, 448 }, 449 { 450 .type = IIO_VOLTAGE, 451 .differential = 1, 452 .indexed = 1, 453 .channel = 1, 454 .channel2 = 2, 455 .address = AD7191_CH_AIN1_AIN2, 456 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 457 BIT(IIO_CHAN_INFO_OFFSET) | 458 BIT(IIO_CHAN_INFO_SAMP_FREQ), 459 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 460 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 461 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), 462 .scan_index = 1, 463 .scan_type = { 464 .sign = 'u', 465 .realbits = 24, 466 .storagebits = 32, 467 .endianness = IIO_BE, 468 }, 469 }, 470 { 471 .type = IIO_VOLTAGE, 472 .differential = 1, 473 .indexed = 1, 474 .channel = 3, 475 .channel2 = 4, 476 .address = AD7191_CH_AIN3_AIN4, 477 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 478 BIT(IIO_CHAN_INFO_OFFSET) | 479 BIT(IIO_CHAN_INFO_SAMP_FREQ), 480 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 481 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 482 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), 483 .scan_index = 2, 484 .scan_type = { 485 .sign = 'u', 486 .realbits = 24, 487 .storagebits = 32, 488 .endianness = IIO_BE, 489 }, 490 }, 491 IIO_CHAN_SOFT_TIMESTAMP(3), 492 }; 493 494 static int ad7191_probe(struct spi_device *spi) 495 { 496 struct device *dev = &spi->dev; 497 struct ad7191_state *st; 498 struct iio_dev *indio_dev; 499 int ret; 500 501 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 502 if (!indio_dev) 503 return -ENOMEM; 504 505 st = iio_priv(indio_dev); 506 507 ret = devm_mutex_init(dev, &st->lock); 508 if (ret) 509 return ret; 510 511 indio_dev->name = "ad7191"; 512 indio_dev->modes = INDIO_DIRECT_MODE; 513 indio_dev->channels = ad7191_channels; 514 indio_dev->num_channels = ARRAY_SIZE(ad7191_channels); 515 indio_dev->info = &ad7191_info; 516 517 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7191_sigma_delta_info); 518 if (ret) 519 return ret; 520 521 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 522 if (ret) 523 return ret; 524 525 ret = ad7191_setup(indio_dev); 526 if (ret) 527 return ret; 528 529 return devm_iio_device_register(dev, indio_dev); 530 } 531 532 static const struct of_device_id ad7191_of_match[] = { 533 { .compatible = "adi,ad7191", }, 534 { } 535 }; 536 MODULE_DEVICE_TABLE(of, ad7191_of_match); 537 538 static const struct spi_device_id ad7191_id_table[] = { 539 { "ad7191" }, 540 { } 541 }; 542 MODULE_DEVICE_TABLE(spi, ad7191_id_table); 543 544 static struct spi_driver ad7191_driver = { 545 .driver = { 546 .name = "ad7191", 547 .of_match_table = ad7191_of_match, 548 }, 549 .probe = ad7191_probe, 550 .id_table = ad7191_id_table, 551 }; 552 module_spi_driver(ad7191_driver); 553 554 MODULE_AUTHOR("Alisa-Dariana Roman <alisa.roman@analog.com>"); 555 MODULE_DESCRIPTION("Analog Devices AD7191 ADC"); 556 MODULE_LICENSE("GPL"); 557 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 558