1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x and AD411x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116 7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 8 * AD7175-8/AD7176-2/AD7177-2 9 * 10 * Copyright (C) 2015, 2024 Analog Devices, Inc. 11 */ 12 13 #include <linux/array_size.h> 14 #include <linux/bitfield.h> 15 #include <linux/bitmap.h> 16 #include <linux/container_of.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/gpio/regmap.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/math64.h> 27 #include <linux/module.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/spi/spi.h> 34 #include <linux/types.h> 35 #include <linux/units.h> 36 37 #include <linux/iio/buffer.h> 38 #include <linux/iio/events.h> 39 #include <linux/iio/iio.h> 40 #include <linux/iio/trigger_consumer.h> 41 #include <linux/iio/triggered_buffer.h> 42 43 #include <linux/iio/adc/ad_sigma_delta.h> 44 45 #define AD7173_REG_COMMS 0x00 46 #define AD7173_REG_ADC_MODE 0x01 47 #define AD7173_REG_INTERFACE_MODE 0x02 48 #define AD7173_REG_CRC 0x03 49 #define AD7173_REG_DATA 0x04 50 #define AD7173_REG_GPIO 0x06 51 #define AD7173_REG_ID 0x07 52 #define AD7173_REG_CH(x) (0x10 + (x)) 53 #define AD7173_REG_SETUP(x) (0x20 + (x)) 54 #define AD7173_REG_FILTER(x) (0x28 + (x)) 55 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 56 #define AD7173_REG_GAIN(x) (0x38 + (x)) 57 58 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 59 60 #define AD7173_CH_ENABLE BIT(15) 61 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 62 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 63 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 64 65 #define AD7173_NO_AINS_PER_CHANNEL 2 66 #define AD7173_CH_ADDRESS(pos, neg) \ 67 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 68 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 69 #define AD7173_AIN_TEMP_POS 17 70 #define AD7173_AIN_TEMP_NEG 18 71 #define AD7173_AIN_POW_MON_POS 19 72 #define AD7173_AIN_POW_MON_NEG 20 73 #define AD7173_AIN_REF_POS 21 74 #define AD7173_AIN_REF_NEG 22 75 76 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \ 77 (x) == AD7173_AIN_REF_NEG) 78 79 #define AD7172_2_ID 0x00d0 80 #define AD7176_ID 0x0c90 81 #define AD7175_ID 0x0cd0 82 #define AD7175_2_ID 0x0cd0 83 #define AD7172_4_ID 0x2050 84 #define AD7173_ID 0x30d0 85 #define AD4111_ID AD7173_ID 86 #define AD4112_ID AD7173_ID 87 #define AD4114_ID AD7173_ID 88 #define AD4113_ID 0x31d0 89 #define AD4116_ID 0x34d0 90 #define AD4115_ID 0x38d0 91 #define AD7175_8_ID 0x3cd0 92 #define AD7177_ID 0x4fd0 93 #define AD7173_ID_MASK GENMASK(15, 4) 94 95 #define AD7173_ADC_MODE_REF_EN BIT(15) 96 #define AD7173_ADC_MODE_SING_CYC BIT(13) 97 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 98 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 99 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 100 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 101 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 102 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 103 104 #define AD7173_GPIO_PDSW BIT(14) 105 #define AD7173_GPIO_OP_EN2_3 BIT(13) 106 #define AD4111_GPIO_GP_OW_EN BIT(12) 107 #define AD7173_GPIO_MUX_IO BIT(12) 108 #define AD7173_GPIO_SYNC_EN BIT(11) 109 #define AD7173_GPIO_ERR_EN BIT(10) 110 #define AD7173_GPIO_ERR_DAT BIT(9) 111 #define AD7173_GPIO_GP_DATA3 BIT(7) 112 #define AD7173_GPIO_GP_DATA2 BIT(6) 113 #define AD7173_GPIO_IP_EN1 BIT(5) 114 #define AD7173_GPIO_IP_EN0 BIT(4) 115 #define AD7173_GPIO_OP_EN1 BIT(3) 116 #define AD7173_GPIO_OP_EN0 BIT(2) 117 #define AD7173_GPIO_GP_DATA1 BIT(1) 118 #define AD7173_GPIO_GP_DATA0 BIT(0) 119 120 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 121 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 122 #define AD4111_GPO01_DATA(x) BIT((x) + 6) 123 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 124 125 #define AD7173_INTERFACE_DATA_STAT BIT(6) 126 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 127 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 128 129 #define AD7173_SETUP_BIPOLAR BIT(12) 130 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 131 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 132 133 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 134 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 135 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 136 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 137 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 138 #define AD7173_VOLTAGE_INT_REF_uV 2500000 139 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 140 #define AD7177_ODR_START_VALUE 0x07 141 #define AD4111_SHUNT_RESISTOR_OHM 50 142 #define AD4111_DIVIDER_RATIO 10 143 #define AD4111_CURRENT_CHAN_CUTOFF 16 144 #define AD4111_VINCOM_INPUT 0x10 145 146 /* pin < num_voltage_in is a normal voltage input */ 147 /* pin >= num_voltage_in_div is a voltage input without a divider */ 148 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \ 149 (pin2) < st->info->num_voltage_in && \ 150 (pin2) >= st->info->num_voltage_in_div) 151 152 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 153 #define AD7173_MAX_CONFIGS 8 154 #define AD4111_OW_DET_THRSH_MV 300 155 156 #define AD7173_MODE_CAL_INT_ZERO 0x4 /* Internal Zero-Scale Calibration */ 157 #define AD7173_MODE_CAL_INT_FULL 0x5 /* Internal Full-Scale Calibration */ 158 #define AD7173_MODE_CAL_SYS_ZERO 0x6 /* System Zero-Scale Calibration */ 159 #define AD7173_MODE_CAL_SYS_FULL 0x7 /* System Full-Scale Calibration */ 160 161 struct ad7173_device_info { 162 const unsigned int *sinc5_data_rates; 163 unsigned int num_sinc5_data_rates; 164 unsigned int odr_start_value; 165 /* 166 * AD4116 has both inputs with a voltage divider and without. 167 * These inputs cannot be mixed in the channel configuration. 168 * Does not include the VINCOM input. 169 */ 170 unsigned int num_voltage_in_div; 171 unsigned int num_channels; 172 unsigned int num_configs; 173 unsigned int num_voltage_in; 174 unsigned int clock; 175 unsigned int id; 176 char *name; 177 const struct ad_sigma_delta_info *sd_info; 178 bool has_current_inputs; 179 bool has_vincom_input; 180 bool has_temp; 181 /* ((AVDD1 − AVSS)/5) */ 182 bool has_pow_supply_monitoring; 183 bool data_reg_only_16bit; 184 bool has_input_buf; 185 bool has_int_ref; 186 bool has_ref2; 187 bool has_internal_fs_calibration; 188 bool has_openwire_det; 189 bool higher_gpio_bits; 190 u8 num_gpios; 191 }; 192 193 struct ad7173_channel_config { 194 /* Openwire detection threshold */ 195 unsigned int openwire_thrsh_raw; 196 int openwire_comp_chan; 197 u8 cfg_slot; 198 bool live; 199 200 /* 201 * Following fields are used to compare equality. If you 202 * make adaptations in it, you most likely also have to adapt 203 * ad7173_is_setup_equal(), too. 204 */ 205 struct_group(config_props, 206 bool bipolar; 207 bool input_buf; 208 u8 odr; 209 u8 ref_sel; 210 ); 211 }; 212 213 struct ad7173_channel { 214 unsigned int ain; 215 struct ad7173_channel_config cfg; 216 u8 syscalib_mode; 217 bool openwire_det_en; 218 }; 219 220 struct ad7173_state { 221 struct ad_sigma_delta sd; 222 const struct ad7173_device_info *info; 223 struct ad7173_channel *channels; 224 struct regulator_bulk_data regulators[3]; 225 unsigned int adc_mode; 226 unsigned int interface_mode; 227 unsigned int num_channels; 228 struct ida cfg_slots_status; 229 unsigned long long config_usage_counter; 230 unsigned long long *config_cnts; 231 struct clk_hw int_clk_hw; 232 struct regmap *reg_gpiocon_regmap; 233 struct gpio_regmap *gpio_regmap; 234 }; 235 236 static unsigned int ad4115_sinc5_data_rates[] = { 237 24845000, 24845000, 20725000, 20725000, /* 0-3 */ 238 15564000, 13841000, 10390000, 10390000, /* 4-7 */ 239 4994000, 2499000, 1000000, 500000, /* 8-11 */ 240 395500, 200000, 100000, 59890, /* 12-15 */ 241 49920, 20000, 16660, 10000, /* 16-19 */ 242 5000, 2500, 2500, /* 20-22 */ 243 }; 244 245 static unsigned int ad4116_sinc5_data_rates[] = { 246 12422360, 12422360, 12422360, 12422360, /* 0-3 */ 247 10362690, 10362690, 7782100, 6290530, /* 4-7 */ 248 5194800, 2496900, 1007600, 499900, /* 8-11 */ 249 390600, 200300, 100000, 59750, /* 12-15 */ 250 49840, 20000, 16650, 10000, /* 16-19 */ 251 5000, 2500, 1250, /* 20-22 */ 252 }; 253 254 static const unsigned int ad7173_sinc5_data_rates[] = { 255 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 256 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 257 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 258 }; 259 260 static const unsigned int ad7175_sinc5_data_rates[] = { 261 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 262 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 263 5000000, 2500000, 1000000, 500000, /* 8-11 */ 264 397500, 200000, 100000, 59920, /* 12-15 */ 265 49960, 20000, 16666, 10000, /* 16-19 */ 266 5000, /* 20 */ 267 }; 268 269 static unsigned int ad4111_current_channel_config[] = { 270 /* Ain sel: pos neg */ 271 0x1E8, /* 15:IIN0+ 8:IIN0− */ 272 0x1C9, /* 14:IIN1+ 9:IIN1− */ 273 0x1AA, /* 13:IIN2+ 10:IIN2− */ 274 0x18B, /* 12:IIN3+ 11:IIN3− */ 275 }; 276 277 static const char *const ad7173_ref_sel_str[] = { 278 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 279 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 280 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 281 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 282 }; 283 284 static const char *const ad7173_clk_sel[] = { 285 "ext-clk", "xtal" 286 }; 287 288 static const struct regmap_range ad7173_range_gpio[] = { 289 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 290 }; 291 292 static const struct regmap_access_table ad7173_access_table = { 293 .yes_ranges = ad7173_range_gpio, 294 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 295 }; 296 297 static const struct regmap_config ad7173_regmap_config = { 298 .reg_bits = 8, 299 .val_bits = 16, 300 .rd_table = &ad7173_access_table, 301 .wr_table = &ad7173_access_table, 302 .read_flag_mask = BIT(6), 303 }; 304 305 enum { 306 AD7173_SYSCALIB_ZERO_SCALE, 307 AD7173_SYSCALIB_FULL_SCALE, 308 }; 309 310 static const char * const ad7173_syscalib_modes[] = { 311 [AD7173_SYSCALIB_ZERO_SCALE] = "zero_scale", 312 [AD7173_SYSCALIB_FULL_SCALE] = "full_scale", 313 }; 314 315 static int ad7173_set_syscalib_mode(struct iio_dev *indio_dev, 316 const struct iio_chan_spec *chan, 317 unsigned int mode) 318 { 319 struct ad7173_state *st = iio_priv(indio_dev); 320 321 st->channels[chan->address].syscalib_mode = mode; 322 323 return 0; 324 } 325 326 static int ad7173_get_syscalib_mode(struct iio_dev *indio_dev, 327 const struct iio_chan_spec *chan) 328 { 329 struct ad7173_state *st = iio_priv(indio_dev); 330 331 return st->channels[chan->address].syscalib_mode; 332 } 333 334 static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev, 335 uintptr_t private, 336 const struct iio_chan_spec *chan, 337 const char *buf, size_t len) 338 { 339 struct ad7173_state *st = iio_priv(indio_dev); 340 bool sys_calib; 341 int ret, mode; 342 343 ret = kstrtobool(buf, &sys_calib); 344 if (ret) 345 return ret; 346 347 if (!iio_device_claim_direct(indio_dev)) 348 return -EBUSY; 349 350 mode = st->channels[chan->address].syscalib_mode; 351 if (sys_calib) { 352 if (mode == AD7173_SYSCALIB_ZERO_SCALE) 353 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO, 354 chan->address); 355 else 356 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_FULL, 357 chan->address); 358 } 359 360 iio_device_release_direct(indio_dev); 361 362 return ret ? : len; 363 } 364 365 static const struct iio_enum ad7173_syscalib_mode_enum = { 366 .items = ad7173_syscalib_modes, 367 .num_items = ARRAY_SIZE(ad7173_syscalib_modes), 368 .set = ad7173_set_syscalib_mode, 369 .get = ad7173_get_syscalib_mode 370 }; 371 372 static const struct iio_chan_spec_ext_info ad7173_calibsys_ext_info[] = { 373 { 374 .name = "sys_calibration", 375 .write = ad7173_write_syscalib, 376 .shared = IIO_SEPARATE, 377 }, 378 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 379 &ad7173_syscalib_mode_enum), 380 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 381 &ad7173_syscalib_mode_enum), 382 { } 383 }; 384 385 static int ad7173_calibrate_all(struct ad7173_state *st, struct iio_dev *indio_dev) 386 { 387 int ret; 388 int i; 389 390 for (i = 0; i < st->num_channels; i++) { 391 if (indio_dev->channels[i].type != IIO_VOLTAGE) 392 continue; 393 394 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, i); 395 if (ret < 0) 396 return ret; 397 398 if (st->info->has_internal_fs_calibration) { 399 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL, i); 400 if (ret < 0) 401 return ret; 402 } 403 } 404 405 return 0; 406 } 407 408 /* 409 * Associative array of channel pairs for open wire detection 410 * The array is indexed by ain and gives the associated channel pair 411 * to perform the open wire detection with 412 * the channel pair [0] is for non differential and pair [1] 413 * is for differential inputs 414 */ 415 static int openwire_ain_to_channel_pair[][2][2] = { 416 /* AIN Single Differential */ 417 [0] = { { 0, 15 }, { 1, 2 } }, 418 [1] = { { 1, 2 }, { 2, 1 } }, 419 [2] = { { 3, 4 }, { 5, 6 } }, 420 [3] = { { 5, 6 }, { 6, 5 } }, 421 [4] = { { 7, 8 }, { 9, 10 } }, 422 [5] = { { 9, 10 }, { 10, 9 } }, 423 [6] = { { 11, 12 }, { 13, 14 } }, 424 [7] = { { 13, 14 }, { 14, 13 } }, 425 }; 426 427 /* 428 * Openwire detection on ad4111 works by running the same input measurement 429 * on two different channels and compare if the difference between the two 430 * measurements exceeds a certain value (typical 300mV) 431 */ 432 static int ad4111_openwire_event(struct iio_dev *indio_dev, 433 const struct iio_chan_spec *chan) 434 { 435 struct ad7173_state *st = iio_priv(indio_dev); 436 struct ad7173_channel *adchan = &st->channels[chan->address]; 437 struct ad7173_channel_config *cfg = &adchan->cfg; 438 int ret, val1, val2; 439 440 ret = regmap_set_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 441 AD4111_GPIO_GP_OW_EN); 442 if (ret) 443 return ret; 444 445 adchan->cfg.openwire_comp_chan = 446 openwire_ain_to_channel_pair[chan->channel][chan->differential][0]; 447 448 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val1); 449 if (ret < 0) { 450 dev_err(&indio_dev->dev, 451 "Error running ad_sigma_delta single conversion: %d", ret); 452 goto out; 453 } 454 455 adchan->cfg.openwire_comp_chan = 456 openwire_ain_to_channel_pair[chan->channel][chan->differential][1]; 457 458 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val2); 459 if (ret < 0) { 460 dev_err(&indio_dev->dev, 461 "Error running ad_sigma_delta single conversion: %d", ret); 462 goto out; 463 } 464 465 if (abs(val1 - val2) > cfg->openwire_thrsh_raw) 466 iio_push_event(indio_dev, 467 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, chan->address, 468 IIO_EV_TYPE_FAULT, IIO_EV_DIR_FAULT_OPENWIRE), 469 iio_get_time_ns(indio_dev)); 470 471 out: 472 adchan->cfg.openwire_comp_chan = -1; 473 regmap_clear_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 474 AD4111_GPIO_GP_OW_EN); 475 return ret; 476 } 477 478 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 479 unsigned int offset, unsigned int *reg, 480 unsigned int *mask) 481 { 482 *mask = AD7173_GPO_DATA(offset); 483 *reg = base; 484 return 0; 485 } 486 487 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 488 unsigned int offset, unsigned int *reg, 489 unsigned int *mask) 490 { 491 *mask = AD4111_GPO01_DATA(offset); 492 *reg = base; 493 return 0; 494 } 495 496 static void ad7173_gpio_disable(void *data) 497 { 498 struct ad7173_state *st = data; 499 unsigned int mask; 500 501 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 502 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 503 } 504 505 static int ad7173_gpio_init(struct ad7173_state *st) 506 { 507 struct gpio_regmap_config gpio_regmap = {}; 508 struct device *dev = &st->sd.spi->dev; 509 unsigned int mask; 510 int ret; 511 512 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 513 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 514 if (ret) 515 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 516 517 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 518 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 519 520 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 521 if (ret) 522 return ret; 523 524 gpio_regmap.parent = dev; 525 gpio_regmap.regmap = st->reg_gpiocon_regmap; 526 gpio_regmap.ngpio = st->info->num_gpios; 527 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 528 if (st->info->higher_gpio_bits) 529 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate; 530 else 531 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 532 533 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 534 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 535 if (ret) 536 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 537 538 return 0; 539 } 540 541 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 542 { 543 return container_of(sd, struct ad7173_state, sd); 544 } 545 546 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 547 { 548 return container_of(hw, struct ad7173_state, int_clk_hw); 549 } 550 551 static void ad7173_ida_destroy(void *data) 552 { 553 struct ad7173_state *st = data; 554 555 ida_destroy(&st->cfg_slots_status); 556 } 557 558 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 559 { 560 memset64(st->config_cnts, 0, st->info->num_configs); 561 st->config_usage_counter = 0; 562 } 563 564 /** 565 * ad7173_is_setup_equal - Compare two channel setups 566 * @cfg1: First channel configuration 567 * @cfg2: Second channel configuration 568 * 569 * Compares all configuration options that affect the registers connected to 570 * SETUP_SEL, namely CONFIGx, FILTERx, GAINx and OFFSETx. 571 * 572 * Returns: true if the setups are identical, false otherwise 573 */ 574 static bool ad7173_is_setup_equal(const struct ad7173_channel_config *cfg1, 575 const struct ad7173_channel_config *cfg2) 576 { 577 /* 578 * This is just to make sure that the comparison is adapted after 579 * struct ad7173_channel_config was changed. 580 */ 581 static_assert(sizeof_field(struct ad7173_channel_config, config_props) == 582 sizeof(struct { 583 bool bipolar; 584 bool input_buf; 585 u8 odr; 586 u8 ref_sel; 587 })); 588 589 return cfg1->bipolar == cfg2->bipolar && 590 cfg1->input_buf == cfg2->input_buf && 591 cfg1->odr == cfg2->odr && 592 cfg1->ref_sel == cfg2->ref_sel; 593 } 594 595 static struct ad7173_channel_config * 596 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 597 { 598 struct ad7173_channel_config *cfg_aux; 599 int i; 600 601 for (i = 0; i < st->num_channels; i++) { 602 cfg_aux = &st->channels[i].cfg; 603 604 if (cfg_aux->live && ad7173_is_setup_equal(cfg, cfg_aux)) 605 return cfg_aux; 606 } 607 return NULL; 608 } 609 610 /* Could be replaced with a generic LRU implementation */ 611 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 612 { 613 int i, lru_position = 0; 614 615 for (i = 1; i < st->info->num_configs; i++) 616 if (st->config_cnts[i] < st->config_cnts[lru_position]) 617 lru_position = i; 618 619 for (i = 0; i < st->num_channels; i++) 620 if (st->channels[i].cfg.cfg_slot == lru_position) 621 st->channels[i].cfg.live = false; 622 623 ida_free(&st->cfg_slots_status, lru_position); 624 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 625 } 626 627 /* Could be replaced with a generic LRU implementation */ 628 static int ad7173_load_config(struct ad7173_state *st, 629 struct ad7173_channel_config *cfg) 630 { 631 unsigned int config; 632 int free_cfg_slot, ret; 633 634 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 635 st->info->num_configs - 1, GFP_KERNEL); 636 if (free_cfg_slot < 0) 637 free_cfg_slot = ad7173_free_config_slot_lru(st); 638 639 cfg->cfg_slot = free_cfg_slot; 640 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 641 642 if (cfg->bipolar) 643 config |= AD7173_SETUP_BIPOLAR; 644 645 if (cfg->input_buf) 646 config |= AD7173_SETUP_AIN_BUF_MASK; 647 648 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 649 if (ret) 650 return ret; 651 652 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 653 AD7173_FILTER_ODR0_MASK & cfg->odr); 654 } 655 656 static int ad7173_config_channel(struct ad7173_state *st, int addr) 657 { 658 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 659 struct ad7173_channel_config *live_cfg; 660 int ret; 661 662 if (!cfg->live) { 663 live_cfg = ad7173_find_live_config(st, cfg); 664 if (live_cfg) { 665 cfg->cfg_slot = live_cfg->cfg_slot; 666 } else { 667 ret = ad7173_load_config(st, cfg); 668 if (ret) 669 return ret; 670 cfg->live = true; 671 } 672 } 673 674 if (st->config_usage_counter == U64_MAX) 675 ad7173_reset_usage_cnts(st); 676 677 st->config_usage_counter++; 678 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 679 680 return 0; 681 } 682 683 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 684 { 685 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 686 unsigned int val; 687 int ret; 688 689 ret = ad7173_config_channel(st, channel); 690 if (ret) 691 return ret; 692 693 val = AD7173_CH_ENABLE | 694 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 695 st->channels[channel].ain; 696 697 if (st->channels[channel].cfg.openwire_comp_chan >= 0) 698 channel = st->channels[channel].cfg.openwire_comp_chan; 699 700 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 701 } 702 703 static int ad7173_set_mode(struct ad_sigma_delta *sd, 704 enum ad_sigma_delta_mode mode) 705 { 706 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 707 708 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 709 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 710 711 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 712 } 713 714 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 715 { 716 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 717 unsigned int interface_mode = st->interface_mode; 718 int ret; 719 720 interface_mode &= ~AD7173_INTERFACE_DATA_STAT; 721 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 722 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 723 if (ret) 724 return ret; 725 726 st->interface_mode = interface_mode; 727 728 return 0; 729 } 730 731 static int ad7173_disable_all(struct ad_sigma_delta *sd) 732 { 733 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 734 int ret; 735 int i; 736 737 for (i = 0; i < st->num_channels; i++) { 738 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 739 if (ret < 0) 740 return ret; 741 } 742 743 return 0; 744 } 745 746 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 747 { 748 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 749 750 if (st->channels[chan].cfg.openwire_comp_chan >= 0) 751 chan = st->channels[chan].cfg.openwire_comp_chan; 752 753 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0); 754 } 755 756 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_4_slots = { 757 .set_channel = ad7173_set_channel, 758 .append_status = ad7173_append_status, 759 .disable_all = ad7173_disable_all, 760 .disable_one = ad7173_disable_one, 761 .set_mode = ad7173_set_mode, 762 .has_registers = true, 763 .has_named_irqs = true, 764 .addr_shift = 0, 765 .read_mask = BIT(6), 766 .status_ch_mask = GENMASK(3, 0), 767 .data_reg = AD7173_REG_DATA, 768 .num_resetclks = 64, 769 .num_slots = 4, 770 }; 771 772 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_8_slots = { 773 .set_channel = ad7173_set_channel, 774 .append_status = ad7173_append_status, 775 .disable_all = ad7173_disable_all, 776 .disable_one = ad7173_disable_one, 777 .set_mode = ad7173_set_mode, 778 .has_registers = true, 779 .has_named_irqs = true, 780 .addr_shift = 0, 781 .read_mask = BIT(6), 782 .status_ch_mask = GENMASK(3, 0), 783 .data_reg = AD7173_REG_DATA, 784 .num_resetclks = 64, 785 .num_slots = 8, 786 }; 787 788 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_16_slots = { 789 .set_channel = ad7173_set_channel, 790 .append_status = ad7173_append_status, 791 .disable_all = ad7173_disable_all, 792 .disable_one = ad7173_disable_one, 793 .set_mode = ad7173_set_mode, 794 .has_registers = true, 795 .has_named_irqs = true, 796 .addr_shift = 0, 797 .read_mask = BIT(6), 798 .status_ch_mask = GENMASK(3, 0), 799 .data_reg = AD7173_REG_DATA, 800 .num_resetclks = 64, 801 .num_slots = 16, 802 }; 803 804 static const struct ad7173_device_info ad4111_device_info = { 805 .name = "ad4111", 806 .id = AD4111_ID, 807 .sd_info = &ad7173_sigma_delta_info_16_slots, 808 .num_voltage_in_div = 8, 809 .num_channels = 16, 810 .num_configs = 8, 811 .num_voltage_in = 8, 812 .num_gpios = 2, 813 .higher_gpio_bits = true, 814 .has_temp = true, 815 .has_vincom_input = true, 816 .has_input_buf = true, 817 .has_current_inputs = true, 818 .has_int_ref = true, 819 .has_internal_fs_calibration = true, 820 .has_openwire_det = true, 821 .clock = 2 * HZ_PER_MHZ, 822 .sinc5_data_rates = ad7173_sinc5_data_rates, 823 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 824 }; 825 826 static const struct ad7173_device_info ad4112_device_info = { 827 .name = "ad4112", 828 .id = AD4112_ID, 829 .sd_info = &ad7173_sigma_delta_info_16_slots, 830 .num_voltage_in_div = 8, 831 .num_channels = 16, 832 .num_configs = 8, 833 .num_voltage_in = 8, 834 .num_gpios = 2, 835 .higher_gpio_bits = true, 836 .has_vincom_input = true, 837 .has_temp = true, 838 .has_input_buf = true, 839 .has_current_inputs = true, 840 .has_int_ref = true, 841 .has_internal_fs_calibration = true, 842 .clock = 2 * HZ_PER_MHZ, 843 .sinc5_data_rates = ad7173_sinc5_data_rates, 844 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 845 }; 846 847 static const struct ad7173_device_info ad4113_device_info = { 848 .name = "ad4113", 849 .id = AD4113_ID, 850 .sd_info = &ad7173_sigma_delta_info_16_slots, 851 .num_voltage_in_div = 8, 852 .num_channels = 16, 853 .num_configs = 8, 854 .num_voltage_in = 8, 855 .num_gpios = 2, 856 .data_reg_only_16bit = true, 857 .higher_gpio_bits = true, 858 .has_vincom_input = true, 859 .has_input_buf = true, 860 .has_int_ref = true, 861 .clock = 2 * HZ_PER_MHZ, 862 .sinc5_data_rates = ad7173_sinc5_data_rates, 863 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 864 }; 865 866 static const struct ad7173_device_info ad4114_device_info = { 867 .name = "ad4114", 868 .id = AD4114_ID, 869 .sd_info = &ad7173_sigma_delta_info_16_slots, 870 .num_voltage_in_div = 16, 871 .num_channels = 16, 872 .num_configs = 8, 873 .num_voltage_in = 16, 874 .num_gpios = 4, 875 .has_vincom_input = true, 876 .has_temp = true, 877 .has_input_buf = true, 878 .has_int_ref = true, 879 .has_internal_fs_calibration = true, 880 .clock = 2 * HZ_PER_MHZ, 881 .sinc5_data_rates = ad7173_sinc5_data_rates, 882 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 883 }; 884 885 static const struct ad7173_device_info ad4115_device_info = { 886 .name = "ad4115", 887 .id = AD4115_ID, 888 .sd_info = &ad7173_sigma_delta_info_16_slots, 889 .num_voltage_in_div = 16, 890 .num_channels = 16, 891 .num_configs = 8, 892 .num_voltage_in = 16, 893 .num_gpios = 4, 894 .has_vincom_input = true, 895 .has_temp = true, 896 .has_input_buf = true, 897 .has_int_ref = true, 898 .has_internal_fs_calibration = true, 899 .clock = 8 * HZ_PER_MHZ, 900 .sinc5_data_rates = ad4115_sinc5_data_rates, 901 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates), 902 }; 903 904 static const struct ad7173_device_info ad4116_device_info = { 905 .name = "ad4116", 906 .id = AD4116_ID, 907 .sd_info = &ad7173_sigma_delta_info_16_slots, 908 .num_voltage_in_div = 11, 909 .num_channels = 16, 910 .num_configs = 8, 911 .num_voltage_in = 16, 912 .num_gpios = 4, 913 .has_vincom_input = true, 914 .has_temp = true, 915 .has_input_buf = true, 916 .has_int_ref = true, 917 .has_internal_fs_calibration = true, 918 .clock = 4 * HZ_PER_MHZ, 919 .sinc5_data_rates = ad4116_sinc5_data_rates, 920 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates), 921 }; 922 923 static const struct ad7173_device_info ad7172_2_device_info = { 924 .name = "ad7172-2", 925 .id = AD7172_2_ID, 926 .sd_info = &ad7173_sigma_delta_info_4_slots, 927 .num_voltage_in = 5, 928 .num_channels = 4, 929 .num_configs = 4, 930 .num_gpios = 2, 931 .has_temp = true, 932 .has_input_buf = true, 933 .has_int_ref = true, 934 .has_pow_supply_monitoring = true, 935 .clock = 2 * HZ_PER_MHZ, 936 .sinc5_data_rates = ad7173_sinc5_data_rates, 937 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 938 }; 939 940 static const struct ad7173_device_info ad7172_4_device_info = { 941 .name = "ad7172-4", 942 .id = AD7172_4_ID, 943 .sd_info = &ad7173_sigma_delta_info_8_slots, 944 .num_voltage_in = 9, 945 .num_channels = 8, 946 .num_configs = 8, 947 .num_gpios = 4, 948 .has_input_buf = true, 949 .has_ref2 = true, 950 .has_pow_supply_monitoring = true, 951 .clock = 2 * HZ_PER_MHZ, 952 .sinc5_data_rates = ad7173_sinc5_data_rates, 953 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 954 }; 955 956 static const struct ad7173_device_info ad7173_8_device_info = { 957 .name = "ad7173-8", 958 .id = AD7173_ID, 959 .sd_info = &ad7173_sigma_delta_info_16_slots, 960 .num_voltage_in = 17, 961 .num_channels = 16, 962 .num_configs = 8, 963 .num_gpios = 4, 964 .has_temp = true, 965 .has_input_buf = true, 966 .has_int_ref = true, 967 .has_ref2 = true, 968 .clock = 2 * HZ_PER_MHZ, 969 .sinc5_data_rates = ad7173_sinc5_data_rates, 970 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 971 }; 972 973 static const struct ad7173_device_info ad7175_2_device_info = { 974 .name = "ad7175-2", 975 .id = AD7175_2_ID, 976 .sd_info = &ad7173_sigma_delta_info_4_slots, 977 .num_voltage_in = 5, 978 .num_channels = 4, 979 .num_configs = 4, 980 .num_gpios = 2, 981 .has_temp = true, 982 .has_input_buf = true, 983 .has_int_ref = true, 984 .has_pow_supply_monitoring = true, 985 .clock = 16 * HZ_PER_MHZ, 986 .sinc5_data_rates = ad7175_sinc5_data_rates, 987 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 988 }; 989 990 static const struct ad7173_device_info ad7175_8_device_info = { 991 .name = "ad7175-8", 992 .id = AD7175_8_ID, 993 .sd_info = &ad7173_sigma_delta_info_16_slots, 994 .num_voltage_in = 17, 995 .num_channels = 16, 996 .num_configs = 8, 997 .num_gpios = 4, 998 .has_temp = true, 999 .has_input_buf = true, 1000 .has_int_ref = true, 1001 .has_ref2 = true, 1002 .has_pow_supply_monitoring = true, 1003 .clock = 16 * HZ_PER_MHZ, 1004 .sinc5_data_rates = ad7175_sinc5_data_rates, 1005 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1006 }; 1007 1008 static const struct ad7173_device_info ad7176_2_device_info = { 1009 .name = "ad7176-2", 1010 .id = AD7176_ID, 1011 .sd_info = &ad7173_sigma_delta_info_4_slots, 1012 .num_voltage_in = 5, 1013 .num_channels = 4, 1014 .num_configs = 4, 1015 .num_gpios = 2, 1016 .has_int_ref = true, 1017 .clock = 16 * HZ_PER_MHZ, 1018 .sinc5_data_rates = ad7175_sinc5_data_rates, 1019 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1020 }; 1021 1022 static const struct ad7173_device_info ad7177_2_device_info = { 1023 .name = "ad7177-2", 1024 .id = AD7177_ID, 1025 .sd_info = &ad7173_sigma_delta_info_4_slots, 1026 .num_voltage_in = 5, 1027 .num_channels = 4, 1028 .num_configs = 4, 1029 .num_gpios = 2, 1030 .has_temp = true, 1031 .has_input_buf = true, 1032 .has_int_ref = true, 1033 .has_pow_supply_monitoring = true, 1034 .clock = 16 * HZ_PER_MHZ, 1035 .odr_start_value = AD7177_ODR_START_VALUE, 1036 .sinc5_data_rates = ad7175_sinc5_data_rates, 1037 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1038 }; 1039 1040 static int ad7173_setup(struct iio_dev *indio_dev) 1041 { 1042 struct ad7173_state *st = iio_priv(indio_dev); 1043 struct device *dev = &st->sd.spi->dev; 1044 u8 buf[AD7173_RESET_LENGTH]; 1045 unsigned int id; 1046 int ret; 1047 1048 /* reset the serial interface */ 1049 memset(buf, 0xff, AD7173_RESET_LENGTH); 1050 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 1051 if (ret < 0) 1052 return ret; 1053 1054 /* datasheet recommends a delay of at least 500us after reset */ 1055 fsleep(500); 1056 1057 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 1058 if (ret) 1059 return ret; 1060 1061 id &= AD7173_ID_MASK; 1062 if (id != st->info->id) 1063 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 1064 id, st->info->id); 1065 1066 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 1067 st->interface_mode = 0x0; 1068 1069 st->config_usage_counter = 0; 1070 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 1071 sizeof(*st->config_cnts), GFP_KERNEL); 1072 if (!st->config_cnts) 1073 return -ENOMEM; 1074 1075 ret = ad7173_calibrate_all(st, indio_dev); 1076 if (ret) 1077 return ret; 1078 1079 /* All channels are enabled by default after a reset */ 1080 return ad7173_disable_all(&st->sd); 1081 } 1082 1083 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 1084 u8 reference_select) 1085 { 1086 int vref; 1087 1088 switch (reference_select) { 1089 case AD7173_SETUP_REF_SEL_EXT_REF: 1090 vref = regulator_get_voltage(st->regulators[0].consumer); 1091 break; 1092 1093 case AD7173_SETUP_REF_SEL_EXT_REF2: 1094 vref = regulator_get_voltage(st->regulators[1].consumer); 1095 break; 1096 1097 case AD7173_SETUP_REF_SEL_INT_REF: 1098 vref = AD7173_VOLTAGE_INT_REF_uV; 1099 break; 1100 1101 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 1102 vref = regulator_get_voltage(st->regulators[2].consumer); 1103 break; 1104 1105 default: 1106 return -EINVAL; 1107 } 1108 1109 if (vref < 0) 1110 return vref; 1111 1112 return vref / (MICRO / MILLI); 1113 } 1114 1115 static int ad7173_read_raw(struct iio_dev *indio_dev, 1116 struct iio_chan_spec const *chan, 1117 int *val, int *val2, long info) 1118 { 1119 struct ad7173_state *st = iio_priv(indio_dev); 1120 struct ad7173_channel *ch = &st->channels[chan->address]; 1121 unsigned int reg; 1122 u64 temp; 1123 int ret; 1124 1125 switch (info) { 1126 case IIO_CHAN_INFO_RAW: 1127 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 1128 if (ret < 0) 1129 return ret; 1130 1131 if (ch->openwire_det_en) { 1132 ret = ad4111_openwire_event(indio_dev, chan); 1133 if (ret < 0) 1134 return ret; 1135 } 1136 1137 return IIO_VAL_INT; 1138 case IIO_CHAN_INFO_SCALE: 1139 1140 switch (chan->type) { 1141 case IIO_TEMP: 1142 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 1143 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 1144 *val = temp; 1145 *val2 = chan->scan_type.realbits; 1146 return IIO_VAL_FRACTIONAL_LOG2; 1147 case IIO_VOLTAGE: 1148 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1149 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 1150 1151 if (chan->channel < st->info->num_voltage_in_div) 1152 *val *= AD4111_DIVIDER_RATIO; 1153 return IIO_VAL_FRACTIONAL_LOG2; 1154 case IIO_CURRENT: 1155 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1156 *val /= AD4111_SHUNT_RESISTOR_OHM; 1157 *val2 = chan->scan_type.realbits - ch->cfg.bipolar; 1158 return IIO_VAL_FRACTIONAL_LOG2; 1159 default: 1160 return -EINVAL; 1161 } 1162 case IIO_CHAN_INFO_OFFSET: 1163 1164 switch (chan->type) { 1165 case IIO_TEMP: 1166 /* 0 Kelvin -> raw sample */ 1167 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 1168 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 1169 temp <<= chan->scan_type.realbits; 1170 temp = DIV_U64_ROUND_CLOSEST(temp, 1171 AD7173_VOLTAGE_INT_REF_uV * 1172 MILLI); 1173 *val = -temp; 1174 return IIO_VAL_INT; 1175 case IIO_VOLTAGE: 1176 case IIO_CURRENT: 1177 *val = -BIT(chan->scan_type.realbits - 1); 1178 return IIO_VAL_INT; 1179 default: 1180 return -EINVAL; 1181 } 1182 case IIO_CHAN_INFO_SAMP_FREQ: 1183 reg = st->channels[chan->address].cfg.odr; 1184 1185 *val = st->info->sinc5_data_rates[reg] / MILLI; 1186 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 1187 1188 return IIO_VAL_INT_PLUS_MICRO; 1189 default: 1190 return -EINVAL; 1191 } 1192 } 1193 1194 static int ad7173_write_raw(struct iio_dev *indio_dev, 1195 struct iio_chan_spec const *chan, 1196 int val, int val2, long info) 1197 { 1198 struct ad7173_state *st = iio_priv(indio_dev); 1199 struct ad7173_channel_config *cfg; 1200 unsigned int freq, i; 1201 int ret = 0; 1202 1203 if (!iio_device_claim_direct(indio_dev)) 1204 return -EBUSY; 1205 1206 switch (info) { 1207 /* 1208 * This attribute sets the sampling frequency for each channel individually. 1209 * There are no issues for raw or buffered reads of an individual channel. 1210 * 1211 * When multiple channels are enabled in buffered mode, the effective 1212 * sampling rate of a channel is lowered in correlation to the number 1213 * of channels enabled and the sampling rate of the other channels. 1214 * 1215 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps 1216 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3 1217 * will take 100ms each. 1218 * 1219 * This will cause the reading of CH1 to be actually done once every 1220 * 200.16ms, an effective rate of 4.99sps. 1221 */ 1222 case IIO_CHAN_INFO_SAMP_FREQ: 1223 freq = val * MILLI + val2 / MILLI; 1224 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 1225 if (freq >= st->info->sinc5_data_rates[i]) 1226 break; 1227 1228 cfg = &st->channels[chan->address].cfg; 1229 cfg->odr = i; 1230 cfg->live = false; 1231 break; 1232 1233 default: 1234 ret = -EINVAL; 1235 break; 1236 } 1237 1238 iio_device_release_direct(indio_dev); 1239 return ret; 1240 } 1241 1242 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 1243 const unsigned long *scan_mask) 1244 { 1245 struct ad7173_state *st = iio_priv(indio_dev); 1246 int i, j, k, ret; 1247 1248 for (i = 0; i < indio_dev->num_channels; i++) { 1249 if (test_bit(i, scan_mask)) 1250 ret = ad7173_set_channel(&st->sd, i); 1251 else 1252 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 1253 if (ret < 0) 1254 return ret; 1255 } 1256 1257 /* 1258 * On some chips, there are more channels that setups, so if there were 1259 * more unique setups requested than the number of available slots, 1260 * ad7173_set_channel() will have written over some of the slots. We 1261 * can detect this by making sure each assigned cfg_slot matches the 1262 * requested configuration. If it doesn't, we know that the slot was 1263 * overwritten by a different channel. 1264 */ 1265 for_each_set_bit(i, scan_mask, indio_dev->num_channels) { 1266 const struct ad7173_channel_config *cfg1, *cfg2; 1267 1268 cfg1 = &st->channels[i].cfg; 1269 1270 for_each_set_bit(j, scan_mask, indio_dev->num_channels) { 1271 cfg2 = &st->channels[j].cfg; 1272 1273 /* 1274 * Only compare configs that are assigned to the same 1275 * SETUP_SEL slot and don't compare channel to itself. 1276 */ 1277 if (i == j || cfg1->cfg_slot != cfg2->cfg_slot) 1278 continue; 1279 1280 /* 1281 * If we find two different configs trying to use the 1282 * same SETUP_SEL slot, then we know that the that we 1283 * have too many unique configurations requested for 1284 * the available slots and at least one was overwritten. 1285 */ 1286 if (!ad7173_is_setup_equal(cfg1, cfg2)) { 1287 /* 1288 * At this point, there isn't a way to tell 1289 * which setups are actually programmed in the 1290 * ADC anymore, so we could read them back to 1291 * see, but it is simpler to just turn off all 1292 * of the live flags so that everything gets 1293 * reprogramed on the next attempt read a sample. 1294 */ 1295 for (k = 0; k < st->num_channels; k++) 1296 st->channels[k].cfg.live = false; 1297 1298 dev_err(&st->sd.spi->dev, 1299 "Too many unique channel configurations requested for scan\n"); 1300 return -EINVAL; 1301 } 1302 } 1303 } 1304 1305 return 0; 1306 } 1307 1308 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1309 unsigned int writeval, unsigned int *readval) 1310 { 1311 struct ad7173_state *st = iio_priv(indio_dev); 1312 u8 reg_size; 1313 1314 if (reg == AD7173_REG_COMMS) 1315 reg_size = 1; 1316 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 1317 reg >= AD7173_REG_OFFSET(0)) 1318 reg_size = 3; 1319 else 1320 reg_size = 2; 1321 1322 if (readval) 1323 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 1324 1325 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 1326 } 1327 1328 static int ad7173_write_event_config(struct iio_dev *indio_dev, 1329 const struct iio_chan_spec *chan, 1330 enum iio_event_type type, 1331 enum iio_event_direction dir, 1332 bool state) 1333 { 1334 struct ad7173_state *st = iio_priv(indio_dev); 1335 struct ad7173_channel *adchan = &st->channels[chan->address]; 1336 1337 switch (type) { 1338 case IIO_EV_TYPE_FAULT: 1339 adchan->openwire_det_en = state; 1340 return 0; 1341 default: 1342 return -EINVAL; 1343 } 1344 } 1345 1346 static int ad7173_read_event_config(struct iio_dev *indio_dev, 1347 const struct iio_chan_spec *chan, 1348 enum iio_event_type type, 1349 enum iio_event_direction dir) 1350 { 1351 struct ad7173_state *st = iio_priv(indio_dev); 1352 struct ad7173_channel *adchan = &st->channels[chan->address]; 1353 1354 switch (type) { 1355 case IIO_EV_TYPE_FAULT: 1356 return adchan->openwire_det_en; 1357 default: 1358 return -EINVAL; 1359 } 1360 } 1361 1362 static const struct iio_event_spec ad4111_events[] = { 1363 { 1364 .type = IIO_EV_TYPE_FAULT, 1365 .dir = IIO_EV_DIR_FAULT_OPENWIRE, 1366 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1367 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 1368 }, 1369 }; 1370 1371 static const struct iio_info ad7173_info = { 1372 .read_raw = &ad7173_read_raw, 1373 .write_raw = &ad7173_write_raw, 1374 .debugfs_reg_access = &ad7173_debug_reg_access, 1375 .validate_trigger = ad_sd_validate_trigger, 1376 .update_scan_mode = ad7173_update_scan_mode, 1377 .write_event_config = ad7173_write_event_config, 1378 .read_event_config = ad7173_read_event_config, 1379 }; 1380 1381 static const struct iio_scan_type ad4113_scan_type = { 1382 .sign = 'u', 1383 .realbits = 16, 1384 .storagebits = 16, 1385 .endianness = IIO_BE, 1386 }; 1387 1388 static const struct iio_chan_spec ad7173_channel_template = { 1389 .type = IIO_VOLTAGE, 1390 .indexed = 1, 1391 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1392 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 1393 .scan_type = { 1394 .sign = 'u', 1395 .realbits = 24, 1396 .storagebits = 32, 1397 .endianness = IIO_BE, 1398 }, 1399 .ext_info = ad7173_calibsys_ext_info, 1400 }; 1401 1402 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 1403 .type = IIO_TEMP, 1404 .channel = AD7173_AIN_TEMP_POS, 1405 .channel2 = AD7173_AIN_TEMP_NEG, 1406 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1407 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1408 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1409 .scan_type = { 1410 .sign = 'u', 1411 .realbits = 24, 1412 .storagebits = 32, 1413 .endianness = IIO_BE, 1414 }, 1415 }; 1416 1417 static void ad7173_disable_regulators(void *data) 1418 { 1419 struct ad7173_state *st = data; 1420 1421 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1422 } 1423 1424 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 1425 unsigned int clk_sel) 1426 { 1427 int ret; 1428 1429 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 1430 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 1431 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 1432 1433 return ret; 1434 } 1435 1436 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 1437 unsigned long parent_rate) 1438 { 1439 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1440 1441 return st->info->clock / HZ_PER_KHZ; 1442 } 1443 1444 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 1445 { 1446 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1447 u32 clk_sel; 1448 1449 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 1450 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 1451 } 1452 1453 static int ad7173_clk_output_prepare(struct clk_hw *hw) 1454 { 1455 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1456 1457 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 1458 } 1459 1460 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 1461 { 1462 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1463 1464 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 1465 } 1466 1467 static const struct clk_ops ad7173_int_clk_ops = { 1468 .recalc_rate = ad7173_clk_recalc_rate, 1469 .is_enabled = ad7173_clk_output_is_enabled, 1470 .prepare = ad7173_clk_output_prepare, 1471 .unprepare = ad7173_clk_output_unprepare, 1472 }; 1473 1474 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 1475 { 1476 struct ad7173_state *st = iio_priv(indio_dev); 1477 struct device *dev = indio_dev->dev.parent; 1478 struct fwnode_handle *fwnode = dev_fwnode(dev); 1479 struct clk_init_data init = {}; 1480 int ret; 1481 1482 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1483 return 0; 1484 1485 init.name = fwnode_get_name(fwnode); 1486 init.ops = &ad7173_int_clk_ops; 1487 1488 st->int_clk_hw.init = &init; 1489 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 1490 if (ret) 1491 return ret; 1492 1493 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1494 &st->int_clk_hw); 1495 } 1496 1497 static int ad4111_validate_current_ain(struct ad7173_state *st, 1498 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL]) 1499 { 1500 struct device *dev = &st->sd.spi->dev; 1501 1502 if (!st->info->has_current_inputs) 1503 return dev_err_probe(dev, -EINVAL, 1504 "Model %s does not support current channels\n", 1505 st->info->name); 1506 1507 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config)) 1508 return dev_err_probe(dev, -EINVAL, 1509 "For current channels single-channel must be <[0-3]>\n"); 1510 1511 return 0; 1512 } 1513 1514 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st, 1515 unsigned int ain0, unsigned int ain1) 1516 { 1517 struct device *dev = &st->sd.spi->dev; 1518 bool special_input0, special_input1; 1519 1520 /* (AVDD1-AVSS)/5 power supply monitoring */ 1521 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG && 1522 st->info->has_pow_supply_monitoring) 1523 return 0; 1524 1525 special_input0 = AD7173_IS_REF_INPUT(ain0) || 1526 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1527 special_input1 = AD7173_IS_REF_INPUT(ain1) || 1528 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1529 1530 if ((ain0 >= st->info->num_voltage_in && !special_input0) || 1531 (ain1 >= st->info->num_voltage_in && !special_input1)) { 1532 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT) 1533 return dev_err_probe(dev, -EINVAL, 1534 "VINCOM not supported for %s\n", st->info->name); 1535 1536 return dev_err_probe(dev, -EINVAL, 1537 "Input pin number out of range for pair (%d %d).\n", 1538 ain0, ain1); 1539 } 1540 1541 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) || 1542 AD4111_IS_VINCOM_MISMATCH(ain1, ain0)) 1543 return dev_err_probe(dev, -EINVAL, 1544 "VINCOM must be paired with inputs having divider.\n"); 1545 1546 if (!special_input0 && !special_input1 && 1547 ((ain0 >= st->info->num_voltage_in_div) != 1548 (ain1 >= st->info->num_voltage_in_div))) 1549 return dev_err_probe(dev, -EINVAL, 1550 "Both inputs must either have a voltage divider or not have: (%d %d).\n", 1551 ain0, ain1); 1552 1553 return 0; 1554 } 1555 1556 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel) 1557 { 1558 struct device *dev = &st->sd.spi->dev; 1559 int ret; 1560 1561 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref) 1562 return dev_err_probe(dev, -EINVAL, 1563 "Internal reference is not available on current model.\n"); 1564 1565 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 1566 return dev_err_probe(dev, -EINVAL, 1567 "External reference 2 is not available on current model.\n"); 1568 1569 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 1570 if (ret < 0) 1571 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1572 ref_sel); 1573 1574 return 0; 1575 } 1576 1577 static int ad7173_validate_openwire_ain_inputs(struct ad7173_state *st, 1578 bool differential, 1579 unsigned int ain0, 1580 unsigned int ain1) 1581 { 1582 /* 1583 * If the channel is configured as differential, 1584 * the ad4111 requires specific ains to be used together 1585 */ 1586 if (differential) 1587 return (ain0 % 2) ? (ain0 - 1) == ain1 : (ain0 + 1) == ain1; 1588 1589 return ain1 == AD4111_VINCOM_INPUT; 1590 } 1591 1592 static unsigned int ad7173_calc_openwire_thrsh_raw(struct ad7173_state *st, 1593 struct iio_chan_spec *chan, 1594 struct ad7173_channel *chan_st_priv, 1595 unsigned int thrsh_mv) { 1596 unsigned int thrsh_raw; 1597 1598 thrsh_raw = 1599 BIT(chan->scan_type.realbits - !!(chan_st_priv->cfg.bipolar)) 1600 * thrsh_mv 1601 / ad7173_get_ref_voltage_milli(st, chan_st_priv->cfg.ref_sel); 1602 if (chan->channel < st->info->num_voltage_in_div) 1603 thrsh_raw /= AD4111_DIVIDER_RATIO; 1604 1605 return thrsh_raw; 1606 } 1607 1608 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 1609 { 1610 struct ad7173_channel *chans_st_arr, *chan_st_priv; 1611 struct ad7173_state *st = iio_priv(indio_dev); 1612 struct device *dev = indio_dev->dev.parent; 1613 struct iio_chan_spec *chan_arr, *chan; 1614 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0; 1615 int ref_sel, ret, num_channels; 1616 1617 num_channels = device_get_child_node_count(dev); 1618 1619 if (st->info->has_temp) 1620 num_channels++; 1621 1622 if (num_channels == 0) 1623 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1624 1625 if (num_channels > st->info->num_channels) 1626 return dev_err_probe(dev, -EINVAL, 1627 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n", 1628 st->info->num_channels); 1629 1630 indio_dev->num_channels = num_channels; 1631 st->num_channels = num_channels; 1632 1633 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 1634 st->num_channels, GFP_KERNEL); 1635 if (!chan_arr) 1636 return -ENOMEM; 1637 1638 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 1639 GFP_KERNEL); 1640 if (!chans_st_arr) 1641 return -ENOMEM; 1642 1643 indio_dev->channels = chan_arr; 1644 st->channels = chans_st_arr; 1645 1646 if (st->info->has_temp) { 1647 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 1648 chan_st_priv = &chans_st_arr[chan_index]; 1649 chan_st_priv->ain = 1650 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 1651 chan_arr[chan_index].channel2); 1652 chan_st_priv->cfg.bipolar = false; 1653 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1654 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1655 chan_st_priv->cfg.odr = st->info->odr_start_value; 1656 chan_st_priv->cfg.openwire_comp_chan = -1; 1657 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1658 if (st->info->data_reg_only_16bit) 1659 chan_arr[chan_index].scan_type = ad4113_scan_type; 1660 1661 chan_index++; 1662 } 1663 1664 device_for_each_child_node_scoped(dev, child) { 1665 bool is_current_chan = false; 1666 1667 chan = &chan_arr[chan_index]; 1668 *chan = ad7173_channel_template; 1669 chan_st_priv = &chans_st_arr[chan_index]; 1670 ret = fwnode_property_read_u32_array(child, "diff-channels", 1671 ain, ARRAY_SIZE(ain)); 1672 if (ret) { 1673 ret = fwnode_property_read_u32(child, "single-channel", 1674 ain); 1675 if (ret) 1676 return dev_err_probe(dev, ret, 1677 "Channel must define one of diff-channels or single-channel.\n"); 1678 1679 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel"); 1680 } else { 1681 chan->differential = true; 1682 } 1683 1684 if (is_current_chan) { 1685 ret = ad4111_validate_current_ain(st, ain); 1686 if (ret) 1687 return ret; 1688 } else { 1689 if (!chan->differential) { 1690 ret = fwnode_property_read_u32(child, 1691 "common-mode-channel", ain + 1); 1692 if (ret) 1693 return dev_err_probe(dev, ret, 1694 "common-mode-channel must be defined for single-ended channels.\n"); 1695 } 1696 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]); 1697 if (ret) 1698 return ret; 1699 } 1700 1701 ret = fwnode_property_match_property_string(child, 1702 "adi,reference-select", 1703 ad7173_ref_sel_str, 1704 ARRAY_SIZE(ad7173_ref_sel_str)); 1705 if (ret < 0) 1706 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1707 else 1708 ref_sel = ret; 1709 1710 ret = ad7173_validate_reference(st, ref_sel); 1711 if (ret) 1712 return ret; 1713 1714 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 1715 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1716 chan_st_priv->cfg.ref_sel = ref_sel; 1717 1718 chan->address = chan_index; 1719 chan->scan_index = chan_index; 1720 chan->channel = ain[0]; 1721 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1722 chan_st_priv->cfg.odr = st->info->odr_start_value; 1723 chan_st_priv->cfg.openwire_comp_chan = -1; 1724 1725 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 1726 if (chan_st_priv->cfg.bipolar) 1727 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 1728 1729 if (is_current_chan) { 1730 chan->type = IIO_CURRENT; 1731 chan->differential = false; 1732 chan->channel2 = 0; 1733 chan_st_priv->ain = ad4111_current_channel_config[ain[0]]; 1734 } else { 1735 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1736 chan->channel2 = ain[1]; 1737 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 1738 if (st->info->has_openwire_det && 1739 ad7173_validate_openwire_ain_inputs(st, chan->differential, ain[0], ain[1])) { 1740 chan->event_spec = ad4111_events; 1741 chan->num_event_specs = ARRAY_SIZE(ad4111_events); 1742 chan_st_priv->cfg.openwire_thrsh_raw = 1743 ad7173_calc_openwire_thrsh_raw(st, chan, chan_st_priv, 1744 AD4111_OW_DET_THRSH_MV); 1745 } 1746 } 1747 1748 if (st->info->data_reg_only_16bit) 1749 chan_arr[chan_index].scan_type = ad4113_scan_type; 1750 1751 chan_index++; 1752 } 1753 return 0; 1754 } 1755 1756 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1757 { 1758 struct ad7173_state *st = iio_priv(indio_dev); 1759 struct device *dev = indio_dev->dev.parent; 1760 int ret; 1761 1762 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1763 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1764 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1765 1766 /* 1767 * If a regulator is not available, it will be set to a dummy regulator. 1768 * Each channel reference is checked with regulator_get_voltage() before 1769 * setting attributes so if any channel uses a dummy supply the driver 1770 * probe will fail. 1771 */ 1772 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1773 st->regulators); 1774 if (ret) 1775 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1776 1777 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1778 if (ret) 1779 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1780 1781 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1782 if (ret) 1783 return dev_err_probe(dev, ret, 1784 "Failed to add regulators disable action\n"); 1785 1786 ret = device_property_match_property_string(dev, "clock-names", 1787 ad7173_clk_sel, 1788 ARRAY_SIZE(ad7173_clk_sel)); 1789 if (ret < 0) { 1790 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1791 AD7173_ADC_MODE_CLOCKSEL_INT); 1792 ad7173_register_clk_provider(indio_dev); 1793 } else { 1794 struct clk *clk; 1795 1796 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1797 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1798 clk = devm_clk_get_enabled(dev, ad7173_clk_sel[ret]); 1799 if (IS_ERR(clk)) 1800 return dev_err_probe(dev, PTR_ERR(clk), 1801 "Failed to get external clock\n"); 1802 } 1803 1804 return ad7173_fw_parse_channel_config(indio_dev); 1805 } 1806 1807 static int ad7173_probe(struct spi_device *spi) 1808 { 1809 struct device *dev = &spi->dev; 1810 struct ad7173_state *st; 1811 struct iio_dev *indio_dev; 1812 int ret; 1813 1814 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1815 if (!indio_dev) 1816 return -ENOMEM; 1817 1818 st = iio_priv(indio_dev); 1819 st->info = spi_get_device_match_data(spi); 1820 if (!st->info) 1821 return -ENODEV; 1822 1823 ida_init(&st->cfg_slots_status); 1824 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1825 if (ret) 1826 return ret; 1827 1828 indio_dev->name = st->info->name; 1829 indio_dev->modes = INDIO_DIRECT_MODE; 1830 indio_dev->info = &ad7173_info; 1831 1832 spi->mode = SPI_MODE_3; 1833 ret = spi_setup(spi); 1834 if (ret) 1835 return ret; 1836 1837 ret = ad_sd_init(&st->sd, indio_dev, spi, st->info->sd_info); 1838 if (ret) 1839 return ret; 1840 1841 ret = ad7173_fw_parse_device_config(indio_dev); 1842 if (ret) 1843 return ret; 1844 1845 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1846 if (ret) 1847 return ret; 1848 1849 ret = ad7173_setup(indio_dev); 1850 if (ret) 1851 return ret; 1852 1853 ret = devm_iio_device_register(dev, indio_dev); 1854 if (ret) 1855 return ret; 1856 1857 return ad7173_gpio_init(st); 1858 } 1859 1860 static const struct of_device_id ad7173_of_match[] = { 1861 { .compatible = "adi,ad4111", .data = &ad4111_device_info }, 1862 { .compatible = "adi,ad4112", .data = &ad4112_device_info }, 1863 { .compatible = "adi,ad4113", .data = &ad4113_device_info }, 1864 { .compatible = "adi,ad4114", .data = &ad4114_device_info }, 1865 { .compatible = "adi,ad4115", .data = &ad4115_device_info }, 1866 { .compatible = "adi,ad4116", .data = &ad4116_device_info }, 1867 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info }, 1868 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info }, 1869 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info }, 1870 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info }, 1871 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info }, 1872 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info }, 1873 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info }, 1874 { } 1875 }; 1876 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1877 1878 static const struct spi_device_id ad7173_id_table[] = { 1879 { "ad4111", (kernel_ulong_t)&ad4111_device_info }, 1880 { "ad4112", (kernel_ulong_t)&ad4112_device_info }, 1881 { "ad4113", (kernel_ulong_t)&ad4113_device_info }, 1882 { "ad4114", (kernel_ulong_t)&ad4114_device_info }, 1883 { "ad4115", (kernel_ulong_t)&ad4115_device_info }, 1884 { "ad4116", (kernel_ulong_t)&ad4116_device_info }, 1885 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info }, 1886 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info }, 1887 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info }, 1888 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info }, 1889 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info }, 1890 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info }, 1891 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info }, 1892 { } 1893 }; 1894 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1895 1896 static struct spi_driver ad7173_driver = { 1897 .driver = { 1898 .name = "ad7173", 1899 .of_match_table = ad7173_of_match, 1900 }, 1901 .probe = ad7173_probe, 1902 .id_table = ad7173_id_table, 1903 }; 1904 module_spi_driver(ad7173_driver); 1905 1906 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1907 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1908 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1909 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver"); 1910 MODULE_LICENSE("GPL"); 1911