1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 7 * AD7175-8/AD7176-2/AD7177-2 8 * 9 * Copyright (C) 2015, 2024 Analog Devices, Inc. 10 */ 11 12 #include <linux/array_size.h> 13 #include <linux/bitfield.h> 14 #include <linux/bitmap.h> 15 #include <linux/container_of.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/err.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/gpio/regmap.h> 23 #include <linux/idr.h> 24 #include <linux/interrupt.h> 25 #include <linux/math64.h> 26 #include <linux/module.h> 27 #include <linux/mod_devicetable.h> 28 #include <linux/property.h> 29 #include <linux/regmap.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 #include <linux/spi/spi.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 36 #include <linux/iio/buffer.h> 37 #include <linux/iio/iio.h> 38 #include <linux/iio/trigger_consumer.h> 39 #include <linux/iio/triggered_buffer.h> 40 41 #include <linux/iio/adc/ad_sigma_delta.h> 42 43 #define AD7173_REG_COMMS 0x00 44 #define AD7173_REG_ADC_MODE 0x01 45 #define AD7173_REG_INTERFACE_MODE 0x02 46 #define AD7173_REG_CRC 0x03 47 #define AD7173_REG_DATA 0x04 48 #define AD7173_REG_GPIO 0x06 49 #define AD7173_REG_ID 0x07 50 #define AD7173_REG_CH(x) (0x10 + (x)) 51 #define AD7173_REG_SETUP(x) (0x20 + (x)) 52 #define AD7173_REG_FILTER(x) (0x28 + (x)) 53 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 54 #define AD7173_REG_GAIN(x) (0x38 + (x)) 55 56 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 57 58 #define AD7173_CH_ENABLE BIT(15) 59 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 60 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 61 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 62 63 #define AD7173_CH_ADDRESS(pos, neg) \ 64 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 65 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 66 #define AD7173_AIN_TEMP_POS 17 67 #define AD7173_AIN_TEMP_NEG 18 68 69 #define AD7172_2_ID 0x00d0 70 #define AD7175_ID 0x0cd0 71 #define AD7176_ID 0x0c90 72 #define AD7175_2_ID 0x0cd0 73 #define AD7172_4_ID 0x2050 74 #define AD7173_ID 0x30d0 75 #define AD7175_8_ID 0x3cd0 76 #define AD7177_ID 0x4fd0 77 #define AD7173_ID_MASK GENMASK(15, 4) 78 79 #define AD7173_ADC_MODE_REF_EN BIT(15) 80 #define AD7173_ADC_MODE_SING_CYC BIT(13) 81 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 82 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 83 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 84 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 85 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 86 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 87 88 #define AD7173_GPIO_PDSW BIT(14) 89 #define AD7173_GPIO_OP_EN2_3 BIT(13) 90 #define AD7173_GPIO_MUX_IO BIT(12) 91 #define AD7173_GPIO_SYNC_EN BIT(11) 92 #define AD7173_GPIO_ERR_EN BIT(10) 93 #define AD7173_GPIO_ERR_DAT BIT(9) 94 #define AD7173_GPIO_GP_DATA3 BIT(7) 95 #define AD7173_GPIO_GP_DATA2 BIT(6) 96 #define AD7173_GPIO_IP_EN1 BIT(5) 97 #define AD7173_GPIO_IP_EN0 BIT(4) 98 #define AD7173_GPIO_OP_EN1 BIT(3) 99 #define AD7173_GPIO_OP_EN0 BIT(2) 100 #define AD7173_GPIO_GP_DATA1 BIT(1) 101 #define AD7173_GPIO_GP_DATA0 BIT(0) 102 103 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 104 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 105 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 106 107 #define AD7173_INTERFACE_DATA_STAT BIT(6) 108 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 109 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 110 111 #define AD7173_SETUP_BIPOLAR BIT(12) 112 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 113 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 114 115 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 116 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 117 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 118 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 119 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 120 #define AD7173_VOLTAGE_INT_REF_uV 2500000 121 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 122 #define AD7177_ODR_START_VALUE 0x07 123 124 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 125 #define AD7173_MAX_CONFIGS 8 126 127 enum ad7173_ids { 128 ID_AD7172_2, 129 ID_AD7172_4, 130 ID_AD7173_8, 131 ID_AD7175_2, 132 ID_AD7175_8, 133 ID_AD7176_2, 134 ID_AD7177_2, 135 }; 136 137 struct ad7173_device_info { 138 const unsigned int *sinc5_data_rates; 139 unsigned int num_sinc5_data_rates; 140 unsigned int odr_start_value; 141 unsigned int num_channels; 142 unsigned int num_configs; 143 unsigned int num_inputs; 144 unsigned int clock; 145 unsigned int id; 146 char *name; 147 bool has_temp; 148 bool has_input_buf; 149 bool has_int_ref; 150 bool has_ref2; 151 u8 num_gpios; 152 }; 153 154 struct ad7173_channel_config { 155 u8 cfg_slot; 156 bool live; 157 158 /* Following fields are used to compare equality. */ 159 struct_group(config_props, 160 bool bipolar; 161 bool input_buf; 162 u8 odr; 163 u8 ref_sel; 164 ); 165 }; 166 167 struct ad7173_channel { 168 unsigned int chan_reg; 169 unsigned int ain; 170 struct ad7173_channel_config cfg; 171 }; 172 173 struct ad7173_state { 174 struct ad_sigma_delta sd; 175 const struct ad7173_device_info *info; 176 struct ad7173_channel *channels; 177 struct regulator_bulk_data regulators[3]; 178 unsigned int adc_mode; 179 unsigned int interface_mode; 180 unsigned int num_channels; 181 struct ida cfg_slots_status; 182 unsigned long long config_usage_counter; 183 unsigned long long *config_cnts; 184 struct clk *ext_clk; 185 struct clk_hw int_clk_hw; 186 #if IS_ENABLED(CONFIG_GPIOLIB) 187 struct regmap *reg_gpiocon_regmap; 188 struct gpio_regmap *gpio_regmap; 189 #endif 190 }; 191 192 static const unsigned int ad7173_sinc5_data_rates[] = { 193 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 194 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 195 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 196 }; 197 198 static const unsigned int ad7175_sinc5_data_rates[] = { 199 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 200 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 201 5000000, 2500000, 1000000, 500000, /* 8-11 */ 202 397500, 200000, 100000, 59920, /* 12-15 */ 203 49960, 20000, 16666, 10000, /* 16-19 */ 204 5000, /* 20 */ 205 }; 206 207 static const struct ad7173_device_info ad7173_device_info[] = { 208 [ID_AD7172_2] = { 209 .name = "ad7172-2", 210 .id = AD7172_2_ID, 211 .num_inputs = 5, 212 .num_channels = 4, 213 .num_configs = 4, 214 .num_gpios = 2, 215 .has_temp = true, 216 .has_input_buf = true, 217 .has_int_ref = true, 218 .clock = 2 * HZ_PER_MHZ, 219 .sinc5_data_rates = ad7173_sinc5_data_rates, 220 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 221 }, 222 [ID_AD7172_4] = { 223 .name = "ad7172-4", 224 .id = AD7172_4_ID, 225 .num_inputs = 9, 226 .num_channels = 8, 227 .num_configs = 8, 228 .num_gpios = 4, 229 .has_temp = false, 230 .has_input_buf = true, 231 .has_ref2 = true, 232 .clock = 2 * HZ_PER_MHZ, 233 .sinc5_data_rates = ad7173_sinc5_data_rates, 234 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 235 }, 236 [ID_AD7173_8] = { 237 .name = "ad7173-8", 238 .id = AD7173_ID, 239 .num_inputs = 17, 240 .num_channels = 16, 241 .num_configs = 8, 242 .num_gpios = 4, 243 .has_temp = true, 244 .has_input_buf = true, 245 .has_int_ref = true, 246 .has_ref2 = true, 247 .clock = 2 * HZ_PER_MHZ, 248 .sinc5_data_rates = ad7173_sinc5_data_rates, 249 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 250 }, 251 [ID_AD7175_2] = { 252 .name = "ad7175-2", 253 .id = AD7175_2_ID, 254 .num_inputs = 5, 255 .num_channels = 4, 256 .num_configs = 4, 257 .num_gpios = 2, 258 .has_temp = true, 259 .has_input_buf = true, 260 .has_int_ref = true, 261 .clock = 16 * HZ_PER_MHZ, 262 .sinc5_data_rates = ad7175_sinc5_data_rates, 263 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 264 }, 265 [ID_AD7175_8] = { 266 .name = "ad7175-8", 267 .id = AD7175_8_ID, 268 .num_inputs = 17, 269 .num_channels = 16, 270 .num_configs = 8, 271 .num_gpios = 4, 272 .has_temp = true, 273 .has_input_buf = true, 274 .has_int_ref = true, 275 .has_ref2 = true, 276 .clock = 16 * HZ_PER_MHZ, 277 .sinc5_data_rates = ad7175_sinc5_data_rates, 278 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 279 }, 280 [ID_AD7176_2] = { 281 .name = "ad7176-2", 282 .id = AD7176_ID, 283 .num_inputs = 5, 284 .num_channels = 4, 285 .num_configs = 4, 286 .num_gpios = 2, 287 .has_temp = false, 288 .has_input_buf = false, 289 .has_int_ref = true, 290 .clock = 16 * HZ_PER_MHZ, 291 .sinc5_data_rates = ad7175_sinc5_data_rates, 292 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 293 }, 294 [ID_AD7177_2] = { 295 .name = "ad7177-2", 296 .id = AD7177_ID, 297 .num_inputs = 5, 298 .num_channels = 4, 299 .num_configs = 4, 300 .num_gpios = 2, 301 .has_temp = true, 302 .has_input_buf = true, 303 .has_int_ref = true, 304 .clock = 16 * HZ_PER_MHZ, 305 .odr_start_value = AD7177_ODR_START_VALUE, 306 .sinc5_data_rates = ad7175_sinc5_data_rates, 307 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 308 }, 309 }; 310 311 static const char *const ad7173_ref_sel_str[] = { 312 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 313 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 314 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 315 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 316 }; 317 318 static const char *const ad7173_clk_sel[] = { 319 "ext-clk", "xtal" 320 }; 321 322 #if IS_ENABLED(CONFIG_GPIOLIB) 323 324 static const struct regmap_range ad7173_range_gpio[] = { 325 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 326 }; 327 328 static const struct regmap_access_table ad7173_access_table = { 329 .yes_ranges = ad7173_range_gpio, 330 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 331 }; 332 333 static const struct regmap_config ad7173_regmap_config = { 334 .reg_bits = 8, 335 .val_bits = 16, 336 .rd_table = &ad7173_access_table, 337 .wr_table = &ad7173_access_table, 338 .read_flag_mask = BIT(6), 339 }; 340 341 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 342 unsigned int offset, unsigned int *reg, 343 unsigned int *mask) 344 { 345 *mask = AD7173_GPO_DATA(offset); 346 *reg = base; 347 return 0; 348 } 349 350 static void ad7173_gpio_disable(void *data) 351 { 352 struct ad7173_state *st = data; 353 unsigned int mask; 354 355 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 356 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 357 } 358 359 static int ad7173_gpio_init(struct ad7173_state *st) 360 { 361 struct gpio_regmap_config gpio_regmap = {}; 362 struct device *dev = &st->sd.spi->dev; 363 unsigned int mask; 364 int ret; 365 366 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 367 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 368 if (ret) 369 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 370 371 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 372 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 373 374 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 375 if (ret) 376 return ret; 377 378 gpio_regmap.parent = dev; 379 gpio_regmap.regmap = st->reg_gpiocon_regmap; 380 gpio_regmap.ngpio = st->info->num_gpios; 381 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 382 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 383 384 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 385 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 386 if (ret) 387 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 388 389 return 0; 390 } 391 #else 392 static int ad7173_gpio_init(struct ad7173_state *st) 393 { 394 return 0; 395 } 396 #endif /* CONFIG_GPIOLIB */ 397 398 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 399 { 400 return container_of(sd, struct ad7173_state, sd); 401 } 402 403 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 404 { 405 return container_of(hw, struct ad7173_state, int_clk_hw); 406 } 407 408 static void ad7173_ida_destroy(void *data) 409 { 410 struct ad7173_state *st = data; 411 412 ida_destroy(&st->cfg_slots_status); 413 } 414 415 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 416 { 417 memset64(st->config_cnts, 0, st->info->num_configs); 418 st->config_usage_counter = 0; 419 } 420 421 static struct ad7173_channel_config * 422 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 423 { 424 struct ad7173_channel_config *cfg_aux; 425 ptrdiff_t cmp_size; 426 int i; 427 428 cmp_size = sizeof_field(struct ad7173_channel_config, config_props); 429 for (i = 0; i < st->num_channels; i++) { 430 cfg_aux = &st->channels[i].cfg; 431 432 if (cfg_aux->live && 433 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size)) 434 return cfg_aux; 435 } 436 return NULL; 437 } 438 439 /* Could be replaced with a generic LRU implementation */ 440 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 441 { 442 int i, lru_position = 0; 443 444 for (i = 1; i < st->info->num_configs; i++) 445 if (st->config_cnts[i] < st->config_cnts[lru_position]) 446 lru_position = i; 447 448 for (i = 0; i < st->num_channels; i++) 449 if (st->channels[i].cfg.cfg_slot == lru_position) 450 st->channels[i].cfg.live = false; 451 452 ida_free(&st->cfg_slots_status, lru_position); 453 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 454 } 455 456 /* Could be replaced with a generic LRU implementation */ 457 static int ad7173_load_config(struct ad7173_state *st, 458 struct ad7173_channel_config *cfg) 459 { 460 unsigned int config; 461 int free_cfg_slot, ret; 462 463 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 464 st->info->num_configs - 1, GFP_KERNEL); 465 if (free_cfg_slot < 0) 466 free_cfg_slot = ad7173_free_config_slot_lru(st); 467 468 cfg->cfg_slot = free_cfg_slot; 469 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 470 471 if (cfg->bipolar) 472 config |= AD7173_SETUP_BIPOLAR; 473 474 if (cfg->input_buf) 475 config |= AD7173_SETUP_AIN_BUF_MASK; 476 477 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 478 if (ret) 479 return ret; 480 481 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 482 AD7173_FILTER_ODR0_MASK & cfg->odr); 483 } 484 485 static int ad7173_config_channel(struct ad7173_state *st, int addr) 486 { 487 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 488 struct ad7173_channel_config *live_cfg; 489 int ret; 490 491 if (!cfg->live) { 492 live_cfg = ad7173_find_live_config(st, cfg); 493 if (live_cfg) { 494 cfg->cfg_slot = live_cfg->cfg_slot; 495 } else { 496 ret = ad7173_load_config(st, cfg); 497 if (ret) 498 return ret; 499 cfg->live = true; 500 } 501 } 502 503 if (st->config_usage_counter == U64_MAX) 504 ad7173_reset_usage_cnts(st); 505 506 st->config_usage_counter++; 507 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 508 509 return 0; 510 } 511 512 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 513 { 514 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 515 unsigned int val; 516 int ret; 517 518 ret = ad7173_config_channel(st, channel); 519 if (ret) 520 return ret; 521 522 val = AD7173_CH_ENABLE | 523 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 524 st->channels[channel].ain; 525 526 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 527 } 528 529 static int ad7173_set_mode(struct ad_sigma_delta *sd, 530 enum ad_sigma_delta_mode mode) 531 { 532 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 533 534 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 535 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 536 537 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 538 } 539 540 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 541 { 542 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 543 unsigned int interface_mode = st->interface_mode; 544 int ret; 545 546 interface_mode &= ~AD7173_INTERFACE_DATA_STAT; 547 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 548 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 549 if (ret) 550 return ret; 551 552 st->interface_mode = interface_mode; 553 554 return 0; 555 } 556 557 static int ad7173_disable_all(struct ad_sigma_delta *sd) 558 { 559 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 560 int ret; 561 int i; 562 563 for (i = 0; i < st->num_channels; i++) { 564 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 565 if (ret < 0) 566 return ret; 567 } 568 569 return 0; 570 } 571 572 static struct ad_sigma_delta_info ad7173_sigma_delta_info = { 573 .set_channel = ad7173_set_channel, 574 .append_status = ad7173_append_status, 575 .disable_all = ad7173_disable_all, 576 .set_mode = ad7173_set_mode, 577 .has_registers = true, 578 .addr_shift = 0, 579 .read_mask = BIT(6), 580 .status_ch_mask = GENMASK(3, 0), 581 .data_reg = AD7173_REG_DATA, 582 }; 583 584 static int ad7173_setup(struct iio_dev *indio_dev) 585 { 586 struct ad7173_state *st = iio_priv(indio_dev); 587 struct device *dev = &st->sd.spi->dev; 588 u8 buf[AD7173_RESET_LENGTH]; 589 unsigned int id; 590 int ret; 591 592 /* reset the serial interface */ 593 memset(buf, 0xff, AD7173_RESET_LENGTH); 594 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 595 if (ret < 0) 596 return ret; 597 598 /* datasheet recommends a delay of at least 500us after reset */ 599 fsleep(500); 600 601 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 602 if (ret) 603 return ret; 604 605 id &= AD7173_ID_MASK; 606 if (id != st->info->id) 607 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 608 id, st->info->id); 609 610 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 611 st->interface_mode = 0x0; 612 613 st->config_usage_counter = 0; 614 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 615 sizeof(*st->config_cnts), GFP_KERNEL); 616 if (!st->config_cnts) 617 return -ENOMEM; 618 619 /* All channels are enabled by default after a reset */ 620 return ad7173_disable_all(&st->sd); 621 } 622 623 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 624 u8 reference_select) 625 { 626 int vref; 627 628 switch (reference_select) { 629 case AD7173_SETUP_REF_SEL_EXT_REF: 630 vref = regulator_get_voltage(st->regulators[0].consumer); 631 break; 632 633 case AD7173_SETUP_REF_SEL_EXT_REF2: 634 vref = regulator_get_voltage(st->regulators[1].consumer); 635 break; 636 637 case AD7173_SETUP_REF_SEL_INT_REF: 638 vref = AD7173_VOLTAGE_INT_REF_uV; 639 break; 640 641 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 642 vref = regulator_get_voltage(st->regulators[2].consumer); 643 break; 644 645 default: 646 return -EINVAL; 647 } 648 649 if (vref < 0) 650 return vref; 651 652 return vref / (MICRO / MILLI); 653 } 654 655 static int ad7173_read_raw(struct iio_dev *indio_dev, 656 struct iio_chan_spec const *chan, 657 int *val, int *val2, long info) 658 { 659 struct ad7173_state *st = iio_priv(indio_dev); 660 struct ad7173_channel *ch = &st->channels[chan->address]; 661 unsigned int reg; 662 u64 temp; 663 int ret; 664 665 switch (info) { 666 case IIO_CHAN_INFO_RAW: 667 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 668 if (ret < 0) 669 return ret; 670 671 /* disable channel after single conversion */ 672 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(chan->address), 2, 0); 673 if (ret < 0) 674 return ret; 675 676 return IIO_VAL_INT; 677 case IIO_CHAN_INFO_SCALE: 678 if (chan->type == IIO_TEMP) { 679 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 680 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 681 *val = temp; 682 *val2 = chan->scan_type.realbits; 683 } else { 684 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 685 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 686 } 687 return IIO_VAL_FRACTIONAL_LOG2; 688 case IIO_CHAN_INFO_OFFSET: 689 if (chan->type == IIO_TEMP) { 690 /* 0 Kelvin -> raw sample */ 691 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 692 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 693 temp <<= chan->scan_type.realbits; 694 temp = DIV_U64_ROUND_CLOSEST(temp, 695 AD7173_VOLTAGE_INT_REF_uV * 696 MILLI); 697 *val = -temp; 698 } else { 699 *val = -BIT(chan->scan_type.realbits - 1); 700 } 701 return IIO_VAL_INT; 702 case IIO_CHAN_INFO_SAMP_FREQ: 703 reg = st->channels[chan->address].cfg.odr; 704 705 *val = st->info->sinc5_data_rates[reg] / MILLI; 706 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 707 708 return IIO_VAL_INT_PLUS_MICRO; 709 default: 710 return -EINVAL; 711 } 712 } 713 714 static int ad7173_write_raw(struct iio_dev *indio_dev, 715 struct iio_chan_spec const *chan, 716 int val, int val2, long info) 717 { 718 struct ad7173_state *st = iio_priv(indio_dev); 719 struct ad7173_channel_config *cfg; 720 unsigned int freq, i; 721 int ret; 722 723 ret = iio_device_claim_direct_mode(indio_dev); 724 if (ret) 725 return ret; 726 727 switch (info) { 728 case IIO_CHAN_INFO_SAMP_FREQ: 729 freq = val * MILLI + val2 / MILLI; 730 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 731 if (freq >= st->info->sinc5_data_rates[i]) 732 break; 733 734 cfg = &st->channels[chan->address].cfg; 735 cfg->odr = i; 736 cfg->live = false; 737 break; 738 739 default: 740 ret = -EINVAL; 741 break; 742 } 743 744 iio_device_release_direct_mode(indio_dev); 745 return ret; 746 } 747 748 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 749 const unsigned long *scan_mask) 750 { 751 struct ad7173_state *st = iio_priv(indio_dev); 752 int i, ret; 753 754 for (i = 0; i < indio_dev->num_channels; i++) { 755 if (test_bit(i, scan_mask)) 756 ret = ad7173_set_channel(&st->sd, i); 757 else 758 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 759 if (ret < 0) 760 return ret; 761 } 762 763 return 0; 764 } 765 766 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 767 unsigned int writeval, unsigned int *readval) 768 { 769 struct ad7173_state *st = iio_priv(indio_dev); 770 u8 reg_size; 771 772 if (reg == AD7173_REG_COMMS) 773 reg_size = 1; 774 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 775 reg >= AD7173_REG_OFFSET(0)) 776 reg_size = 3; 777 else 778 reg_size = 2; 779 780 if (readval) 781 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 782 783 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 784 } 785 786 static const struct iio_info ad7173_info = { 787 .read_raw = &ad7173_read_raw, 788 .write_raw = &ad7173_write_raw, 789 .debugfs_reg_access = &ad7173_debug_reg_access, 790 .validate_trigger = ad_sd_validate_trigger, 791 .update_scan_mode = ad7173_update_scan_mode, 792 }; 793 794 static const struct iio_chan_spec ad7173_channel_template = { 795 .type = IIO_VOLTAGE, 796 .indexed = 1, 797 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 798 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 799 .scan_type = { 800 .sign = 'u', 801 .realbits = 24, 802 .storagebits = 32, 803 .endianness = IIO_BE, 804 }, 805 }; 806 807 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 808 .type = IIO_TEMP, 809 .channel = AD7173_AIN_TEMP_POS, 810 .channel2 = AD7173_AIN_TEMP_NEG, 811 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 812 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 813 BIT(IIO_CHAN_INFO_SAMP_FREQ), 814 .scan_type = { 815 .sign = 'u', 816 .realbits = 24, 817 .storagebits = 32, 818 .endianness = IIO_BE, 819 }, 820 }; 821 822 static void ad7173_disable_regulators(void *data) 823 { 824 struct ad7173_state *st = data; 825 826 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 827 } 828 829 static void ad7173_clk_disable_unprepare(void *clk) 830 { 831 clk_disable_unprepare(clk); 832 } 833 834 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 835 unsigned int clk_sel) 836 { 837 int ret; 838 839 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 840 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 841 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 842 843 return ret; 844 } 845 846 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 847 unsigned long parent_rate) 848 { 849 struct ad7173_state *st = clk_hw_to_ad7173(hw); 850 851 return st->info->clock / HZ_PER_KHZ; 852 } 853 854 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 855 { 856 struct ad7173_state *st = clk_hw_to_ad7173(hw); 857 u32 clk_sel; 858 859 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 860 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 861 } 862 863 static int ad7173_clk_output_prepare(struct clk_hw *hw) 864 { 865 struct ad7173_state *st = clk_hw_to_ad7173(hw); 866 867 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 868 } 869 870 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 871 { 872 struct ad7173_state *st = clk_hw_to_ad7173(hw); 873 874 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 875 } 876 877 static const struct clk_ops ad7173_int_clk_ops = { 878 .recalc_rate = ad7173_clk_recalc_rate, 879 .is_enabled = ad7173_clk_output_is_enabled, 880 .prepare = ad7173_clk_output_prepare, 881 .unprepare = ad7173_clk_output_unprepare, 882 }; 883 884 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 885 { 886 struct ad7173_state *st = iio_priv(indio_dev); 887 struct device *dev = indio_dev->dev.parent; 888 struct fwnode_handle *fwnode = dev_fwnode(dev); 889 struct clk_init_data init = {}; 890 int ret; 891 892 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 893 return 0; 894 895 init.name = fwnode_get_name(fwnode); 896 init.ops = &ad7173_int_clk_ops; 897 898 st->int_clk_hw.init = &init; 899 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 900 if (ret) 901 return ret; 902 903 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 904 &st->int_clk_hw); 905 } 906 907 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 908 { 909 struct ad7173_channel *chans_st_arr, *chan_st_priv; 910 struct ad7173_state *st = iio_priv(indio_dev); 911 struct device *dev = indio_dev->dev.parent; 912 struct iio_chan_spec *chan_arr, *chan; 913 unsigned int ain[2], chan_index = 0; 914 int ref_sel, ret; 915 916 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 917 st->num_channels, GFP_KERNEL); 918 if (!chan_arr) 919 return -ENOMEM; 920 921 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 922 GFP_KERNEL); 923 if (!chans_st_arr) 924 return -ENOMEM; 925 926 indio_dev->channels = chan_arr; 927 st->channels = chans_st_arr; 928 929 if (st->info->has_temp) { 930 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 931 chan_st_priv = &chans_st_arr[chan_index]; 932 chan_st_priv->ain = 933 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 934 chan_arr[chan_index].channel2); 935 chan_st_priv->cfg.bipolar = false; 936 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 937 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 938 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 939 940 chan_index++; 941 } 942 943 device_for_each_child_node_scoped(dev, child) { 944 chan = &chan_arr[chan_index]; 945 chan_st_priv = &chans_st_arr[chan_index]; 946 ret = fwnode_property_read_u32_array(child, "diff-channels", 947 ain, ARRAY_SIZE(ain)); 948 if (ret) 949 return ret; 950 951 if (ain[0] >= st->info->num_inputs || 952 ain[1] >= st->info->num_inputs) 953 return dev_err_probe(dev, -EINVAL, 954 "Input pin number out of range for pair (%d %d).\n", 955 ain[0], ain[1]); 956 957 ret = fwnode_property_match_property_string(child, 958 "adi,reference-select", 959 ad7173_ref_sel_str, 960 ARRAY_SIZE(ad7173_ref_sel_str)); 961 if (ret < 0) 962 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 963 else 964 ref_sel = ret; 965 966 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && 967 !st->info->has_int_ref) 968 return dev_err_probe(dev, -EINVAL, 969 "Internal reference is not available on current model.\n"); 970 971 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 972 return dev_err_probe(dev, -EINVAL, 973 "External reference 2 is not available on current model.\n"); 974 975 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 976 if (ret < 0) 977 return dev_err_probe(dev, ret, 978 "Cannot use reference %u\n", ref_sel); 979 980 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 981 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 982 chan_st_priv->cfg.ref_sel = ref_sel; 983 984 *chan = ad7173_channel_template; 985 chan->address = chan_index; 986 chan->scan_index = chan_index; 987 chan->channel = ain[0]; 988 chan->channel2 = ain[1]; 989 chan->differential = true; 990 991 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 992 chan_st_priv->chan_reg = chan_index; 993 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 994 chan_st_priv->cfg.odr = 0; 995 996 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 997 if (chan_st_priv->cfg.bipolar) 998 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 999 1000 chan_index++; 1001 } 1002 return 0; 1003 } 1004 1005 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1006 { 1007 struct ad7173_state *st = iio_priv(indio_dev); 1008 struct device *dev = indio_dev->dev.parent; 1009 unsigned int num_channels; 1010 int ret; 1011 1012 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1013 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1014 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1015 1016 /* 1017 * If a regulator is not available, it will be set to a dummy regulator. 1018 * Each channel reference is checked with regulator_get_voltage() before 1019 * setting attributes so if any channel uses a dummy supply the driver 1020 * probe will fail. 1021 */ 1022 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1023 st->regulators); 1024 if (ret) 1025 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1026 1027 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1028 if (ret) 1029 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1030 1031 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1032 if (ret) 1033 return dev_err_probe(dev, ret, 1034 "Failed to add regulators disable action\n"); 1035 1036 ret = device_property_match_property_string(dev, "clock-names", 1037 ad7173_clk_sel, 1038 ARRAY_SIZE(ad7173_clk_sel)); 1039 if (ret < 0) { 1040 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1041 AD7173_ADC_MODE_CLOCKSEL_INT); 1042 ad7173_register_clk_provider(indio_dev); 1043 } else { 1044 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1045 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1046 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]); 1047 if (IS_ERR(st->ext_clk)) 1048 return dev_err_probe(dev, PTR_ERR(st->ext_clk), 1049 "Failed to get external clock\n"); 1050 1051 ret = clk_prepare_enable(st->ext_clk); 1052 if (ret) 1053 return dev_err_probe(dev, ret, 1054 "Failed to enable external clock\n"); 1055 1056 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare, 1057 st->ext_clk); 1058 if (ret) 1059 return ret; 1060 } 1061 1062 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy"); 1063 if (ret < 0) 1064 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n"); 1065 1066 ad7173_sigma_delta_info.irq_line = ret; 1067 1068 num_channels = device_get_child_node_count(dev); 1069 1070 if (st->info->has_temp) 1071 num_channels++; 1072 1073 if (num_channels == 0) 1074 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1075 indio_dev->num_channels = num_channels; 1076 st->num_channels = num_channels; 1077 1078 return ad7173_fw_parse_channel_config(indio_dev); 1079 } 1080 1081 static int ad7173_probe(struct spi_device *spi) 1082 { 1083 struct device *dev = &spi->dev; 1084 struct ad7173_state *st; 1085 struct iio_dev *indio_dev; 1086 int ret; 1087 1088 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1089 if (!indio_dev) 1090 return -ENOMEM; 1091 1092 st = iio_priv(indio_dev); 1093 st->info = spi_get_device_match_data(spi); 1094 if (!st->info) 1095 return -ENODEV; 1096 1097 ida_init(&st->cfg_slots_status); 1098 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1099 if (ret) 1100 return ret; 1101 1102 indio_dev->name = st->info->name; 1103 indio_dev->modes = INDIO_DIRECT_MODE; 1104 indio_dev->info = &ad7173_info; 1105 1106 spi->mode = SPI_MODE_3; 1107 spi_setup(spi); 1108 1109 ad7173_sigma_delta_info.num_slots = st->info->num_configs; 1110 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7173_sigma_delta_info); 1111 if (ret) 1112 return ret; 1113 1114 ret = ad7173_fw_parse_device_config(indio_dev); 1115 if (ret) 1116 return ret; 1117 1118 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1119 if (ret) 1120 return ret; 1121 1122 ret = ad7173_setup(indio_dev); 1123 if (ret) 1124 return ret; 1125 1126 ret = devm_iio_device_register(dev, indio_dev); 1127 if (ret) 1128 return ret; 1129 1130 if (IS_ENABLED(CONFIG_GPIOLIB)) 1131 return ad7173_gpio_init(st); 1132 1133 return 0; 1134 } 1135 1136 static const struct of_device_id ad7173_of_match[] = { 1137 { .compatible = "adi,ad7172-2", 1138 .data = &ad7173_device_info[ID_AD7172_2]}, 1139 { .compatible = "adi,ad7172-4", 1140 .data = &ad7173_device_info[ID_AD7172_4]}, 1141 { .compatible = "adi,ad7173-8", 1142 .data = &ad7173_device_info[ID_AD7173_8]}, 1143 { .compatible = "adi,ad7175-2", 1144 .data = &ad7173_device_info[ID_AD7175_2]}, 1145 { .compatible = "adi,ad7175-8", 1146 .data = &ad7173_device_info[ID_AD7175_8]}, 1147 { .compatible = "adi,ad7176-2", 1148 .data = &ad7173_device_info[ID_AD7176_2]}, 1149 { .compatible = "adi,ad7177-2", 1150 .data = &ad7173_device_info[ID_AD7177_2]}, 1151 { } 1152 }; 1153 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1154 1155 static const struct spi_device_id ad7173_id_table[] = { 1156 { "ad7172-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7172_2]}, 1157 { "ad7172-4", (kernel_ulong_t)&ad7173_device_info[ID_AD7172_4]}, 1158 { "ad7173-8", (kernel_ulong_t)&ad7173_device_info[ID_AD7173_8]}, 1159 { "ad7175-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7175_2]}, 1160 { "ad7175-8", (kernel_ulong_t)&ad7173_device_info[ID_AD7175_8]}, 1161 { "ad7176-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7176_2]}, 1162 { "ad7177-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7177_2]}, 1163 { } 1164 }; 1165 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1166 1167 static struct spi_driver ad7173_driver = { 1168 .driver = { 1169 .name = "ad7173", 1170 .of_match_table = ad7173_of_match, 1171 }, 1172 .probe = ad7173_probe, 1173 .id_table = ad7173_id_table, 1174 }; 1175 module_spi_driver(ad7173_driver); 1176 1177 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1178 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1179 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1180 MODULE_DESCRIPTION("Analog Devices AD7172/AD7173/AD7175/AD7176 ADC driver"); 1181 MODULE_LICENSE("GPL"); 1182