1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x and AD411x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116 7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 8 * AD7175-8/AD7176-2/AD7177-2 9 * 10 * Copyright (C) 2015, 2024 Analog Devices, Inc. 11 */ 12 13 #include <linux/array_size.h> 14 #include <linux/bitfield.h> 15 #include <linux/bitmap.h> 16 #include <linux/container_of.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/gpio/regmap.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/math64.h> 27 #include <linux/module.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/spi/spi.h> 34 #include <linux/types.h> 35 #include <linux/units.h> 36 37 #include <linux/iio/buffer.h> 38 #include <linux/iio/iio.h> 39 #include <linux/iio/trigger_consumer.h> 40 #include <linux/iio/triggered_buffer.h> 41 42 #include <linux/iio/adc/ad_sigma_delta.h> 43 44 #define AD7173_REG_COMMS 0x00 45 #define AD7173_REG_ADC_MODE 0x01 46 #define AD7173_REG_INTERFACE_MODE 0x02 47 #define AD7173_REG_CRC 0x03 48 #define AD7173_REG_DATA 0x04 49 #define AD7173_REG_GPIO 0x06 50 #define AD7173_REG_ID 0x07 51 #define AD7173_REG_CH(x) (0x10 + (x)) 52 #define AD7173_REG_SETUP(x) (0x20 + (x)) 53 #define AD7173_REG_FILTER(x) (0x28 + (x)) 54 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 55 #define AD7173_REG_GAIN(x) (0x38 + (x)) 56 57 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 58 59 #define AD7173_CH_ENABLE BIT(15) 60 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 61 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 62 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 63 64 #define AD7173_NO_AINS_PER_CHANNEL 2 65 #define AD7173_CH_ADDRESS(pos, neg) \ 66 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 67 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 68 #define AD7173_AIN_TEMP_POS 17 69 #define AD7173_AIN_TEMP_NEG 18 70 #define AD7173_AIN_POW_MON_POS 19 71 #define AD7173_AIN_POW_MON_NEG 20 72 #define AD7173_AIN_REF_POS 21 73 #define AD7173_AIN_REF_NEG 22 74 75 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \ 76 (x) == AD7173_AIN_REF_NEG) 77 78 #define AD7172_2_ID 0x00d0 79 #define AD7176_ID 0x0c90 80 #define AD7175_ID 0x0cd0 81 #define AD7175_2_ID 0x0cd0 82 #define AD7172_4_ID 0x2050 83 #define AD7173_ID 0x30d0 84 #define AD4111_ID AD7173_ID 85 #define AD4112_ID AD7173_ID 86 #define AD4114_ID AD7173_ID 87 #define AD4113_ID 0x31d0 88 #define AD4116_ID 0x34d0 89 #define AD4115_ID 0x38d0 90 #define AD7175_8_ID 0x3cd0 91 #define AD7177_ID 0x4fd0 92 #define AD7173_ID_MASK GENMASK(15, 4) 93 94 #define AD7173_ADC_MODE_REF_EN BIT(15) 95 #define AD7173_ADC_MODE_SING_CYC BIT(13) 96 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 97 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 98 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 99 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 100 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 101 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 102 103 #define AD7173_GPIO_PDSW BIT(14) 104 #define AD7173_GPIO_OP_EN2_3 BIT(13) 105 #define AD7173_GPIO_MUX_IO BIT(12) 106 #define AD7173_GPIO_SYNC_EN BIT(11) 107 #define AD7173_GPIO_ERR_EN BIT(10) 108 #define AD7173_GPIO_ERR_DAT BIT(9) 109 #define AD7173_GPIO_GP_DATA3 BIT(7) 110 #define AD7173_GPIO_GP_DATA2 BIT(6) 111 #define AD7173_GPIO_IP_EN1 BIT(5) 112 #define AD7173_GPIO_IP_EN0 BIT(4) 113 #define AD7173_GPIO_OP_EN1 BIT(3) 114 #define AD7173_GPIO_OP_EN0 BIT(2) 115 #define AD7173_GPIO_GP_DATA1 BIT(1) 116 #define AD7173_GPIO_GP_DATA0 BIT(0) 117 118 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 119 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 120 #define AD4111_GPO01_DATA(x) BIT((x) + 6) 121 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 122 123 #define AD7173_INTERFACE_DATA_STAT BIT(6) 124 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 125 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 126 127 #define AD7173_SETUP_BIPOLAR BIT(12) 128 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 129 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 130 131 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 132 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 133 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 134 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 135 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 136 #define AD7173_VOLTAGE_INT_REF_uV 2500000 137 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 138 #define AD7177_ODR_START_VALUE 0x07 139 #define AD4111_SHUNT_RESISTOR_OHM 50 140 #define AD4111_DIVIDER_RATIO 10 141 #define AD4111_CURRENT_CHAN_CUTOFF 16 142 #define AD4111_VINCOM_INPUT 0x10 143 144 /* pin < num_voltage_in is a normal voltage input */ 145 /* pin >= num_voltage_in_div is a voltage input without a divider */ 146 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \ 147 (pin2) < st->info->num_voltage_in && \ 148 (pin2) >= st->info->num_voltage_in_div) 149 150 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 151 #define AD7173_MAX_CONFIGS 8 152 153 struct ad7173_device_info { 154 const unsigned int *sinc5_data_rates; 155 unsigned int num_sinc5_data_rates; 156 unsigned int odr_start_value; 157 /* 158 * AD4116 has both inputs with a voltage divider and without. 159 * These inputs cannot be mixed in the channel configuration. 160 * Does not include the VINCOM input. 161 */ 162 unsigned int num_voltage_in_div; 163 unsigned int num_channels; 164 unsigned int num_configs; 165 unsigned int num_voltage_in; 166 unsigned int clock; 167 unsigned int id; 168 char *name; 169 bool has_current_inputs; 170 bool has_vincom_input; 171 bool has_temp; 172 /* ((AVDD1 − AVSS)/5) */ 173 bool has_pow_supply_monitoring; 174 bool data_reg_only_16bit; 175 bool has_input_buf; 176 bool has_int_ref; 177 bool has_ref2; 178 bool higher_gpio_bits; 179 u8 num_gpios; 180 }; 181 182 struct ad7173_channel_config { 183 u8 cfg_slot; 184 bool live; 185 186 /* Following fields are used to compare equality. */ 187 struct_group(config_props, 188 bool bipolar; 189 bool input_buf; 190 u8 odr; 191 u8 ref_sel; 192 ); 193 }; 194 195 struct ad7173_channel { 196 unsigned int chan_reg; 197 unsigned int ain; 198 struct ad7173_channel_config cfg; 199 }; 200 201 struct ad7173_state { 202 struct ad_sigma_delta sd; 203 struct ad_sigma_delta_info sigma_delta_info; 204 const struct ad7173_device_info *info; 205 struct ad7173_channel *channels; 206 struct regulator_bulk_data regulators[3]; 207 unsigned int adc_mode; 208 unsigned int interface_mode; 209 unsigned int num_channels; 210 struct ida cfg_slots_status; 211 unsigned long long config_usage_counter; 212 unsigned long long *config_cnts; 213 struct clk *ext_clk; 214 struct clk_hw int_clk_hw; 215 #if IS_ENABLED(CONFIG_GPIOLIB) 216 struct regmap *reg_gpiocon_regmap; 217 struct gpio_regmap *gpio_regmap; 218 #endif 219 }; 220 221 static unsigned int ad4115_sinc5_data_rates[] = { 222 24845000, 24845000, 20725000, 20725000, /* 0-3 */ 223 15564000, 13841000, 10390000, 10390000, /* 4-7 */ 224 4994000, 2499000, 1000000, 500000, /* 8-11 */ 225 395500, 200000, 100000, 59890, /* 12-15 */ 226 49920, 20000, 16660, 10000, /* 16-19 */ 227 5000, 2500, 2500, /* 20-22 */ 228 }; 229 230 static unsigned int ad4116_sinc5_data_rates[] = { 231 12422360, 12422360, 12422360, 12422360, /* 0-3 */ 232 10362690, 10362690, 7782100, 6290530, /* 4-7 */ 233 5194800, 2496900, 1007600, 499900, /* 8-11 */ 234 390600, 200300, 100000, 59750, /* 12-15 */ 235 49840, 20000, 16650, 10000, /* 16-19 */ 236 5000, 2500, 1250, /* 20-22 */ 237 }; 238 239 static const unsigned int ad7173_sinc5_data_rates[] = { 240 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 241 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 242 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 243 }; 244 245 static const unsigned int ad7175_sinc5_data_rates[] = { 246 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 247 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 248 5000000, 2500000, 1000000, 500000, /* 8-11 */ 249 397500, 200000, 100000, 59920, /* 12-15 */ 250 49960, 20000, 16666, 10000, /* 16-19 */ 251 5000, /* 20 */ 252 }; 253 254 static unsigned int ad4111_current_channel_config[] = { 255 /* Ain sel: pos neg */ 256 0x1E8, /* 15:IIN0+ 8:IIN0− */ 257 0x1C9, /* 14:IIN1+ 9:IIN1− */ 258 0x1AA, /* 13:IIN2+ 10:IIN2− */ 259 0x18B, /* 12:IIN3+ 11:IIN3− */ 260 }; 261 262 static const struct ad7173_device_info ad4111_device_info = { 263 .name = "ad4111", 264 .id = AD4111_ID, 265 .num_voltage_in_div = 8, 266 .num_channels = 16, 267 .num_configs = 8, 268 .num_voltage_in = 8, 269 .num_gpios = 2, 270 .higher_gpio_bits = true, 271 .has_temp = true, 272 .has_vincom_input = true, 273 .has_input_buf = true, 274 .has_current_inputs = true, 275 .has_int_ref = true, 276 .clock = 2 * HZ_PER_MHZ, 277 .sinc5_data_rates = ad7173_sinc5_data_rates, 278 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 279 }; 280 281 static const struct ad7173_device_info ad4112_device_info = { 282 .name = "ad4112", 283 .id = AD4112_ID, 284 .num_voltage_in_div = 8, 285 .num_channels = 16, 286 .num_configs = 8, 287 .num_voltage_in = 8, 288 .num_gpios = 2, 289 .higher_gpio_bits = true, 290 .has_vincom_input = true, 291 .has_temp = true, 292 .has_input_buf = true, 293 .has_current_inputs = true, 294 .has_int_ref = true, 295 .clock = 2 * HZ_PER_MHZ, 296 .sinc5_data_rates = ad7173_sinc5_data_rates, 297 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 298 }; 299 300 static const struct ad7173_device_info ad4113_device_info = { 301 .name = "ad4113", 302 .id = AD4113_ID, 303 .num_voltage_in_div = 8, 304 .num_channels = 16, 305 .num_configs = 8, 306 .num_voltage_in = 8, 307 .num_gpios = 2, 308 .data_reg_only_16bit = true, 309 .higher_gpio_bits = true, 310 .has_vincom_input = true, 311 .has_input_buf = true, 312 .has_int_ref = true, 313 .clock = 2 * HZ_PER_MHZ, 314 .sinc5_data_rates = ad7173_sinc5_data_rates, 315 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 316 }; 317 318 static const struct ad7173_device_info ad4114_device_info = { 319 .name = "ad4114", 320 .id = AD4114_ID, 321 .num_voltage_in_div = 16, 322 .num_channels = 16, 323 .num_configs = 8, 324 .num_voltage_in = 16, 325 .num_gpios = 4, 326 .has_vincom_input = true, 327 .has_temp = true, 328 .has_input_buf = true, 329 .has_int_ref = true, 330 .clock = 2 * HZ_PER_MHZ, 331 .sinc5_data_rates = ad7173_sinc5_data_rates, 332 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 333 }; 334 335 static const struct ad7173_device_info ad4115_device_info = { 336 .name = "ad4115", 337 .id = AD4115_ID, 338 .num_voltage_in_div = 16, 339 .num_channels = 16, 340 .num_configs = 8, 341 .num_voltage_in = 16, 342 .num_gpios = 4, 343 .has_vincom_input = true, 344 .has_temp = true, 345 .has_input_buf = true, 346 .has_int_ref = true, 347 .clock = 8 * HZ_PER_MHZ, 348 .sinc5_data_rates = ad4115_sinc5_data_rates, 349 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates), 350 }; 351 352 static const struct ad7173_device_info ad4116_device_info = { 353 .name = "ad4116", 354 .id = AD4116_ID, 355 .num_voltage_in_div = 11, 356 .num_channels = 16, 357 .num_configs = 8, 358 .num_voltage_in = 16, 359 .num_gpios = 4, 360 .has_vincom_input = true, 361 .has_temp = true, 362 .has_input_buf = true, 363 .has_int_ref = true, 364 .clock = 4 * HZ_PER_MHZ, 365 .sinc5_data_rates = ad4116_sinc5_data_rates, 366 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates), 367 }; 368 369 static const struct ad7173_device_info ad7172_2_device_info = { 370 .name = "ad7172-2", 371 .id = AD7172_2_ID, 372 .num_voltage_in = 5, 373 .num_channels = 4, 374 .num_configs = 4, 375 .num_gpios = 2, 376 .has_temp = true, 377 .has_input_buf = true, 378 .has_int_ref = true, 379 .has_pow_supply_monitoring = true, 380 .clock = 2 * HZ_PER_MHZ, 381 .sinc5_data_rates = ad7173_sinc5_data_rates, 382 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 383 }; 384 385 static const struct ad7173_device_info ad7172_4_device_info = { 386 .name = "ad7172-4", 387 .id = AD7172_4_ID, 388 .num_voltage_in = 9, 389 .num_channels = 8, 390 .num_configs = 8, 391 .num_gpios = 4, 392 .has_input_buf = true, 393 .has_ref2 = true, 394 .has_pow_supply_monitoring = true, 395 .clock = 2 * HZ_PER_MHZ, 396 .sinc5_data_rates = ad7173_sinc5_data_rates, 397 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 398 }; 399 400 static const struct ad7173_device_info ad7173_8_device_info = { 401 .name = "ad7173-8", 402 .id = AD7173_ID, 403 .num_voltage_in = 17, 404 .num_channels = 16, 405 .num_configs = 8, 406 .num_gpios = 4, 407 .has_temp = true, 408 .has_input_buf = true, 409 .has_int_ref = true, 410 .has_ref2 = true, 411 .clock = 2 * HZ_PER_MHZ, 412 .sinc5_data_rates = ad7173_sinc5_data_rates, 413 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 414 }; 415 416 static const struct ad7173_device_info ad7175_2_device_info = { 417 .name = "ad7175-2", 418 .id = AD7175_2_ID, 419 .num_voltage_in = 5, 420 .num_channels = 4, 421 .num_configs = 4, 422 .num_gpios = 2, 423 .has_temp = true, 424 .has_input_buf = true, 425 .has_int_ref = true, 426 .has_pow_supply_monitoring = true, 427 .clock = 16 * HZ_PER_MHZ, 428 .sinc5_data_rates = ad7175_sinc5_data_rates, 429 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 430 }; 431 432 static const struct ad7173_device_info ad7175_8_device_info = { 433 .name = "ad7175-8", 434 .id = AD7175_8_ID, 435 .num_voltage_in = 17, 436 .num_channels = 16, 437 .num_configs = 8, 438 .num_gpios = 4, 439 .has_temp = true, 440 .has_input_buf = true, 441 .has_int_ref = true, 442 .has_ref2 = true, 443 .has_pow_supply_monitoring = true, 444 .clock = 16 * HZ_PER_MHZ, 445 .sinc5_data_rates = ad7175_sinc5_data_rates, 446 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 447 }; 448 449 static const struct ad7173_device_info ad7176_2_device_info = { 450 .name = "ad7176-2", 451 .id = AD7176_ID, 452 .num_voltage_in = 5, 453 .num_channels = 4, 454 .num_configs = 4, 455 .num_gpios = 2, 456 .has_int_ref = true, 457 .clock = 16 * HZ_PER_MHZ, 458 .sinc5_data_rates = ad7175_sinc5_data_rates, 459 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 460 }; 461 462 static const struct ad7173_device_info ad7177_2_device_info = { 463 .name = "ad7177-2", 464 .id = AD7177_ID, 465 .num_voltage_in = 5, 466 .num_channels = 4, 467 .num_configs = 4, 468 .num_gpios = 2, 469 .has_temp = true, 470 .has_input_buf = true, 471 .has_int_ref = true, 472 .has_pow_supply_monitoring = true, 473 .clock = 16 * HZ_PER_MHZ, 474 .odr_start_value = AD7177_ODR_START_VALUE, 475 .sinc5_data_rates = ad7175_sinc5_data_rates, 476 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 477 }; 478 479 static const char *const ad7173_ref_sel_str[] = { 480 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 481 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 482 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 483 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 484 }; 485 486 static const char *const ad7173_clk_sel[] = { 487 "ext-clk", "xtal" 488 }; 489 490 #if IS_ENABLED(CONFIG_GPIOLIB) 491 492 static const struct regmap_range ad7173_range_gpio[] = { 493 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 494 }; 495 496 static const struct regmap_access_table ad7173_access_table = { 497 .yes_ranges = ad7173_range_gpio, 498 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 499 }; 500 501 static const struct regmap_config ad7173_regmap_config = { 502 .reg_bits = 8, 503 .val_bits = 16, 504 .rd_table = &ad7173_access_table, 505 .wr_table = &ad7173_access_table, 506 .read_flag_mask = BIT(6), 507 }; 508 509 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 510 unsigned int offset, unsigned int *reg, 511 unsigned int *mask) 512 { 513 *mask = AD7173_GPO_DATA(offset); 514 *reg = base; 515 return 0; 516 } 517 518 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 519 unsigned int offset, unsigned int *reg, 520 unsigned int *mask) 521 { 522 *mask = AD4111_GPO01_DATA(offset); 523 *reg = base; 524 return 0; 525 } 526 527 static void ad7173_gpio_disable(void *data) 528 { 529 struct ad7173_state *st = data; 530 unsigned int mask; 531 532 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 533 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 534 } 535 536 static int ad7173_gpio_init(struct ad7173_state *st) 537 { 538 struct gpio_regmap_config gpio_regmap = {}; 539 struct device *dev = &st->sd.spi->dev; 540 unsigned int mask; 541 int ret; 542 543 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 544 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 545 if (ret) 546 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 547 548 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 549 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 550 551 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 552 if (ret) 553 return ret; 554 555 gpio_regmap.parent = dev; 556 gpio_regmap.regmap = st->reg_gpiocon_regmap; 557 gpio_regmap.ngpio = st->info->num_gpios; 558 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 559 if (st->info->higher_gpio_bits) 560 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate; 561 else 562 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 563 564 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 565 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 566 if (ret) 567 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 568 569 return 0; 570 } 571 #else 572 static int ad7173_gpio_init(struct ad7173_state *st) 573 { 574 return 0; 575 } 576 #endif /* CONFIG_GPIOLIB */ 577 578 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 579 { 580 return container_of(sd, struct ad7173_state, sd); 581 } 582 583 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 584 { 585 return container_of(hw, struct ad7173_state, int_clk_hw); 586 } 587 588 static void ad7173_ida_destroy(void *data) 589 { 590 struct ad7173_state *st = data; 591 592 ida_destroy(&st->cfg_slots_status); 593 } 594 595 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 596 { 597 memset64(st->config_cnts, 0, st->info->num_configs); 598 st->config_usage_counter = 0; 599 } 600 601 static struct ad7173_channel_config * 602 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 603 { 604 struct ad7173_channel_config *cfg_aux; 605 ptrdiff_t cmp_size; 606 int i; 607 608 cmp_size = sizeof_field(struct ad7173_channel_config, config_props); 609 for (i = 0; i < st->num_channels; i++) { 610 cfg_aux = &st->channels[i].cfg; 611 612 if (cfg_aux->live && 613 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size)) 614 return cfg_aux; 615 } 616 return NULL; 617 } 618 619 /* Could be replaced with a generic LRU implementation */ 620 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 621 { 622 int i, lru_position = 0; 623 624 for (i = 1; i < st->info->num_configs; i++) 625 if (st->config_cnts[i] < st->config_cnts[lru_position]) 626 lru_position = i; 627 628 for (i = 0; i < st->num_channels; i++) 629 if (st->channels[i].cfg.cfg_slot == lru_position) 630 st->channels[i].cfg.live = false; 631 632 ida_free(&st->cfg_slots_status, lru_position); 633 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 634 } 635 636 /* Could be replaced with a generic LRU implementation */ 637 static int ad7173_load_config(struct ad7173_state *st, 638 struct ad7173_channel_config *cfg) 639 { 640 unsigned int config; 641 int free_cfg_slot, ret; 642 643 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 644 st->info->num_configs - 1, GFP_KERNEL); 645 if (free_cfg_slot < 0) 646 free_cfg_slot = ad7173_free_config_slot_lru(st); 647 648 cfg->cfg_slot = free_cfg_slot; 649 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 650 651 if (cfg->bipolar) 652 config |= AD7173_SETUP_BIPOLAR; 653 654 if (cfg->input_buf) 655 config |= AD7173_SETUP_AIN_BUF_MASK; 656 657 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 658 if (ret) 659 return ret; 660 661 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 662 AD7173_FILTER_ODR0_MASK & cfg->odr); 663 } 664 665 static int ad7173_config_channel(struct ad7173_state *st, int addr) 666 { 667 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 668 struct ad7173_channel_config *live_cfg; 669 int ret; 670 671 if (!cfg->live) { 672 live_cfg = ad7173_find_live_config(st, cfg); 673 if (live_cfg) { 674 cfg->cfg_slot = live_cfg->cfg_slot; 675 } else { 676 ret = ad7173_load_config(st, cfg); 677 if (ret) 678 return ret; 679 cfg->live = true; 680 } 681 } 682 683 if (st->config_usage_counter == U64_MAX) 684 ad7173_reset_usage_cnts(st); 685 686 st->config_usage_counter++; 687 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 688 689 return 0; 690 } 691 692 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 693 { 694 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 695 unsigned int val; 696 int ret; 697 698 ret = ad7173_config_channel(st, channel); 699 if (ret) 700 return ret; 701 702 val = AD7173_CH_ENABLE | 703 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 704 st->channels[channel].ain; 705 706 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 707 } 708 709 static int ad7173_set_mode(struct ad_sigma_delta *sd, 710 enum ad_sigma_delta_mode mode) 711 { 712 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 713 714 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 715 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 716 717 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 718 } 719 720 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 721 { 722 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 723 unsigned int interface_mode = st->interface_mode; 724 int ret; 725 726 interface_mode &= ~AD7173_INTERFACE_DATA_STAT; 727 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 728 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 729 if (ret) 730 return ret; 731 732 st->interface_mode = interface_mode; 733 734 return 0; 735 } 736 737 static int ad7173_disable_all(struct ad_sigma_delta *sd) 738 { 739 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 740 int ret; 741 int i; 742 743 for (i = 0; i < st->num_channels; i++) { 744 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 745 if (ret < 0) 746 return ret; 747 } 748 749 return 0; 750 } 751 752 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 753 { 754 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0); 755 } 756 757 static const struct ad_sigma_delta_info ad7173_sigma_delta_info = { 758 .set_channel = ad7173_set_channel, 759 .append_status = ad7173_append_status, 760 .disable_all = ad7173_disable_all, 761 .disable_one = ad7173_disable_one, 762 .set_mode = ad7173_set_mode, 763 .has_registers = true, 764 .addr_shift = 0, 765 .read_mask = BIT(6), 766 .status_ch_mask = GENMASK(3, 0), 767 .data_reg = AD7173_REG_DATA, 768 }; 769 770 static int ad7173_setup(struct iio_dev *indio_dev) 771 { 772 struct ad7173_state *st = iio_priv(indio_dev); 773 struct device *dev = &st->sd.spi->dev; 774 u8 buf[AD7173_RESET_LENGTH]; 775 unsigned int id; 776 int ret; 777 778 /* reset the serial interface */ 779 memset(buf, 0xff, AD7173_RESET_LENGTH); 780 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 781 if (ret < 0) 782 return ret; 783 784 /* datasheet recommends a delay of at least 500us after reset */ 785 fsleep(500); 786 787 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 788 if (ret) 789 return ret; 790 791 id &= AD7173_ID_MASK; 792 if (id != st->info->id) 793 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 794 id, st->info->id); 795 796 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 797 st->interface_mode = 0x0; 798 799 st->config_usage_counter = 0; 800 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 801 sizeof(*st->config_cnts), GFP_KERNEL); 802 if (!st->config_cnts) 803 return -ENOMEM; 804 805 /* All channels are enabled by default after a reset */ 806 return ad7173_disable_all(&st->sd); 807 } 808 809 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 810 u8 reference_select) 811 { 812 int vref; 813 814 switch (reference_select) { 815 case AD7173_SETUP_REF_SEL_EXT_REF: 816 vref = regulator_get_voltage(st->regulators[0].consumer); 817 break; 818 819 case AD7173_SETUP_REF_SEL_EXT_REF2: 820 vref = regulator_get_voltage(st->regulators[1].consumer); 821 break; 822 823 case AD7173_SETUP_REF_SEL_INT_REF: 824 vref = AD7173_VOLTAGE_INT_REF_uV; 825 break; 826 827 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 828 vref = regulator_get_voltage(st->regulators[2].consumer); 829 break; 830 831 default: 832 return -EINVAL; 833 } 834 835 if (vref < 0) 836 return vref; 837 838 return vref / (MICRO / MILLI); 839 } 840 841 static int ad7173_read_raw(struct iio_dev *indio_dev, 842 struct iio_chan_spec const *chan, 843 int *val, int *val2, long info) 844 { 845 struct ad7173_state *st = iio_priv(indio_dev); 846 struct ad7173_channel *ch = &st->channels[chan->address]; 847 unsigned int reg; 848 u64 temp; 849 int ret; 850 851 switch (info) { 852 case IIO_CHAN_INFO_RAW: 853 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 854 if (ret < 0) 855 return ret; 856 857 return IIO_VAL_INT; 858 case IIO_CHAN_INFO_SCALE: 859 860 switch (chan->type) { 861 case IIO_TEMP: 862 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 863 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 864 *val = temp; 865 *val2 = chan->scan_type.realbits; 866 return IIO_VAL_FRACTIONAL_LOG2; 867 case IIO_VOLTAGE: 868 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 869 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 870 871 if (chan->channel < st->info->num_voltage_in_div) 872 *val *= AD4111_DIVIDER_RATIO; 873 return IIO_VAL_FRACTIONAL_LOG2; 874 case IIO_CURRENT: 875 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 876 *val /= AD4111_SHUNT_RESISTOR_OHM; 877 *val2 = chan->scan_type.realbits - ch->cfg.bipolar; 878 return IIO_VAL_FRACTIONAL_LOG2; 879 default: 880 return -EINVAL; 881 } 882 case IIO_CHAN_INFO_OFFSET: 883 884 switch (chan->type) { 885 case IIO_TEMP: 886 /* 0 Kelvin -> raw sample */ 887 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 888 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 889 temp <<= chan->scan_type.realbits; 890 temp = DIV_U64_ROUND_CLOSEST(temp, 891 AD7173_VOLTAGE_INT_REF_uV * 892 MILLI); 893 *val = -temp; 894 return IIO_VAL_INT; 895 case IIO_VOLTAGE: 896 case IIO_CURRENT: 897 *val = -BIT(chan->scan_type.realbits - 1); 898 return IIO_VAL_INT; 899 default: 900 return -EINVAL; 901 } 902 case IIO_CHAN_INFO_SAMP_FREQ: 903 reg = st->channels[chan->address].cfg.odr; 904 905 *val = st->info->sinc5_data_rates[reg] / MILLI; 906 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 907 908 return IIO_VAL_INT_PLUS_MICRO; 909 default: 910 return -EINVAL; 911 } 912 } 913 914 static int ad7173_write_raw(struct iio_dev *indio_dev, 915 struct iio_chan_spec const *chan, 916 int val, int val2, long info) 917 { 918 struct ad7173_state *st = iio_priv(indio_dev); 919 struct ad7173_channel_config *cfg; 920 unsigned int freq, i; 921 int ret; 922 923 ret = iio_device_claim_direct_mode(indio_dev); 924 if (ret) 925 return ret; 926 927 switch (info) { 928 /* 929 * This attribute sets the sampling frequency for each channel individually. 930 * There are no issues for raw or buffered reads of an individual channel. 931 * 932 * When multiple channels are enabled in buffered mode, the effective 933 * sampling rate of a channel is lowered in correlation to the number 934 * of channels enabled and the sampling rate of the other channels. 935 * 936 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps 937 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3 938 * will take 100ms each. 939 * 940 * This will cause the reading of CH1 to be actually done once every 941 * 200.16ms, an effective rate of 4.99sps. 942 */ 943 case IIO_CHAN_INFO_SAMP_FREQ: 944 freq = val * MILLI + val2 / MILLI; 945 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 946 if (freq >= st->info->sinc5_data_rates[i]) 947 break; 948 949 cfg = &st->channels[chan->address].cfg; 950 cfg->odr = i; 951 cfg->live = false; 952 break; 953 954 default: 955 ret = -EINVAL; 956 break; 957 } 958 959 iio_device_release_direct_mode(indio_dev); 960 return ret; 961 } 962 963 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 964 const unsigned long *scan_mask) 965 { 966 struct ad7173_state *st = iio_priv(indio_dev); 967 int i, ret; 968 969 for (i = 0; i < indio_dev->num_channels; i++) { 970 if (test_bit(i, scan_mask)) 971 ret = ad7173_set_channel(&st->sd, i); 972 else 973 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 974 if (ret < 0) 975 return ret; 976 } 977 978 return 0; 979 } 980 981 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 982 unsigned int writeval, unsigned int *readval) 983 { 984 struct ad7173_state *st = iio_priv(indio_dev); 985 u8 reg_size; 986 987 if (reg == AD7173_REG_COMMS) 988 reg_size = 1; 989 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 990 reg >= AD7173_REG_OFFSET(0)) 991 reg_size = 3; 992 else 993 reg_size = 2; 994 995 if (readval) 996 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 997 998 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 999 } 1000 1001 static const struct iio_info ad7173_info = { 1002 .read_raw = &ad7173_read_raw, 1003 .write_raw = &ad7173_write_raw, 1004 .debugfs_reg_access = &ad7173_debug_reg_access, 1005 .validate_trigger = ad_sd_validate_trigger, 1006 .update_scan_mode = ad7173_update_scan_mode, 1007 }; 1008 1009 static const struct iio_scan_type ad4113_scan_type = { 1010 .sign = 'u', 1011 .realbits = 16, 1012 .storagebits = 16, 1013 .endianness = IIO_BE, 1014 }; 1015 1016 static const struct iio_chan_spec ad7173_channel_template = { 1017 .type = IIO_VOLTAGE, 1018 .indexed = 1, 1019 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1020 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 1021 .scan_type = { 1022 .sign = 'u', 1023 .realbits = 24, 1024 .storagebits = 32, 1025 .endianness = IIO_BE, 1026 }, 1027 }; 1028 1029 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 1030 .type = IIO_TEMP, 1031 .channel = AD7173_AIN_TEMP_POS, 1032 .channel2 = AD7173_AIN_TEMP_NEG, 1033 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1034 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1035 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1036 .scan_type = { 1037 .sign = 'u', 1038 .realbits = 24, 1039 .storagebits = 32, 1040 .endianness = IIO_BE, 1041 }, 1042 }; 1043 1044 static void ad7173_disable_regulators(void *data) 1045 { 1046 struct ad7173_state *st = data; 1047 1048 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1049 } 1050 1051 static void ad7173_clk_disable_unprepare(void *clk) 1052 { 1053 clk_disable_unprepare(clk); 1054 } 1055 1056 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 1057 unsigned int clk_sel) 1058 { 1059 int ret; 1060 1061 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 1062 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 1063 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 1064 1065 return ret; 1066 } 1067 1068 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 1069 unsigned long parent_rate) 1070 { 1071 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1072 1073 return st->info->clock / HZ_PER_KHZ; 1074 } 1075 1076 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 1077 { 1078 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1079 u32 clk_sel; 1080 1081 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 1082 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 1083 } 1084 1085 static int ad7173_clk_output_prepare(struct clk_hw *hw) 1086 { 1087 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1088 1089 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 1090 } 1091 1092 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 1093 { 1094 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1095 1096 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 1097 } 1098 1099 static const struct clk_ops ad7173_int_clk_ops = { 1100 .recalc_rate = ad7173_clk_recalc_rate, 1101 .is_enabled = ad7173_clk_output_is_enabled, 1102 .prepare = ad7173_clk_output_prepare, 1103 .unprepare = ad7173_clk_output_unprepare, 1104 }; 1105 1106 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 1107 { 1108 struct ad7173_state *st = iio_priv(indio_dev); 1109 struct device *dev = indio_dev->dev.parent; 1110 struct fwnode_handle *fwnode = dev_fwnode(dev); 1111 struct clk_init_data init = {}; 1112 int ret; 1113 1114 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1115 return 0; 1116 1117 init.name = fwnode_get_name(fwnode); 1118 init.ops = &ad7173_int_clk_ops; 1119 1120 st->int_clk_hw.init = &init; 1121 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 1122 if (ret) 1123 return ret; 1124 1125 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1126 &st->int_clk_hw); 1127 } 1128 1129 static int ad4111_validate_current_ain(struct ad7173_state *st, 1130 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL]) 1131 { 1132 struct device *dev = &st->sd.spi->dev; 1133 1134 if (!st->info->has_current_inputs) 1135 return dev_err_probe(dev, -EINVAL, 1136 "Model %s does not support current channels\n", 1137 st->info->name); 1138 1139 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config)) 1140 return dev_err_probe(dev, -EINVAL, 1141 "For current channels single-channel must be <[0-3]>\n"); 1142 1143 return 0; 1144 } 1145 1146 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st, 1147 unsigned int ain0, unsigned int ain1) 1148 { 1149 struct device *dev = &st->sd.spi->dev; 1150 bool special_input0, special_input1; 1151 1152 /* (AVDD1-AVSS)/5 power supply monitoring */ 1153 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG && 1154 st->info->has_pow_supply_monitoring) 1155 return 0; 1156 1157 special_input0 = AD7173_IS_REF_INPUT(ain0) || 1158 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1159 special_input1 = AD7173_IS_REF_INPUT(ain1) || 1160 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1161 1162 if ((ain0 >= st->info->num_voltage_in && !special_input0) || 1163 (ain1 >= st->info->num_voltage_in && !special_input1)) { 1164 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT) 1165 return dev_err_probe(dev, -EINVAL, 1166 "VINCOM not supported for %s\n", st->info->name); 1167 1168 return dev_err_probe(dev, -EINVAL, 1169 "Input pin number out of range for pair (%d %d).\n", 1170 ain0, ain1); 1171 } 1172 1173 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) || 1174 AD4111_IS_VINCOM_MISMATCH(ain1, ain0)) 1175 return dev_err_probe(dev, -EINVAL, 1176 "VINCOM must be paired with inputs having divider.\n"); 1177 1178 if (!special_input0 && !special_input1 && 1179 ((ain0 >= st->info->num_voltage_in_div) != 1180 (ain1 >= st->info->num_voltage_in_div))) 1181 return dev_err_probe(dev, -EINVAL, 1182 "Both inputs must either have a voltage divider or not have: (%d %d).\n", 1183 ain0, ain1); 1184 1185 return 0; 1186 } 1187 1188 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel) 1189 { 1190 struct device *dev = &st->sd.spi->dev; 1191 int ret; 1192 1193 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref) 1194 return dev_err_probe(dev, -EINVAL, 1195 "Internal reference is not available on current model.\n"); 1196 1197 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 1198 return dev_err_probe(dev, -EINVAL, 1199 "External reference 2 is not available on current model.\n"); 1200 1201 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 1202 if (ret < 0) 1203 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1204 ref_sel); 1205 1206 return 0; 1207 } 1208 1209 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 1210 { 1211 struct ad7173_channel *chans_st_arr, *chan_st_priv; 1212 struct ad7173_state *st = iio_priv(indio_dev); 1213 struct device *dev = indio_dev->dev.parent; 1214 struct iio_chan_spec *chan_arr, *chan; 1215 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0; 1216 int ref_sel, ret, num_channels; 1217 1218 num_channels = device_get_child_node_count(dev); 1219 1220 if (st->info->has_temp) 1221 num_channels++; 1222 1223 if (num_channels == 0) 1224 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1225 1226 if (num_channels > st->info->num_channels) 1227 return dev_err_probe(dev, -EINVAL, 1228 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n", 1229 st->info->num_channels); 1230 1231 indio_dev->num_channels = num_channels; 1232 st->num_channels = num_channels; 1233 1234 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 1235 st->num_channels, GFP_KERNEL); 1236 if (!chan_arr) 1237 return -ENOMEM; 1238 1239 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 1240 GFP_KERNEL); 1241 if (!chans_st_arr) 1242 return -ENOMEM; 1243 1244 indio_dev->channels = chan_arr; 1245 st->channels = chans_st_arr; 1246 1247 if (st->info->has_temp) { 1248 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 1249 chan_st_priv = &chans_st_arr[chan_index]; 1250 chan_st_priv->ain = 1251 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 1252 chan_arr[chan_index].channel2); 1253 chan_st_priv->cfg.bipolar = false; 1254 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1255 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1256 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1257 if (st->info->data_reg_only_16bit) 1258 chan_arr[chan_index].scan_type = ad4113_scan_type; 1259 1260 chan_index++; 1261 } 1262 1263 device_for_each_child_node_scoped(dev, child) { 1264 bool is_current_chan = false; 1265 1266 chan = &chan_arr[chan_index]; 1267 *chan = ad7173_channel_template; 1268 chan_st_priv = &chans_st_arr[chan_index]; 1269 ret = fwnode_property_read_u32_array(child, "diff-channels", 1270 ain, ARRAY_SIZE(ain)); 1271 if (ret) { 1272 ret = fwnode_property_read_u32(child, "single-channel", 1273 ain); 1274 if (ret) 1275 return dev_err_probe(dev, ret, 1276 "Channel must define one of diff-channels or single-channel.\n"); 1277 1278 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel"); 1279 } else { 1280 chan->differential = true; 1281 } 1282 1283 if (is_current_chan) { 1284 ret = ad4111_validate_current_ain(st, ain); 1285 if (ret) 1286 return ret; 1287 } else { 1288 if (!chan->differential) { 1289 ret = fwnode_property_read_u32(child, 1290 "common-mode-channel", ain + 1); 1291 if (ret) 1292 return dev_err_probe(dev, ret, 1293 "common-mode-channel must be defined for single-ended channels.\n"); 1294 } 1295 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]); 1296 if (ret) 1297 return ret; 1298 } 1299 1300 ret = fwnode_property_match_property_string(child, 1301 "adi,reference-select", 1302 ad7173_ref_sel_str, 1303 ARRAY_SIZE(ad7173_ref_sel_str)); 1304 if (ret < 0) 1305 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1306 else 1307 ref_sel = ret; 1308 1309 ret = ad7173_validate_reference(st, ref_sel); 1310 if (ret) 1311 return ret; 1312 1313 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 1314 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1315 chan_st_priv->cfg.ref_sel = ref_sel; 1316 1317 chan->address = chan_index; 1318 chan->scan_index = chan_index; 1319 chan->channel = ain[0]; 1320 chan_st_priv->chan_reg = chan_index; 1321 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1322 chan_st_priv->cfg.odr = 0; 1323 1324 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 1325 if (chan_st_priv->cfg.bipolar) 1326 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 1327 1328 if (is_current_chan) { 1329 chan->type = IIO_CURRENT; 1330 chan->differential = false; 1331 chan->channel2 = 0; 1332 chan_st_priv->ain = ad4111_current_channel_config[ain[0]]; 1333 } else { 1334 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1335 chan->channel2 = ain[1]; 1336 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 1337 } 1338 1339 if (st->info->data_reg_only_16bit) 1340 chan_arr[chan_index].scan_type = ad4113_scan_type; 1341 1342 chan_index++; 1343 } 1344 return 0; 1345 } 1346 1347 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1348 { 1349 struct ad7173_state *st = iio_priv(indio_dev); 1350 struct device *dev = indio_dev->dev.parent; 1351 int ret; 1352 1353 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1354 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1355 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1356 1357 /* 1358 * If a regulator is not available, it will be set to a dummy regulator. 1359 * Each channel reference is checked with regulator_get_voltage() before 1360 * setting attributes so if any channel uses a dummy supply the driver 1361 * probe will fail. 1362 */ 1363 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1364 st->regulators); 1365 if (ret) 1366 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1367 1368 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1369 if (ret) 1370 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1371 1372 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1373 if (ret) 1374 return dev_err_probe(dev, ret, 1375 "Failed to add regulators disable action\n"); 1376 1377 ret = device_property_match_property_string(dev, "clock-names", 1378 ad7173_clk_sel, 1379 ARRAY_SIZE(ad7173_clk_sel)); 1380 if (ret < 0) { 1381 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1382 AD7173_ADC_MODE_CLOCKSEL_INT); 1383 ad7173_register_clk_provider(indio_dev); 1384 } else { 1385 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1386 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1387 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]); 1388 if (IS_ERR(st->ext_clk)) 1389 return dev_err_probe(dev, PTR_ERR(st->ext_clk), 1390 "Failed to get external clock\n"); 1391 1392 ret = clk_prepare_enable(st->ext_clk); 1393 if (ret) 1394 return dev_err_probe(dev, ret, 1395 "Failed to enable external clock\n"); 1396 1397 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare, 1398 st->ext_clk); 1399 if (ret) 1400 return ret; 1401 } 1402 1403 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy"); 1404 if (ret < 0) 1405 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n"); 1406 1407 st->sigma_delta_info.irq_line = ret; 1408 1409 return ad7173_fw_parse_channel_config(indio_dev); 1410 } 1411 1412 static int ad7173_probe(struct spi_device *spi) 1413 { 1414 struct device *dev = &spi->dev; 1415 struct ad7173_state *st; 1416 struct iio_dev *indio_dev; 1417 int ret; 1418 1419 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1420 if (!indio_dev) 1421 return -ENOMEM; 1422 1423 st = iio_priv(indio_dev); 1424 st->info = spi_get_device_match_data(spi); 1425 if (!st->info) 1426 return -ENODEV; 1427 1428 ida_init(&st->cfg_slots_status); 1429 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1430 if (ret) 1431 return ret; 1432 1433 indio_dev->name = st->info->name; 1434 indio_dev->modes = INDIO_DIRECT_MODE; 1435 indio_dev->info = &ad7173_info; 1436 1437 spi->mode = SPI_MODE_3; 1438 spi_setup(spi); 1439 1440 st->sigma_delta_info = ad7173_sigma_delta_info; 1441 st->sigma_delta_info.num_slots = st->info->num_configs; 1442 ret = ad_sd_init(&st->sd, indio_dev, spi, &st->sigma_delta_info); 1443 if (ret) 1444 return ret; 1445 1446 ret = ad7173_fw_parse_device_config(indio_dev); 1447 if (ret) 1448 return ret; 1449 1450 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1451 if (ret) 1452 return ret; 1453 1454 ret = ad7173_setup(indio_dev); 1455 if (ret) 1456 return ret; 1457 1458 ret = devm_iio_device_register(dev, indio_dev); 1459 if (ret) 1460 return ret; 1461 1462 if (IS_ENABLED(CONFIG_GPIOLIB)) 1463 return ad7173_gpio_init(st); 1464 1465 return 0; 1466 } 1467 1468 static const struct of_device_id ad7173_of_match[] = { 1469 { .compatible = "adi,ad4111", .data = &ad4111_device_info }, 1470 { .compatible = "adi,ad4112", .data = &ad4112_device_info }, 1471 { .compatible = "adi,ad4113", .data = &ad4113_device_info }, 1472 { .compatible = "adi,ad4114", .data = &ad4114_device_info }, 1473 { .compatible = "adi,ad4115", .data = &ad4115_device_info }, 1474 { .compatible = "adi,ad4116", .data = &ad4116_device_info }, 1475 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info }, 1476 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info }, 1477 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info }, 1478 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info }, 1479 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info }, 1480 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info }, 1481 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info }, 1482 { } 1483 }; 1484 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1485 1486 static const struct spi_device_id ad7173_id_table[] = { 1487 { "ad4111", (kernel_ulong_t)&ad4111_device_info }, 1488 { "ad4112", (kernel_ulong_t)&ad4112_device_info }, 1489 { "ad4113", (kernel_ulong_t)&ad4113_device_info }, 1490 { "ad4114", (kernel_ulong_t)&ad4114_device_info }, 1491 { "ad4115", (kernel_ulong_t)&ad4115_device_info }, 1492 { "ad4116", (kernel_ulong_t)&ad4116_device_info }, 1493 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info }, 1494 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info }, 1495 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info }, 1496 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info }, 1497 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info }, 1498 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info }, 1499 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info }, 1500 { } 1501 }; 1502 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1503 1504 static struct spi_driver ad7173_driver = { 1505 .driver = { 1506 .name = "ad7173", 1507 .of_match_table = ad7173_of_match, 1508 }, 1509 .probe = ad7173_probe, 1510 .id_table = ad7173_id_table, 1511 }; 1512 module_spi_driver(ad7173_driver); 1513 1514 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1515 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1516 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1517 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver"); 1518 MODULE_LICENSE("GPL"); 1519