1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x and AD411x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD4111/AD4112/AD4114/AD4115/AD4116 7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 8 * AD7175-8/AD7176-2/AD7177-2 9 * 10 * Copyright (C) 2015, 2024 Analog Devices, Inc. 11 */ 12 13 #include <linux/array_size.h> 14 #include <linux/bitfield.h> 15 #include <linux/bitmap.h> 16 #include <linux/container_of.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/gpio/regmap.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/math64.h> 27 #include <linux/module.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/spi/spi.h> 34 #include <linux/types.h> 35 #include <linux/units.h> 36 37 #include <linux/iio/buffer.h> 38 #include <linux/iio/iio.h> 39 #include <linux/iio/trigger_consumer.h> 40 #include <linux/iio/triggered_buffer.h> 41 42 #include <linux/iio/adc/ad_sigma_delta.h> 43 44 #define AD7173_REG_COMMS 0x00 45 #define AD7173_REG_ADC_MODE 0x01 46 #define AD7173_REG_INTERFACE_MODE 0x02 47 #define AD7173_REG_CRC 0x03 48 #define AD7173_REG_DATA 0x04 49 #define AD7173_REG_GPIO 0x06 50 #define AD7173_REG_ID 0x07 51 #define AD7173_REG_CH(x) (0x10 + (x)) 52 #define AD7173_REG_SETUP(x) (0x20 + (x)) 53 #define AD7173_REG_FILTER(x) (0x28 + (x)) 54 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 55 #define AD7173_REG_GAIN(x) (0x38 + (x)) 56 57 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 58 59 #define AD7173_CH_ENABLE BIT(15) 60 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 61 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 62 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 63 64 #define AD7173_NO_AINS_PER_CHANNEL 2 65 #define AD7173_CH_ADDRESS(pos, neg) \ 66 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 67 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 68 #define AD7173_AIN_TEMP_POS 17 69 #define AD7173_AIN_TEMP_NEG 18 70 #define AD7173_AIN_POW_MON_POS 19 71 #define AD7173_AIN_POW_MON_NEG 20 72 #define AD7173_AIN_REF_POS 21 73 #define AD7173_AIN_REF_NEG 22 74 75 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \ 76 (x) == AD7173_AIN_REF_NEG) 77 78 #define AD7172_2_ID 0x00d0 79 #define AD7175_ID 0x0cd0 80 #define AD7176_ID 0x0c90 81 #define AD7175_2_ID 0x0cd0 82 #define AD7172_4_ID 0x2050 83 #define AD7173_ID 0x30d0 84 #define AD4111_ID AD7173_ID 85 #define AD4112_ID AD7173_ID 86 #define AD4114_ID AD7173_ID 87 #define AD4116_ID 0x34d0 88 #define AD4115_ID 0x38d0 89 #define AD7175_8_ID 0x3cd0 90 #define AD7177_ID 0x4fd0 91 #define AD7173_ID_MASK GENMASK(15, 4) 92 93 #define AD7173_ADC_MODE_REF_EN BIT(15) 94 #define AD7173_ADC_MODE_SING_CYC BIT(13) 95 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 96 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 97 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 98 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 99 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 100 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 101 102 #define AD7173_GPIO_PDSW BIT(14) 103 #define AD7173_GPIO_OP_EN2_3 BIT(13) 104 #define AD7173_GPIO_MUX_IO BIT(12) 105 #define AD7173_GPIO_SYNC_EN BIT(11) 106 #define AD7173_GPIO_ERR_EN BIT(10) 107 #define AD7173_GPIO_ERR_DAT BIT(9) 108 #define AD7173_GPIO_GP_DATA3 BIT(7) 109 #define AD7173_GPIO_GP_DATA2 BIT(6) 110 #define AD7173_GPIO_IP_EN1 BIT(5) 111 #define AD7173_GPIO_IP_EN0 BIT(4) 112 #define AD7173_GPIO_OP_EN1 BIT(3) 113 #define AD7173_GPIO_OP_EN0 BIT(2) 114 #define AD7173_GPIO_GP_DATA1 BIT(1) 115 #define AD7173_GPIO_GP_DATA0 BIT(0) 116 117 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 118 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 119 #define AD4111_GPO01_DATA(x) BIT((x) + 6) 120 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 121 122 #define AD7173_INTERFACE_DATA_STAT BIT(6) 123 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 124 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 125 126 #define AD7173_SETUP_BIPOLAR BIT(12) 127 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 128 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 129 130 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 131 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 132 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 133 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 134 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 135 #define AD7173_VOLTAGE_INT_REF_uV 2500000 136 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 137 #define AD7177_ODR_START_VALUE 0x07 138 #define AD4111_SHUNT_RESISTOR_OHM 50 139 #define AD4111_DIVIDER_RATIO 10 140 #define AD4111_CURRENT_CHAN_CUTOFF 16 141 #define AD4111_VINCOM_INPUT 0x10 142 143 /* pin < num_voltage_in is a normal voltage input */ 144 /* pin >= num_voltage_in_div is a voltage input without a divider */ 145 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \ 146 (pin2) < st->info->num_voltage_in && \ 147 (pin2) >= st->info->num_voltage_in_div) 148 149 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 150 #define AD7173_MAX_CONFIGS 8 151 152 struct ad7173_device_info { 153 const unsigned int *sinc5_data_rates; 154 unsigned int num_sinc5_data_rates; 155 unsigned int odr_start_value; 156 /* 157 * AD4116 has both inputs with a voltage divider and without. 158 * These inputs cannot be mixed in the channel configuration. 159 * Does not include the VINCOM input. 160 */ 161 unsigned int num_voltage_in_div; 162 unsigned int num_channels; 163 unsigned int num_configs; 164 unsigned int num_voltage_in; 165 unsigned int clock; 166 unsigned int id; 167 char *name; 168 bool has_current_inputs; 169 bool has_vincom_input; 170 bool has_temp; 171 /* ((AVDD1 − AVSS)/5) */ 172 bool has_pow_supply_monitoring; 173 bool has_input_buf; 174 bool has_int_ref; 175 bool has_ref2; 176 bool higher_gpio_bits; 177 u8 num_gpios; 178 }; 179 180 struct ad7173_channel_config { 181 u8 cfg_slot; 182 bool live; 183 184 /* Following fields are used to compare equality. */ 185 struct_group(config_props, 186 bool bipolar; 187 bool input_buf; 188 u8 odr; 189 u8 ref_sel; 190 ); 191 }; 192 193 struct ad7173_channel { 194 unsigned int chan_reg; 195 unsigned int ain; 196 struct ad7173_channel_config cfg; 197 }; 198 199 struct ad7173_state { 200 struct ad_sigma_delta sd; 201 const struct ad7173_device_info *info; 202 struct ad7173_channel *channels; 203 struct regulator_bulk_data regulators[3]; 204 unsigned int adc_mode; 205 unsigned int interface_mode; 206 unsigned int num_channels; 207 struct ida cfg_slots_status; 208 unsigned long long config_usage_counter; 209 unsigned long long *config_cnts; 210 struct clk *ext_clk; 211 struct clk_hw int_clk_hw; 212 #if IS_ENABLED(CONFIG_GPIOLIB) 213 struct regmap *reg_gpiocon_regmap; 214 struct gpio_regmap *gpio_regmap; 215 #endif 216 }; 217 218 static unsigned int ad4115_sinc5_data_rates[] = { 219 24845000, 24845000, 20725000, 20725000, /* 0-3 */ 220 15564000, 13841000, 10390000, 10390000, /* 4-7 */ 221 4994000, 2499000, 1000000, 500000, /* 8-11 */ 222 395500, 200000, 100000, 59890, /* 12-15 */ 223 49920, 20000, 16660, 10000, /* 16-19 */ 224 5000, 2500, 2500, /* 20-22 */ 225 }; 226 227 static unsigned int ad4116_sinc5_data_rates[] = { 228 12422360, 12422360, 12422360, 12422360, /* 0-3 */ 229 10362690, 10362690, 7782100, 6290530, /* 4-7 */ 230 5194800, 2496900, 1007600, 499900, /* 8-11 */ 231 390600, 200300, 100000, 59750, /* 12-15 */ 232 49840, 20000, 16650, 10000, /* 16-19 */ 233 5000, 2500, 1250, /* 20-22 */ 234 }; 235 236 static const unsigned int ad7173_sinc5_data_rates[] = { 237 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 238 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 239 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 240 }; 241 242 static const unsigned int ad7175_sinc5_data_rates[] = { 243 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 244 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 245 5000000, 2500000, 1000000, 500000, /* 8-11 */ 246 397500, 200000, 100000, 59920, /* 12-15 */ 247 49960, 20000, 16666, 10000, /* 16-19 */ 248 5000, /* 20 */ 249 }; 250 251 static unsigned int ad4111_current_channel_config[] = { 252 /* Ain sel: pos neg */ 253 0x1E8, /* 15:IIN0+ 8:IIN0− */ 254 0x1C9, /* 14:IIN1+ 9:IIN1− */ 255 0x1AA, /* 13:IIN2+ 10:IIN2− */ 256 0x18B, /* 12:IIN3+ 11:IIN3− */ 257 }; 258 259 static const struct ad7173_device_info ad4111_device_info = { 260 .name = "ad4111", 261 .id = AD4111_ID, 262 .num_voltage_in_div = 8, 263 .num_channels = 16, 264 .num_configs = 8, 265 .num_voltage_in = 8, 266 .num_gpios = 2, 267 .higher_gpio_bits = true, 268 .has_temp = true, 269 .has_vincom_input = true, 270 .has_input_buf = true, 271 .has_current_inputs = true, 272 .has_int_ref = true, 273 .clock = 2 * HZ_PER_MHZ, 274 .sinc5_data_rates = ad7173_sinc5_data_rates, 275 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 276 }; 277 278 static const struct ad7173_device_info ad4112_device_info = { 279 .name = "ad4112", 280 .id = AD4112_ID, 281 .num_voltage_in_div = 8, 282 .num_channels = 16, 283 .num_configs = 8, 284 .num_voltage_in = 8, 285 .num_gpios = 2, 286 .higher_gpio_bits = true, 287 .has_vincom_input = true, 288 .has_temp = true, 289 .has_input_buf = true, 290 .has_current_inputs = true, 291 .has_int_ref = true, 292 .clock = 2 * HZ_PER_MHZ, 293 .sinc5_data_rates = ad7173_sinc5_data_rates, 294 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 295 }; 296 297 static const struct ad7173_device_info ad4114_device_info = { 298 .name = "ad4114", 299 .id = AD4114_ID, 300 .num_voltage_in_div = 16, 301 .num_channels = 16, 302 .num_configs = 8, 303 .num_voltage_in = 16, 304 .num_gpios = 4, 305 .higher_gpio_bits = true, 306 .has_vincom_input = true, 307 .has_temp = true, 308 .has_input_buf = true, 309 .has_int_ref = true, 310 .clock = 2 * HZ_PER_MHZ, 311 .sinc5_data_rates = ad7173_sinc5_data_rates, 312 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 313 }; 314 315 static const struct ad7173_device_info ad4115_device_info = { 316 .name = "ad4115", 317 .id = AD4115_ID, 318 .num_voltage_in_div = 16, 319 .num_channels = 16, 320 .num_configs = 8, 321 .num_voltage_in = 16, 322 .num_gpios = 4, 323 .higher_gpio_bits = true, 324 .has_vincom_input = true, 325 .has_temp = true, 326 .has_input_buf = true, 327 .has_int_ref = true, 328 .clock = 8 * HZ_PER_MHZ, 329 .sinc5_data_rates = ad4115_sinc5_data_rates, 330 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates), 331 }; 332 333 static const struct ad7173_device_info ad4116_device_info = { 334 .name = "ad4116", 335 .id = AD4116_ID, 336 .num_voltage_in_div = 11, 337 .num_channels = 16, 338 .num_configs = 8, 339 .num_voltage_in = 16, 340 .num_gpios = 4, 341 .higher_gpio_bits = true, 342 .has_vincom_input = true, 343 .has_temp = true, 344 .has_input_buf = true, 345 .has_int_ref = true, 346 .clock = 4 * HZ_PER_MHZ, 347 .sinc5_data_rates = ad4116_sinc5_data_rates, 348 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates), 349 }; 350 351 static const struct ad7173_device_info ad7172_2_device_info = { 352 .name = "ad7172-2", 353 .id = AD7172_2_ID, 354 .num_voltage_in = 5, 355 .num_channels = 4, 356 .num_configs = 4, 357 .num_gpios = 2, 358 .has_temp = true, 359 .has_input_buf = true, 360 .has_int_ref = true, 361 .has_pow_supply_monitoring = true, 362 .clock = 2 * HZ_PER_MHZ, 363 .sinc5_data_rates = ad7173_sinc5_data_rates, 364 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 365 }; 366 367 static const struct ad7173_device_info ad7172_4_device_info = { 368 .name = "ad7172-4", 369 .id = AD7172_4_ID, 370 .num_voltage_in = 9, 371 .num_channels = 8, 372 .num_configs = 8, 373 .num_gpios = 4, 374 .has_input_buf = true, 375 .has_ref2 = true, 376 .has_pow_supply_monitoring = true, 377 .clock = 2 * HZ_PER_MHZ, 378 .sinc5_data_rates = ad7173_sinc5_data_rates, 379 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 380 }; 381 382 static const struct ad7173_device_info ad7173_8_device_info = { 383 .name = "ad7173-8", 384 .id = AD7173_ID, 385 .num_voltage_in = 17, 386 .num_channels = 16, 387 .num_configs = 8, 388 .num_gpios = 4, 389 .has_temp = true, 390 .has_input_buf = true, 391 .has_int_ref = true, 392 .has_ref2 = true, 393 .clock = 2 * HZ_PER_MHZ, 394 .sinc5_data_rates = ad7173_sinc5_data_rates, 395 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 396 }; 397 398 static const struct ad7173_device_info ad7175_2_device_info = { 399 .name = "ad7175-2", 400 .id = AD7175_2_ID, 401 .num_voltage_in = 5, 402 .num_channels = 4, 403 .num_configs = 4, 404 .num_gpios = 2, 405 .has_temp = true, 406 .has_input_buf = true, 407 .has_int_ref = true, 408 .has_pow_supply_monitoring = true, 409 .clock = 16 * HZ_PER_MHZ, 410 .sinc5_data_rates = ad7175_sinc5_data_rates, 411 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 412 }; 413 414 static const struct ad7173_device_info ad7175_8_device_info = { 415 .name = "ad7175-8", 416 .id = AD7175_8_ID, 417 .num_voltage_in = 17, 418 .num_channels = 16, 419 .num_configs = 8, 420 .num_gpios = 4, 421 .has_temp = true, 422 .has_input_buf = true, 423 .has_int_ref = true, 424 .has_ref2 = true, 425 .has_pow_supply_monitoring = true, 426 .clock = 16 * HZ_PER_MHZ, 427 .sinc5_data_rates = ad7175_sinc5_data_rates, 428 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 429 }; 430 431 static const struct ad7173_device_info ad7176_2_device_info = { 432 .name = "ad7176-2", 433 .id = AD7176_ID, 434 .num_voltage_in = 5, 435 .num_channels = 4, 436 .num_configs = 4, 437 .num_gpios = 2, 438 .has_int_ref = true, 439 .clock = 16 * HZ_PER_MHZ, 440 .sinc5_data_rates = ad7175_sinc5_data_rates, 441 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 442 }; 443 444 static const struct ad7173_device_info ad7177_2_device_info = { 445 .name = "ad7177-2", 446 .id = AD7177_ID, 447 .num_voltage_in = 5, 448 .num_channels = 4, 449 .num_configs = 4, 450 .num_gpios = 2, 451 .has_temp = true, 452 .has_input_buf = true, 453 .has_int_ref = true, 454 .has_pow_supply_monitoring = true, 455 .clock = 16 * HZ_PER_MHZ, 456 .odr_start_value = AD7177_ODR_START_VALUE, 457 .sinc5_data_rates = ad7175_sinc5_data_rates, 458 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 459 }; 460 461 static const char *const ad7173_ref_sel_str[] = { 462 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 463 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 464 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 465 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 466 }; 467 468 static const char *const ad7173_clk_sel[] = { 469 "ext-clk", "xtal" 470 }; 471 472 #if IS_ENABLED(CONFIG_GPIOLIB) 473 474 static const struct regmap_range ad7173_range_gpio[] = { 475 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 476 }; 477 478 static const struct regmap_access_table ad7173_access_table = { 479 .yes_ranges = ad7173_range_gpio, 480 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 481 }; 482 483 static const struct regmap_config ad7173_regmap_config = { 484 .reg_bits = 8, 485 .val_bits = 16, 486 .rd_table = &ad7173_access_table, 487 .wr_table = &ad7173_access_table, 488 .read_flag_mask = BIT(6), 489 }; 490 491 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 492 unsigned int offset, unsigned int *reg, 493 unsigned int *mask) 494 { 495 *mask = AD7173_GPO_DATA(offset); 496 *reg = base; 497 return 0; 498 } 499 500 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 501 unsigned int offset, unsigned int *reg, 502 unsigned int *mask) 503 { 504 *mask = AD4111_GPO01_DATA(offset); 505 *reg = base; 506 return 0; 507 } 508 509 static void ad7173_gpio_disable(void *data) 510 { 511 struct ad7173_state *st = data; 512 unsigned int mask; 513 514 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 515 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 516 } 517 518 static int ad7173_gpio_init(struct ad7173_state *st) 519 { 520 struct gpio_regmap_config gpio_regmap = {}; 521 struct device *dev = &st->sd.spi->dev; 522 unsigned int mask; 523 int ret; 524 525 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 526 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 527 if (ret) 528 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 529 530 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 531 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 532 533 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 534 if (ret) 535 return ret; 536 537 gpio_regmap.parent = dev; 538 gpio_regmap.regmap = st->reg_gpiocon_regmap; 539 gpio_regmap.ngpio = st->info->num_gpios; 540 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 541 if (st->info->higher_gpio_bits) 542 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate; 543 else 544 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 545 546 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 547 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 548 if (ret) 549 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 550 551 return 0; 552 } 553 #else 554 static int ad7173_gpio_init(struct ad7173_state *st) 555 { 556 return 0; 557 } 558 #endif /* CONFIG_GPIOLIB */ 559 560 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 561 { 562 return container_of(sd, struct ad7173_state, sd); 563 } 564 565 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 566 { 567 return container_of(hw, struct ad7173_state, int_clk_hw); 568 } 569 570 static void ad7173_ida_destroy(void *data) 571 { 572 struct ad7173_state *st = data; 573 574 ida_destroy(&st->cfg_slots_status); 575 } 576 577 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 578 { 579 memset64(st->config_cnts, 0, st->info->num_configs); 580 st->config_usage_counter = 0; 581 } 582 583 static struct ad7173_channel_config * 584 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 585 { 586 struct ad7173_channel_config *cfg_aux; 587 ptrdiff_t cmp_size; 588 int i; 589 590 cmp_size = sizeof_field(struct ad7173_channel_config, config_props); 591 for (i = 0; i < st->num_channels; i++) { 592 cfg_aux = &st->channels[i].cfg; 593 594 if (cfg_aux->live && 595 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size)) 596 return cfg_aux; 597 } 598 return NULL; 599 } 600 601 /* Could be replaced with a generic LRU implementation */ 602 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 603 { 604 int i, lru_position = 0; 605 606 for (i = 1; i < st->info->num_configs; i++) 607 if (st->config_cnts[i] < st->config_cnts[lru_position]) 608 lru_position = i; 609 610 for (i = 0; i < st->num_channels; i++) 611 if (st->channels[i].cfg.cfg_slot == lru_position) 612 st->channels[i].cfg.live = false; 613 614 ida_free(&st->cfg_slots_status, lru_position); 615 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 616 } 617 618 /* Could be replaced with a generic LRU implementation */ 619 static int ad7173_load_config(struct ad7173_state *st, 620 struct ad7173_channel_config *cfg) 621 { 622 unsigned int config; 623 int free_cfg_slot, ret; 624 625 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 626 st->info->num_configs - 1, GFP_KERNEL); 627 if (free_cfg_slot < 0) 628 free_cfg_slot = ad7173_free_config_slot_lru(st); 629 630 cfg->cfg_slot = free_cfg_slot; 631 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 632 633 if (cfg->bipolar) 634 config |= AD7173_SETUP_BIPOLAR; 635 636 if (cfg->input_buf) 637 config |= AD7173_SETUP_AIN_BUF_MASK; 638 639 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 640 if (ret) 641 return ret; 642 643 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 644 AD7173_FILTER_ODR0_MASK & cfg->odr); 645 } 646 647 static int ad7173_config_channel(struct ad7173_state *st, int addr) 648 { 649 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 650 struct ad7173_channel_config *live_cfg; 651 int ret; 652 653 if (!cfg->live) { 654 live_cfg = ad7173_find_live_config(st, cfg); 655 if (live_cfg) { 656 cfg->cfg_slot = live_cfg->cfg_slot; 657 } else { 658 ret = ad7173_load_config(st, cfg); 659 if (ret) 660 return ret; 661 cfg->live = true; 662 } 663 } 664 665 if (st->config_usage_counter == U64_MAX) 666 ad7173_reset_usage_cnts(st); 667 668 st->config_usage_counter++; 669 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 670 671 return 0; 672 } 673 674 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 675 { 676 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 677 unsigned int val; 678 int ret; 679 680 ret = ad7173_config_channel(st, channel); 681 if (ret) 682 return ret; 683 684 val = AD7173_CH_ENABLE | 685 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 686 st->channels[channel].ain; 687 688 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 689 } 690 691 static int ad7173_set_mode(struct ad_sigma_delta *sd, 692 enum ad_sigma_delta_mode mode) 693 { 694 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 695 696 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 697 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 698 699 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 700 } 701 702 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 703 { 704 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 705 unsigned int interface_mode = st->interface_mode; 706 int ret; 707 708 interface_mode &= ~AD7173_INTERFACE_DATA_STAT; 709 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 710 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 711 if (ret) 712 return ret; 713 714 st->interface_mode = interface_mode; 715 716 return 0; 717 } 718 719 static int ad7173_disable_all(struct ad_sigma_delta *sd) 720 { 721 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 722 int ret; 723 int i; 724 725 for (i = 0; i < st->num_channels; i++) { 726 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 727 if (ret < 0) 728 return ret; 729 } 730 731 return 0; 732 } 733 734 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 735 { 736 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0); 737 } 738 739 static struct ad_sigma_delta_info ad7173_sigma_delta_info = { 740 .set_channel = ad7173_set_channel, 741 .append_status = ad7173_append_status, 742 .disable_all = ad7173_disable_all, 743 .disable_one = ad7173_disable_one, 744 .set_mode = ad7173_set_mode, 745 .has_registers = true, 746 .addr_shift = 0, 747 .read_mask = BIT(6), 748 .status_ch_mask = GENMASK(3, 0), 749 .data_reg = AD7173_REG_DATA, 750 }; 751 752 static int ad7173_setup(struct iio_dev *indio_dev) 753 { 754 struct ad7173_state *st = iio_priv(indio_dev); 755 struct device *dev = &st->sd.spi->dev; 756 u8 buf[AD7173_RESET_LENGTH]; 757 unsigned int id; 758 int ret; 759 760 /* reset the serial interface */ 761 memset(buf, 0xff, AD7173_RESET_LENGTH); 762 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 763 if (ret < 0) 764 return ret; 765 766 /* datasheet recommends a delay of at least 500us after reset */ 767 fsleep(500); 768 769 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 770 if (ret) 771 return ret; 772 773 id &= AD7173_ID_MASK; 774 if (id != st->info->id) 775 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 776 id, st->info->id); 777 778 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 779 st->interface_mode = 0x0; 780 781 st->config_usage_counter = 0; 782 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 783 sizeof(*st->config_cnts), GFP_KERNEL); 784 if (!st->config_cnts) 785 return -ENOMEM; 786 787 /* All channels are enabled by default after a reset */ 788 return ad7173_disable_all(&st->sd); 789 } 790 791 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 792 u8 reference_select) 793 { 794 int vref; 795 796 switch (reference_select) { 797 case AD7173_SETUP_REF_SEL_EXT_REF: 798 vref = regulator_get_voltage(st->regulators[0].consumer); 799 break; 800 801 case AD7173_SETUP_REF_SEL_EXT_REF2: 802 vref = regulator_get_voltage(st->regulators[1].consumer); 803 break; 804 805 case AD7173_SETUP_REF_SEL_INT_REF: 806 vref = AD7173_VOLTAGE_INT_REF_uV; 807 break; 808 809 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 810 vref = regulator_get_voltage(st->regulators[2].consumer); 811 break; 812 813 default: 814 return -EINVAL; 815 } 816 817 if (vref < 0) 818 return vref; 819 820 return vref / (MICRO / MILLI); 821 } 822 823 static int ad7173_read_raw(struct iio_dev *indio_dev, 824 struct iio_chan_spec const *chan, 825 int *val, int *val2, long info) 826 { 827 struct ad7173_state *st = iio_priv(indio_dev); 828 struct ad7173_channel *ch = &st->channels[chan->address]; 829 unsigned int reg; 830 u64 temp; 831 int ret; 832 833 switch (info) { 834 case IIO_CHAN_INFO_RAW: 835 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 836 if (ret < 0) 837 return ret; 838 839 return IIO_VAL_INT; 840 case IIO_CHAN_INFO_SCALE: 841 842 switch (chan->type) { 843 case IIO_TEMP: 844 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 845 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 846 *val = temp; 847 *val2 = chan->scan_type.realbits; 848 return IIO_VAL_FRACTIONAL_LOG2; 849 case IIO_VOLTAGE: 850 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 851 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 852 853 if (chan->channel < st->info->num_voltage_in_div) 854 *val *= AD4111_DIVIDER_RATIO; 855 return IIO_VAL_FRACTIONAL_LOG2; 856 case IIO_CURRENT: 857 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 858 *val /= AD4111_SHUNT_RESISTOR_OHM; 859 *val2 = chan->scan_type.realbits - ch->cfg.bipolar; 860 return IIO_VAL_FRACTIONAL_LOG2; 861 default: 862 return -EINVAL; 863 } 864 case IIO_CHAN_INFO_OFFSET: 865 866 switch (chan->type) { 867 case IIO_TEMP: 868 /* 0 Kelvin -> raw sample */ 869 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 870 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 871 temp <<= chan->scan_type.realbits; 872 temp = DIV_U64_ROUND_CLOSEST(temp, 873 AD7173_VOLTAGE_INT_REF_uV * 874 MILLI); 875 *val = -temp; 876 return IIO_VAL_INT; 877 case IIO_VOLTAGE: 878 case IIO_CURRENT: 879 *val = -BIT(chan->scan_type.realbits - 1); 880 return IIO_VAL_INT; 881 default: 882 return -EINVAL; 883 } 884 case IIO_CHAN_INFO_SAMP_FREQ: 885 reg = st->channels[chan->address].cfg.odr; 886 887 *val = st->info->sinc5_data_rates[reg] / MILLI; 888 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 889 890 return IIO_VAL_INT_PLUS_MICRO; 891 default: 892 return -EINVAL; 893 } 894 } 895 896 static int ad7173_write_raw(struct iio_dev *indio_dev, 897 struct iio_chan_spec const *chan, 898 int val, int val2, long info) 899 { 900 struct ad7173_state *st = iio_priv(indio_dev); 901 struct ad7173_channel_config *cfg; 902 unsigned int freq, i; 903 int ret; 904 905 ret = iio_device_claim_direct_mode(indio_dev); 906 if (ret) 907 return ret; 908 909 switch (info) { 910 /* 911 * This attribute sets the sampling frequency for each channel individually. 912 * There are no issues for raw or buffered reads of an individual channel. 913 * 914 * When multiple channels are enabled in buffered mode, the effective 915 * sampling rate of a channel is lowered in correlation to the number 916 * of channels enabled and the sampling rate of the other channels. 917 * 918 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps 919 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3 920 * will take 100ms each. 921 * 922 * This will cause the reading of CH1 to be actually done once every 923 * 200.16ms, an effective rate of 4.99sps. 924 */ 925 case IIO_CHAN_INFO_SAMP_FREQ: 926 freq = val * MILLI + val2 / MILLI; 927 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 928 if (freq >= st->info->sinc5_data_rates[i]) 929 break; 930 931 cfg = &st->channels[chan->address].cfg; 932 cfg->odr = i; 933 cfg->live = false; 934 break; 935 936 default: 937 ret = -EINVAL; 938 break; 939 } 940 941 iio_device_release_direct_mode(indio_dev); 942 return ret; 943 } 944 945 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 946 const unsigned long *scan_mask) 947 { 948 struct ad7173_state *st = iio_priv(indio_dev); 949 int i, ret; 950 951 for (i = 0; i < indio_dev->num_channels; i++) { 952 if (test_bit(i, scan_mask)) 953 ret = ad7173_set_channel(&st->sd, i); 954 else 955 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 956 if (ret < 0) 957 return ret; 958 } 959 960 return 0; 961 } 962 963 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 964 unsigned int writeval, unsigned int *readval) 965 { 966 struct ad7173_state *st = iio_priv(indio_dev); 967 u8 reg_size; 968 969 if (reg == AD7173_REG_COMMS) 970 reg_size = 1; 971 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 972 reg >= AD7173_REG_OFFSET(0)) 973 reg_size = 3; 974 else 975 reg_size = 2; 976 977 if (readval) 978 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 979 980 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 981 } 982 983 static const struct iio_info ad7173_info = { 984 .read_raw = &ad7173_read_raw, 985 .write_raw = &ad7173_write_raw, 986 .debugfs_reg_access = &ad7173_debug_reg_access, 987 .validate_trigger = ad_sd_validate_trigger, 988 .update_scan_mode = ad7173_update_scan_mode, 989 }; 990 991 static const struct iio_chan_spec ad7173_channel_template = { 992 .type = IIO_VOLTAGE, 993 .indexed = 1, 994 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 995 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 996 .scan_type = { 997 .sign = 'u', 998 .realbits = 24, 999 .storagebits = 32, 1000 .endianness = IIO_BE, 1001 }, 1002 }; 1003 1004 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 1005 .type = IIO_TEMP, 1006 .channel = AD7173_AIN_TEMP_POS, 1007 .channel2 = AD7173_AIN_TEMP_NEG, 1008 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1009 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1010 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1011 .scan_type = { 1012 .sign = 'u', 1013 .realbits = 24, 1014 .storagebits = 32, 1015 .endianness = IIO_BE, 1016 }, 1017 }; 1018 1019 static void ad7173_disable_regulators(void *data) 1020 { 1021 struct ad7173_state *st = data; 1022 1023 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1024 } 1025 1026 static void ad7173_clk_disable_unprepare(void *clk) 1027 { 1028 clk_disable_unprepare(clk); 1029 } 1030 1031 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 1032 unsigned int clk_sel) 1033 { 1034 int ret; 1035 1036 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 1037 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 1038 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 1039 1040 return ret; 1041 } 1042 1043 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 1044 unsigned long parent_rate) 1045 { 1046 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1047 1048 return st->info->clock / HZ_PER_KHZ; 1049 } 1050 1051 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 1052 { 1053 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1054 u32 clk_sel; 1055 1056 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 1057 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 1058 } 1059 1060 static int ad7173_clk_output_prepare(struct clk_hw *hw) 1061 { 1062 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1063 1064 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 1065 } 1066 1067 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 1068 { 1069 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1070 1071 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 1072 } 1073 1074 static const struct clk_ops ad7173_int_clk_ops = { 1075 .recalc_rate = ad7173_clk_recalc_rate, 1076 .is_enabled = ad7173_clk_output_is_enabled, 1077 .prepare = ad7173_clk_output_prepare, 1078 .unprepare = ad7173_clk_output_unprepare, 1079 }; 1080 1081 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 1082 { 1083 struct ad7173_state *st = iio_priv(indio_dev); 1084 struct device *dev = indio_dev->dev.parent; 1085 struct fwnode_handle *fwnode = dev_fwnode(dev); 1086 struct clk_init_data init = {}; 1087 int ret; 1088 1089 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1090 return 0; 1091 1092 init.name = fwnode_get_name(fwnode); 1093 init.ops = &ad7173_int_clk_ops; 1094 1095 st->int_clk_hw.init = &init; 1096 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 1097 if (ret) 1098 return ret; 1099 1100 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1101 &st->int_clk_hw); 1102 } 1103 1104 static int ad4111_validate_current_ain(struct ad7173_state *st, 1105 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL]) 1106 { 1107 struct device *dev = &st->sd.spi->dev; 1108 1109 if (!st->info->has_current_inputs) 1110 return dev_err_probe(dev, -EINVAL, 1111 "Model %s does not support current channels\n", 1112 st->info->name); 1113 1114 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config)) 1115 return dev_err_probe(dev, -EINVAL, 1116 "For current channels single-channel must be <[0-3]>\n"); 1117 1118 return 0; 1119 } 1120 1121 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st, 1122 unsigned int ain0, unsigned int ain1) 1123 { 1124 struct device *dev = &st->sd.spi->dev; 1125 bool special_input0, special_input1; 1126 1127 /* (AVDD1-AVSS)/5 power supply monitoring */ 1128 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG && 1129 st->info->has_pow_supply_monitoring) 1130 return 0; 1131 1132 special_input0 = AD7173_IS_REF_INPUT(ain0) || 1133 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1134 special_input1 = AD7173_IS_REF_INPUT(ain1) || 1135 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1136 1137 if ((ain0 >= st->info->num_voltage_in && !special_input0) || 1138 (ain1 >= st->info->num_voltage_in && !special_input1)) { 1139 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT) 1140 return dev_err_probe(dev, -EINVAL, 1141 "VINCOM not supported for %s\n", st->info->name); 1142 1143 return dev_err_probe(dev, -EINVAL, 1144 "Input pin number out of range for pair (%d %d).\n", 1145 ain0, ain1); 1146 } 1147 1148 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) || 1149 AD4111_IS_VINCOM_MISMATCH(ain1, ain0)) 1150 return dev_err_probe(dev, -EINVAL, 1151 "VINCOM must be paired with inputs having divider.\n"); 1152 1153 if (!special_input0 && !special_input1 && 1154 ((ain0 >= st->info->num_voltage_in_div) != 1155 (ain1 >= st->info->num_voltage_in_div))) 1156 return dev_err_probe(dev, -EINVAL, 1157 "Both inputs must either have a voltage divider or not have: (%d %d).\n", 1158 ain0, ain1); 1159 1160 return 0; 1161 } 1162 1163 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel) 1164 { 1165 struct device *dev = &st->sd.spi->dev; 1166 int ret; 1167 1168 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref) 1169 return dev_err_probe(dev, -EINVAL, 1170 "Internal reference is not available on current model.\n"); 1171 1172 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 1173 return dev_err_probe(dev, -EINVAL, 1174 "External reference 2 is not available on current model.\n"); 1175 1176 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 1177 if (ret < 0) 1178 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1179 ref_sel); 1180 1181 return 0; 1182 } 1183 1184 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 1185 { 1186 struct ad7173_channel *chans_st_arr, *chan_st_priv; 1187 struct ad7173_state *st = iio_priv(indio_dev); 1188 struct device *dev = indio_dev->dev.parent; 1189 struct iio_chan_spec *chan_arr, *chan; 1190 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0; 1191 int ref_sel, ret, num_channels; 1192 1193 num_channels = device_get_child_node_count(dev); 1194 1195 if (st->info->has_temp) 1196 num_channels++; 1197 1198 if (num_channels == 0) 1199 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1200 1201 if (num_channels > st->info->num_channels) 1202 return dev_err_probe(dev, -EINVAL, 1203 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n", 1204 st->info->num_channels); 1205 1206 indio_dev->num_channels = num_channels; 1207 st->num_channels = num_channels; 1208 1209 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 1210 st->num_channels, GFP_KERNEL); 1211 if (!chan_arr) 1212 return -ENOMEM; 1213 1214 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 1215 GFP_KERNEL); 1216 if (!chans_st_arr) 1217 return -ENOMEM; 1218 1219 indio_dev->channels = chan_arr; 1220 st->channels = chans_st_arr; 1221 1222 if (st->info->has_temp) { 1223 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 1224 chan_st_priv = &chans_st_arr[chan_index]; 1225 chan_st_priv->ain = 1226 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 1227 chan_arr[chan_index].channel2); 1228 chan_st_priv->cfg.bipolar = false; 1229 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1230 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1231 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1232 1233 chan_index++; 1234 } 1235 1236 device_for_each_child_node_scoped(dev, child) { 1237 bool is_current_chan = false; 1238 1239 chan = &chan_arr[chan_index]; 1240 *chan = ad7173_channel_template; 1241 chan_st_priv = &chans_st_arr[chan_index]; 1242 ret = fwnode_property_read_u32_array(child, "diff-channels", 1243 ain, ARRAY_SIZE(ain)); 1244 if (ret) { 1245 ret = fwnode_property_read_u32(child, "single-channel", 1246 ain); 1247 if (ret) 1248 return dev_err_probe(dev, ret, 1249 "Channel must define one of diff-channels or single-channel.\n"); 1250 1251 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel"); 1252 } else { 1253 chan->differential = true; 1254 } 1255 1256 if (is_current_chan) { 1257 ret = ad4111_validate_current_ain(st, ain); 1258 if (ret) 1259 return ret; 1260 } else { 1261 if (!chan->differential) { 1262 ret = fwnode_property_read_u32(child, 1263 "common-mode-channel", ain + 1); 1264 if (ret) 1265 return dev_err_probe(dev, ret, 1266 "common-mode-channel must be defined for single-ended channels.\n"); 1267 } 1268 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]); 1269 if (ret) 1270 return ret; 1271 } 1272 1273 ret = fwnode_property_match_property_string(child, 1274 "adi,reference-select", 1275 ad7173_ref_sel_str, 1276 ARRAY_SIZE(ad7173_ref_sel_str)); 1277 if (ret < 0) 1278 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1279 else 1280 ref_sel = ret; 1281 1282 ret = ad7173_validate_reference(st, ref_sel); 1283 if (ret) 1284 return ret; 1285 1286 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 1287 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1288 chan_st_priv->cfg.ref_sel = ref_sel; 1289 1290 chan->address = chan_index; 1291 chan->scan_index = chan_index; 1292 chan->channel = ain[0]; 1293 chan_st_priv->chan_reg = chan_index; 1294 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1295 chan_st_priv->cfg.odr = 0; 1296 1297 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 1298 if (chan_st_priv->cfg.bipolar) 1299 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 1300 1301 if (is_current_chan) { 1302 chan->type = IIO_CURRENT; 1303 chan->differential = false; 1304 chan->channel2 = 0; 1305 chan_st_priv->ain = ad4111_current_channel_config[ain[0]]; 1306 } else { 1307 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1308 chan->channel2 = ain[1]; 1309 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 1310 } 1311 1312 chan_index++; 1313 } 1314 return 0; 1315 } 1316 1317 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1318 { 1319 struct ad7173_state *st = iio_priv(indio_dev); 1320 struct device *dev = indio_dev->dev.parent; 1321 int ret; 1322 1323 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1324 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1325 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1326 1327 /* 1328 * If a regulator is not available, it will be set to a dummy regulator. 1329 * Each channel reference is checked with regulator_get_voltage() before 1330 * setting attributes so if any channel uses a dummy supply the driver 1331 * probe will fail. 1332 */ 1333 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1334 st->regulators); 1335 if (ret) 1336 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1337 1338 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1339 if (ret) 1340 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1341 1342 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1343 if (ret) 1344 return dev_err_probe(dev, ret, 1345 "Failed to add regulators disable action\n"); 1346 1347 ret = device_property_match_property_string(dev, "clock-names", 1348 ad7173_clk_sel, 1349 ARRAY_SIZE(ad7173_clk_sel)); 1350 if (ret < 0) { 1351 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1352 AD7173_ADC_MODE_CLOCKSEL_INT); 1353 ad7173_register_clk_provider(indio_dev); 1354 } else { 1355 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1356 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1357 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]); 1358 if (IS_ERR(st->ext_clk)) 1359 return dev_err_probe(dev, PTR_ERR(st->ext_clk), 1360 "Failed to get external clock\n"); 1361 1362 ret = clk_prepare_enable(st->ext_clk); 1363 if (ret) 1364 return dev_err_probe(dev, ret, 1365 "Failed to enable external clock\n"); 1366 1367 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare, 1368 st->ext_clk); 1369 if (ret) 1370 return ret; 1371 } 1372 1373 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy"); 1374 if (ret < 0) 1375 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n"); 1376 1377 ad7173_sigma_delta_info.irq_line = ret; 1378 1379 return ad7173_fw_parse_channel_config(indio_dev); 1380 } 1381 1382 static int ad7173_probe(struct spi_device *spi) 1383 { 1384 struct device *dev = &spi->dev; 1385 struct ad7173_state *st; 1386 struct iio_dev *indio_dev; 1387 int ret; 1388 1389 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1390 if (!indio_dev) 1391 return -ENOMEM; 1392 1393 st = iio_priv(indio_dev); 1394 st->info = spi_get_device_match_data(spi); 1395 if (!st->info) 1396 return -ENODEV; 1397 1398 ida_init(&st->cfg_slots_status); 1399 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1400 if (ret) 1401 return ret; 1402 1403 indio_dev->name = st->info->name; 1404 indio_dev->modes = INDIO_DIRECT_MODE; 1405 indio_dev->info = &ad7173_info; 1406 1407 spi->mode = SPI_MODE_3; 1408 spi_setup(spi); 1409 1410 ad7173_sigma_delta_info.num_slots = st->info->num_configs; 1411 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7173_sigma_delta_info); 1412 if (ret) 1413 return ret; 1414 1415 ret = ad7173_fw_parse_device_config(indio_dev); 1416 if (ret) 1417 return ret; 1418 1419 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1420 if (ret) 1421 return ret; 1422 1423 ret = ad7173_setup(indio_dev); 1424 if (ret) 1425 return ret; 1426 1427 ret = devm_iio_device_register(dev, indio_dev); 1428 if (ret) 1429 return ret; 1430 1431 if (IS_ENABLED(CONFIG_GPIOLIB)) 1432 return ad7173_gpio_init(st); 1433 1434 return 0; 1435 } 1436 1437 static const struct of_device_id ad7173_of_match[] = { 1438 { .compatible = "ad4111", .data = &ad4111_device_info }, 1439 { .compatible = "ad4112", .data = &ad4112_device_info }, 1440 { .compatible = "ad4114", .data = &ad4114_device_info }, 1441 { .compatible = "ad4115", .data = &ad4115_device_info }, 1442 { .compatible = "ad4116", .data = &ad4116_device_info }, 1443 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info }, 1444 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info }, 1445 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info }, 1446 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info }, 1447 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info }, 1448 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info }, 1449 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info }, 1450 { } 1451 }; 1452 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1453 1454 static const struct spi_device_id ad7173_id_table[] = { 1455 { "ad4111", (kernel_ulong_t)&ad4111_device_info }, 1456 { "ad4112", (kernel_ulong_t)&ad4112_device_info }, 1457 { "ad4114", (kernel_ulong_t)&ad4114_device_info }, 1458 { "ad4115", (kernel_ulong_t)&ad4115_device_info }, 1459 { "ad4116", (kernel_ulong_t)&ad4116_device_info }, 1460 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info }, 1461 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info }, 1462 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info }, 1463 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info }, 1464 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info }, 1465 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info }, 1466 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info }, 1467 { } 1468 }; 1469 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1470 1471 static struct spi_driver ad7173_driver = { 1472 .driver = { 1473 .name = "ad7173", 1474 .of_match_table = ad7173_of_match, 1475 }, 1476 .probe = ad7173_probe, 1477 .id_table = ad7173_id_table, 1478 }; 1479 module_spi_driver(ad7173_driver); 1480 1481 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1482 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1483 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1484 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver"); 1485 MODULE_LICENSE("GPL"); 1486