1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x and AD411x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116 7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 8 * AD7175-8/AD7176-2/AD7177-2 9 * 10 * Copyright (C) 2015, 2024 Analog Devices, Inc. 11 */ 12 13 #include <linux/array_size.h> 14 #include <linux/bitfield.h> 15 #include <linux/bitmap.h> 16 #include <linux/container_of.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/gpio/regmap.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/math64.h> 27 #include <linux/module.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/spi/spi.h> 34 #include <linux/types.h> 35 #include <linux/units.h> 36 37 #include <linux/iio/buffer.h> 38 #include <linux/iio/events.h> 39 #include <linux/iio/iio.h> 40 #include <linux/iio/trigger_consumer.h> 41 #include <linux/iio/triggered_buffer.h> 42 43 #include <linux/iio/adc/ad_sigma_delta.h> 44 45 #define AD7173_REG_COMMS 0x00 46 #define AD7173_REG_ADC_MODE 0x01 47 #define AD7173_REG_INTERFACE_MODE 0x02 48 #define AD7173_REG_CRC 0x03 49 #define AD7173_REG_DATA 0x04 50 #define AD7173_REG_GPIO 0x06 51 #define AD7173_REG_ID 0x07 52 #define AD7173_REG_CH(x) (0x10 + (x)) 53 #define AD7173_REG_SETUP(x) (0x20 + (x)) 54 #define AD7173_REG_FILTER(x) (0x28 + (x)) 55 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 56 #define AD7173_REG_GAIN(x) (0x38 + (x)) 57 58 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 59 60 #define AD7173_CH_ENABLE BIT(15) 61 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 62 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 63 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 64 65 #define AD7173_NO_AINS_PER_CHANNEL 2 66 #define AD7173_CH_ADDRESS(pos, neg) \ 67 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 68 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 69 #define AD7173_AIN_TEMP_POS 17 70 #define AD7173_AIN_TEMP_NEG 18 71 #define AD7173_AIN_POW_MON_POS 19 72 #define AD7173_AIN_POW_MON_NEG 20 73 #define AD7173_AIN_REF_POS 21 74 #define AD7173_AIN_REF_NEG 22 75 76 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \ 77 (x) == AD7173_AIN_REF_NEG) 78 79 #define AD7172_2_ID 0x00d0 80 #define AD7176_ID 0x0c90 81 #define AD7175_ID 0x0cd0 82 #define AD7175_2_ID 0x0cd0 83 #define AD7172_4_ID 0x2050 84 #define AD7173_ID 0x30d0 85 #define AD4111_ID AD7173_ID 86 #define AD4112_ID AD7173_ID 87 #define AD4114_ID AD7173_ID 88 #define AD4113_ID 0x31d0 89 #define AD4116_ID 0x34d0 90 #define AD4115_ID 0x38d0 91 #define AD7175_8_ID 0x3cd0 92 #define AD7177_ID 0x4fd0 93 #define AD7173_ID_MASK GENMASK(15, 4) 94 95 #define AD7173_ADC_MODE_REF_EN BIT(15) 96 #define AD7173_ADC_MODE_SING_CYC BIT(13) 97 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 98 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 99 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 100 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 101 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 102 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 103 104 #define AD7173_GPIO_PDSW BIT(14) 105 #define AD7173_GPIO_OP_EN2_3 BIT(13) 106 #define AD4111_GPIO_GP_OW_EN BIT(12) 107 #define AD7173_GPIO_MUX_IO BIT(12) 108 #define AD7173_GPIO_SYNC_EN BIT(11) 109 #define AD7173_GPIO_ERR_EN BIT(10) 110 #define AD7173_GPIO_ERR_DAT BIT(9) 111 #define AD7173_GPIO_GP_DATA3 BIT(7) 112 #define AD7173_GPIO_GP_DATA2 BIT(6) 113 #define AD7173_GPIO_IP_EN1 BIT(5) 114 #define AD7173_GPIO_IP_EN0 BIT(4) 115 #define AD7173_GPIO_OP_EN1 BIT(3) 116 #define AD7173_GPIO_OP_EN0 BIT(2) 117 #define AD7173_GPIO_GP_DATA1 BIT(1) 118 #define AD7173_GPIO_GP_DATA0 BIT(0) 119 120 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 121 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 122 #define AD4111_GPO01_DATA(x) BIT((x) + 6) 123 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 124 125 #define AD7173_INTERFACE_DATA_STAT BIT(6) 126 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 127 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 128 129 #define AD7173_SETUP_BIPOLAR BIT(12) 130 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 131 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 132 133 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 134 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 135 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 136 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 137 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 138 #define AD7173_VOLTAGE_INT_REF_uV 2500000 139 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 140 #define AD7177_ODR_START_VALUE 0x07 141 #define AD4111_SHUNT_RESISTOR_OHM 50 142 #define AD4111_DIVIDER_RATIO 10 143 #define AD4111_CURRENT_CHAN_CUTOFF 16 144 #define AD4111_VINCOM_INPUT 0x10 145 146 /* pin < num_voltage_in is a normal voltage input */ 147 /* pin >= num_voltage_in_div is a voltage input without a divider */ 148 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \ 149 (pin2) < st->info->num_voltage_in && \ 150 (pin2) >= st->info->num_voltage_in_div) 151 152 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 153 #define AD7173_MAX_CONFIGS 8 154 #define AD4111_OW_DET_THRSH_MV 300 155 156 #define AD7173_MODE_CAL_INT_ZERO 0x4 /* Internal Zero-Scale Calibration */ 157 #define AD7173_MODE_CAL_INT_FULL 0x5 /* Internal Full-Scale Calibration */ 158 #define AD7173_MODE_CAL_SYS_ZERO 0x6 /* System Zero-Scale Calibration */ 159 #define AD7173_MODE_CAL_SYS_FULL 0x7 /* System Full-Scale Calibration */ 160 161 struct ad7173_device_info { 162 const unsigned int *sinc5_data_rates; 163 unsigned int num_sinc5_data_rates; 164 unsigned int odr_start_value; 165 /* 166 * AD4116 has both inputs with a voltage divider and without. 167 * These inputs cannot be mixed in the channel configuration. 168 * Does not include the VINCOM input. 169 */ 170 unsigned int num_voltage_in_div; 171 unsigned int num_channels; 172 unsigned int num_configs; 173 unsigned int num_voltage_in; 174 unsigned int clock; 175 unsigned int id; 176 char *name; 177 const struct ad_sigma_delta_info *sd_info; 178 bool has_current_inputs; 179 bool has_vincom_input; 180 bool has_temp; 181 /* ((AVDD1 − AVSS)/5) */ 182 bool has_pow_supply_monitoring; 183 bool data_reg_only_16bit; 184 bool has_input_buf; 185 bool has_int_ref; 186 bool has_ref2; 187 bool has_internal_fs_calibration; 188 bool has_openwire_det; 189 bool higher_gpio_bits; 190 u8 num_gpios; 191 }; 192 193 struct ad7173_channel_config { 194 /* Openwire detection threshold */ 195 unsigned int openwire_thrsh_raw; 196 int openwire_comp_chan; 197 u8 cfg_slot; 198 bool live; 199 200 /* 201 * Following fields are used to compare equality. If you 202 * make adaptations in it, you most likely also have to adapt 203 * ad7173_find_live_config(), too. 204 */ 205 struct_group(config_props, 206 bool bipolar; 207 bool input_buf; 208 u8 odr; 209 u8 ref_sel; 210 ); 211 }; 212 213 struct ad7173_channel { 214 unsigned int ain; 215 struct ad7173_channel_config cfg; 216 u8 syscalib_mode; 217 bool openwire_det_en; 218 }; 219 220 struct ad7173_state { 221 struct ad_sigma_delta sd; 222 const struct ad7173_device_info *info; 223 struct ad7173_channel *channels; 224 struct regulator_bulk_data regulators[3]; 225 unsigned int adc_mode; 226 unsigned int interface_mode; 227 unsigned int num_channels; 228 struct ida cfg_slots_status; 229 unsigned long long config_usage_counter; 230 unsigned long long *config_cnts; 231 struct clk_hw int_clk_hw; 232 struct regmap *reg_gpiocon_regmap; 233 struct gpio_regmap *gpio_regmap; 234 }; 235 236 static unsigned int ad4115_sinc5_data_rates[] = { 237 24845000, 24845000, 20725000, 20725000, /* 0-3 */ 238 15564000, 13841000, 10390000, 10390000, /* 4-7 */ 239 4994000, 2499000, 1000000, 500000, /* 8-11 */ 240 395500, 200000, 100000, 59890, /* 12-15 */ 241 49920, 20000, 16660, 10000, /* 16-19 */ 242 5000, 2500, 2500, /* 20-22 */ 243 }; 244 245 static unsigned int ad4116_sinc5_data_rates[] = { 246 12422360, 12422360, 12422360, 12422360, /* 0-3 */ 247 10362690, 10362690, 7782100, 6290530, /* 4-7 */ 248 5194800, 2496900, 1007600, 499900, /* 8-11 */ 249 390600, 200300, 100000, 59750, /* 12-15 */ 250 49840, 20000, 16650, 10000, /* 16-19 */ 251 5000, 2500, 1250, /* 20-22 */ 252 }; 253 254 static const unsigned int ad7173_sinc5_data_rates[] = { 255 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 256 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 257 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 258 }; 259 260 static const unsigned int ad7175_sinc5_data_rates[] = { 261 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 262 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 263 5000000, 2500000, 1000000, 500000, /* 8-11 */ 264 397500, 200000, 100000, 59920, /* 12-15 */ 265 49960, 20000, 16666, 10000, /* 16-19 */ 266 5000, /* 20 */ 267 }; 268 269 static unsigned int ad4111_current_channel_config[] = { 270 /* Ain sel: pos neg */ 271 0x1E8, /* 15:IIN0+ 8:IIN0− */ 272 0x1C9, /* 14:IIN1+ 9:IIN1− */ 273 0x1AA, /* 13:IIN2+ 10:IIN2− */ 274 0x18B, /* 12:IIN3+ 11:IIN3− */ 275 }; 276 277 static const char *const ad7173_ref_sel_str[] = { 278 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 279 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 280 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 281 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 282 }; 283 284 static const char *const ad7173_clk_sel[] = { 285 "ext-clk", "xtal" 286 }; 287 288 static const struct regmap_range ad7173_range_gpio[] = { 289 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 290 }; 291 292 static const struct regmap_access_table ad7173_access_table = { 293 .yes_ranges = ad7173_range_gpio, 294 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 295 }; 296 297 static const struct regmap_config ad7173_regmap_config = { 298 .reg_bits = 8, 299 .val_bits = 16, 300 .rd_table = &ad7173_access_table, 301 .wr_table = &ad7173_access_table, 302 .read_flag_mask = BIT(6), 303 }; 304 305 enum { 306 AD7173_SYSCALIB_ZERO_SCALE, 307 AD7173_SYSCALIB_FULL_SCALE, 308 }; 309 310 static const char * const ad7173_syscalib_modes[] = { 311 [AD7173_SYSCALIB_ZERO_SCALE] = "zero_scale", 312 [AD7173_SYSCALIB_FULL_SCALE] = "full_scale", 313 }; 314 315 static int ad7173_set_syscalib_mode(struct iio_dev *indio_dev, 316 const struct iio_chan_spec *chan, 317 unsigned int mode) 318 { 319 struct ad7173_state *st = iio_priv(indio_dev); 320 321 st->channels[chan->address].syscalib_mode = mode; 322 323 return 0; 324 } 325 326 static int ad7173_get_syscalib_mode(struct iio_dev *indio_dev, 327 const struct iio_chan_spec *chan) 328 { 329 struct ad7173_state *st = iio_priv(indio_dev); 330 331 return st->channels[chan->address].syscalib_mode; 332 } 333 334 static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev, 335 uintptr_t private, 336 const struct iio_chan_spec *chan, 337 const char *buf, size_t len) 338 { 339 struct ad7173_state *st = iio_priv(indio_dev); 340 bool sys_calib; 341 int ret, mode; 342 343 ret = kstrtobool(buf, &sys_calib); 344 if (ret) 345 return ret; 346 347 if (!iio_device_claim_direct(indio_dev)) 348 return -EBUSY; 349 350 mode = st->channels[chan->address].syscalib_mode; 351 if (sys_calib) { 352 if (mode == AD7173_SYSCALIB_ZERO_SCALE) 353 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO, 354 chan->address); 355 else 356 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_FULL, 357 chan->address); 358 } 359 360 iio_device_release_direct(indio_dev); 361 362 return ret ? : len; 363 } 364 365 static const struct iio_enum ad7173_syscalib_mode_enum = { 366 .items = ad7173_syscalib_modes, 367 .num_items = ARRAY_SIZE(ad7173_syscalib_modes), 368 .set = ad7173_set_syscalib_mode, 369 .get = ad7173_get_syscalib_mode 370 }; 371 372 static const struct iio_chan_spec_ext_info ad7173_calibsys_ext_info[] = { 373 { 374 .name = "sys_calibration", 375 .write = ad7173_write_syscalib, 376 .shared = IIO_SEPARATE, 377 }, 378 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 379 &ad7173_syscalib_mode_enum), 380 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 381 &ad7173_syscalib_mode_enum), 382 { } 383 }; 384 385 static int ad7173_calibrate_all(struct ad7173_state *st, struct iio_dev *indio_dev) 386 { 387 int ret; 388 int i; 389 390 for (i = 0; i < st->num_channels; i++) { 391 if (indio_dev->channels[i].type != IIO_VOLTAGE) 392 continue; 393 394 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, i); 395 if (ret < 0) 396 return ret; 397 398 if (st->info->has_internal_fs_calibration) { 399 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL, i); 400 if (ret < 0) 401 return ret; 402 } 403 } 404 405 return 0; 406 } 407 408 /* 409 * Associative array of channel pairs for open wire detection 410 * The array is indexed by ain and gives the associated channel pair 411 * to perform the open wire detection with 412 * the channel pair [0] is for non differential and pair [1] 413 * is for differential inputs 414 */ 415 static int openwire_ain_to_channel_pair[][2][2] = { 416 /* AIN Single Differential */ 417 [0] = { { 0, 15 }, { 1, 2 } }, 418 [1] = { { 1, 2 }, { 2, 1 } }, 419 [2] = { { 3, 4 }, { 5, 6 } }, 420 [3] = { { 5, 6 }, { 6, 5 } }, 421 [4] = { { 7, 8 }, { 9, 10 } }, 422 [5] = { { 9, 10 }, { 10, 9 } }, 423 [6] = { { 11, 12 }, { 13, 14 } }, 424 [7] = { { 13, 14 }, { 14, 13 } }, 425 }; 426 427 /* 428 * Openwire detection on ad4111 works by running the same input measurement 429 * on two different channels and compare if the difference between the two 430 * measurements exceeds a certain value (typical 300mV) 431 */ 432 static int ad4111_openwire_event(struct iio_dev *indio_dev, 433 const struct iio_chan_spec *chan) 434 { 435 struct ad7173_state *st = iio_priv(indio_dev); 436 struct ad7173_channel *adchan = &st->channels[chan->address]; 437 struct ad7173_channel_config *cfg = &adchan->cfg; 438 int ret, val1, val2; 439 440 ret = regmap_set_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 441 AD4111_GPIO_GP_OW_EN); 442 if (ret) 443 return ret; 444 445 adchan->cfg.openwire_comp_chan = 446 openwire_ain_to_channel_pair[chan->channel][chan->differential][0]; 447 448 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val1); 449 if (ret < 0) { 450 dev_err(&indio_dev->dev, 451 "Error running ad_sigma_delta single conversion: %d", ret); 452 goto out; 453 } 454 455 adchan->cfg.openwire_comp_chan = 456 openwire_ain_to_channel_pair[chan->channel][chan->differential][1]; 457 458 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val2); 459 if (ret < 0) { 460 dev_err(&indio_dev->dev, 461 "Error running ad_sigma_delta single conversion: %d", ret); 462 goto out; 463 } 464 465 if (abs(val1 - val2) > cfg->openwire_thrsh_raw) 466 iio_push_event(indio_dev, 467 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, chan->address, 468 IIO_EV_TYPE_FAULT, IIO_EV_DIR_FAULT_OPENWIRE), 469 iio_get_time_ns(indio_dev)); 470 471 out: 472 adchan->cfg.openwire_comp_chan = -1; 473 regmap_clear_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 474 AD4111_GPIO_GP_OW_EN); 475 return ret; 476 } 477 478 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 479 unsigned int offset, unsigned int *reg, 480 unsigned int *mask) 481 { 482 *mask = AD7173_GPO_DATA(offset); 483 *reg = base; 484 return 0; 485 } 486 487 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 488 unsigned int offset, unsigned int *reg, 489 unsigned int *mask) 490 { 491 *mask = AD4111_GPO01_DATA(offset); 492 *reg = base; 493 return 0; 494 } 495 496 static void ad7173_gpio_disable(void *data) 497 { 498 struct ad7173_state *st = data; 499 unsigned int mask; 500 501 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 502 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 503 } 504 505 static int ad7173_gpio_init(struct ad7173_state *st) 506 { 507 struct gpio_regmap_config gpio_regmap = {}; 508 struct device *dev = &st->sd.spi->dev; 509 unsigned int mask; 510 int ret; 511 512 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 513 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 514 if (ret) 515 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 516 517 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 518 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 519 520 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 521 if (ret) 522 return ret; 523 524 gpio_regmap.parent = dev; 525 gpio_regmap.regmap = st->reg_gpiocon_regmap; 526 gpio_regmap.ngpio = st->info->num_gpios; 527 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 528 if (st->info->higher_gpio_bits) 529 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate; 530 else 531 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 532 533 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 534 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 535 if (ret) 536 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 537 538 return 0; 539 } 540 541 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 542 { 543 return container_of(sd, struct ad7173_state, sd); 544 } 545 546 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 547 { 548 return container_of(hw, struct ad7173_state, int_clk_hw); 549 } 550 551 static void ad7173_ida_destroy(void *data) 552 { 553 struct ad7173_state *st = data; 554 555 ida_destroy(&st->cfg_slots_status); 556 } 557 558 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 559 { 560 memset64(st->config_cnts, 0, st->info->num_configs); 561 st->config_usage_counter = 0; 562 } 563 564 static struct ad7173_channel_config * 565 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 566 { 567 struct ad7173_channel_config *cfg_aux; 568 int i; 569 570 /* 571 * This is just to make sure that the comparison is adapted after 572 * struct ad7173_channel_config was changed. 573 */ 574 static_assert(sizeof_field(struct ad7173_channel_config, config_props) == 575 sizeof(struct { 576 bool bipolar; 577 bool input_buf; 578 u8 odr; 579 u8 ref_sel; 580 })); 581 582 for (i = 0; i < st->num_channels; i++) { 583 cfg_aux = &st->channels[i].cfg; 584 585 if (cfg_aux->live && 586 cfg->bipolar == cfg_aux->bipolar && 587 cfg->input_buf == cfg_aux->input_buf && 588 cfg->odr == cfg_aux->odr && 589 cfg->ref_sel == cfg_aux->ref_sel) 590 return cfg_aux; 591 } 592 return NULL; 593 } 594 595 /* Could be replaced with a generic LRU implementation */ 596 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 597 { 598 int i, lru_position = 0; 599 600 for (i = 1; i < st->info->num_configs; i++) 601 if (st->config_cnts[i] < st->config_cnts[lru_position]) 602 lru_position = i; 603 604 for (i = 0; i < st->num_channels; i++) 605 if (st->channels[i].cfg.cfg_slot == lru_position) 606 st->channels[i].cfg.live = false; 607 608 ida_free(&st->cfg_slots_status, lru_position); 609 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 610 } 611 612 /* Could be replaced with a generic LRU implementation */ 613 static int ad7173_load_config(struct ad7173_state *st, 614 struct ad7173_channel_config *cfg) 615 { 616 unsigned int config; 617 int free_cfg_slot, ret; 618 619 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 620 st->info->num_configs - 1, GFP_KERNEL); 621 if (free_cfg_slot < 0) 622 free_cfg_slot = ad7173_free_config_slot_lru(st); 623 624 cfg->cfg_slot = free_cfg_slot; 625 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 626 627 if (cfg->bipolar) 628 config |= AD7173_SETUP_BIPOLAR; 629 630 if (cfg->input_buf) 631 config |= AD7173_SETUP_AIN_BUF_MASK; 632 633 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 634 if (ret) 635 return ret; 636 637 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 638 AD7173_FILTER_ODR0_MASK & cfg->odr); 639 } 640 641 static int ad7173_config_channel(struct ad7173_state *st, int addr) 642 { 643 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 644 struct ad7173_channel_config *live_cfg; 645 int ret; 646 647 if (!cfg->live) { 648 live_cfg = ad7173_find_live_config(st, cfg); 649 if (live_cfg) { 650 cfg->cfg_slot = live_cfg->cfg_slot; 651 } else { 652 ret = ad7173_load_config(st, cfg); 653 if (ret) 654 return ret; 655 cfg->live = true; 656 } 657 } 658 659 if (st->config_usage_counter == U64_MAX) 660 ad7173_reset_usage_cnts(st); 661 662 st->config_usage_counter++; 663 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 664 665 return 0; 666 } 667 668 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 669 { 670 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 671 unsigned int val; 672 int ret; 673 674 ret = ad7173_config_channel(st, channel); 675 if (ret) 676 return ret; 677 678 val = AD7173_CH_ENABLE | 679 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 680 st->channels[channel].ain; 681 682 if (st->channels[channel].cfg.openwire_comp_chan >= 0) 683 channel = st->channels[channel].cfg.openwire_comp_chan; 684 685 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 686 } 687 688 static int ad7173_set_mode(struct ad_sigma_delta *sd, 689 enum ad_sigma_delta_mode mode) 690 { 691 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 692 693 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 694 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 695 696 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 697 } 698 699 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 700 { 701 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 702 unsigned int interface_mode = st->interface_mode; 703 int ret; 704 705 interface_mode &= ~AD7173_INTERFACE_DATA_STAT; 706 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 707 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 708 if (ret) 709 return ret; 710 711 st->interface_mode = interface_mode; 712 713 return 0; 714 } 715 716 static int ad7173_disable_all(struct ad_sigma_delta *sd) 717 { 718 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 719 int ret; 720 int i; 721 722 for (i = 0; i < st->num_channels; i++) { 723 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 724 if (ret < 0) 725 return ret; 726 } 727 728 return 0; 729 } 730 731 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 732 { 733 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 734 735 if (st->channels[chan].cfg.openwire_comp_chan >= 0) 736 chan = st->channels[chan].cfg.openwire_comp_chan; 737 738 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0); 739 } 740 741 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_4_slots = { 742 .set_channel = ad7173_set_channel, 743 .append_status = ad7173_append_status, 744 .disable_all = ad7173_disable_all, 745 .disable_one = ad7173_disable_one, 746 .set_mode = ad7173_set_mode, 747 .has_registers = true, 748 .has_named_irqs = true, 749 .addr_shift = 0, 750 .read_mask = BIT(6), 751 .status_ch_mask = GENMASK(3, 0), 752 .data_reg = AD7173_REG_DATA, 753 .num_resetclks = 64, 754 .num_slots = 4, 755 }; 756 757 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_8_slots = { 758 .set_channel = ad7173_set_channel, 759 .append_status = ad7173_append_status, 760 .disable_all = ad7173_disable_all, 761 .disable_one = ad7173_disable_one, 762 .set_mode = ad7173_set_mode, 763 .has_registers = true, 764 .has_named_irqs = true, 765 .addr_shift = 0, 766 .read_mask = BIT(6), 767 .status_ch_mask = GENMASK(3, 0), 768 .data_reg = AD7173_REG_DATA, 769 .num_resetclks = 64, 770 .num_slots = 8, 771 }; 772 773 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_16_slots = { 774 .set_channel = ad7173_set_channel, 775 .append_status = ad7173_append_status, 776 .disable_all = ad7173_disable_all, 777 .disable_one = ad7173_disable_one, 778 .set_mode = ad7173_set_mode, 779 .has_registers = true, 780 .has_named_irqs = true, 781 .addr_shift = 0, 782 .read_mask = BIT(6), 783 .status_ch_mask = GENMASK(3, 0), 784 .data_reg = AD7173_REG_DATA, 785 .num_resetclks = 64, 786 .num_slots = 16, 787 }; 788 789 static const struct ad7173_device_info ad4111_device_info = { 790 .name = "ad4111", 791 .id = AD4111_ID, 792 .sd_info = &ad7173_sigma_delta_info_16_slots, 793 .num_voltage_in_div = 8, 794 .num_channels = 16, 795 .num_configs = 8, 796 .num_voltage_in = 8, 797 .num_gpios = 2, 798 .higher_gpio_bits = true, 799 .has_temp = true, 800 .has_vincom_input = true, 801 .has_input_buf = true, 802 .has_current_inputs = true, 803 .has_int_ref = true, 804 .has_internal_fs_calibration = true, 805 .has_openwire_det = true, 806 .clock = 2 * HZ_PER_MHZ, 807 .sinc5_data_rates = ad7173_sinc5_data_rates, 808 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 809 }; 810 811 static const struct ad7173_device_info ad4112_device_info = { 812 .name = "ad4112", 813 .id = AD4112_ID, 814 .sd_info = &ad7173_sigma_delta_info_16_slots, 815 .num_voltage_in_div = 8, 816 .num_channels = 16, 817 .num_configs = 8, 818 .num_voltage_in = 8, 819 .num_gpios = 2, 820 .higher_gpio_bits = true, 821 .has_vincom_input = true, 822 .has_temp = true, 823 .has_input_buf = true, 824 .has_current_inputs = true, 825 .has_int_ref = true, 826 .has_internal_fs_calibration = true, 827 .clock = 2 * HZ_PER_MHZ, 828 .sinc5_data_rates = ad7173_sinc5_data_rates, 829 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 830 }; 831 832 static const struct ad7173_device_info ad4113_device_info = { 833 .name = "ad4113", 834 .id = AD4113_ID, 835 .sd_info = &ad7173_sigma_delta_info_16_slots, 836 .num_voltage_in_div = 8, 837 .num_channels = 16, 838 .num_configs = 8, 839 .num_voltage_in = 8, 840 .num_gpios = 2, 841 .data_reg_only_16bit = true, 842 .higher_gpio_bits = true, 843 .has_vincom_input = true, 844 .has_input_buf = true, 845 .has_int_ref = true, 846 .clock = 2 * HZ_PER_MHZ, 847 .sinc5_data_rates = ad7173_sinc5_data_rates, 848 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 849 }; 850 851 static const struct ad7173_device_info ad4114_device_info = { 852 .name = "ad4114", 853 .id = AD4114_ID, 854 .sd_info = &ad7173_sigma_delta_info_16_slots, 855 .num_voltage_in_div = 16, 856 .num_channels = 16, 857 .num_configs = 8, 858 .num_voltage_in = 16, 859 .num_gpios = 4, 860 .has_vincom_input = true, 861 .has_temp = true, 862 .has_input_buf = true, 863 .has_int_ref = true, 864 .has_internal_fs_calibration = true, 865 .clock = 2 * HZ_PER_MHZ, 866 .sinc5_data_rates = ad7173_sinc5_data_rates, 867 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 868 }; 869 870 static const struct ad7173_device_info ad4115_device_info = { 871 .name = "ad4115", 872 .id = AD4115_ID, 873 .sd_info = &ad7173_sigma_delta_info_16_slots, 874 .num_voltage_in_div = 16, 875 .num_channels = 16, 876 .num_configs = 8, 877 .num_voltage_in = 16, 878 .num_gpios = 4, 879 .has_vincom_input = true, 880 .has_temp = true, 881 .has_input_buf = true, 882 .has_int_ref = true, 883 .has_internal_fs_calibration = true, 884 .clock = 8 * HZ_PER_MHZ, 885 .sinc5_data_rates = ad4115_sinc5_data_rates, 886 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates), 887 }; 888 889 static const struct ad7173_device_info ad4116_device_info = { 890 .name = "ad4116", 891 .id = AD4116_ID, 892 .sd_info = &ad7173_sigma_delta_info_16_slots, 893 .num_voltage_in_div = 11, 894 .num_channels = 16, 895 .num_configs = 8, 896 .num_voltage_in = 16, 897 .num_gpios = 4, 898 .has_vincom_input = true, 899 .has_temp = true, 900 .has_input_buf = true, 901 .has_int_ref = true, 902 .has_internal_fs_calibration = true, 903 .clock = 4 * HZ_PER_MHZ, 904 .sinc5_data_rates = ad4116_sinc5_data_rates, 905 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates), 906 }; 907 908 static const struct ad7173_device_info ad7172_2_device_info = { 909 .name = "ad7172-2", 910 .id = AD7172_2_ID, 911 .sd_info = &ad7173_sigma_delta_info_4_slots, 912 .num_voltage_in = 5, 913 .num_channels = 4, 914 .num_configs = 4, 915 .num_gpios = 2, 916 .has_temp = true, 917 .has_input_buf = true, 918 .has_int_ref = true, 919 .has_pow_supply_monitoring = true, 920 .clock = 2 * HZ_PER_MHZ, 921 .sinc5_data_rates = ad7173_sinc5_data_rates, 922 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 923 }; 924 925 static const struct ad7173_device_info ad7172_4_device_info = { 926 .name = "ad7172-4", 927 .id = AD7172_4_ID, 928 .sd_info = &ad7173_sigma_delta_info_8_slots, 929 .num_voltage_in = 9, 930 .num_channels = 8, 931 .num_configs = 8, 932 .num_gpios = 4, 933 .has_input_buf = true, 934 .has_ref2 = true, 935 .has_pow_supply_monitoring = true, 936 .clock = 2 * HZ_PER_MHZ, 937 .sinc5_data_rates = ad7173_sinc5_data_rates, 938 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 939 }; 940 941 static const struct ad7173_device_info ad7173_8_device_info = { 942 .name = "ad7173-8", 943 .id = AD7173_ID, 944 .sd_info = &ad7173_sigma_delta_info_16_slots, 945 .num_voltage_in = 17, 946 .num_channels = 16, 947 .num_configs = 8, 948 .num_gpios = 4, 949 .has_temp = true, 950 .has_input_buf = true, 951 .has_int_ref = true, 952 .has_ref2 = true, 953 .clock = 2 * HZ_PER_MHZ, 954 .sinc5_data_rates = ad7173_sinc5_data_rates, 955 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 956 }; 957 958 static const struct ad7173_device_info ad7175_2_device_info = { 959 .name = "ad7175-2", 960 .id = AD7175_2_ID, 961 .sd_info = &ad7173_sigma_delta_info_4_slots, 962 .num_voltage_in = 5, 963 .num_channels = 4, 964 .num_configs = 4, 965 .num_gpios = 2, 966 .has_temp = true, 967 .has_input_buf = true, 968 .has_int_ref = true, 969 .has_pow_supply_monitoring = true, 970 .clock = 16 * HZ_PER_MHZ, 971 .sinc5_data_rates = ad7175_sinc5_data_rates, 972 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 973 }; 974 975 static const struct ad7173_device_info ad7175_8_device_info = { 976 .name = "ad7175-8", 977 .id = AD7175_8_ID, 978 .sd_info = &ad7173_sigma_delta_info_16_slots, 979 .num_voltage_in = 17, 980 .num_channels = 16, 981 .num_configs = 8, 982 .num_gpios = 4, 983 .has_temp = true, 984 .has_input_buf = true, 985 .has_int_ref = true, 986 .has_ref2 = true, 987 .has_pow_supply_monitoring = true, 988 .clock = 16 * HZ_PER_MHZ, 989 .sinc5_data_rates = ad7175_sinc5_data_rates, 990 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 991 }; 992 993 static const struct ad7173_device_info ad7176_2_device_info = { 994 .name = "ad7176-2", 995 .id = AD7176_ID, 996 .sd_info = &ad7173_sigma_delta_info_4_slots, 997 .num_voltage_in = 5, 998 .num_channels = 4, 999 .num_configs = 4, 1000 .num_gpios = 2, 1001 .has_int_ref = true, 1002 .clock = 16 * HZ_PER_MHZ, 1003 .sinc5_data_rates = ad7175_sinc5_data_rates, 1004 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1005 }; 1006 1007 static const struct ad7173_device_info ad7177_2_device_info = { 1008 .name = "ad7177-2", 1009 .id = AD7177_ID, 1010 .sd_info = &ad7173_sigma_delta_info_4_slots, 1011 .num_voltage_in = 5, 1012 .num_channels = 4, 1013 .num_configs = 4, 1014 .num_gpios = 2, 1015 .has_temp = true, 1016 .has_input_buf = true, 1017 .has_int_ref = true, 1018 .has_pow_supply_monitoring = true, 1019 .clock = 16 * HZ_PER_MHZ, 1020 .odr_start_value = AD7177_ODR_START_VALUE, 1021 .sinc5_data_rates = ad7175_sinc5_data_rates, 1022 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1023 }; 1024 1025 static int ad7173_setup(struct iio_dev *indio_dev) 1026 { 1027 struct ad7173_state *st = iio_priv(indio_dev); 1028 struct device *dev = &st->sd.spi->dev; 1029 u8 buf[AD7173_RESET_LENGTH]; 1030 unsigned int id; 1031 int ret; 1032 1033 /* reset the serial interface */ 1034 memset(buf, 0xff, AD7173_RESET_LENGTH); 1035 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 1036 if (ret < 0) 1037 return ret; 1038 1039 /* datasheet recommends a delay of at least 500us after reset */ 1040 fsleep(500); 1041 1042 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 1043 if (ret) 1044 return ret; 1045 1046 id &= AD7173_ID_MASK; 1047 if (id != st->info->id) 1048 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 1049 id, st->info->id); 1050 1051 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 1052 st->interface_mode = 0x0; 1053 1054 st->config_usage_counter = 0; 1055 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 1056 sizeof(*st->config_cnts), GFP_KERNEL); 1057 if (!st->config_cnts) 1058 return -ENOMEM; 1059 1060 ret = ad7173_calibrate_all(st, indio_dev); 1061 if (ret) 1062 return ret; 1063 1064 /* All channels are enabled by default after a reset */ 1065 return ad7173_disable_all(&st->sd); 1066 } 1067 1068 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 1069 u8 reference_select) 1070 { 1071 int vref; 1072 1073 switch (reference_select) { 1074 case AD7173_SETUP_REF_SEL_EXT_REF: 1075 vref = regulator_get_voltage(st->regulators[0].consumer); 1076 break; 1077 1078 case AD7173_SETUP_REF_SEL_EXT_REF2: 1079 vref = regulator_get_voltage(st->regulators[1].consumer); 1080 break; 1081 1082 case AD7173_SETUP_REF_SEL_INT_REF: 1083 vref = AD7173_VOLTAGE_INT_REF_uV; 1084 break; 1085 1086 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 1087 vref = regulator_get_voltage(st->regulators[2].consumer); 1088 break; 1089 1090 default: 1091 return -EINVAL; 1092 } 1093 1094 if (vref < 0) 1095 return vref; 1096 1097 return vref / (MICRO / MILLI); 1098 } 1099 1100 static int ad7173_read_raw(struct iio_dev *indio_dev, 1101 struct iio_chan_spec const *chan, 1102 int *val, int *val2, long info) 1103 { 1104 struct ad7173_state *st = iio_priv(indio_dev); 1105 struct ad7173_channel *ch = &st->channels[chan->address]; 1106 unsigned int reg; 1107 u64 temp; 1108 int ret; 1109 1110 switch (info) { 1111 case IIO_CHAN_INFO_RAW: 1112 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 1113 if (ret < 0) 1114 return ret; 1115 1116 if (ch->openwire_det_en) { 1117 ret = ad4111_openwire_event(indio_dev, chan); 1118 if (ret < 0) 1119 return ret; 1120 } 1121 1122 return IIO_VAL_INT; 1123 case IIO_CHAN_INFO_SCALE: 1124 1125 switch (chan->type) { 1126 case IIO_TEMP: 1127 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 1128 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 1129 *val = temp; 1130 *val2 = chan->scan_type.realbits; 1131 return IIO_VAL_FRACTIONAL_LOG2; 1132 case IIO_VOLTAGE: 1133 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1134 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 1135 1136 if (chan->channel < st->info->num_voltage_in_div) 1137 *val *= AD4111_DIVIDER_RATIO; 1138 return IIO_VAL_FRACTIONAL_LOG2; 1139 case IIO_CURRENT: 1140 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1141 *val /= AD4111_SHUNT_RESISTOR_OHM; 1142 *val2 = chan->scan_type.realbits - ch->cfg.bipolar; 1143 return IIO_VAL_FRACTIONAL_LOG2; 1144 default: 1145 return -EINVAL; 1146 } 1147 case IIO_CHAN_INFO_OFFSET: 1148 1149 switch (chan->type) { 1150 case IIO_TEMP: 1151 /* 0 Kelvin -> raw sample */ 1152 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 1153 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 1154 temp <<= chan->scan_type.realbits; 1155 temp = DIV_U64_ROUND_CLOSEST(temp, 1156 AD7173_VOLTAGE_INT_REF_uV * 1157 MILLI); 1158 *val = -temp; 1159 return IIO_VAL_INT; 1160 case IIO_VOLTAGE: 1161 case IIO_CURRENT: 1162 *val = -BIT(chan->scan_type.realbits - 1); 1163 return IIO_VAL_INT; 1164 default: 1165 return -EINVAL; 1166 } 1167 case IIO_CHAN_INFO_SAMP_FREQ: 1168 reg = st->channels[chan->address].cfg.odr; 1169 1170 *val = st->info->sinc5_data_rates[reg] / MILLI; 1171 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 1172 1173 return IIO_VAL_INT_PLUS_MICRO; 1174 default: 1175 return -EINVAL; 1176 } 1177 } 1178 1179 static int ad7173_write_raw(struct iio_dev *indio_dev, 1180 struct iio_chan_spec const *chan, 1181 int val, int val2, long info) 1182 { 1183 struct ad7173_state *st = iio_priv(indio_dev); 1184 struct ad7173_channel_config *cfg; 1185 unsigned int freq, i; 1186 int ret = 0; 1187 1188 if (!iio_device_claim_direct(indio_dev)) 1189 return -EBUSY; 1190 1191 switch (info) { 1192 /* 1193 * This attribute sets the sampling frequency for each channel individually. 1194 * There are no issues for raw or buffered reads of an individual channel. 1195 * 1196 * When multiple channels are enabled in buffered mode, the effective 1197 * sampling rate of a channel is lowered in correlation to the number 1198 * of channels enabled and the sampling rate of the other channels. 1199 * 1200 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps 1201 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3 1202 * will take 100ms each. 1203 * 1204 * This will cause the reading of CH1 to be actually done once every 1205 * 200.16ms, an effective rate of 4.99sps. 1206 */ 1207 case IIO_CHAN_INFO_SAMP_FREQ: 1208 freq = val * MILLI + val2 / MILLI; 1209 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 1210 if (freq >= st->info->sinc5_data_rates[i]) 1211 break; 1212 1213 cfg = &st->channels[chan->address].cfg; 1214 cfg->odr = i; 1215 cfg->live = false; 1216 break; 1217 1218 default: 1219 ret = -EINVAL; 1220 break; 1221 } 1222 1223 iio_device_release_direct(indio_dev); 1224 return ret; 1225 } 1226 1227 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 1228 const unsigned long *scan_mask) 1229 { 1230 struct ad7173_state *st = iio_priv(indio_dev); 1231 int i, ret; 1232 1233 for (i = 0; i < indio_dev->num_channels; i++) { 1234 if (test_bit(i, scan_mask)) 1235 ret = ad7173_set_channel(&st->sd, i); 1236 else 1237 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 1238 if (ret < 0) 1239 return ret; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1246 unsigned int writeval, unsigned int *readval) 1247 { 1248 struct ad7173_state *st = iio_priv(indio_dev); 1249 u8 reg_size; 1250 1251 if (reg == AD7173_REG_COMMS) 1252 reg_size = 1; 1253 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 1254 reg >= AD7173_REG_OFFSET(0)) 1255 reg_size = 3; 1256 else 1257 reg_size = 2; 1258 1259 if (readval) 1260 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 1261 1262 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 1263 } 1264 1265 static int ad7173_write_event_config(struct iio_dev *indio_dev, 1266 const struct iio_chan_spec *chan, 1267 enum iio_event_type type, 1268 enum iio_event_direction dir, 1269 bool state) 1270 { 1271 struct ad7173_state *st = iio_priv(indio_dev); 1272 struct ad7173_channel *adchan = &st->channels[chan->address]; 1273 1274 switch (type) { 1275 case IIO_EV_TYPE_FAULT: 1276 adchan->openwire_det_en = state; 1277 return 0; 1278 default: 1279 return -EINVAL; 1280 } 1281 } 1282 1283 static int ad7173_read_event_config(struct iio_dev *indio_dev, 1284 const struct iio_chan_spec *chan, 1285 enum iio_event_type type, 1286 enum iio_event_direction dir) 1287 { 1288 struct ad7173_state *st = iio_priv(indio_dev); 1289 struct ad7173_channel *adchan = &st->channels[chan->address]; 1290 1291 switch (type) { 1292 case IIO_EV_TYPE_FAULT: 1293 return adchan->openwire_det_en; 1294 default: 1295 return -EINVAL; 1296 } 1297 } 1298 1299 static const struct iio_event_spec ad4111_events[] = { 1300 { 1301 .type = IIO_EV_TYPE_FAULT, 1302 .dir = IIO_EV_DIR_FAULT_OPENWIRE, 1303 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1304 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 1305 }, 1306 }; 1307 1308 static const struct iio_info ad7173_info = { 1309 .read_raw = &ad7173_read_raw, 1310 .write_raw = &ad7173_write_raw, 1311 .debugfs_reg_access = &ad7173_debug_reg_access, 1312 .validate_trigger = ad_sd_validate_trigger, 1313 .update_scan_mode = ad7173_update_scan_mode, 1314 .write_event_config = ad7173_write_event_config, 1315 .read_event_config = ad7173_read_event_config, 1316 }; 1317 1318 static const struct iio_scan_type ad4113_scan_type = { 1319 .sign = 'u', 1320 .realbits = 16, 1321 .storagebits = 16, 1322 .endianness = IIO_BE, 1323 }; 1324 1325 static const struct iio_chan_spec ad7173_channel_template = { 1326 .type = IIO_VOLTAGE, 1327 .indexed = 1, 1328 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1329 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 1330 .scan_type = { 1331 .sign = 'u', 1332 .realbits = 24, 1333 .storagebits = 32, 1334 .endianness = IIO_BE, 1335 }, 1336 .ext_info = ad7173_calibsys_ext_info, 1337 }; 1338 1339 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 1340 .type = IIO_TEMP, 1341 .channel = AD7173_AIN_TEMP_POS, 1342 .channel2 = AD7173_AIN_TEMP_NEG, 1343 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1344 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1345 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1346 .scan_type = { 1347 .sign = 'u', 1348 .realbits = 24, 1349 .storagebits = 32, 1350 .endianness = IIO_BE, 1351 }, 1352 }; 1353 1354 static void ad7173_disable_regulators(void *data) 1355 { 1356 struct ad7173_state *st = data; 1357 1358 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1359 } 1360 1361 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 1362 unsigned int clk_sel) 1363 { 1364 int ret; 1365 1366 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 1367 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 1368 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 1369 1370 return ret; 1371 } 1372 1373 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 1374 unsigned long parent_rate) 1375 { 1376 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1377 1378 return st->info->clock / HZ_PER_KHZ; 1379 } 1380 1381 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 1382 { 1383 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1384 u32 clk_sel; 1385 1386 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 1387 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 1388 } 1389 1390 static int ad7173_clk_output_prepare(struct clk_hw *hw) 1391 { 1392 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1393 1394 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 1395 } 1396 1397 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 1398 { 1399 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1400 1401 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 1402 } 1403 1404 static const struct clk_ops ad7173_int_clk_ops = { 1405 .recalc_rate = ad7173_clk_recalc_rate, 1406 .is_enabled = ad7173_clk_output_is_enabled, 1407 .prepare = ad7173_clk_output_prepare, 1408 .unprepare = ad7173_clk_output_unprepare, 1409 }; 1410 1411 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 1412 { 1413 struct ad7173_state *st = iio_priv(indio_dev); 1414 struct device *dev = indio_dev->dev.parent; 1415 struct fwnode_handle *fwnode = dev_fwnode(dev); 1416 struct clk_init_data init = {}; 1417 int ret; 1418 1419 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1420 return 0; 1421 1422 init.name = fwnode_get_name(fwnode); 1423 init.ops = &ad7173_int_clk_ops; 1424 1425 st->int_clk_hw.init = &init; 1426 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 1427 if (ret) 1428 return ret; 1429 1430 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1431 &st->int_clk_hw); 1432 } 1433 1434 static int ad4111_validate_current_ain(struct ad7173_state *st, 1435 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL]) 1436 { 1437 struct device *dev = &st->sd.spi->dev; 1438 1439 if (!st->info->has_current_inputs) 1440 return dev_err_probe(dev, -EINVAL, 1441 "Model %s does not support current channels\n", 1442 st->info->name); 1443 1444 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config)) 1445 return dev_err_probe(dev, -EINVAL, 1446 "For current channels single-channel must be <[0-3]>\n"); 1447 1448 return 0; 1449 } 1450 1451 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st, 1452 unsigned int ain0, unsigned int ain1) 1453 { 1454 struct device *dev = &st->sd.spi->dev; 1455 bool special_input0, special_input1; 1456 1457 /* (AVDD1-AVSS)/5 power supply monitoring */ 1458 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG && 1459 st->info->has_pow_supply_monitoring) 1460 return 0; 1461 1462 special_input0 = AD7173_IS_REF_INPUT(ain0) || 1463 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1464 special_input1 = AD7173_IS_REF_INPUT(ain1) || 1465 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1466 1467 if ((ain0 >= st->info->num_voltage_in && !special_input0) || 1468 (ain1 >= st->info->num_voltage_in && !special_input1)) { 1469 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT) 1470 return dev_err_probe(dev, -EINVAL, 1471 "VINCOM not supported for %s\n", st->info->name); 1472 1473 return dev_err_probe(dev, -EINVAL, 1474 "Input pin number out of range for pair (%d %d).\n", 1475 ain0, ain1); 1476 } 1477 1478 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) || 1479 AD4111_IS_VINCOM_MISMATCH(ain1, ain0)) 1480 return dev_err_probe(dev, -EINVAL, 1481 "VINCOM must be paired with inputs having divider.\n"); 1482 1483 if (!special_input0 && !special_input1 && 1484 ((ain0 >= st->info->num_voltage_in_div) != 1485 (ain1 >= st->info->num_voltage_in_div))) 1486 return dev_err_probe(dev, -EINVAL, 1487 "Both inputs must either have a voltage divider or not have: (%d %d).\n", 1488 ain0, ain1); 1489 1490 return 0; 1491 } 1492 1493 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel) 1494 { 1495 struct device *dev = &st->sd.spi->dev; 1496 int ret; 1497 1498 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref) 1499 return dev_err_probe(dev, -EINVAL, 1500 "Internal reference is not available on current model.\n"); 1501 1502 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 1503 return dev_err_probe(dev, -EINVAL, 1504 "External reference 2 is not available on current model.\n"); 1505 1506 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 1507 if (ret < 0) 1508 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1509 ref_sel); 1510 1511 return 0; 1512 } 1513 1514 static int ad7173_validate_openwire_ain_inputs(struct ad7173_state *st, 1515 bool differential, 1516 unsigned int ain0, 1517 unsigned int ain1) 1518 { 1519 /* 1520 * If the channel is configured as differential, 1521 * the ad4111 requires specific ains to be used together 1522 */ 1523 if (differential) 1524 return (ain0 % 2) ? (ain0 - 1) == ain1 : (ain0 + 1) == ain1; 1525 1526 return ain1 == AD4111_VINCOM_INPUT; 1527 } 1528 1529 static unsigned int ad7173_calc_openwire_thrsh_raw(struct ad7173_state *st, 1530 struct iio_chan_spec *chan, 1531 struct ad7173_channel *chan_st_priv, 1532 unsigned int thrsh_mv) { 1533 unsigned int thrsh_raw; 1534 1535 thrsh_raw = 1536 BIT(chan->scan_type.realbits - !!(chan_st_priv->cfg.bipolar)) 1537 * thrsh_mv 1538 / ad7173_get_ref_voltage_milli(st, chan_st_priv->cfg.ref_sel); 1539 if (chan->channel < st->info->num_voltage_in_div) 1540 thrsh_raw /= AD4111_DIVIDER_RATIO; 1541 1542 return thrsh_raw; 1543 } 1544 1545 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 1546 { 1547 struct ad7173_channel *chans_st_arr, *chan_st_priv; 1548 struct ad7173_state *st = iio_priv(indio_dev); 1549 struct device *dev = indio_dev->dev.parent; 1550 struct iio_chan_spec *chan_arr, *chan; 1551 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0; 1552 int ref_sel, ret, num_channels; 1553 1554 num_channels = device_get_child_node_count(dev); 1555 1556 if (st->info->has_temp) 1557 num_channels++; 1558 1559 if (num_channels == 0) 1560 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1561 1562 if (num_channels > st->info->num_channels) 1563 return dev_err_probe(dev, -EINVAL, 1564 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n", 1565 st->info->num_channels); 1566 1567 indio_dev->num_channels = num_channels; 1568 st->num_channels = num_channels; 1569 1570 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 1571 st->num_channels, GFP_KERNEL); 1572 if (!chan_arr) 1573 return -ENOMEM; 1574 1575 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 1576 GFP_KERNEL); 1577 if (!chans_st_arr) 1578 return -ENOMEM; 1579 1580 indio_dev->channels = chan_arr; 1581 st->channels = chans_st_arr; 1582 1583 if (st->info->has_temp) { 1584 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 1585 chan_st_priv = &chans_st_arr[chan_index]; 1586 chan_st_priv->ain = 1587 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 1588 chan_arr[chan_index].channel2); 1589 chan_st_priv->cfg.bipolar = false; 1590 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1591 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1592 chan_st_priv->cfg.odr = st->info->odr_start_value; 1593 chan_st_priv->cfg.openwire_comp_chan = -1; 1594 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1595 if (st->info->data_reg_only_16bit) 1596 chan_arr[chan_index].scan_type = ad4113_scan_type; 1597 1598 chan_index++; 1599 } 1600 1601 device_for_each_child_node_scoped(dev, child) { 1602 bool is_current_chan = false; 1603 1604 chan = &chan_arr[chan_index]; 1605 *chan = ad7173_channel_template; 1606 chan_st_priv = &chans_st_arr[chan_index]; 1607 ret = fwnode_property_read_u32_array(child, "diff-channels", 1608 ain, ARRAY_SIZE(ain)); 1609 if (ret) { 1610 ret = fwnode_property_read_u32(child, "single-channel", 1611 ain); 1612 if (ret) 1613 return dev_err_probe(dev, ret, 1614 "Channel must define one of diff-channels or single-channel.\n"); 1615 1616 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel"); 1617 } else { 1618 chan->differential = true; 1619 } 1620 1621 if (is_current_chan) { 1622 ret = ad4111_validate_current_ain(st, ain); 1623 if (ret) 1624 return ret; 1625 } else { 1626 if (!chan->differential) { 1627 ret = fwnode_property_read_u32(child, 1628 "common-mode-channel", ain + 1); 1629 if (ret) 1630 return dev_err_probe(dev, ret, 1631 "common-mode-channel must be defined for single-ended channels.\n"); 1632 } 1633 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]); 1634 if (ret) 1635 return ret; 1636 } 1637 1638 ret = fwnode_property_match_property_string(child, 1639 "adi,reference-select", 1640 ad7173_ref_sel_str, 1641 ARRAY_SIZE(ad7173_ref_sel_str)); 1642 if (ret < 0) 1643 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1644 else 1645 ref_sel = ret; 1646 1647 ret = ad7173_validate_reference(st, ref_sel); 1648 if (ret) 1649 return ret; 1650 1651 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 1652 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1653 chan_st_priv->cfg.ref_sel = ref_sel; 1654 1655 chan->address = chan_index; 1656 chan->scan_index = chan_index; 1657 chan->channel = ain[0]; 1658 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1659 chan_st_priv->cfg.odr = st->info->odr_start_value; 1660 chan_st_priv->cfg.openwire_comp_chan = -1; 1661 1662 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 1663 if (chan_st_priv->cfg.bipolar) 1664 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 1665 1666 if (is_current_chan) { 1667 chan->type = IIO_CURRENT; 1668 chan->differential = false; 1669 chan->channel2 = 0; 1670 chan_st_priv->ain = ad4111_current_channel_config[ain[0]]; 1671 } else { 1672 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1673 chan->channel2 = ain[1]; 1674 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 1675 if (st->info->has_openwire_det && 1676 ad7173_validate_openwire_ain_inputs(st, chan->differential, ain[0], ain[1])) { 1677 chan->event_spec = ad4111_events; 1678 chan->num_event_specs = ARRAY_SIZE(ad4111_events); 1679 chan_st_priv->cfg.openwire_thrsh_raw = 1680 ad7173_calc_openwire_thrsh_raw(st, chan, chan_st_priv, 1681 AD4111_OW_DET_THRSH_MV); 1682 } 1683 } 1684 1685 if (st->info->data_reg_only_16bit) 1686 chan_arr[chan_index].scan_type = ad4113_scan_type; 1687 1688 chan_index++; 1689 } 1690 return 0; 1691 } 1692 1693 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1694 { 1695 struct ad7173_state *st = iio_priv(indio_dev); 1696 struct device *dev = indio_dev->dev.parent; 1697 int ret; 1698 1699 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1700 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1701 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1702 1703 /* 1704 * If a regulator is not available, it will be set to a dummy regulator. 1705 * Each channel reference is checked with regulator_get_voltage() before 1706 * setting attributes so if any channel uses a dummy supply the driver 1707 * probe will fail. 1708 */ 1709 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1710 st->regulators); 1711 if (ret) 1712 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1713 1714 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1715 if (ret) 1716 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1717 1718 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1719 if (ret) 1720 return dev_err_probe(dev, ret, 1721 "Failed to add regulators disable action\n"); 1722 1723 ret = device_property_match_property_string(dev, "clock-names", 1724 ad7173_clk_sel, 1725 ARRAY_SIZE(ad7173_clk_sel)); 1726 if (ret < 0) { 1727 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1728 AD7173_ADC_MODE_CLOCKSEL_INT); 1729 ad7173_register_clk_provider(indio_dev); 1730 } else { 1731 struct clk *clk; 1732 1733 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1734 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1735 clk = devm_clk_get_enabled(dev, ad7173_clk_sel[ret]); 1736 if (IS_ERR(clk)) 1737 return dev_err_probe(dev, PTR_ERR(clk), 1738 "Failed to get external clock\n"); 1739 } 1740 1741 return ad7173_fw_parse_channel_config(indio_dev); 1742 } 1743 1744 static int ad7173_probe(struct spi_device *spi) 1745 { 1746 struct device *dev = &spi->dev; 1747 struct ad7173_state *st; 1748 struct iio_dev *indio_dev; 1749 int ret; 1750 1751 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1752 if (!indio_dev) 1753 return -ENOMEM; 1754 1755 st = iio_priv(indio_dev); 1756 st->info = spi_get_device_match_data(spi); 1757 if (!st->info) 1758 return -ENODEV; 1759 1760 ida_init(&st->cfg_slots_status); 1761 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1762 if (ret) 1763 return ret; 1764 1765 indio_dev->name = st->info->name; 1766 indio_dev->modes = INDIO_DIRECT_MODE; 1767 indio_dev->info = &ad7173_info; 1768 1769 spi->mode = SPI_MODE_3; 1770 ret = spi_setup(spi); 1771 if (ret) 1772 return ret; 1773 1774 ret = ad_sd_init(&st->sd, indio_dev, spi, st->info->sd_info); 1775 if (ret) 1776 return ret; 1777 1778 ret = ad7173_fw_parse_device_config(indio_dev); 1779 if (ret) 1780 return ret; 1781 1782 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1783 if (ret) 1784 return ret; 1785 1786 ret = ad7173_setup(indio_dev); 1787 if (ret) 1788 return ret; 1789 1790 ret = devm_iio_device_register(dev, indio_dev); 1791 if (ret) 1792 return ret; 1793 1794 return ad7173_gpio_init(st); 1795 } 1796 1797 static const struct of_device_id ad7173_of_match[] = { 1798 { .compatible = "adi,ad4111", .data = &ad4111_device_info }, 1799 { .compatible = "adi,ad4112", .data = &ad4112_device_info }, 1800 { .compatible = "adi,ad4113", .data = &ad4113_device_info }, 1801 { .compatible = "adi,ad4114", .data = &ad4114_device_info }, 1802 { .compatible = "adi,ad4115", .data = &ad4115_device_info }, 1803 { .compatible = "adi,ad4116", .data = &ad4116_device_info }, 1804 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info }, 1805 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info }, 1806 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info }, 1807 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info }, 1808 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info }, 1809 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info }, 1810 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info }, 1811 { } 1812 }; 1813 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1814 1815 static const struct spi_device_id ad7173_id_table[] = { 1816 { "ad4111", (kernel_ulong_t)&ad4111_device_info }, 1817 { "ad4112", (kernel_ulong_t)&ad4112_device_info }, 1818 { "ad4113", (kernel_ulong_t)&ad4113_device_info }, 1819 { "ad4114", (kernel_ulong_t)&ad4114_device_info }, 1820 { "ad4115", (kernel_ulong_t)&ad4115_device_info }, 1821 { "ad4116", (kernel_ulong_t)&ad4116_device_info }, 1822 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info }, 1823 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info }, 1824 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info }, 1825 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info }, 1826 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info }, 1827 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info }, 1828 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info }, 1829 { } 1830 }; 1831 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1832 1833 static struct spi_driver ad7173_driver = { 1834 .driver = { 1835 .name = "ad7173", 1836 .of_match_table = ad7173_of_match, 1837 }, 1838 .probe = ad7173_probe, 1839 .id_table = ad7173_id_table, 1840 }; 1841 module_spi_driver(ad7173_driver); 1842 1843 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1844 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1845 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1846 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver"); 1847 MODULE_LICENSE("GPL"); 1848