1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x and AD411x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116 7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 8 * AD7175-8/AD7176-2/AD7177-2 9 * 10 * Copyright (C) 2015, 2024 Analog Devices, Inc. 11 */ 12 13 #include <linux/array_size.h> 14 #include <linux/bitfield.h> 15 #include <linux/bitmap.h> 16 #include <linux/container_of.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/gpio/regmap.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/math64.h> 27 #include <linux/module.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/spi/spi.h> 34 #include <linux/types.h> 35 #include <linux/units.h> 36 37 #include <linux/iio/buffer.h> 38 #include <linux/iio/events.h> 39 #include <linux/iio/iio.h> 40 #include <linux/iio/trigger_consumer.h> 41 #include <linux/iio/triggered_buffer.h> 42 43 #include <linux/iio/adc/ad_sigma_delta.h> 44 45 #define AD7173_REG_COMMS 0x00 46 #define AD7173_REG_ADC_MODE 0x01 47 #define AD7173_REG_INTERFACE_MODE 0x02 48 #define AD7173_REG_CRC 0x03 49 #define AD7173_REG_DATA 0x04 50 #define AD7173_REG_GPIO 0x06 51 #define AD7173_REG_ID 0x07 52 #define AD7173_REG_CH(x) (0x10 + (x)) 53 #define AD7173_REG_SETUP(x) (0x20 + (x)) 54 #define AD7173_REG_FILTER(x) (0x28 + (x)) 55 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 56 #define AD7173_REG_GAIN(x) (0x38 + (x)) 57 58 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 59 60 #define AD7173_CH_ENABLE BIT(15) 61 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 62 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 63 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 64 65 #define AD7173_NO_AINS_PER_CHANNEL 2 66 #define AD7173_CH_ADDRESS(pos, neg) \ 67 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 68 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 69 #define AD7173_AIN_TEMP_POS 17 70 #define AD7173_AIN_TEMP_NEG 18 71 #define AD7173_AIN_POW_MON_POS 19 72 #define AD7173_AIN_POW_MON_NEG 20 73 #define AD7173_AIN_REF_POS 21 74 #define AD7173_AIN_REF_NEG 22 75 76 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \ 77 (x) == AD7173_AIN_REF_NEG) 78 79 #define AD7172_2_ID 0x00d0 80 #define AD7176_ID 0x0c90 81 #define AD7175_ID 0x0cd0 82 #define AD7175_2_ID 0x0cd0 83 #define AD7172_4_ID 0x2050 84 #define AD7173_ID 0x30d0 85 #define AD4111_ID AD7173_ID 86 #define AD4112_ID AD7173_ID 87 #define AD4114_ID AD7173_ID 88 #define AD4113_ID 0x31d0 89 #define AD4116_ID 0x34d0 90 #define AD4115_ID 0x38d0 91 #define AD7175_8_ID 0x3cd0 92 #define AD7177_ID 0x4fd0 93 #define AD7173_ID_MASK GENMASK(15, 4) 94 95 #define AD7173_ADC_MODE_REF_EN BIT(15) 96 #define AD7173_ADC_MODE_SING_CYC BIT(13) 97 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 98 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 99 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 100 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 101 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 102 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 103 104 #define AD7173_GPIO_PDSW BIT(14) 105 #define AD7173_GPIO_OP_EN2_3 BIT(13) 106 #define AD4111_GPIO_GP_OW_EN BIT(12) 107 #define AD7173_GPIO_MUX_IO BIT(12) 108 #define AD7173_GPIO_SYNC_EN BIT(11) 109 #define AD7173_GPIO_ERR_EN BIT(10) 110 #define AD7173_GPIO_ERR_DAT BIT(9) 111 #define AD7173_GPIO_GP_DATA3 BIT(7) 112 #define AD7173_GPIO_GP_DATA2 BIT(6) 113 #define AD7173_GPIO_IP_EN1 BIT(5) 114 #define AD7173_GPIO_IP_EN0 BIT(4) 115 #define AD7173_GPIO_OP_EN1 BIT(3) 116 #define AD7173_GPIO_OP_EN0 BIT(2) 117 #define AD7173_GPIO_GP_DATA1 BIT(1) 118 #define AD7173_GPIO_GP_DATA0 BIT(0) 119 120 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 121 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 122 #define AD4111_GPO01_DATA(x) BIT((x) + 6) 123 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 124 125 #define AD7173_INTERFACE_DATA_STAT BIT(6) 126 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 127 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 128 129 #define AD7173_SETUP_BIPOLAR BIT(12) 130 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 131 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 132 133 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 134 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 135 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 136 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 137 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 138 #define AD7173_VOLTAGE_INT_REF_uV 2500000 139 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 140 #define AD7177_ODR_START_VALUE 0x07 141 #define AD4111_SHUNT_RESISTOR_OHM 50 142 #define AD4111_DIVIDER_RATIO 10 143 #define AD4111_CURRENT_CHAN_CUTOFF 16 144 #define AD4111_VINCOM_INPUT 0x10 145 146 /* pin < num_voltage_in is a normal voltage input */ 147 /* pin >= num_voltage_in_div is a voltage input without a divider */ 148 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \ 149 (pin2) < st->info->num_voltage_in && \ 150 (pin2) >= st->info->num_voltage_in_div) 151 152 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 153 #define AD7173_MAX_CONFIGS 8 154 #define AD4111_OW_DET_THRSH_MV 300 155 156 #define AD7173_MODE_CAL_INT_ZERO 0x4 /* Internal Zero-Scale Calibration */ 157 #define AD7173_MODE_CAL_INT_FULL 0x5 /* Internal Full-Scale Calibration */ 158 #define AD7173_MODE_CAL_SYS_ZERO 0x6 /* System Zero-Scale Calibration */ 159 #define AD7173_MODE_CAL_SYS_FULL 0x7 /* System Full-Scale Calibration */ 160 161 struct ad7173_device_info { 162 const unsigned int *sinc5_data_rates; 163 unsigned int num_sinc5_data_rates; 164 unsigned int odr_start_value; 165 /* 166 * AD4116 has both inputs with a voltage divider and without. 167 * These inputs cannot be mixed in the channel configuration. 168 * Does not include the VINCOM input. 169 */ 170 unsigned int num_voltage_in_div; 171 unsigned int num_channels; 172 unsigned int num_configs; 173 unsigned int num_voltage_in; 174 unsigned int clock; 175 unsigned int id; 176 char *name; 177 const struct ad_sigma_delta_info *sd_info; 178 bool has_current_inputs; 179 bool has_vincom_input; 180 bool has_temp; 181 /* ((AVDD1 − AVSS)/5) */ 182 bool has_pow_supply_monitoring; 183 bool data_reg_only_16bit; 184 bool has_input_buf; 185 bool has_int_ref; 186 bool has_ref2; 187 bool has_internal_fs_calibration; 188 bool has_openwire_det; 189 bool higher_gpio_bits; 190 u8 num_gpios; 191 }; 192 193 struct ad7173_channel_config { 194 /* Openwire detection threshold */ 195 unsigned int openwire_thrsh_raw; 196 int openwire_comp_chan; 197 u8 cfg_slot; 198 bool live; 199 200 /* 201 * Following fields are used to compare equality. If you 202 * make adaptations in it, you most likely also have to adapt 203 * ad7173_find_live_config(), too. 204 */ 205 struct_group(config_props, 206 bool bipolar; 207 bool input_buf; 208 u8 odr; 209 u8 ref_sel; 210 ); 211 }; 212 213 struct ad7173_channel { 214 unsigned int ain; 215 struct ad7173_channel_config cfg; 216 u8 syscalib_mode; 217 bool openwire_det_en; 218 }; 219 220 struct ad7173_state { 221 struct ad_sigma_delta sd; 222 const struct ad7173_device_info *info; 223 struct ad7173_channel *channels; 224 struct regulator_bulk_data regulators[3]; 225 unsigned int adc_mode; 226 unsigned int interface_mode; 227 unsigned int num_channels; 228 struct ida cfg_slots_status; 229 unsigned long long config_usage_counter; 230 unsigned long long *config_cnts; 231 struct clk *ext_clk; 232 struct clk_hw int_clk_hw; 233 #if IS_ENABLED(CONFIG_GPIOLIB) 234 struct regmap *reg_gpiocon_regmap; 235 struct gpio_regmap *gpio_regmap; 236 #endif 237 }; 238 239 static unsigned int ad4115_sinc5_data_rates[] = { 240 24845000, 24845000, 20725000, 20725000, /* 0-3 */ 241 15564000, 13841000, 10390000, 10390000, /* 4-7 */ 242 4994000, 2499000, 1000000, 500000, /* 8-11 */ 243 395500, 200000, 100000, 59890, /* 12-15 */ 244 49920, 20000, 16660, 10000, /* 16-19 */ 245 5000, 2500, 2500, /* 20-22 */ 246 }; 247 248 static unsigned int ad4116_sinc5_data_rates[] = { 249 12422360, 12422360, 12422360, 12422360, /* 0-3 */ 250 10362690, 10362690, 7782100, 6290530, /* 4-7 */ 251 5194800, 2496900, 1007600, 499900, /* 8-11 */ 252 390600, 200300, 100000, 59750, /* 12-15 */ 253 49840, 20000, 16650, 10000, /* 16-19 */ 254 5000, 2500, 1250, /* 20-22 */ 255 }; 256 257 static const unsigned int ad7173_sinc5_data_rates[] = { 258 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 259 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 260 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 261 }; 262 263 static const unsigned int ad7175_sinc5_data_rates[] = { 264 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 265 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 266 5000000, 2500000, 1000000, 500000, /* 8-11 */ 267 397500, 200000, 100000, 59920, /* 12-15 */ 268 49960, 20000, 16666, 10000, /* 16-19 */ 269 5000, /* 20 */ 270 }; 271 272 static unsigned int ad4111_current_channel_config[] = { 273 /* Ain sel: pos neg */ 274 0x1E8, /* 15:IIN0+ 8:IIN0− */ 275 0x1C9, /* 14:IIN1+ 9:IIN1− */ 276 0x1AA, /* 13:IIN2+ 10:IIN2− */ 277 0x18B, /* 12:IIN3+ 11:IIN3− */ 278 }; 279 280 static const char *const ad7173_ref_sel_str[] = { 281 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 282 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 283 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 284 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 285 }; 286 287 static const char *const ad7173_clk_sel[] = { 288 "ext-clk", "xtal" 289 }; 290 291 #if IS_ENABLED(CONFIG_GPIOLIB) 292 293 static const struct regmap_range ad7173_range_gpio[] = { 294 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 295 }; 296 297 static const struct regmap_access_table ad7173_access_table = { 298 .yes_ranges = ad7173_range_gpio, 299 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 300 }; 301 302 static const struct regmap_config ad7173_regmap_config = { 303 .reg_bits = 8, 304 .val_bits = 16, 305 .rd_table = &ad7173_access_table, 306 .wr_table = &ad7173_access_table, 307 .read_flag_mask = BIT(6), 308 }; 309 310 enum { 311 AD7173_SYSCALIB_ZERO_SCALE, 312 AD7173_SYSCALIB_FULL_SCALE, 313 }; 314 315 static const char * const ad7173_syscalib_modes[] = { 316 [AD7173_SYSCALIB_ZERO_SCALE] = "zero_scale", 317 [AD7173_SYSCALIB_FULL_SCALE] = "full_scale", 318 }; 319 320 static int ad7173_set_syscalib_mode(struct iio_dev *indio_dev, 321 const struct iio_chan_spec *chan, 322 unsigned int mode) 323 { 324 struct ad7173_state *st = iio_priv(indio_dev); 325 326 st->channels[chan->channel].syscalib_mode = mode; 327 328 return 0; 329 } 330 331 static int ad7173_get_syscalib_mode(struct iio_dev *indio_dev, 332 const struct iio_chan_spec *chan) 333 { 334 struct ad7173_state *st = iio_priv(indio_dev); 335 336 return st->channels[chan->channel].syscalib_mode; 337 } 338 339 static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev, 340 uintptr_t private, 341 const struct iio_chan_spec *chan, 342 const char *buf, size_t len) 343 { 344 struct ad7173_state *st = iio_priv(indio_dev); 345 bool sys_calib; 346 int ret, mode; 347 348 ret = kstrtobool(buf, &sys_calib); 349 if (ret) 350 return ret; 351 352 if (!iio_device_claim_direct(indio_dev)) 353 return -EBUSY; 354 355 mode = st->channels[chan->channel].syscalib_mode; 356 if (sys_calib) { 357 if (mode == AD7173_SYSCALIB_ZERO_SCALE) 358 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO, 359 chan->address); 360 else 361 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_FULL, 362 chan->address); 363 } 364 365 iio_device_release_direct(indio_dev); 366 367 return ret ? : len; 368 } 369 370 static const struct iio_enum ad7173_syscalib_mode_enum = { 371 .items = ad7173_syscalib_modes, 372 .num_items = ARRAY_SIZE(ad7173_syscalib_modes), 373 .set = ad7173_set_syscalib_mode, 374 .get = ad7173_get_syscalib_mode 375 }; 376 377 static const struct iio_chan_spec_ext_info ad7173_calibsys_ext_info[] = { 378 { 379 .name = "sys_calibration", 380 .write = ad7173_write_syscalib, 381 .shared = IIO_SEPARATE, 382 }, 383 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 384 &ad7173_syscalib_mode_enum), 385 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 386 &ad7173_syscalib_mode_enum), 387 { } 388 }; 389 390 static int ad7173_calibrate_all(struct ad7173_state *st, struct iio_dev *indio_dev) 391 { 392 int ret; 393 int i; 394 395 for (i = 0; i < st->num_channels; i++) { 396 if (indio_dev->channels[i].type != IIO_VOLTAGE) 397 continue; 398 399 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, st->channels[i].ain); 400 if (ret < 0) 401 return ret; 402 403 if (st->info->has_internal_fs_calibration) { 404 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL, 405 st->channels[i].ain); 406 if (ret < 0) 407 return ret; 408 } 409 } 410 411 return 0; 412 } 413 414 /* 415 * Associative array of channel pairs for open wire detection 416 * The array is indexed by ain and gives the associated channel pair 417 * to perform the open wire detection with 418 * the channel pair [0] is for non differential and pair [1] 419 * is for differential inputs 420 */ 421 static int openwire_ain_to_channel_pair[][2][2] = { 422 /* AIN Single Differential */ 423 [0] = { { 0, 15 }, { 1, 2 } }, 424 [1] = { { 1, 2 }, { 2, 1 } }, 425 [2] = { { 3, 4 }, { 5, 6 } }, 426 [3] = { { 5, 6 }, { 6, 5 } }, 427 [4] = { { 7, 8 }, { 9, 10 } }, 428 [5] = { { 9, 10 }, { 10, 9 } }, 429 [6] = { { 11, 12 }, { 13, 14 } }, 430 [7] = { { 13, 14 }, { 14, 13 } }, 431 }; 432 433 /* 434 * Openwire detection on ad4111 works by running the same input measurement 435 * on two different channels and compare if the difference between the two 436 * measurements exceeds a certain value (typical 300mV) 437 */ 438 static int ad4111_openwire_event(struct iio_dev *indio_dev, 439 const struct iio_chan_spec *chan) 440 { 441 struct ad7173_state *st = iio_priv(indio_dev); 442 struct ad7173_channel *adchan = &st->channels[chan->address]; 443 struct ad7173_channel_config *cfg = &adchan->cfg; 444 int ret, val1, val2; 445 446 ret = regmap_set_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 447 AD4111_GPIO_GP_OW_EN); 448 if (ret) 449 return ret; 450 451 adchan->cfg.openwire_comp_chan = 452 openwire_ain_to_channel_pair[chan->channel][chan->differential][0]; 453 454 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val1); 455 if (ret < 0) { 456 dev_err(&indio_dev->dev, 457 "Error running ad_sigma_delta single conversion: %d", ret); 458 goto out; 459 } 460 461 adchan->cfg.openwire_comp_chan = 462 openwire_ain_to_channel_pair[chan->channel][chan->differential][1]; 463 464 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val2); 465 if (ret < 0) { 466 dev_err(&indio_dev->dev, 467 "Error running ad_sigma_delta single conversion: %d", ret); 468 goto out; 469 } 470 471 if (abs(val1 - val2) > cfg->openwire_thrsh_raw) 472 iio_push_event(indio_dev, 473 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, chan->address, 474 IIO_EV_TYPE_FAULT, IIO_EV_DIR_FAULT_OPENWIRE), 475 iio_get_time_ns(indio_dev)); 476 477 out: 478 adchan->cfg.openwire_comp_chan = -1; 479 regmap_clear_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 480 AD4111_GPIO_GP_OW_EN); 481 return ret; 482 } 483 484 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 485 unsigned int offset, unsigned int *reg, 486 unsigned int *mask) 487 { 488 *mask = AD7173_GPO_DATA(offset); 489 *reg = base; 490 return 0; 491 } 492 493 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 494 unsigned int offset, unsigned int *reg, 495 unsigned int *mask) 496 { 497 *mask = AD4111_GPO01_DATA(offset); 498 *reg = base; 499 return 0; 500 } 501 502 static void ad7173_gpio_disable(void *data) 503 { 504 struct ad7173_state *st = data; 505 unsigned int mask; 506 507 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 508 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 509 } 510 511 static int ad7173_gpio_init(struct ad7173_state *st) 512 { 513 struct gpio_regmap_config gpio_regmap = {}; 514 struct device *dev = &st->sd.spi->dev; 515 unsigned int mask; 516 int ret; 517 518 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 519 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 520 if (ret) 521 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 522 523 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 524 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 525 526 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 527 if (ret) 528 return ret; 529 530 gpio_regmap.parent = dev; 531 gpio_regmap.regmap = st->reg_gpiocon_regmap; 532 gpio_regmap.ngpio = st->info->num_gpios; 533 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 534 if (st->info->higher_gpio_bits) 535 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate; 536 else 537 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 538 539 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 540 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 541 if (ret) 542 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 543 544 return 0; 545 } 546 #else 547 static int ad7173_gpio_init(struct ad7173_state *st) 548 { 549 return 0; 550 } 551 #endif /* CONFIG_GPIOLIB */ 552 553 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 554 { 555 return container_of(sd, struct ad7173_state, sd); 556 } 557 558 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 559 { 560 return container_of(hw, struct ad7173_state, int_clk_hw); 561 } 562 563 static void ad7173_ida_destroy(void *data) 564 { 565 struct ad7173_state *st = data; 566 567 ida_destroy(&st->cfg_slots_status); 568 } 569 570 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 571 { 572 memset64(st->config_cnts, 0, st->info->num_configs); 573 st->config_usage_counter = 0; 574 } 575 576 static struct ad7173_channel_config * 577 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 578 { 579 struct ad7173_channel_config *cfg_aux; 580 int i; 581 582 /* 583 * This is just to make sure that the comparison is adapted after 584 * struct ad7173_channel_config was changed. 585 */ 586 static_assert(sizeof_field(struct ad7173_channel_config, config_props) == 587 sizeof(struct { 588 bool bipolar; 589 bool input_buf; 590 u8 odr; 591 u8 ref_sel; 592 })); 593 594 for (i = 0; i < st->num_channels; i++) { 595 cfg_aux = &st->channels[i].cfg; 596 597 if (cfg_aux->live && 598 cfg->bipolar == cfg_aux->bipolar && 599 cfg->input_buf == cfg_aux->input_buf && 600 cfg->odr == cfg_aux->odr && 601 cfg->ref_sel == cfg_aux->ref_sel) 602 return cfg_aux; 603 } 604 return NULL; 605 } 606 607 /* Could be replaced with a generic LRU implementation */ 608 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 609 { 610 int i, lru_position = 0; 611 612 for (i = 1; i < st->info->num_configs; i++) 613 if (st->config_cnts[i] < st->config_cnts[lru_position]) 614 lru_position = i; 615 616 for (i = 0; i < st->num_channels; i++) 617 if (st->channels[i].cfg.cfg_slot == lru_position) 618 st->channels[i].cfg.live = false; 619 620 ida_free(&st->cfg_slots_status, lru_position); 621 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 622 } 623 624 /* Could be replaced with a generic LRU implementation */ 625 static int ad7173_load_config(struct ad7173_state *st, 626 struct ad7173_channel_config *cfg) 627 { 628 unsigned int config; 629 int free_cfg_slot, ret; 630 631 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 632 st->info->num_configs - 1, GFP_KERNEL); 633 if (free_cfg_slot < 0) 634 free_cfg_slot = ad7173_free_config_slot_lru(st); 635 636 cfg->cfg_slot = free_cfg_slot; 637 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 638 639 if (cfg->bipolar) 640 config |= AD7173_SETUP_BIPOLAR; 641 642 if (cfg->input_buf) 643 config |= AD7173_SETUP_AIN_BUF_MASK; 644 645 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 646 if (ret) 647 return ret; 648 649 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 650 AD7173_FILTER_ODR0_MASK & cfg->odr); 651 } 652 653 static int ad7173_config_channel(struct ad7173_state *st, int addr) 654 { 655 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 656 struct ad7173_channel_config *live_cfg; 657 int ret; 658 659 if (!cfg->live) { 660 live_cfg = ad7173_find_live_config(st, cfg); 661 if (live_cfg) { 662 cfg->cfg_slot = live_cfg->cfg_slot; 663 } else { 664 ret = ad7173_load_config(st, cfg); 665 if (ret) 666 return ret; 667 cfg->live = true; 668 } 669 } 670 671 if (st->config_usage_counter == U64_MAX) 672 ad7173_reset_usage_cnts(st); 673 674 st->config_usage_counter++; 675 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 676 677 return 0; 678 } 679 680 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 681 { 682 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 683 unsigned int val; 684 int ret; 685 686 ret = ad7173_config_channel(st, channel); 687 if (ret) 688 return ret; 689 690 val = AD7173_CH_ENABLE | 691 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 692 st->channels[channel].ain; 693 694 if (st->channels[channel].cfg.openwire_comp_chan >= 0) 695 channel = st->channels[channel].cfg.openwire_comp_chan; 696 697 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 698 } 699 700 static int ad7173_set_mode(struct ad_sigma_delta *sd, 701 enum ad_sigma_delta_mode mode) 702 { 703 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 704 705 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 706 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 707 708 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 709 } 710 711 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 712 { 713 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 714 unsigned int interface_mode = st->interface_mode; 715 int ret; 716 717 interface_mode &= ~AD7173_INTERFACE_DATA_STAT; 718 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 719 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 720 if (ret) 721 return ret; 722 723 st->interface_mode = interface_mode; 724 725 return 0; 726 } 727 728 static int ad7173_disable_all(struct ad_sigma_delta *sd) 729 { 730 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 731 int ret; 732 int i; 733 734 for (i = 0; i < st->num_channels; i++) { 735 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 736 if (ret < 0) 737 return ret; 738 } 739 740 return 0; 741 } 742 743 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 744 { 745 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 746 747 if (st->channels[chan].cfg.openwire_comp_chan >= 0) 748 chan = st->channels[chan].cfg.openwire_comp_chan; 749 750 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0); 751 } 752 753 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_4_slots = { 754 .set_channel = ad7173_set_channel, 755 .append_status = ad7173_append_status, 756 .disable_all = ad7173_disable_all, 757 .disable_one = ad7173_disable_one, 758 .set_mode = ad7173_set_mode, 759 .has_registers = true, 760 .has_named_irqs = true, 761 .addr_shift = 0, 762 .read_mask = BIT(6), 763 .status_ch_mask = GENMASK(3, 0), 764 .data_reg = AD7173_REG_DATA, 765 .num_resetclks = 64, 766 .num_slots = 4, 767 }; 768 769 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_8_slots = { 770 .set_channel = ad7173_set_channel, 771 .append_status = ad7173_append_status, 772 .disable_all = ad7173_disable_all, 773 .disable_one = ad7173_disable_one, 774 .set_mode = ad7173_set_mode, 775 .has_registers = true, 776 .has_named_irqs = true, 777 .addr_shift = 0, 778 .read_mask = BIT(6), 779 .status_ch_mask = GENMASK(3, 0), 780 .data_reg = AD7173_REG_DATA, 781 .num_resetclks = 64, 782 .num_slots = 8, 783 }; 784 785 static const struct ad7173_device_info ad4111_device_info = { 786 .name = "ad4111", 787 .id = AD4111_ID, 788 .sd_info = &ad7173_sigma_delta_info_8_slots, 789 .num_voltage_in_div = 8, 790 .num_channels = 16, 791 .num_configs = 8, 792 .num_voltage_in = 8, 793 .num_gpios = 2, 794 .higher_gpio_bits = true, 795 .has_temp = true, 796 .has_vincom_input = true, 797 .has_input_buf = true, 798 .has_current_inputs = true, 799 .has_int_ref = true, 800 .has_internal_fs_calibration = true, 801 .has_openwire_det = true, 802 .clock = 2 * HZ_PER_MHZ, 803 .sinc5_data_rates = ad7173_sinc5_data_rates, 804 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 805 }; 806 807 static const struct ad7173_device_info ad4112_device_info = { 808 .name = "ad4112", 809 .id = AD4112_ID, 810 .sd_info = &ad7173_sigma_delta_info_8_slots, 811 .num_voltage_in_div = 8, 812 .num_channels = 16, 813 .num_configs = 8, 814 .num_voltage_in = 8, 815 .num_gpios = 2, 816 .higher_gpio_bits = true, 817 .has_vincom_input = true, 818 .has_temp = true, 819 .has_input_buf = true, 820 .has_current_inputs = true, 821 .has_int_ref = true, 822 .has_internal_fs_calibration = true, 823 .clock = 2 * HZ_PER_MHZ, 824 .sinc5_data_rates = ad7173_sinc5_data_rates, 825 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 826 }; 827 828 static const struct ad7173_device_info ad4113_device_info = { 829 .name = "ad4113", 830 .id = AD4113_ID, 831 .sd_info = &ad7173_sigma_delta_info_8_slots, 832 .num_voltage_in_div = 8, 833 .num_channels = 16, 834 .num_configs = 8, 835 .num_voltage_in = 8, 836 .num_gpios = 2, 837 .data_reg_only_16bit = true, 838 .higher_gpio_bits = true, 839 .has_vincom_input = true, 840 .has_input_buf = true, 841 .has_int_ref = true, 842 .clock = 2 * HZ_PER_MHZ, 843 .sinc5_data_rates = ad7173_sinc5_data_rates, 844 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 845 }; 846 847 static const struct ad7173_device_info ad4114_device_info = { 848 .name = "ad4114", 849 .id = AD4114_ID, 850 .sd_info = &ad7173_sigma_delta_info_8_slots, 851 .num_voltage_in_div = 16, 852 .num_channels = 16, 853 .num_configs = 8, 854 .num_voltage_in = 16, 855 .num_gpios = 4, 856 .has_vincom_input = true, 857 .has_temp = true, 858 .has_input_buf = true, 859 .has_int_ref = true, 860 .has_internal_fs_calibration = true, 861 .clock = 2 * HZ_PER_MHZ, 862 .sinc5_data_rates = ad7173_sinc5_data_rates, 863 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 864 }; 865 866 static const struct ad7173_device_info ad4115_device_info = { 867 .name = "ad4115", 868 .id = AD4115_ID, 869 .sd_info = &ad7173_sigma_delta_info_8_slots, 870 .num_voltage_in_div = 16, 871 .num_channels = 16, 872 .num_configs = 8, 873 .num_voltage_in = 16, 874 .num_gpios = 4, 875 .has_vincom_input = true, 876 .has_temp = true, 877 .has_input_buf = true, 878 .has_int_ref = true, 879 .has_internal_fs_calibration = true, 880 .clock = 8 * HZ_PER_MHZ, 881 .sinc5_data_rates = ad4115_sinc5_data_rates, 882 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates), 883 }; 884 885 static const struct ad7173_device_info ad4116_device_info = { 886 .name = "ad4116", 887 .id = AD4116_ID, 888 .sd_info = &ad7173_sigma_delta_info_8_slots, 889 .num_voltage_in_div = 11, 890 .num_channels = 16, 891 .num_configs = 8, 892 .num_voltage_in = 16, 893 .num_gpios = 4, 894 .has_vincom_input = true, 895 .has_temp = true, 896 .has_input_buf = true, 897 .has_int_ref = true, 898 .has_internal_fs_calibration = true, 899 .clock = 4 * HZ_PER_MHZ, 900 .sinc5_data_rates = ad4116_sinc5_data_rates, 901 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates), 902 }; 903 904 static const struct ad7173_device_info ad7172_2_device_info = { 905 .name = "ad7172-2", 906 .id = AD7172_2_ID, 907 .sd_info = &ad7173_sigma_delta_info_8_slots, 908 .num_voltage_in = 5, 909 .num_channels = 4, 910 .num_configs = 4, 911 .num_gpios = 2, 912 .has_temp = true, 913 .has_input_buf = true, 914 .has_int_ref = true, 915 .has_pow_supply_monitoring = true, 916 .clock = 2 * HZ_PER_MHZ, 917 .sinc5_data_rates = ad7173_sinc5_data_rates, 918 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 919 }; 920 921 static const struct ad7173_device_info ad7172_4_device_info = { 922 .name = "ad7172-4", 923 .id = AD7172_4_ID, 924 .sd_info = &ad7173_sigma_delta_info_8_slots, 925 .num_voltage_in = 9, 926 .num_channels = 8, 927 .num_configs = 8, 928 .num_gpios = 4, 929 .has_input_buf = true, 930 .has_ref2 = true, 931 .has_pow_supply_monitoring = true, 932 .clock = 2 * HZ_PER_MHZ, 933 .sinc5_data_rates = ad7173_sinc5_data_rates, 934 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 935 }; 936 937 static const struct ad7173_device_info ad7173_8_device_info = { 938 .name = "ad7173-8", 939 .id = AD7173_ID, 940 .sd_info = &ad7173_sigma_delta_info_8_slots, 941 .num_voltage_in = 17, 942 .num_channels = 16, 943 .num_configs = 8, 944 .num_gpios = 4, 945 .has_temp = true, 946 .has_input_buf = true, 947 .has_int_ref = true, 948 .has_ref2 = true, 949 .clock = 2 * HZ_PER_MHZ, 950 .sinc5_data_rates = ad7173_sinc5_data_rates, 951 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 952 }; 953 954 static const struct ad7173_device_info ad7175_2_device_info = { 955 .name = "ad7175-2", 956 .id = AD7175_2_ID, 957 .sd_info = &ad7173_sigma_delta_info_8_slots, 958 .num_voltage_in = 5, 959 .num_channels = 4, 960 .num_configs = 4, 961 .num_gpios = 2, 962 .has_temp = true, 963 .has_input_buf = true, 964 .has_int_ref = true, 965 .has_pow_supply_monitoring = true, 966 .clock = 16 * HZ_PER_MHZ, 967 .sinc5_data_rates = ad7175_sinc5_data_rates, 968 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 969 }; 970 971 static const struct ad7173_device_info ad7175_8_device_info = { 972 .name = "ad7175-8", 973 .id = AD7175_8_ID, 974 .sd_info = &ad7173_sigma_delta_info_8_slots, 975 .num_voltage_in = 17, 976 .num_channels = 16, 977 .num_configs = 8, 978 .num_gpios = 4, 979 .has_temp = true, 980 .has_input_buf = true, 981 .has_int_ref = true, 982 .has_ref2 = true, 983 .has_pow_supply_monitoring = true, 984 .clock = 16 * HZ_PER_MHZ, 985 .sinc5_data_rates = ad7175_sinc5_data_rates, 986 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 987 }; 988 989 static const struct ad7173_device_info ad7176_2_device_info = { 990 .name = "ad7176-2", 991 .id = AD7176_ID, 992 .sd_info = &ad7173_sigma_delta_info_4_slots, 993 .num_voltage_in = 5, 994 .num_channels = 4, 995 .num_configs = 4, 996 .num_gpios = 2, 997 .has_int_ref = true, 998 .clock = 16 * HZ_PER_MHZ, 999 .sinc5_data_rates = ad7175_sinc5_data_rates, 1000 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1001 }; 1002 1003 static const struct ad7173_device_info ad7177_2_device_info = { 1004 .name = "ad7177-2", 1005 .id = AD7177_ID, 1006 .sd_info = &ad7173_sigma_delta_info_4_slots, 1007 .num_voltage_in = 5, 1008 .num_channels = 4, 1009 .num_configs = 4, 1010 .num_gpios = 2, 1011 .has_temp = true, 1012 .has_input_buf = true, 1013 .has_int_ref = true, 1014 .has_pow_supply_monitoring = true, 1015 .clock = 16 * HZ_PER_MHZ, 1016 .odr_start_value = AD7177_ODR_START_VALUE, 1017 .sinc5_data_rates = ad7175_sinc5_data_rates, 1018 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1019 }; 1020 1021 static int ad7173_setup(struct iio_dev *indio_dev) 1022 { 1023 struct ad7173_state *st = iio_priv(indio_dev); 1024 struct device *dev = &st->sd.spi->dev; 1025 u8 buf[AD7173_RESET_LENGTH]; 1026 unsigned int id; 1027 int ret; 1028 1029 /* reset the serial interface */ 1030 memset(buf, 0xff, AD7173_RESET_LENGTH); 1031 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 1032 if (ret < 0) 1033 return ret; 1034 1035 /* datasheet recommends a delay of at least 500us after reset */ 1036 fsleep(500); 1037 1038 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 1039 if (ret) 1040 return ret; 1041 1042 id &= AD7173_ID_MASK; 1043 if (id != st->info->id) 1044 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 1045 id, st->info->id); 1046 1047 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 1048 st->interface_mode = 0x0; 1049 1050 st->config_usage_counter = 0; 1051 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 1052 sizeof(*st->config_cnts), GFP_KERNEL); 1053 if (!st->config_cnts) 1054 return -ENOMEM; 1055 1056 ret = ad7173_calibrate_all(st, indio_dev); 1057 if (ret) 1058 return ret; 1059 1060 /* All channels are enabled by default after a reset */ 1061 return ad7173_disable_all(&st->sd); 1062 } 1063 1064 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 1065 u8 reference_select) 1066 { 1067 int vref; 1068 1069 switch (reference_select) { 1070 case AD7173_SETUP_REF_SEL_EXT_REF: 1071 vref = regulator_get_voltage(st->regulators[0].consumer); 1072 break; 1073 1074 case AD7173_SETUP_REF_SEL_EXT_REF2: 1075 vref = regulator_get_voltage(st->regulators[1].consumer); 1076 break; 1077 1078 case AD7173_SETUP_REF_SEL_INT_REF: 1079 vref = AD7173_VOLTAGE_INT_REF_uV; 1080 break; 1081 1082 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 1083 vref = regulator_get_voltage(st->regulators[2].consumer); 1084 break; 1085 1086 default: 1087 return -EINVAL; 1088 } 1089 1090 if (vref < 0) 1091 return vref; 1092 1093 return vref / (MICRO / MILLI); 1094 } 1095 1096 static int ad7173_read_raw(struct iio_dev *indio_dev, 1097 struct iio_chan_spec const *chan, 1098 int *val, int *val2, long info) 1099 { 1100 struct ad7173_state *st = iio_priv(indio_dev); 1101 struct ad7173_channel *ch = &st->channels[chan->address]; 1102 unsigned int reg; 1103 u64 temp; 1104 int ret; 1105 1106 switch (info) { 1107 case IIO_CHAN_INFO_RAW: 1108 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 1109 if (ret < 0) 1110 return ret; 1111 1112 if (ch->openwire_det_en) { 1113 ret = ad4111_openwire_event(indio_dev, chan); 1114 if (ret < 0) 1115 return ret; 1116 } 1117 1118 return IIO_VAL_INT; 1119 case IIO_CHAN_INFO_SCALE: 1120 1121 switch (chan->type) { 1122 case IIO_TEMP: 1123 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 1124 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 1125 *val = temp; 1126 *val2 = chan->scan_type.realbits; 1127 return IIO_VAL_FRACTIONAL_LOG2; 1128 case IIO_VOLTAGE: 1129 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1130 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 1131 1132 if (chan->channel < st->info->num_voltage_in_div) 1133 *val *= AD4111_DIVIDER_RATIO; 1134 return IIO_VAL_FRACTIONAL_LOG2; 1135 case IIO_CURRENT: 1136 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1137 *val /= AD4111_SHUNT_RESISTOR_OHM; 1138 *val2 = chan->scan_type.realbits - ch->cfg.bipolar; 1139 return IIO_VAL_FRACTIONAL_LOG2; 1140 default: 1141 return -EINVAL; 1142 } 1143 case IIO_CHAN_INFO_OFFSET: 1144 1145 switch (chan->type) { 1146 case IIO_TEMP: 1147 /* 0 Kelvin -> raw sample */ 1148 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 1149 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 1150 temp <<= chan->scan_type.realbits; 1151 temp = DIV_U64_ROUND_CLOSEST(temp, 1152 AD7173_VOLTAGE_INT_REF_uV * 1153 MILLI); 1154 *val = -temp; 1155 return IIO_VAL_INT; 1156 case IIO_VOLTAGE: 1157 case IIO_CURRENT: 1158 *val = -BIT(chan->scan_type.realbits - 1); 1159 return IIO_VAL_INT; 1160 default: 1161 return -EINVAL; 1162 } 1163 case IIO_CHAN_INFO_SAMP_FREQ: 1164 reg = st->channels[chan->address].cfg.odr; 1165 1166 *val = st->info->sinc5_data_rates[reg] / MILLI; 1167 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 1168 1169 return IIO_VAL_INT_PLUS_MICRO; 1170 default: 1171 return -EINVAL; 1172 } 1173 } 1174 1175 static int ad7173_write_raw(struct iio_dev *indio_dev, 1176 struct iio_chan_spec const *chan, 1177 int val, int val2, long info) 1178 { 1179 struct ad7173_state *st = iio_priv(indio_dev); 1180 struct ad7173_channel_config *cfg; 1181 unsigned int freq, i; 1182 int ret = 0; 1183 1184 if (!iio_device_claim_direct(indio_dev)) 1185 return -EBUSY; 1186 1187 switch (info) { 1188 /* 1189 * This attribute sets the sampling frequency for each channel individually. 1190 * There are no issues for raw or buffered reads of an individual channel. 1191 * 1192 * When multiple channels are enabled in buffered mode, the effective 1193 * sampling rate of a channel is lowered in correlation to the number 1194 * of channels enabled and the sampling rate of the other channels. 1195 * 1196 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps 1197 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3 1198 * will take 100ms each. 1199 * 1200 * This will cause the reading of CH1 to be actually done once every 1201 * 200.16ms, an effective rate of 4.99sps. 1202 */ 1203 case IIO_CHAN_INFO_SAMP_FREQ: 1204 freq = val * MILLI + val2 / MILLI; 1205 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 1206 if (freq >= st->info->sinc5_data_rates[i]) 1207 break; 1208 1209 cfg = &st->channels[chan->address].cfg; 1210 cfg->odr = i; 1211 cfg->live = false; 1212 break; 1213 1214 default: 1215 ret = -EINVAL; 1216 break; 1217 } 1218 1219 iio_device_release_direct(indio_dev); 1220 return ret; 1221 } 1222 1223 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 1224 const unsigned long *scan_mask) 1225 { 1226 struct ad7173_state *st = iio_priv(indio_dev); 1227 int i, ret; 1228 1229 for (i = 0; i < indio_dev->num_channels; i++) { 1230 if (test_bit(i, scan_mask)) 1231 ret = ad7173_set_channel(&st->sd, i); 1232 else 1233 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 1234 if (ret < 0) 1235 return ret; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1242 unsigned int writeval, unsigned int *readval) 1243 { 1244 struct ad7173_state *st = iio_priv(indio_dev); 1245 u8 reg_size; 1246 1247 if (reg == AD7173_REG_COMMS) 1248 reg_size = 1; 1249 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 1250 reg >= AD7173_REG_OFFSET(0)) 1251 reg_size = 3; 1252 else 1253 reg_size = 2; 1254 1255 if (readval) 1256 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 1257 1258 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 1259 } 1260 1261 static int ad7173_write_event_config(struct iio_dev *indio_dev, 1262 const struct iio_chan_spec *chan, 1263 enum iio_event_type type, 1264 enum iio_event_direction dir, 1265 bool state) 1266 { 1267 struct ad7173_state *st = iio_priv(indio_dev); 1268 struct ad7173_channel *adchan = &st->channels[chan->address]; 1269 1270 switch (type) { 1271 case IIO_EV_TYPE_FAULT: 1272 adchan->openwire_det_en = state; 1273 return 0; 1274 default: 1275 return -EINVAL; 1276 } 1277 } 1278 1279 static int ad7173_read_event_config(struct iio_dev *indio_dev, 1280 const struct iio_chan_spec *chan, 1281 enum iio_event_type type, 1282 enum iio_event_direction dir) 1283 { 1284 struct ad7173_state *st = iio_priv(indio_dev); 1285 struct ad7173_channel *adchan = &st->channels[chan->address]; 1286 1287 switch (type) { 1288 case IIO_EV_TYPE_FAULT: 1289 return adchan->openwire_det_en; 1290 default: 1291 return -EINVAL; 1292 } 1293 } 1294 1295 static const struct iio_event_spec ad4111_events[] = { 1296 { 1297 .type = IIO_EV_TYPE_FAULT, 1298 .dir = IIO_EV_DIR_FAULT_OPENWIRE, 1299 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1300 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 1301 }, 1302 }; 1303 1304 static const struct iio_info ad7173_info = { 1305 .read_raw = &ad7173_read_raw, 1306 .write_raw = &ad7173_write_raw, 1307 .debugfs_reg_access = &ad7173_debug_reg_access, 1308 .validate_trigger = ad_sd_validate_trigger, 1309 .update_scan_mode = ad7173_update_scan_mode, 1310 .write_event_config = ad7173_write_event_config, 1311 .read_event_config = ad7173_read_event_config, 1312 }; 1313 1314 static const struct iio_scan_type ad4113_scan_type = { 1315 .sign = 'u', 1316 .realbits = 16, 1317 .storagebits = 16, 1318 .endianness = IIO_BE, 1319 }; 1320 1321 static const struct iio_chan_spec ad7173_channel_template = { 1322 .type = IIO_VOLTAGE, 1323 .indexed = 1, 1324 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1325 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 1326 .scan_type = { 1327 .sign = 'u', 1328 .realbits = 24, 1329 .storagebits = 32, 1330 .endianness = IIO_BE, 1331 }, 1332 .ext_info = ad7173_calibsys_ext_info, 1333 }; 1334 1335 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 1336 .type = IIO_TEMP, 1337 .channel = AD7173_AIN_TEMP_POS, 1338 .channel2 = AD7173_AIN_TEMP_NEG, 1339 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1340 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1341 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1342 .scan_type = { 1343 .sign = 'u', 1344 .realbits = 24, 1345 .storagebits = 32, 1346 .endianness = IIO_BE, 1347 }, 1348 }; 1349 1350 static void ad7173_disable_regulators(void *data) 1351 { 1352 struct ad7173_state *st = data; 1353 1354 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1355 } 1356 1357 static void ad7173_clk_disable_unprepare(void *clk) 1358 { 1359 clk_disable_unprepare(clk); 1360 } 1361 1362 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 1363 unsigned int clk_sel) 1364 { 1365 int ret; 1366 1367 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 1368 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 1369 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 1370 1371 return ret; 1372 } 1373 1374 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 1375 unsigned long parent_rate) 1376 { 1377 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1378 1379 return st->info->clock / HZ_PER_KHZ; 1380 } 1381 1382 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 1383 { 1384 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1385 u32 clk_sel; 1386 1387 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 1388 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 1389 } 1390 1391 static int ad7173_clk_output_prepare(struct clk_hw *hw) 1392 { 1393 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1394 1395 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 1396 } 1397 1398 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 1399 { 1400 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1401 1402 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 1403 } 1404 1405 static const struct clk_ops ad7173_int_clk_ops = { 1406 .recalc_rate = ad7173_clk_recalc_rate, 1407 .is_enabled = ad7173_clk_output_is_enabled, 1408 .prepare = ad7173_clk_output_prepare, 1409 .unprepare = ad7173_clk_output_unprepare, 1410 }; 1411 1412 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 1413 { 1414 struct ad7173_state *st = iio_priv(indio_dev); 1415 struct device *dev = indio_dev->dev.parent; 1416 struct fwnode_handle *fwnode = dev_fwnode(dev); 1417 struct clk_init_data init = {}; 1418 int ret; 1419 1420 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1421 return 0; 1422 1423 init.name = fwnode_get_name(fwnode); 1424 init.ops = &ad7173_int_clk_ops; 1425 1426 st->int_clk_hw.init = &init; 1427 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 1428 if (ret) 1429 return ret; 1430 1431 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1432 &st->int_clk_hw); 1433 } 1434 1435 static int ad4111_validate_current_ain(struct ad7173_state *st, 1436 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL]) 1437 { 1438 struct device *dev = &st->sd.spi->dev; 1439 1440 if (!st->info->has_current_inputs) 1441 return dev_err_probe(dev, -EINVAL, 1442 "Model %s does not support current channels\n", 1443 st->info->name); 1444 1445 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config)) 1446 return dev_err_probe(dev, -EINVAL, 1447 "For current channels single-channel must be <[0-3]>\n"); 1448 1449 return 0; 1450 } 1451 1452 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st, 1453 unsigned int ain0, unsigned int ain1) 1454 { 1455 struct device *dev = &st->sd.spi->dev; 1456 bool special_input0, special_input1; 1457 1458 /* (AVDD1-AVSS)/5 power supply monitoring */ 1459 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG && 1460 st->info->has_pow_supply_monitoring) 1461 return 0; 1462 1463 special_input0 = AD7173_IS_REF_INPUT(ain0) || 1464 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1465 special_input1 = AD7173_IS_REF_INPUT(ain1) || 1466 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1467 1468 if ((ain0 >= st->info->num_voltage_in && !special_input0) || 1469 (ain1 >= st->info->num_voltage_in && !special_input1)) { 1470 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT) 1471 return dev_err_probe(dev, -EINVAL, 1472 "VINCOM not supported for %s\n", st->info->name); 1473 1474 return dev_err_probe(dev, -EINVAL, 1475 "Input pin number out of range for pair (%d %d).\n", 1476 ain0, ain1); 1477 } 1478 1479 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) || 1480 AD4111_IS_VINCOM_MISMATCH(ain1, ain0)) 1481 return dev_err_probe(dev, -EINVAL, 1482 "VINCOM must be paired with inputs having divider.\n"); 1483 1484 if (!special_input0 && !special_input1 && 1485 ((ain0 >= st->info->num_voltage_in_div) != 1486 (ain1 >= st->info->num_voltage_in_div))) 1487 return dev_err_probe(dev, -EINVAL, 1488 "Both inputs must either have a voltage divider or not have: (%d %d).\n", 1489 ain0, ain1); 1490 1491 return 0; 1492 } 1493 1494 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel) 1495 { 1496 struct device *dev = &st->sd.spi->dev; 1497 int ret; 1498 1499 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref) 1500 return dev_err_probe(dev, -EINVAL, 1501 "Internal reference is not available on current model.\n"); 1502 1503 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 1504 return dev_err_probe(dev, -EINVAL, 1505 "External reference 2 is not available on current model.\n"); 1506 1507 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 1508 if (ret < 0) 1509 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1510 ref_sel); 1511 1512 return 0; 1513 } 1514 1515 static int ad7173_validate_openwire_ain_inputs(struct ad7173_state *st, 1516 bool differential, 1517 unsigned int ain0, 1518 unsigned int ain1) 1519 { 1520 /* 1521 * If the channel is configured as differential, 1522 * the ad4111 requires specific ains to be used together 1523 */ 1524 if (differential) 1525 return (ain0 % 2) ? (ain0 - 1) == ain1 : (ain0 + 1) == ain1; 1526 1527 return ain1 == AD4111_VINCOM_INPUT; 1528 } 1529 1530 static unsigned int ad7173_calc_openwire_thrsh_raw(struct ad7173_state *st, 1531 struct iio_chan_spec *chan, 1532 struct ad7173_channel *chan_st_priv, 1533 unsigned int thrsh_mv) { 1534 unsigned int thrsh_raw; 1535 1536 thrsh_raw = 1537 BIT(chan->scan_type.realbits - !!(chan_st_priv->cfg.bipolar)) 1538 * thrsh_mv 1539 / ad7173_get_ref_voltage_milli(st, chan_st_priv->cfg.ref_sel); 1540 if (chan->channel < st->info->num_voltage_in_div) 1541 thrsh_raw /= AD4111_DIVIDER_RATIO; 1542 1543 return thrsh_raw; 1544 } 1545 1546 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 1547 { 1548 struct ad7173_channel *chans_st_arr, *chan_st_priv; 1549 struct ad7173_state *st = iio_priv(indio_dev); 1550 struct device *dev = indio_dev->dev.parent; 1551 struct iio_chan_spec *chan_arr, *chan; 1552 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0; 1553 int ref_sel, ret, num_channels; 1554 1555 num_channels = device_get_child_node_count(dev); 1556 1557 if (st->info->has_temp) 1558 num_channels++; 1559 1560 if (num_channels == 0) 1561 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1562 1563 if (num_channels > st->info->num_channels) 1564 return dev_err_probe(dev, -EINVAL, 1565 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n", 1566 st->info->num_channels); 1567 1568 indio_dev->num_channels = num_channels; 1569 st->num_channels = num_channels; 1570 1571 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 1572 st->num_channels, GFP_KERNEL); 1573 if (!chan_arr) 1574 return -ENOMEM; 1575 1576 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 1577 GFP_KERNEL); 1578 if (!chans_st_arr) 1579 return -ENOMEM; 1580 1581 indio_dev->channels = chan_arr; 1582 st->channels = chans_st_arr; 1583 1584 if (st->info->has_temp) { 1585 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 1586 chan_st_priv = &chans_st_arr[chan_index]; 1587 chan_st_priv->ain = 1588 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 1589 chan_arr[chan_index].channel2); 1590 chan_st_priv->cfg.bipolar = false; 1591 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1592 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1593 chan_st_priv->cfg.openwire_comp_chan = -1; 1594 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1595 if (st->info->data_reg_only_16bit) 1596 chan_arr[chan_index].scan_type = ad4113_scan_type; 1597 1598 chan_index++; 1599 } 1600 1601 device_for_each_child_node_scoped(dev, child) { 1602 bool is_current_chan = false; 1603 1604 chan = &chan_arr[chan_index]; 1605 *chan = ad7173_channel_template; 1606 chan_st_priv = &chans_st_arr[chan_index]; 1607 ret = fwnode_property_read_u32_array(child, "diff-channels", 1608 ain, ARRAY_SIZE(ain)); 1609 if (ret) { 1610 ret = fwnode_property_read_u32(child, "single-channel", 1611 ain); 1612 if (ret) 1613 return dev_err_probe(dev, ret, 1614 "Channel must define one of diff-channels or single-channel.\n"); 1615 1616 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel"); 1617 } else { 1618 chan->differential = true; 1619 } 1620 1621 if (is_current_chan) { 1622 ret = ad4111_validate_current_ain(st, ain); 1623 if (ret) 1624 return ret; 1625 } else { 1626 if (!chan->differential) { 1627 ret = fwnode_property_read_u32(child, 1628 "common-mode-channel", ain + 1); 1629 if (ret) 1630 return dev_err_probe(dev, ret, 1631 "common-mode-channel must be defined for single-ended channels.\n"); 1632 } 1633 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]); 1634 if (ret) 1635 return ret; 1636 } 1637 1638 ret = fwnode_property_match_property_string(child, 1639 "adi,reference-select", 1640 ad7173_ref_sel_str, 1641 ARRAY_SIZE(ad7173_ref_sel_str)); 1642 if (ret < 0) 1643 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1644 else 1645 ref_sel = ret; 1646 1647 ret = ad7173_validate_reference(st, ref_sel); 1648 if (ret) 1649 return ret; 1650 1651 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 1652 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1653 chan_st_priv->cfg.ref_sel = ref_sel; 1654 1655 chan->address = chan_index; 1656 chan->scan_index = chan_index; 1657 chan->channel = ain[0]; 1658 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1659 chan_st_priv->cfg.odr = 0; 1660 chan_st_priv->cfg.openwire_comp_chan = -1; 1661 1662 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 1663 if (chan_st_priv->cfg.bipolar) 1664 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 1665 1666 if (is_current_chan) { 1667 chan->type = IIO_CURRENT; 1668 chan->differential = false; 1669 chan->channel2 = 0; 1670 chan_st_priv->ain = ad4111_current_channel_config[ain[0]]; 1671 } else { 1672 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1673 chan->channel2 = ain[1]; 1674 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 1675 if (st->info->has_openwire_det && 1676 ad7173_validate_openwire_ain_inputs(st, chan->differential, ain[0], ain[1])) { 1677 chan->event_spec = ad4111_events; 1678 chan->num_event_specs = ARRAY_SIZE(ad4111_events); 1679 chan_st_priv->cfg.openwire_thrsh_raw = 1680 ad7173_calc_openwire_thrsh_raw(st, chan, chan_st_priv, 1681 AD4111_OW_DET_THRSH_MV); 1682 } 1683 } 1684 1685 if (st->info->data_reg_only_16bit) 1686 chan_arr[chan_index].scan_type = ad4113_scan_type; 1687 1688 chan_index++; 1689 } 1690 return 0; 1691 } 1692 1693 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1694 { 1695 struct ad7173_state *st = iio_priv(indio_dev); 1696 struct device *dev = indio_dev->dev.parent; 1697 int ret; 1698 1699 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1700 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1701 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1702 1703 /* 1704 * If a regulator is not available, it will be set to a dummy regulator. 1705 * Each channel reference is checked with regulator_get_voltage() before 1706 * setting attributes so if any channel uses a dummy supply the driver 1707 * probe will fail. 1708 */ 1709 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1710 st->regulators); 1711 if (ret) 1712 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1713 1714 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1715 if (ret) 1716 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1717 1718 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1719 if (ret) 1720 return dev_err_probe(dev, ret, 1721 "Failed to add regulators disable action\n"); 1722 1723 ret = device_property_match_property_string(dev, "clock-names", 1724 ad7173_clk_sel, 1725 ARRAY_SIZE(ad7173_clk_sel)); 1726 if (ret < 0) { 1727 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1728 AD7173_ADC_MODE_CLOCKSEL_INT); 1729 ad7173_register_clk_provider(indio_dev); 1730 } else { 1731 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1732 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1733 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]); 1734 if (IS_ERR(st->ext_clk)) 1735 return dev_err_probe(dev, PTR_ERR(st->ext_clk), 1736 "Failed to get external clock\n"); 1737 1738 ret = clk_prepare_enable(st->ext_clk); 1739 if (ret) 1740 return dev_err_probe(dev, ret, 1741 "Failed to enable external clock\n"); 1742 1743 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare, 1744 st->ext_clk); 1745 if (ret) 1746 return ret; 1747 } 1748 1749 return ad7173_fw_parse_channel_config(indio_dev); 1750 } 1751 1752 static int ad7173_probe(struct spi_device *spi) 1753 { 1754 struct device *dev = &spi->dev; 1755 struct ad7173_state *st; 1756 struct iio_dev *indio_dev; 1757 int ret; 1758 1759 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1760 if (!indio_dev) 1761 return -ENOMEM; 1762 1763 st = iio_priv(indio_dev); 1764 st->info = spi_get_device_match_data(spi); 1765 if (!st->info) 1766 return -ENODEV; 1767 1768 ida_init(&st->cfg_slots_status); 1769 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1770 if (ret) 1771 return ret; 1772 1773 indio_dev->name = st->info->name; 1774 indio_dev->modes = INDIO_DIRECT_MODE; 1775 indio_dev->info = &ad7173_info; 1776 1777 spi->mode = SPI_MODE_3; 1778 spi_setup(spi); 1779 1780 ret = ad_sd_init(&st->sd, indio_dev, spi, st->info->sd_info); 1781 if (ret) 1782 return ret; 1783 1784 ret = ad7173_fw_parse_device_config(indio_dev); 1785 if (ret) 1786 return ret; 1787 1788 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1789 if (ret) 1790 return ret; 1791 1792 ret = ad7173_setup(indio_dev); 1793 if (ret) 1794 return ret; 1795 1796 ret = devm_iio_device_register(dev, indio_dev); 1797 if (ret) 1798 return ret; 1799 1800 if (IS_ENABLED(CONFIG_GPIOLIB)) 1801 return ad7173_gpio_init(st); 1802 1803 return 0; 1804 } 1805 1806 static const struct of_device_id ad7173_of_match[] = { 1807 { .compatible = "adi,ad4111", .data = &ad4111_device_info }, 1808 { .compatible = "adi,ad4112", .data = &ad4112_device_info }, 1809 { .compatible = "adi,ad4113", .data = &ad4113_device_info }, 1810 { .compatible = "adi,ad4114", .data = &ad4114_device_info }, 1811 { .compatible = "adi,ad4115", .data = &ad4115_device_info }, 1812 { .compatible = "adi,ad4116", .data = &ad4116_device_info }, 1813 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info }, 1814 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info }, 1815 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info }, 1816 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info }, 1817 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info }, 1818 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info }, 1819 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info }, 1820 { } 1821 }; 1822 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1823 1824 static const struct spi_device_id ad7173_id_table[] = { 1825 { "ad4111", (kernel_ulong_t)&ad4111_device_info }, 1826 { "ad4112", (kernel_ulong_t)&ad4112_device_info }, 1827 { "ad4113", (kernel_ulong_t)&ad4113_device_info }, 1828 { "ad4114", (kernel_ulong_t)&ad4114_device_info }, 1829 { "ad4115", (kernel_ulong_t)&ad4115_device_info }, 1830 { "ad4116", (kernel_ulong_t)&ad4116_device_info }, 1831 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info }, 1832 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info }, 1833 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info }, 1834 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info }, 1835 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info }, 1836 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info }, 1837 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info }, 1838 { } 1839 }; 1840 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1841 1842 static struct spi_driver ad7173_driver = { 1843 .driver = { 1844 .name = "ad7173", 1845 .of_match_table = ad7173_of_match, 1846 }, 1847 .probe = ad7173_probe, 1848 .id_table = ad7173_id_table, 1849 }; 1850 module_spi_driver(ad7173_driver); 1851 1852 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1853 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1854 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1855 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver"); 1856 MODULE_LICENSE("GPL"); 1857