1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7124 SPI ADC driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 * Copyright 2025 BayLibre, SAS 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/kernel.h> 18 #include <linux/kfifo.h> 19 #include <linux/minmax.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/property.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/spi/spi.h> 25 #include <linux/sprintf.h> 26 #include <linux/units.h> 27 28 #include <linux/iio/iio.h> 29 #include <linux/iio/adc/ad_sigma_delta.h> 30 #include <linux/iio/sysfs.h> 31 32 /* AD7124 registers */ 33 #define AD7124_COMMS 0x00 34 #define AD7124_STATUS 0x00 35 #define AD7124_ADC_CONTROL 0x01 36 #define AD7124_DATA 0x02 37 #define AD7124_IO_CONTROL_1 0x03 38 #define AD7124_IO_CONTROL_2 0x04 39 #define AD7124_ID 0x05 40 #define AD7124_ERROR 0x06 41 #define AD7124_ERROR_EN 0x07 42 #define AD7124_MCLK_COUNT 0x08 43 #define AD7124_CHANNEL(x) (0x09 + (x)) 44 #define AD7124_CONFIG(x) (0x19 + (x)) 45 #define AD7124_FILTER(x) (0x21 + (x)) 46 #define AD7124_OFFSET(x) (0x29 + (x)) 47 #define AD7124_GAIN(x) (0x31 + (x)) 48 49 /* AD7124_STATUS */ 50 #define AD7124_STATUS_POR_FLAG BIT(4) 51 52 /* AD7124_ADC_CONTROL */ 53 #define AD7124_ADC_CONTROL_CLK_SEL GENMASK(1, 0) 54 #define AD7124_ADC_CONTROL_CLK_SEL_INT 0 55 #define AD7124_ADC_CONTROL_CLK_SEL_INT_OUT 1 56 #define AD7124_ADC_CONTROL_CLK_SEL_EXT 2 57 #define AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4 3 58 #define AD7124_ADC_CONTROL_MODE GENMASK(5, 2) 59 #define AD7124_ADC_CONTROL_MODE_CONTINUOUS 0 60 #define AD7124_ADC_CONTROL_MODE_SINGLE 1 61 #define AD7124_ADC_CONTROL_MODE_STANDBY 2 62 #define AD7124_ADC_CONTROL_MODE_POWERDOWN 3 63 #define AD7124_ADC_CONTROL_MODE_IDLE 4 64 #define AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB 5 /* Internal Zero-Scale Calibration */ 65 #define AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB 6 /* Internal Full-Scale Calibration */ 66 #define AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB 7 /* System Zero-Scale Calibration */ 67 #define AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB 8 /* System Full-Scale Calibration */ 68 #define AD7124_ADC_CONTROL_POWER_MODE GENMASK(7, 6) 69 #define AD7124_ADC_CONTROL_POWER_MODE_LOW 0 70 #define AD7124_ADC_CONTROL_POWER_MODE_MID 1 71 #define AD7124_ADC_CONTROL_POWER_MODE_FULL 2 72 #define AD7124_ADC_CONTROL_REF_EN BIT(8) 73 #define AD7124_ADC_CONTROL_DATA_STATUS BIT(10) 74 75 /* AD7124_ID */ 76 #define AD7124_ID_SILICON_REVISION GENMASK(3, 0) 77 #define AD7124_ID_DEVICE_ID GENMASK(7, 4) 78 #define AD7124_ID_DEVICE_ID_AD7124_4 0x0 79 #define AD7124_ID_DEVICE_ID_AD7124_8 0x1 80 81 /* AD7124_CHANNEL_X */ 82 #define AD7124_CHANNEL_ENABLE BIT(15) 83 #define AD7124_CHANNEL_SETUP GENMASK(14, 12) 84 #define AD7124_CHANNEL_AINP GENMASK(9, 5) 85 #define AD7124_CHANNEL_AINM GENMASK(4, 0) 86 #define AD7124_CHANNEL_AINx_TEMPSENSOR 16 87 #define AD7124_CHANNEL_AINx_AVSS 17 88 89 /* AD7124_CONFIG_X */ 90 #define AD7124_CONFIG_BIPOLAR BIT(11) 91 #define AD7124_CONFIG_IN_BUFF GENMASK(6, 5) 92 #define AD7124_CONFIG_AIN_BUFP BIT(6) 93 #define AD7124_CONFIG_AIN_BUFM BIT(5) 94 #define AD7124_CONFIG_REF_SEL GENMASK(4, 3) 95 #define AD7124_CONFIG_PGA GENMASK(2, 0) 96 97 /* AD7124_FILTER_X */ 98 #define AD7124_FILTER_FILTER GENMASK(23, 21) 99 #define AD7124_FILTER_FILTER_SINC4 0 100 #define AD7124_FILTER_FILTER_SINC3 2 101 #define AD7124_FILTER_FILTER_SINC4_SINC1 4 102 #define AD7124_FILTER_FILTER_SINC3_SINC1 5 103 #define AD7124_FILTER_FILTER_SINC3_PF 7 104 #define AD7124_FILTER_REJ60 BIT(20) 105 #define AD7124_FILTER_POST_FILTER GENMASK(19, 17) 106 #define AD7124_FILTER_POST_FILTER_47dB 2 107 #define AD7124_FILTER_POST_FILTER_62dB 3 108 #define AD7124_FILTER_POST_FILTER_86dB 5 109 #define AD7124_FILTER_POST_FILTER_92dB 6 110 #define AD7124_FILTER_SINGLE_CYCLE BIT(16) 111 #define AD7124_FILTER_FS GENMASK(10, 0) 112 113 #define AD7124_MAX_CONFIGS 8 114 #define AD7124_MAX_CHANNELS 16 115 116 #define AD7124_INT_CLK_HZ 614400 117 118 /* AD7124 input sources */ 119 120 enum ad7124_ref_sel { 121 AD7124_REFIN1, 122 AD7124_REFIN2, 123 AD7124_INT_REF, 124 AD7124_AVDD_REF, 125 }; 126 127 enum ad7124_power_mode { 128 AD7124_LOW_POWER, 129 AD7124_MID_POWER, 130 AD7124_FULL_POWER, 131 }; 132 133 static const unsigned int ad7124_gain[8] = { 134 1, 2, 4, 8, 16, 32, 64, 128 135 }; 136 137 static const unsigned int ad7124_reg_size[] = { 138 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2, 139 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 140 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 141 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 142 3, 3, 3, 3, 3 143 }; 144 145 static const int ad7124_master_clk_freq_hz[3] = { 146 [AD7124_LOW_POWER] = AD7124_INT_CLK_HZ / 8, 147 [AD7124_MID_POWER] = AD7124_INT_CLK_HZ / 4, 148 [AD7124_FULL_POWER] = AD7124_INT_CLK_HZ, 149 }; 150 151 static const char * const ad7124_ref_names[] = { 152 [AD7124_REFIN1] = "refin1", 153 [AD7124_REFIN2] = "refin2", 154 [AD7124_INT_REF] = "int", 155 [AD7124_AVDD_REF] = "avdd", 156 }; 157 158 struct ad7124_chip_info { 159 const char *name; 160 unsigned int chip_id; 161 unsigned int num_inputs; 162 }; 163 164 enum ad7124_filter_type { 165 AD7124_FILTER_TYPE_SINC3, 166 AD7124_FILTER_TYPE_SINC3_PF1, 167 AD7124_FILTER_TYPE_SINC3_PF2, 168 AD7124_FILTER_TYPE_SINC3_PF3, 169 AD7124_FILTER_TYPE_SINC3_PF4, 170 AD7124_FILTER_TYPE_SINC3_REJ60, 171 AD7124_FILTER_TYPE_SINC3_SINC1, 172 AD7124_FILTER_TYPE_SINC4, 173 AD7124_FILTER_TYPE_SINC4_REJ60, 174 AD7124_FILTER_TYPE_SINC4_SINC1, 175 }; 176 177 struct ad7124_channel_config { 178 bool live; 179 unsigned int cfg_slot; 180 unsigned int requested_odr; 181 unsigned int requested_odr_micro; 182 /* 183 * Following fields are used to compare for equality. If you 184 * make adaptations in it, you most likely also have to adapt 185 * ad7124_find_similar_live_cfg(), too. 186 */ 187 struct_group(config_props, 188 enum ad7124_ref_sel refsel; 189 bool bipolar; 190 bool buf_positive; 191 bool buf_negative; 192 unsigned int vref_mv; 193 unsigned int pga_bits; 194 unsigned int odr_sel_bits; 195 enum ad7124_filter_type filter_type; 196 unsigned int calibration_offset; 197 unsigned int calibration_gain; 198 ); 199 }; 200 201 struct ad7124_channel { 202 unsigned int nr; 203 struct ad7124_channel_config cfg; 204 unsigned int ain; 205 unsigned int slot; 206 u8 syscalib_mode; 207 }; 208 209 struct ad7124_state { 210 const struct ad7124_chip_info *chip_info; 211 struct ad_sigma_delta sd; 212 struct ad7124_channel *channels; 213 struct regulator *vref[4]; 214 u32 clk_hz; 215 unsigned int adc_control; 216 unsigned int num_channels; 217 struct mutex cfgs_lock; /* lock for configs access */ 218 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */ 219 220 /* 221 * Stores the power-on reset value for the GAIN(x) registers which are 222 * needed for measurements at gain 1 (i.e. CONFIG(x).PGA == 0) 223 */ 224 unsigned int gain_default; 225 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); 226 }; 227 228 static const struct ad7124_chip_info ad7124_4_chip_info = { 229 .name = "ad7124-4", 230 .chip_id = AD7124_ID_DEVICE_ID_AD7124_4, 231 .num_inputs = 8, 232 }; 233 234 static const struct ad7124_chip_info ad7124_8_chip_info = { 235 .name = "ad7124-8", 236 .chip_id = AD7124_ID_DEVICE_ID_AD7124_8, 237 .num_inputs = 16, 238 }; 239 240 static int ad7124_find_closest_match(const int *array, 241 unsigned int size, int val) 242 { 243 int i, idx; 244 unsigned int diff_new, diff_old; 245 246 diff_old = U32_MAX; 247 idx = 0; 248 249 for (i = 0; i < size; i++) { 250 diff_new = abs(val - array[i]); 251 if (diff_new < diff_old) { 252 diff_old = diff_new; 253 idx = i; 254 } 255 } 256 257 return idx; 258 } 259 260 static int ad7124_spi_write_mask(struct ad7124_state *st, 261 unsigned int addr, 262 unsigned long mask, 263 unsigned int val, 264 unsigned int bytes) 265 { 266 unsigned int readval; 267 int ret; 268 269 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval); 270 if (ret < 0) 271 return ret; 272 273 readval &= ~mask; 274 readval |= val; 275 276 return ad_sd_write_reg(&st->sd, addr, bytes, readval); 277 } 278 279 static int ad7124_set_mode(struct ad_sigma_delta *sd, 280 enum ad_sigma_delta_mode mode) 281 { 282 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 283 284 st->adc_control &= ~AD7124_ADC_CONTROL_MODE; 285 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, mode); 286 287 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 288 } 289 290 static u32 ad7124_get_fclk_hz(struct ad7124_state *st) 291 { 292 enum ad7124_power_mode power_mode; 293 u32 fclk_hz; 294 295 power_mode = FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, st->adc_control); 296 fclk_hz = st->clk_hz; 297 298 switch (power_mode) { 299 case AD7124_LOW_POWER: 300 fclk_hz /= 8; 301 break; 302 case AD7124_MID_POWER: 303 fclk_hz /= 4; 304 break; 305 default: 306 break; 307 } 308 309 return fclk_hz; 310 } 311 312 static u32 ad7124_get_fs_factor(struct ad7124_state *st, unsigned int channel) 313 { 314 enum ad7124_power_mode power_mode = 315 FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, st->adc_control); 316 u32 avg = power_mode == AD7124_LOW_POWER ? 8 : 16; 317 318 /* 319 * These are the "zero-latency" factors from the data sheet. For the 320 * sinc1 filters, these aren't documented, but derived by taking the 321 * single-channel formula from the sinc1 section of the data sheet and 322 * multiplying that by the sinc3/4 factor from the corresponding zero- 323 * latency sections. 324 */ 325 switch (st->channels[channel].cfg.filter_type) { 326 case AD7124_FILTER_TYPE_SINC4: 327 case AD7124_FILTER_TYPE_SINC4_REJ60: 328 return 4 * 32; 329 case AD7124_FILTER_TYPE_SINC4_SINC1: 330 return 4 * avg * 32; 331 case AD7124_FILTER_TYPE_SINC3_SINC1: 332 return 3 * avg * 32; 333 default: 334 return 3 * 32; 335 } 336 } 337 338 static u32 ad7124_get_fadc_divisor(struct ad7124_state *st, unsigned int channel) 339 { 340 u32 factor = ad7124_get_fs_factor(st, channel); 341 342 /* 343 * The output data rate (f_ADC) is f_CLK / divisor. We are returning 344 * the divisor. 345 */ 346 return st->channels[channel].cfg.odr_sel_bits * factor; 347 } 348 349 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel) 350 { 351 struct ad7124_channel_config *cfg = &st->channels[channel].cfg; 352 unsigned int fclk, factor, divisor, odr_sel_bits; 353 354 fclk = ad7124_get_fclk_hz(st); 355 factor = ad7124_get_fs_factor(st, channel); 356 357 /* 358 * FS[10:0] = fCLK / (fADC x 32 * N) where: 359 * fADC is the output data rate 360 * fCLK is the master clock frequency 361 * N is number of conversions per sample (depends on filter type) 362 * FS[10:0] are the bits in the filter register 363 * FS[10:0] can have a value from 1 to 2047 364 */ 365 divisor = cfg->requested_odr * factor + 366 cfg->requested_odr_micro * factor / MICRO; 367 odr_sel_bits = clamp(DIV_ROUND_CLOSEST(fclk, divisor), 1, 2047); 368 369 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits) 370 st->channels[channel].cfg.live = false; 371 372 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits; 373 } 374 375 static int ad7124_get_3db_filter_factor(struct ad7124_state *st, 376 unsigned int channel) 377 { 378 struct ad7124_channel_config *cfg = &st->channels[channel].cfg; 379 380 /* 381 * 3dB point is the f_CLK rate times some factor. This functions returns 382 * the factor times 1000. 383 */ 384 switch (cfg->filter_type) { 385 case AD7124_FILTER_TYPE_SINC3: 386 case AD7124_FILTER_TYPE_SINC3_REJ60: 387 case AD7124_FILTER_TYPE_SINC3_SINC1: 388 return 272; 389 case AD7124_FILTER_TYPE_SINC4: 390 case AD7124_FILTER_TYPE_SINC4_REJ60: 391 case AD7124_FILTER_TYPE_SINC4_SINC1: 392 return 230; 393 case AD7124_FILTER_TYPE_SINC3_PF1: 394 return 633; 395 case AD7124_FILTER_TYPE_SINC3_PF2: 396 return 605; 397 case AD7124_FILTER_TYPE_SINC3_PF3: 398 return 669; 399 case AD7124_FILTER_TYPE_SINC3_PF4: 400 return 759; 401 default: 402 return -EINVAL; 403 } 404 } 405 406 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st, 407 struct ad7124_channel_config *cfg) 408 { 409 struct ad7124_channel_config *cfg_aux; 410 int i; 411 412 /* 413 * This is just to make sure that the comparison is adapted after 414 * struct ad7124_channel_config was changed. 415 */ 416 static_assert(sizeof_field(struct ad7124_channel_config, config_props) == 417 sizeof(struct { 418 enum ad7124_ref_sel refsel; 419 bool bipolar; 420 bool buf_positive; 421 bool buf_negative; 422 unsigned int vref_mv; 423 unsigned int pga_bits; 424 unsigned int odr_sel_bits; 425 enum ad7124_filter_type filter_type; 426 unsigned int calibration_offset; 427 unsigned int calibration_gain; 428 })); 429 430 for (i = 0; i < st->num_channels; i++) { 431 cfg_aux = &st->channels[i].cfg; 432 433 if (cfg_aux->live && 434 cfg->refsel == cfg_aux->refsel && 435 cfg->bipolar == cfg_aux->bipolar && 436 cfg->buf_positive == cfg_aux->buf_positive && 437 cfg->buf_negative == cfg_aux->buf_negative && 438 cfg->vref_mv == cfg_aux->vref_mv && 439 cfg->pga_bits == cfg_aux->pga_bits && 440 cfg->odr_sel_bits == cfg_aux->odr_sel_bits && 441 cfg->filter_type == cfg_aux->filter_type && 442 cfg->calibration_offset == cfg_aux->calibration_offset && 443 cfg->calibration_gain == cfg_aux->calibration_gain) 444 return cfg_aux; 445 } 446 447 return NULL; 448 } 449 450 static int ad7124_find_free_config_slot(struct ad7124_state *st) 451 { 452 unsigned int free_cfg_slot; 453 454 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS); 455 if (free_cfg_slot == AD7124_MAX_CONFIGS) 456 return -1; 457 458 return free_cfg_slot; 459 } 460 461 /* Only called during probe, so dev_err_probe() can be used */ 462 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg) 463 { 464 struct device *dev = &st->sd.spi->dev; 465 unsigned int refsel = cfg->refsel; 466 467 switch (refsel) { 468 case AD7124_REFIN1: 469 case AD7124_REFIN2: 470 case AD7124_AVDD_REF: 471 if (IS_ERR(st->vref[refsel])) 472 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]), 473 "Error, trying to use external voltage reference without a %s regulator.\n", 474 ad7124_ref_names[refsel]); 475 476 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]); 477 /* Conversion from uV to mV */ 478 cfg->vref_mv /= 1000; 479 return 0; 480 case AD7124_INT_REF: 481 cfg->vref_mv = 2500; 482 st->adc_control |= AD7124_ADC_CONTROL_REF_EN; 483 return 0; 484 default: 485 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel); 486 } 487 } 488 489 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg, 490 unsigned int cfg_slot) 491 { 492 unsigned int val, filter; 493 unsigned int rej60 = 0; 494 unsigned int post = 0; 495 int ret; 496 497 cfg->cfg_slot = cfg_slot; 498 499 ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg->cfg_slot), 3, cfg->calibration_offset); 500 if (ret) 501 return ret; 502 503 ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg->cfg_slot), 3, cfg->calibration_gain); 504 if (ret) 505 return ret; 506 507 val = FIELD_PREP(AD7124_CONFIG_BIPOLAR, cfg->bipolar) | 508 FIELD_PREP(AD7124_CONFIG_REF_SEL, cfg->refsel) | 509 (cfg->buf_positive ? AD7124_CONFIG_AIN_BUFP : 0) | 510 (cfg->buf_negative ? AD7124_CONFIG_AIN_BUFM : 0) | 511 FIELD_PREP(AD7124_CONFIG_PGA, cfg->pga_bits); 512 513 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val); 514 if (ret < 0) 515 return ret; 516 517 switch (cfg->filter_type) { 518 case AD7124_FILTER_TYPE_SINC3: 519 filter = AD7124_FILTER_FILTER_SINC3; 520 break; 521 case AD7124_FILTER_TYPE_SINC3_PF1: 522 filter = AD7124_FILTER_FILTER_SINC3_PF; 523 post = AD7124_FILTER_POST_FILTER_47dB; 524 break; 525 case AD7124_FILTER_TYPE_SINC3_PF2: 526 filter = AD7124_FILTER_FILTER_SINC3_PF; 527 post = AD7124_FILTER_POST_FILTER_62dB; 528 break; 529 case AD7124_FILTER_TYPE_SINC3_PF3: 530 filter = AD7124_FILTER_FILTER_SINC3_PF; 531 post = AD7124_FILTER_POST_FILTER_86dB; 532 break; 533 case AD7124_FILTER_TYPE_SINC3_PF4: 534 filter = AD7124_FILTER_FILTER_SINC3_PF; 535 post = AD7124_FILTER_POST_FILTER_92dB; 536 break; 537 case AD7124_FILTER_TYPE_SINC3_REJ60: 538 filter = AD7124_FILTER_FILTER_SINC3; 539 rej60 = 1; 540 break; 541 case AD7124_FILTER_TYPE_SINC3_SINC1: 542 filter = AD7124_FILTER_FILTER_SINC3_SINC1; 543 break; 544 case AD7124_FILTER_TYPE_SINC4: 545 filter = AD7124_FILTER_FILTER_SINC4; 546 break; 547 case AD7124_FILTER_TYPE_SINC4_REJ60: 548 filter = AD7124_FILTER_FILTER_SINC4; 549 rej60 = 1; 550 break; 551 case AD7124_FILTER_TYPE_SINC4_SINC1: 552 filter = AD7124_FILTER_FILTER_SINC4_SINC1; 553 break; 554 default: 555 return -EINVAL; 556 } 557 558 /* 559 * NB: AD7124_FILTER_SINGLE_CYCLE is always set so that we get the same 560 * sampling frequency even when only one channel is enabled in a 561 * buffered read. If it was not set, the N in ad7124_set_channel_odr() 562 * would be 1 and we would get a faster sampling frequency than what 563 * was requested. 564 */ 565 return ad_sd_write_reg(&st->sd, AD7124_FILTER(cfg->cfg_slot), 3, 566 FIELD_PREP(AD7124_FILTER_FILTER, filter) | 567 FIELD_PREP(AD7124_FILTER_REJ60, rej60) | 568 FIELD_PREP(AD7124_FILTER_POST_FILTER, post) | 569 AD7124_FILTER_SINGLE_CYCLE | 570 FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits)); 571 } 572 573 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st) 574 { 575 struct ad7124_channel_config *lru_cfg; 576 struct ad7124_channel_config *cfg; 577 int ret; 578 int i; 579 580 /* 581 * Pop least recently used config from the fifo 582 * in order to make room for the new one 583 */ 584 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg); 585 if (ret <= 0) 586 return NULL; 587 588 lru_cfg->live = false; 589 590 /* mark slot as free */ 591 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0); 592 593 /* invalidate all other configs that pointed to this one */ 594 for (i = 0; i < st->num_channels; i++) { 595 cfg = &st->channels[i].cfg; 596 597 if (cfg->cfg_slot == lru_cfg->cfg_slot) 598 cfg->live = false; 599 } 600 601 return lru_cfg; 602 } 603 604 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg) 605 { 606 struct ad7124_channel_config *lru_cfg; 607 int free_cfg_slot; 608 609 free_cfg_slot = ad7124_find_free_config_slot(st); 610 if (free_cfg_slot >= 0) { 611 /* push the new config in configs queue */ 612 kfifo_put(&st->live_cfgs_fifo, cfg); 613 } else { 614 /* pop one config to make room for the new one */ 615 lru_cfg = ad7124_pop_config(st); 616 if (!lru_cfg) 617 return -EINVAL; 618 619 /* push the new config in configs queue */ 620 free_cfg_slot = lru_cfg->cfg_slot; 621 kfifo_put(&st->live_cfgs_fifo, cfg); 622 } 623 624 /* mark slot as used */ 625 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1); 626 627 return ad7124_write_config(st, cfg, free_cfg_slot); 628 } 629 630 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch) 631 { 632 ch->cfg.live = true; 633 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain | 634 FIELD_PREP(AD7124_CHANNEL_SETUP, ch->cfg.cfg_slot) | 635 AD7124_CHANNEL_ENABLE); 636 } 637 638 static int ad7124_prepare_read(struct ad7124_state *st, int address) 639 { 640 struct ad7124_channel_config *cfg = &st->channels[address].cfg; 641 struct ad7124_channel_config *live_cfg; 642 643 /* 644 * Before doing any reads assign the channel a configuration. 645 * Check if channel's config is on the device 646 */ 647 if (!cfg->live) { 648 /* check if config matches another one */ 649 live_cfg = ad7124_find_similar_live_cfg(st, cfg); 650 if (!live_cfg) 651 ad7124_push_config(st, cfg); 652 else 653 cfg->cfg_slot = live_cfg->cfg_slot; 654 } 655 656 /* point channel to the config slot and enable */ 657 return ad7124_enable_channel(st, &st->channels[address]); 658 } 659 660 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 661 { 662 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 663 664 return ad7124_prepare_read(st, channel); 665 } 666 667 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 668 { 669 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 670 int ret; 671 672 mutex_lock(&st->cfgs_lock); 673 ret = __ad7124_set_channel(sd, channel); 674 mutex_unlock(&st->cfgs_lock); 675 676 return ret; 677 } 678 679 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append) 680 { 681 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 682 unsigned int adc_control = st->adc_control; 683 int ret; 684 685 if (append) 686 adc_control |= AD7124_ADC_CONTROL_DATA_STATUS; 687 else 688 adc_control &= ~AD7124_ADC_CONTROL_DATA_STATUS; 689 690 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control); 691 if (ret < 0) 692 return ret; 693 694 st->adc_control = adc_control; 695 696 return 0; 697 } 698 699 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 700 { 701 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 702 703 /* The relevant thing here is that AD7124_CHANNEL_ENABLE is cleared. */ 704 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0); 705 } 706 707 static int ad7124_disable_all(struct ad_sigma_delta *sd) 708 { 709 int ret; 710 int i; 711 712 for (i = 0; i < 16; i++) { 713 ret = ad7124_disable_one(sd, i); 714 if (ret < 0) 715 return ret; 716 } 717 718 return 0; 719 } 720 721 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = { 722 .set_channel = ad7124_set_channel, 723 .append_status = ad7124_append_status, 724 .disable_all = ad7124_disable_all, 725 .disable_one = ad7124_disable_one, 726 .set_mode = ad7124_set_mode, 727 .has_registers = true, 728 .addr_shift = 0, 729 .read_mask = BIT(6), 730 .status_ch_mask = GENMASK(3, 0), 731 .data_reg = AD7124_DATA, 732 .num_slots = 8, 733 .irq_flags = IRQF_TRIGGER_FALLING, 734 .num_resetclks = 64, 735 }; 736 737 static const int ad7124_voltage_scales[][2] = { 738 { 0, 1164 }, 739 { 0, 2328 }, 740 { 0, 4656 }, 741 { 0, 9313 }, 742 { 0, 18626 }, 743 { 0, 37252 }, 744 { 0, 74505 }, 745 { 0, 149011 }, 746 { 0, 298023 }, 747 }; 748 749 static int ad7124_read_avail(struct iio_dev *indio_dev, 750 struct iio_chan_spec const *chan, 751 const int **vals, int *type, int *length, long info) 752 { 753 switch (info) { 754 case IIO_CHAN_INFO_SCALE: 755 *vals = (const int *)ad7124_voltage_scales; 756 *type = IIO_VAL_INT_PLUS_NANO; 757 *length = ARRAY_SIZE(ad7124_voltage_scales) * 2; 758 return IIO_AVAIL_LIST; 759 default: 760 return -EINVAL; 761 } 762 } 763 764 static int ad7124_read_raw(struct iio_dev *indio_dev, 765 struct iio_chan_spec const *chan, 766 int *val, int *val2, long info) 767 { 768 struct ad7124_state *st = iio_priv(indio_dev); 769 int idx, ret; 770 771 switch (info) { 772 case IIO_CHAN_INFO_RAW: 773 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 774 if (ret < 0) 775 return ret; 776 777 return IIO_VAL_INT; 778 case IIO_CHAN_INFO_SCALE: 779 switch (chan->type) { 780 case IIO_VOLTAGE: 781 mutex_lock(&st->cfgs_lock); 782 783 idx = st->channels[chan->address].cfg.pga_bits; 784 *val = st->channels[chan->address].cfg.vref_mv; 785 if (st->channels[chan->address].cfg.bipolar) 786 *val2 = chan->scan_type.realbits - 1 + idx; 787 else 788 *val2 = chan->scan_type.realbits + idx; 789 790 mutex_unlock(&st->cfgs_lock); 791 return IIO_VAL_FRACTIONAL_LOG2; 792 793 case IIO_TEMP: 794 /* 795 * According to the data sheet 796 * Temperature (°C) 797 * = ((Conversion − 0x800000)/13584) − 272.5 798 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584 799 * = (Conversion − 12090248) / 13584 800 * So scale with 1000/13584 to yield °mC. Reduce by 8 to 801 * 125/1698. 802 */ 803 *val = 125; 804 *val2 = 1698; 805 return IIO_VAL_FRACTIONAL; 806 807 default: 808 return -EINVAL; 809 } 810 811 case IIO_CHAN_INFO_OFFSET: 812 switch (chan->type) { 813 case IIO_VOLTAGE: 814 mutex_lock(&st->cfgs_lock); 815 if (st->channels[chan->address].cfg.bipolar) 816 *val = -(1 << (chan->scan_type.realbits - 1)); 817 else 818 *val = 0; 819 820 mutex_unlock(&st->cfgs_lock); 821 return IIO_VAL_INT; 822 823 case IIO_TEMP: 824 /* see calculation above */ 825 *val = -12090248; 826 return IIO_VAL_INT; 827 828 default: 829 return -EINVAL; 830 } 831 832 case IIO_CHAN_INFO_SAMP_FREQ: { 833 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg; 834 835 guard(mutex)(&st->cfgs_lock); 836 837 switch (cfg->filter_type) { 838 case AD7124_FILTER_TYPE_SINC3: 839 case AD7124_FILTER_TYPE_SINC3_REJ60: 840 case AD7124_FILTER_TYPE_SINC3_SINC1: 841 case AD7124_FILTER_TYPE_SINC4: 842 case AD7124_FILTER_TYPE_SINC4_REJ60: 843 case AD7124_FILTER_TYPE_SINC4_SINC1: 844 *val = ad7124_get_fclk_hz(st); 845 *val2 = ad7124_get_fadc_divisor(st, chan->address); 846 return IIO_VAL_FRACTIONAL; 847 /* 848 * Post filters force the chip to a fixed rate. These are the 849 * single-channel rates from the data sheet divided by 3 for 850 * the multi-channel case (data sheet doesn't explicitly state 851 * this but confirmed through testing). 852 */ 853 case AD7124_FILTER_TYPE_SINC3_PF1: 854 *val = 300; 855 *val2 = 33; 856 return IIO_VAL_FRACTIONAL; 857 case AD7124_FILTER_TYPE_SINC3_PF2: 858 *val = 25; 859 *val2 = 3; 860 return IIO_VAL_FRACTIONAL; 861 case AD7124_FILTER_TYPE_SINC3_PF3: 862 *val = 20; 863 *val2 = 3; 864 return IIO_VAL_FRACTIONAL; 865 case AD7124_FILTER_TYPE_SINC3_PF4: 866 *val = 50; 867 *val2 = 9; 868 return IIO_VAL_FRACTIONAL; 869 default: 870 return -EINVAL; 871 } 872 } 873 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: { 874 guard(mutex)(&st->cfgs_lock); 875 876 ret = ad7124_get_3db_filter_factor(st, chan->address); 877 if (ret < 0) 878 return ret; 879 880 /* 3dB point is the f_CLK rate times a fractional value */ 881 *val = ret * ad7124_get_fclk_hz(st); 882 *val2 = MILLI * ad7124_get_fadc_divisor(st, chan->address); 883 return IIO_VAL_FRACTIONAL; 884 } 885 default: 886 return -EINVAL; 887 } 888 } 889 890 static int ad7124_write_raw(struct iio_dev *indio_dev, 891 struct iio_chan_spec const *chan, 892 int val, int val2, long info) 893 { 894 struct ad7124_state *st = iio_priv(indio_dev); 895 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg; 896 unsigned int res, gain, full_scale, vref; 897 898 guard(mutex)(&st->cfgs_lock); 899 900 switch (info) { 901 case IIO_CHAN_INFO_SAMP_FREQ: 902 if (val2 < 0 || val < 0 || (val2 == 0 && val == 0)) 903 return -EINVAL; 904 905 cfg->requested_odr = val; 906 cfg->requested_odr_micro = val2; 907 ad7124_set_channel_odr(st, chan->address); 908 909 return 0; 910 case IIO_CHAN_INFO_SCALE: 911 if (val != 0) 912 return -EINVAL; 913 914 if (st->channels[chan->address].cfg.bipolar) 915 full_scale = 1 << (chan->scan_type.realbits - 1); 916 else 917 full_scale = 1 << chan->scan_type.realbits; 918 919 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL; 920 res = DIV_ROUND_CLOSEST(vref, full_scale); 921 gain = DIV_ROUND_CLOSEST(res, val2); 922 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain); 923 924 if (st->channels[chan->address].cfg.pga_bits != res) 925 st->channels[chan->address].cfg.live = false; 926 927 st->channels[chan->address].cfg.pga_bits = res; 928 return 0; 929 default: 930 return -EINVAL; 931 } 932 } 933 934 static int ad7124_reg_access(struct iio_dev *indio_dev, 935 unsigned int reg, 936 unsigned int writeval, 937 unsigned int *readval) 938 { 939 struct ad7124_state *st = iio_priv(indio_dev); 940 int ret; 941 942 if (reg >= ARRAY_SIZE(ad7124_reg_size)) 943 return -EINVAL; 944 945 if (readval) 946 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg], 947 readval); 948 else 949 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg], 950 writeval); 951 952 return ret; 953 } 954 955 static int ad7124_update_scan_mode(struct iio_dev *indio_dev, 956 const unsigned long *scan_mask) 957 { 958 struct ad7124_state *st = iio_priv(indio_dev); 959 bool bit_set; 960 int ret; 961 int i; 962 963 guard(mutex)(&st->cfgs_lock); 964 965 for (i = 0; i < st->num_channels; i++) { 966 bit_set = test_bit(i, scan_mask); 967 if (bit_set) 968 ret = __ad7124_set_channel(&st->sd, i); 969 else 970 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_ENABLE, 971 0, 2); 972 if (ret < 0) 973 return ret; 974 } 975 976 return 0; 977 } 978 979 static const struct iio_info ad7124_info = { 980 .read_avail = ad7124_read_avail, 981 .read_raw = ad7124_read_raw, 982 .write_raw = ad7124_write_raw, 983 .debugfs_reg_access = &ad7124_reg_access, 984 .validate_trigger = ad_sd_validate_trigger, 985 .update_scan_mode = ad7124_update_scan_mode, 986 }; 987 988 /* Only called during probe, so dev_err_probe() can be used */ 989 static int ad7124_soft_reset(struct ad7124_state *st) 990 { 991 struct device *dev = &st->sd.spi->dev; 992 unsigned int readval, timeout; 993 int ret; 994 995 ret = ad_sd_reset(&st->sd); 996 if (ret < 0) 997 return ret; 998 999 fsleep(200); 1000 timeout = 100; 1001 do { 1002 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval); 1003 if (ret < 0) 1004 return dev_err_probe(dev, ret, "Error reading status register\n"); 1005 1006 if (!(readval & AD7124_STATUS_POR_FLAG)) 1007 break; 1008 1009 /* The AD7124 requires typically 2ms to power up and settle */ 1010 usleep_range(100, 2000); 1011 } while (--timeout); 1012 1013 if (readval & AD7124_STATUS_POR_FLAG) 1014 return dev_err_probe(dev, -EIO, "Soft reset failed\n"); 1015 1016 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &st->gain_default); 1017 if (ret < 0) 1018 return dev_err_probe(dev, ret, "Error reading gain register\n"); 1019 1020 dev_dbg(dev, "Reset value of GAIN register is 0x%x\n", st->gain_default); 1021 1022 return 0; 1023 } 1024 1025 static int ad7124_check_chip_id(struct ad7124_state *st) 1026 { 1027 struct device *dev = &st->sd.spi->dev; 1028 unsigned int readval, chip_id, silicon_rev; 1029 int ret; 1030 1031 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval); 1032 if (ret < 0) 1033 return dev_err_probe(dev, ret, "Failure to read ID register\n"); 1034 1035 chip_id = FIELD_GET(AD7124_ID_DEVICE_ID, readval); 1036 silicon_rev = FIELD_GET(AD7124_ID_SILICON_REVISION, readval); 1037 1038 if (chip_id != st->chip_info->chip_id) 1039 return dev_err_probe(dev, -ENODEV, 1040 "Chip ID mismatch: expected %u, got %u\n", 1041 st->chip_info->chip_id, chip_id); 1042 1043 if (silicon_rev == 0) 1044 return dev_err_probe(dev, -ENODEV, 1045 "Silicon revision empty. Chip may not be present\n"); 1046 1047 return 0; 1048 } 1049 1050 enum { 1051 AD7124_SYSCALIB_ZERO_SCALE, 1052 AD7124_SYSCALIB_FULL_SCALE, 1053 }; 1054 1055 static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan_spec *chan) 1056 { 1057 struct device *dev = &st->sd.spi->dev; 1058 struct ad7124_channel *ch = &st->channels[chan->address]; 1059 int ret; 1060 1061 if (ch->syscalib_mode == AD7124_SYSCALIB_ZERO_SCALE) { 1062 ch->cfg.calibration_offset = 0x800000; 1063 1064 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB, 1065 chan->address); 1066 if (ret < 0) 1067 return ret; 1068 1069 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(ch->cfg.cfg_slot), 3, 1070 &ch->cfg.calibration_offset); 1071 if (ret < 0) 1072 return ret; 1073 1074 dev_dbg(dev, "offset for channel %lu after zero-scale calibration: 0x%x\n", 1075 chan->address, ch->cfg.calibration_offset); 1076 } else { 1077 ch->cfg.calibration_gain = st->gain_default; 1078 1079 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB, 1080 chan->address); 1081 if (ret < 0) 1082 return ret; 1083 1084 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(ch->cfg.cfg_slot), 3, 1085 &ch->cfg.calibration_gain); 1086 if (ret < 0) 1087 return ret; 1088 1089 dev_dbg(dev, "gain for channel %lu after full-scale calibration: 0x%x\n", 1090 chan->address, ch->cfg.calibration_gain); 1091 } 1092 1093 return 0; 1094 } 1095 1096 static ssize_t ad7124_write_syscalib(struct iio_dev *indio_dev, 1097 uintptr_t private, 1098 const struct iio_chan_spec *chan, 1099 const char *buf, size_t len) 1100 { 1101 struct ad7124_state *st = iio_priv(indio_dev); 1102 bool sys_calib; 1103 int ret; 1104 1105 ret = kstrtobool(buf, &sys_calib); 1106 if (ret) 1107 return ret; 1108 1109 if (!sys_calib) 1110 return len; 1111 1112 if (!iio_device_claim_direct(indio_dev)) 1113 return -EBUSY; 1114 1115 ret = ad7124_syscalib_locked(st, chan); 1116 1117 iio_device_release_direct(indio_dev); 1118 1119 return ret ?: len; 1120 } 1121 1122 static const char * const ad7124_syscalib_modes[] = { 1123 [AD7124_SYSCALIB_ZERO_SCALE] = "zero_scale", 1124 [AD7124_SYSCALIB_FULL_SCALE] = "full_scale", 1125 }; 1126 1127 static int ad7124_set_syscalib_mode(struct iio_dev *indio_dev, 1128 const struct iio_chan_spec *chan, 1129 unsigned int mode) 1130 { 1131 struct ad7124_state *st = iio_priv(indio_dev); 1132 1133 st->channels[chan->address].syscalib_mode = mode; 1134 1135 return 0; 1136 } 1137 1138 static int ad7124_get_syscalib_mode(struct iio_dev *indio_dev, 1139 const struct iio_chan_spec *chan) 1140 { 1141 struct ad7124_state *st = iio_priv(indio_dev); 1142 1143 return st->channels[chan->address].syscalib_mode; 1144 } 1145 1146 static const struct iio_enum ad7124_syscalib_mode_enum = { 1147 .items = ad7124_syscalib_modes, 1148 .num_items = ARRAY_SIZE(ad7124_syscalib_modes), 1149 .set = ad7124_set_syscalib_mode, 1150 .get = ad7124_get_syscalib_mode 1151 }; 1152 1153 static const char * const ad7124_filter_types[] = { 1154 [AD7124_FILTER_TYPE_SINC3] = "sinc3", 1155 [AD7124_FILTER_TYPE_SINC3_PF1] = "sinc3+pf1", 1156 [AD7124_FILTER_TYPE_SINC3_PF2] = "sinc3+pf2", 1157 [AD7124_FILTER_TYPE_SINC3_PF3] = "sinc3+pf3", 1158 [AD7124_FILTER_TYPE_SINC3_PF4] = "sinc3+pf4", 1159 [AD7124_FILTER_TYPE_SINC3_REJ60] = "sinc3+rej60", 1160 [AD7124_FILTER_TYPE_SINC3_SINC1] = "sinc3+sinc1", 1161 [AD7124_FILTER_TYPE_SINC4] = "sinc4", 1162 [AD7124_FILTER_TYPE_SINC4_REJ60] = "sinc4+rej60", 1163 [AD7124_FILTER_TYPE_SINC4_SINC1] = "sinc4+sinc1", 1164 }; 1165 1166 static int ad7124_set_filter_type_attr(struct iio_dev *dev, 1167 const struct iio_chan_spec *chan, 1168 unsigned int value) 1169 { 1170 struct ad7124_state *st = iio_priv(dev); 1171 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg; 1172 1173 guard(mutex)(&st->cfgs_lock); 1174 1175 cfg->live = false; 1176 cfg->filter_type = value; 1177 ad7124_set_channel_odr(st, chan->address); 1178 1179 return 0; 1180 } 1181 1182 static int ad7124_get_filter_type_attr(struct iio_dev *dev, 1183 const struct iio_chan_spec *chan) 1184 { 1185 struct ad7124_state *st = iio_priv(dev); 1186 1187 guard(mutex)(&st->cfgs_lock); 1188 1189 return st->channels[chan->address].cfg.filter_type; 1190 } 1191 1192 static const struct iio_enum ad7124_filter_type_enum = { 1193 .items = ad7124_filter_types, 1194 .num_items = ARRAY_SIZE(ad7124_filter_types), 1195 .set = ad7124_set_filter_type_attr, 1196 .get = ad7124_get_filter_type_attr, 1197 }; 1198 1199 static const struct iio_chan_spec_ext_info ad7124_calibsys_ext_info[] = { 1200 { 1201 .name = "sys_calibration", 1202 .write = ad7124_write_syscalib, 1203 .shared = IIO_SEPARATE, 1204 }, 1205 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 1206 &ad7124_syscalib_mode_enum), 1207 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 1208 &ad7124_syscalib_mode_enum), 1209 IIO_ENUM("filter_type", IIO_SEPARATE, &ad7124_filter_type_enum), 1210 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE, 1211 &ad7124_filter_type_enum), 1212 { } 1213 }; 1214 1215 static const struct iio_chan_spec ad7124_channel_template = { 1216 .type = IIO_VOLTAGE, 1217 .indexed = 1, 1218 .differential = 1, 1219 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1220 BIT(IIO_CHAN_INFO_SCALE) | 1221 BIT(IIO_CHAN_INFO_OFFSET) | 1222 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 1223 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 1224 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), 1225 .scan_type = { 1226 .sign = 'u', 1227 .realbits = 24, 1228 .storagebits = 32, 1229 .endianness = IIO_BE, 1230 }, 1231 .ext_info = ad7124_calibsys_ext_info, 1232 }; 1233 1234 /* 1235 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4 1236 * while they are fine for ad7124-8. Values above 31 don't fit 1237 * into the register field and so are invalid for sure. 1238 */ 1239 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info) 1240 { 1241 if (ain >= info->num_inputs && ain < 16) 1242 return false; 1243 1244 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM); 1245 } 1246 1247 static int ad7124_parse_channel_config(struct iio_dev *indio_dev, 1248 struct device *dev) 1249 { 1250 struct ad7124_state *st = iio_priv(indio_dev); 1251 struct ad7124_channel_config *cfg; 1252 struct ad7124_channel *channels; 1253 struct iio_chan_spec *chan; 1254 unsigned int ain[2], channel = 0, tmp; 1255 unsigned int num_channels; 1256 int ret; 1257 1258 num_channels = device_get_child_node_count(dev); 1259 1260 /* 1261 * The driver assigns each logical channel defined in the device tree 1262 * statically one channel register. So only accept 16 such logical 1263 * channels to not treat CONFIG_0 (i.e. the register following 1264 * CHANNEL_15) as an additional channel register. The driver could be 1265 * improved to lift this limitation. 1266 */ 1267 if (num_channels > AD7124_MAX_CHANNELS) 1268 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n"); 1269 1270 /* Add one for temperature */ 1271 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS); 1272 1273 chan = devm_kcalloc(dev, st->num_channels, 1274 sizeof(*chan), GFP_KERNEL); 1275 if (!chan) 1276 return -ENOMEM; 1277 1278 channels = devm_kcalloc(dev, st->num_channels, sizeof(*channels), 1279 GFP_KERNEL); 1280 if (!channels) 1281 return -ENOMEM; 1282 1283 indio_dev->channels = chan; 1284 indio_dev->num_channels = st->num_channels; 1285 st->channels = channels; 1286 1287 device_for_each_child_node_scoped(dev, child) { 1288 ret = fwnode_property_read_u32(child, "reg", &channel); 1289 if (ret) 1290 return dev_err_probe(dev, ret, 1291 "Failed to parse reg property of %pfwP\n", child); 1292 1293 if (channel >= num_channels) 1294 return dev_err_probe(dev, -EINVAL, 1295 "Channel index >= number of channels in %pfwP\n", child); 1296 1297 ret = fwnode_property_read_u32_array(child, "diff-channels", 1298 ain, 2); 1299 if (ret) 1300 return dev_err_probe(dev, ret, 1301 "Failed to parse diff-channels property of %pfwP\n", child); 1302 1303 if (!ad7124_valid_input_select(ain[0], st->chip_info) || 1304 !ad7124_valid_input_select(ain[1], st->chip_info)) 1305 return dev_err_probe(dev, -EINVAL, 1306 "diff-channels property of %pfwP contains invalid data\n", child); 1307 1308 st->channels[channel].nr = channel; 1309 st->channels[channel].ain = FIELD_PREP(AD7124_CHANNEL_AINP, ain[0]) | 1310 FIELD_PREP(AD7124_CHANNEL_AINM, ain[1]); 1311 1312 cfg = &st->channels[channel].cfg; 1313 cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 1314 1315 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp); 1316 if (ret) 1317 cfg->refsel = AD7124_INT_REF; 1318 else 1319 cfg->refsel = tmp; 1320 1321 cfg->buf_positive = 1322 fwnode_property_read_bool(child, "adi,buffered-positive"); 1323 cfg->buf_negative = 1324 fwnode_property_read_bool(child, "adi,buffered-negative"); 1325 1326 chan[channel] = ad7124_channel_template; 1327 chan[channel].address = channel; 1328 chan[channel].scan_index = channel; 1329 chan[channel].channel = ain[0]; 1330 chan[channel].channel2 = ain[1]; 1331 } 1332 1333 if (num_channels < AD7124_MAX_CHANNELS) { 1334 st->channels[num_channels] = (struct ad7124_channel) { 1335 .nr = num_channels, 1336 .ain = FIELD_PREP(AD7124_CHANNEL_AINP, AD7124_CHANNEL_AINx_TEMPSENSOR) | 1337 FIELD_PREP(AD7124_CHANNEL_AINM, AD7124_CHANNEL_AINx_AVSS), 1338 .cfg = { 1339 .bipolar = true, 1340 }, 1341 }; 1342 1343 chan[num_channels] = (struct iio_chan_spec) { 1344 .type = IIO_TEMP, 1345 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1346 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1347 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1348 .scan_type = { 1349 /* 1350 * You might find it strange that a bipolar 1351 * measurement yields an unsigned value, but 1352 * this matches the device's manual. 1353 */ 1354 .sign = 'u', 1355 .realbits = 24, 1356 .storagebits = 32, 1357 .endianness = IIO_BE, 1358 }, 1359 .address = num_channels, 1360 .scan_index = num_channels, 1361 }; 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int ad7124_setup(struct ad7124_state *st) 1368 { 1369 struct device *dev = &st->sd.spi->dev; 1370 unsigned int power_mode, clk_sel; 1371 struct clk *mclk; 1372 int i, ret; 1373 1374 /* 1375 * Always use full power mode for max performance. If needed, the driver 1376 * could be adapted to use a dynamic power mode based on the requested 1377 * output data rate. 1378 */ 1379 power_mode = AD7124_ADC_CONTROL_POWER_MODE_FULL; 1380 1381 /* 1382 * This "mclk" business is needed for backwards compatibility with old 1383 * devicetrees that specified a fake clock named "mclk" to select the 1384 * power mode. 1385 */ 1386 mclk = devm_clk_get_optional_enabled(dev, "mclk"); 1387 if (IS_ERR(mclk)) 1388 return dev_err_probe(dev, PTR_ERR(mclk), "Failed to get mclk\n"); 1389 1390 if (mclk) { 1391 unsigned long mclk_hz; 1392 1393 mclk_hz = clk_get_rate(mclk); 1394 if (!mclk_hz) 1395 return dev_err_probe(dev, -EINVAL, 1396 "Failed to get mclk rate\n"); 1397 1398 /* 1399 * This logic is a bit backwards, which is why it is only here 1400 * for backwards compatibility. The driver should be able to set 1401 * the power mode as it sees fit and the f_clk/mclk rate should 1402 * be dynamic accordingly. But here, we are selecting a fixed 1403 * power mode based on the given "mclk" rate. 1404 */ 1405 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz, 1406 ARRAY_SIZE(ad7124_master_clk_freq_hz), mclk_hz); 1407 1408 if (mclk_hz != ad7124_master_clk_freq_hz[power_mode]) { 1409 ret = clk_set_rate(mclk, mclk_hz); 1410 if (ret) 1411 return dev_err_probe(dev, ret, 1412 "Failed to set mclk rate\n"); 1413 } 1414 1415 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT; 1416 st->clk_hz = AD7124_INT_CLK_HZ; 1417 } else if (!device_property_present(dev, "clocks") && 1418 device_property_present(dev, "#clock-cells")) { 1419 #ifdef CONFIG_COMMON_CLK 1420 struct clk_hw *clk_hw; 1421 1422 const char *name __free(kfree) = kasprintf(GFP_KERNEL, "%pfwP-clk", 1423 dev_fwnode(dev)); 1424 if (!name) 1425 return -ENOMEM; 1426 1427 clk_hw = devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, 1428 AD7124_INT_CLK_HZ); 1429 if (IS_ERR(clk_hw)) 1430 return dev_err_probe(dev, PTR_ERR(clk_hw), 1431 "Failed to register clock provider\n"); 1432 1433 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1434 clk_hw); 1435 if (ret) 1436 return dev_err_probe(dev, ret, 1437 "Failed to add clock provider\n"); 1438 #endif 1439 1440 /* 1441 * Treat the clock as always on. This way we don't have to deal 1442 * with someone trying to enable/disable the clock while we are 1443 * reading samples. 1444 */ 1445 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT_OUT; 1446 st->clk_hz = AD7124_INT_CLK_HZ; 1447 } else { 1448 struct clk *clk; 1449 1450 clk = devm_clk_get_optional_enabled(dev, NULL); 1451 if (IS_ERR(clk)) 1452 return dev_err_probe(dev, PTR_ERR(clk), 1453 "Failed to get external clock\n"); 1454 1455 if (clk) { 1456 unsigned long clk_hz; 1457 1458 clk_hz = clk_get_rate(clk); 1459 if (!clk_hz) 1460 return dev_err_probe(dev, -EINVAL, 1461 "Failed to get external clock rate\n"); 1462 1463 /* 1464 * The external clock may be 4x the nominal clock rate, 1465 * in which case the ADC needs to be configured to 1466 * divide it by 4. Using MEGA is a bit arbitrary, but 1467 * the expected clock rates are either 614.4 kHz or 1468 * 2.4576 MHz, so this should work. 1469 */ 1470 if (clk_hz > (1 * HZ_PER_MHZ)) { 1471 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4; 1472 st->clk_hz = clk_hz / 4; 1473 } else { 1474 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT; 1475 st->clk_hz = clk_hz; 1476 } 1477 } else { 1478 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT; 1479 st->clk_hz = AD7124_INT_CLK_HZ; 1480 } 1481 } 1482 1483 st->adc_control &= ~AD7124_ADC_CONTROL_CLK_SEL; 1484 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_CLK_SEL, clk_sel); 1485 1486 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE; 1487 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, power_mode); 1488 1489 st->adc_control &= ~AD7124_ADC_CONTROL_MODE; 1490 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, AD_SD_MODE_IDLE); 1491 1492 mutex_init(&st->cfgs_lock); 1493 INIT_KFIFO(st->live_cfgs_fifo); 1494 for (i = 0; i < st->num_channels; i++) { 1495 struct ad7124_channel_config *cfg = &st->channels[i].cfg; 1496 1497 ret = ad7124_init_config_vref(st, cfg); 1498 if (ret < 0) 1499 return ret; 1500 1501 /* Default filter type on the ADC after reset. */ 1502 cfg->filter_type = AD7124_FILTER_TYPE_SINC4; 1503 1504 /* 1505 * 9.38 SPS is the minimum output data rate supported 1506 * regardless of the selected power mode. Round it up to 10 and 1507 * set all channels to this default value. 1508 */ 1509 cfg->requested_odr = 10; 1510 ad7124_set_channel_odr(st, i); 1511 } 1512 1513 ad7124_disable_all(&st->sd); 1514 1515 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 1516 if (ret < 0) 1517 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n"); 1518 1519 return ret; 1520 } 1521 1522 static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev) 1523 { 1524 struct device *dev = &st->sd.spi->dev; 1525 int ret, i; 1526 1527 for (i = 0; i < st->num_channels; i++) { 1528 1529 if (indio_dev->channels[i].type != IIO_VOLTAGE) 1530 continue; 1531 1532 /* 1533 * For calibration the OFFSET register should hold its reset default 1534 * value. For the GAIN register there is no such requirement but 1535 * for gain 1 it should hold the reset default value, too. So to 1536 * simplify matters use the reset default value for both. 1537 */ 1538 st->channels[i].cfg.calibration_offset = 0x800000; 1539 st->channels[i].cfg.calibration_gain = st->gain_default; 1540 1541 /* 1542 * Full-scale calibration isn't supported at gain 1, so skip in 1543 * that case. Note that untypically full-scale calibration has 1544 * to happen before zero-scale calibration. This only applies to 1545 * the internal calibration. For system calibration it's as 1546 * usual: first zero-scale then full-scale calibration. 1547 */ 1548 if (st->channels[i].cfg.pga_bits > 0) { 1549 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB, i); 1550 if (ret < 0) 1551 return ret; 1552 1553 /* 1554 * read out the resulting value of GAIN 1555 * after full-scale calibration because the next 1556 * ad_sd_calibrate() call overwrites this via 1557 * ad_sigma_delta_set_channel() -> ad7124_set_channel() 1558 * ... -> ad7124_enable_channel(). 1559 */ 1560 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(st->channels[i].cfg.cfg_slot), 3, 1561 &st->channels[i].cfg.calibration_gain); 1562 if (ret < 0) 1563 return ret; 1564 } 1565 1566 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB, i); 1567 if (ret < 0) 1568 return ret; 1569 1570 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(st->channels[i].cfg.cfg_slot), 3, 1571 &st->channels[i].cfg.calibration_offset); 1572 if (ret < 0) 1573 return ret; 1574 1575 dev_dbg(dev, "offset and gain for channel %d = 0x%x + 0x%x\n", i, 1576 st->channels[i].cfg.calibration_offset, 1577 st->channels[i].cfg.calibration_gain); 1578 } 1579 1580 return 0; 1581 } 1582 1583 static int ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev) 1584 { 1585 int ret; 1586 unsigned int adc_control = st->adc_control; 1587 1588 /* 1589 * Calibration isn't supported at full power, so speed down a bit. 1590 * Setting .adc_control is enough here because the control register is 1591 * written as part of ad_sd_calibrate() -> ad_sigma_delta_set_mode(). 1592 * The resulting calibration is then also valid for high-speed, so just 1593 * restore adc_control afterwards. 1594 */ 1595 if (FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, adc_control) >= AD7124_FULL_POWER) { 1596 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE; 1597 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, AD7124_MID_POWER); 1598 } 1599 1600 ret = __ad7124_calibrate_all(st, indio_dev); 1601 1602 st->adc_control = adc_control; 1603 1604 return ret; 1605 } 1606 1607 static void ad7124_reg_disable(void *r) 1608 { 1609 regulator_disable(r); 1610 } 1611 1612 static int ad7124_probe(struct spi_device *spi) 1613 { 1614 const struct ad7124_chip_info *info; 1615 struct device *dev = &spi->dev; 1616 struct ad7124_state *st; 1617 struct iio_dev *indio_dev; 1618 int i, ret; 1619 1620 info = spi_get_device_match_data(spi); 1621 if (!info) 1622 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n"); 1623 1624 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1625 if (!indio_dev) 1626 return -ENOMEM; 1627 1628 st = iio_priv(indio_dev); 1629 1630 st->chip_info = info; 1631 1632 indio_dev->name = st->chip_info->name; 1633 indio_dev->modes = INDIO_DIRECT_MODE; 1634 indio_dev->info = &ad7124_info; 1635 1636 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info); 1637 if (ret < 0) 1638 return ret; 1639 1640 ret = ad7124_parse_channel_config(indio_dev, &spi->dev); 1641 if (ret < 0) 1642 return ret; 1643 1644 for (i = 0; i < ARRAY_SIZE(st->vref); i++) { 1645 if (i == AD7124_INT_REF) 1646 continue; 1647 1648 st->vref[i] = devm_regulator_get_optional(&spi->dev, 1649 ad7124_ref_names[i]); 1650 if (PTR_ERR(st->vref[i]) == -ENODEV) 1651 continue; 1652 else if (IS_ERR(st->vref[i])) 1653 return PTR_ERR(st->vref[i]); 1654 1655 ret = regulator_enable(st->vref[i]); 1656 if (ret) 1657 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i); 1658 1659 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable, 1660 st->vref[i]); 1661 if (ret) 1662 return ret; 1663 } 1664 1665 ret = ad7124_soft_reset(st); 1666 if (ret < 0) 1667 return ret; 1668 1669 ret = ad7124_check_chip_id(st); 1670 if (ret) 1671 return ret; 1672 1673 ret = ad7124_setup(st); 1674 if (ret < 0) 1675 return ret; 1676 1677 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 1678 if (ret < 0) 1679 return dev_err_probe(dev, ret, "Failed to setup triggers\n"); 1680 1681 ret = ad7124_calibrate_all(st, indio_dev); 1682 if (ret) 1683 return ret; 1684 1685 ret = devm_iio_device_register(&spi->dev, indio_dev); 1686 if (ret < 0) 1687 return dev_err_probe(dev, ret, "Failed to register iio device\n"); 1688 1689 return 0; 1690 } 1691 1692 static const struct of_device_id ad7124_of_match[] = { 1693 { .compatible = "adi,ad7124-4", .data = &ad7124_4_chip_info }, 1694 { .compatible = "adi,ad7124-8", .data = &ad7124_8_chip_info }, 1695 { } 1696 }; 1697 MODULE_DEVICE_TABLE(of, ad7124_of_match); 1698 1699 static const struct spi_device_id ad71124_ids[] = { 1700 { "ad7124-4", (kernel_ulong_t)&ad7124_4_chip_info }, 1701 { "ad7124-8", (kernel_ulong_t)&ad7124_8_chip_info }, 1702 { } 1703 }; 1704 MODULE_DEVICE_TABLE(spi, ad71124_ids); 1705 1706 static struct spi_driver ad71124_driver = { 1707 .driver = { 1708 .name = "ad7124", 1709 .of_match_table = ad7124_of_match, 1710 }, 1711 .probe = ad7124_probe, 1712 .id_table = ad71124_ids, 1713 }; 1714 module_spi_driver(ad71124_driver); 1715 1716 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1717 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver"); 1718 MODULE_LICENSE("GPL"); 1719 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1720