1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7124 SPI ADC driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/kfifo.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/property.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 22 #include <linux/iio/iio.h> 23 #include <linux/iio/adc/ad_sigma_delta.h> 24 #include <linux/iio/sysfs.h> 25 26 /* AD7124 registers */ 27 #define AD7124_COMMS 0x00 28 #define AD7124_STATUS 0x00 29 #define AD7124_ADC_CONTROL 0x01 30 #define AD7124_DATA 0x02 31 #define AD7124_IO_CONTROL_1 0x03 32 #define AD7124_IO_CONTROL_2 0x04 33 #define AD7124_ID 0x05 34 #define AD7124_ERROR 0x06 35 #define AD7124_ERROR_EN 0x07 36 #define AD7124_MCLK_COUNT 0x08 37 #define AD7124_CHANNEL(x) (0x09 + (x)) 38 #define AD7124_CONFIG(x) (0x19 + (x)) 39 #define AD7124_FILTER(x) (0x21 + (x)) 40 #define AD7124_OFFSET(x) (0x29 + (x)) 41 #define AD7124_GAIN(x) (0x31 + (x)) 42 43 /* AD7124_STATUS */ 44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4) 45 46 /* AD7124_ADC_CONTROL */ 47 #define AD7124_ADC_STATUS_EN_MSK BIT(10) 48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x) 49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8) 50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x) 51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6) 52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x) 53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2) 54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x) 55 56 /* AD7124 ID */ 57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4) 58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x) 59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0) 60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x) 61 62 #define CHIPID_AD7124_4 0x0 63 #define CHIPID_AD7124_8 0x1 64 65 /* AD7124_CHANNEL_X */ 66 #define AD7124_CHANNEL_EN_MSK BIT(15) 67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x) 68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12) 69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x) 70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5) 71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x) 72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0) 73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x) 74 75 /* AD7124_CONFIG_X */ 76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11) 77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x) 78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3) 79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x) 80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0) 81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x) 82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5) 83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x) 84 85 /* AD7124_FILTER_X */ 86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0) 87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x) 88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21) 89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x) 90 91 #define AD7124_SINC3_FILTER 2 92 #define AD7124_SINC4_FILTER 0 93 94 #define AD7124_CONF_ADDR_OFFSET 20 95 #define AD7124_MAX_CONFIGS 8 96 #define AD7124_MAX_CHANNELS 16 97 98 enum ad7124_ids { 99 ID_AD7124_4, 100 ID_AD7124_8, 101 }; 102 103 enum ad7124_ref_sel { 104 AD7124_REFIN1, 105 AD7124_REFIN2, 106 AD7124_INT_REF, 107 AD7124_AVDD_REF, 108 }; 109 110 enum ad7124_power_mode { 111 AD7124_LOW_POWER, 112 AD7124_MID_POWER, 113 AD7124_FULL_POWER, 114 }; 115 116 static const unsigned int ad7124_gain[8] = { 117 1, 2, 4, 8, 16, 32, 64, 128 118 }; 119 120 static const unsigned int ad7124_reg_size[] = { 121 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2, 122 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 123 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 124 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 125 3, 3, 3, 3, 3 126 }; 127 128 static const int ad7124_master_clk_freq_hz[3] = { 129 [AD7124_LOW_POWER] = 76800, 130 [AD7124_MID_POWER] = 153600, 131 [AD7124_FULL_POWER] = 614400, 132 }; 133 134 static const char * const ad7124_ref_names[] = { 135 [AD7124_REFIN1] = "refin1", 136 [AD7124_REFIN2] = "refin2", 137 [AD7124_INT_REF] = "int", 138 [AD7124_AVDD_REF] = "avdd", 139 }; 140 141 struct ad7124_chip_info { 142 const char *name; 143 unsigned int chip_id; 144 unsigned int num_inputs; 145 }; 146 147 struct ad7124_channel_config { 148 bool live; 149 unsigned int cfg_slot; 150 enum ad7124_ref_sel refsel; 151 bool bipolar; 152 bool buf_positive; 153 bool buf_negative; 154 unsigned int vref_mv; 155 unsigned int pga_bits; 156 unsigned int odr; 157 unsigned int odr_sel_bits; 158 unsigned int filter_type; 159 }; 160 161 struct ad7124_channel { 162 unsigned int nr; 163 struct ad7124_channel_config cfg; 164 unsigned int ain; 165 unsigned int slot; 166 }; 167 168 struct ad7124_state { 169 const struct ad7124_chip_info *chip_info; 170 struct ad_sigma_delta sd; 171 struct ad7124_channel *channels; 172 struct regulator *vref[4]; 173 struct clk *mclk; 174 unsigned int adc_control; 175 unsigned int num_channels; 176 struct mutex cfgs_lock; /* lock for configs access */ 177 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */ 178 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); 179 }; 180 181 static const struct iio_chan_spec ad7124_channel_template = { 182 .type = IIO_VOLTAGE, 183 .indexed = 1, 184 .differential = 1, 185 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 186 BIT(IIO_CHAN_INFO_SCALE) | 187 BIT(IIO_CHAN_INFO_OFFSET) | 188 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 189 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 190 .scan_type = { 191 .sign = 'u', 192 .realbits = 24, 193 .storagebits = 32, 194 .endianness = IIO_BE, 195 }, 196 }; 197 198 static struct ad7124_chip_info ad7124_chip_info_tbl[] = { 199 [ID_AD7124_4] = { 200 .name = "ad7124-4", 201 .chip_id = CHIPID_AD7124_4, 202 .num_inputs = 8, 203 }, 204 [ID_AD7124_8] = { 205 .name = "ad7124-8", 206 .chip_id = CHIPID_AD7124_8, 207 .num_inputs = 16, 208 }, 209 }; 210 211 static int ad7124_find_closest_match(const int *array, 212 unsigned int size, int val) 213 { 214 int i, idx; 215 unsigned int diff_new, diff_old; 216 217 diff_old = U32_MAX; 218 idx = 0; 219 220 for (i = 0; i < size; i++) { 221 diff_new = abs(val - array[i]); 222 if (diff_new < diff_old) { 223 diff_old = diff_new; 224 idx = i; 225 } 226 } 227 228 return idx; 229 } 230 231 static int ad7124_spi_write_mask(struct ad7124_state *st, 232 unsigned int addr, 233 unsigned long mask, 234 unsigned int val, 235 unsigned int bytes) 236 { 237 unsigned int readval; 238 int ret; 239 240 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval); 241 if (ret < 0) 242 return ret; 243 244 readval &= ~mask; 245 readval |= val; 246 247 return ad_sd_write_reg(&st->sd, addr, bytes, readval); 248 } 249 250 static int ad7124_set_mode(struct ad_sigma_delta *sd, 251 enum ad_sigma_delta_mode mode) 252 { 253 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 254 255 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK; 256 st->adc_control |= AD7124_ADC_CTRL_MODE(mode); 257 258 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 259 } 260 261 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr) 262 { 263 unsigned int fclk, odr_sel_bits; 264 265 fclk = clk_get_rate(st->mclk); 266 /* 267 * FS[10:0] = fCLK / (fADC x 32) where: 268 * fADC is the output data rate 269 * fCLK is the master clock frequency 270 * FS[10:0] are the bits in the filter register 271 * FS[10:0] can have a value from 1 to 2047 272 */ 273 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); 274 if (odr_sel_bits < 1) 275 odr_sel_bits = 1; 276 else if (odr_sel_bits > 2047) 277 odr_sel_bits = 2047; 278 279 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits) 280 st->channels[channel].cfg.live = false; 281 282 /* fADC = fCLK / (FS[10:0] x 32) */ 283 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); 284 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits; 285 } 286 287 static int ad7124_get_3db_filter_freq(struct ad7124_state *st, 288 unsigned int channel) 289 { 290 unsigned int fadc; 291 292 fadc = st->channels[channel].cfg.odr; 293 294 switch (st->channels[channel].cfg.filter_type) { 295 case AD7124_SINC3_FILTER: 296 return DIV_ROUND_CLOSEST(fadc * 230, 1000); 297 case AD7124_SINC4_FILTER: 298 return DIV_ROUND_CLOSEST(fadc * 262, 1000); 299 default: 300 return -EINVAL; 301 } 302 } 303 304 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel, 305 unsigned int freq) 306 { 307 unsigned int sinc4_3db_odr; 308 unsigned int sinc3_3db_odr; 309 unsigned int new_filter; 310 unsigned int new_odr; 311 312 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230); 313 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262); 314 315 if (sinc4_3db_odr > sinc3_3db_odr) { 316 new_filter = AD7124_SINC3_FILTER; 317 new_odr = sinc4_3db_odr; 318 } else { 319 new_filter = AD7124_SINC4_FILTER; 320 new_odr = sinc3_3db_odr; 321 } 322 323 if (new_odr != st->channels[channel].cfg.odr) 324 st->channels[channel].cfg.live = false; 325 326 st->channels[channel].cfg.filter_type = new_filter; 327 st->channels[channel].cfg.odr = new_odr; 328 } 329 330 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st, 331 struct ad7124_channel_config *cfg) 332 { 333 struct ad7124_channel_config *cfg_aux; 334 ptrdiff_t cmp_size; 335 int i; 336 337 cmp_size = (u8 *)&cfg->live - (u8 *)cfg; 338 for (i = 0; i < st->num_channels; i++) { 339 cfg_aux = &st->channels[i].cfg; 340 341 if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size)) 342 return cfg_aux; 343 } 344 345 return NULL; 346 } 347 348 static int ad7124_find_free_config_slot(struct ad7124_state *st) 349 { 350 unsigned int free_cfg_slot; 351 352 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS); 353 if (free_cfg_slot == AD7124_MAX_CONFIGS) 354 return -1; 355 356 return free_cfg_slot; 357 } 358 359 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg) 360 { 361 unsigned int refsel = cfg->refsel; 362 363 switch (refsel) { 364 case AD7124_REFIN1: 365 case AD7124_REFIN2: 366 case AD7124_AVDD_REF: 367 if (IS_ERR(st->vref[refsel])) { 368 dev_err(&st->sd.spi->dev, 369 "Error, trying to use external voltage reference without a %s regulator.\n", 370 ad7124_ref_names[refsel]); 371 return PTR_ERR(st->vref[refsel]); 372 } 373 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]); 374 /* Conversion from uV to mV */ 375 cfg->vref_mv /= 1000; 376 return 0; 377 case AD7124_INT_REF: 378 cfg->vref_mv = 2500; 379 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK; 380 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1); 381 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 382 2, st->adc_control); 383 default: 384 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel); 385 return -EINVAL; 386 } 387 } 388 389 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg, 390 unsigned int cfg_slot) 391 { 392 unsigned int tmp; 393 unsigned int val; 394 int ret; 395 396 cfg->cfg_slot = cfg_slot; 397 398 tmp = (cfg->buf_positive << 1) + cfg->buf_negative; 399 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) | 400 AD7124_CONFIG_IN_BUFF(tmp); 401 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val); 402 if (ret < 0) 403 return ret; 404 405 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type); 406 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK, 407 tmp, 3); 408 if (ret < 0) 409 return ret; 410 411 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK, 412 AD7124_FILTER_FS(cfg->odr_sel_bits), 3); 413 if (ret < 0) 414 return ret; 415 416 return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK, 417 AD7124_CONFIG_PGA(cfg->pga_bits), 2); 418 } 419 420 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st) 421 { 422 struct ad7124_channel_config *lru_cfg; 423 struct ad7124_channel_config *cfg; 424 int ret; 425 int i; 426 427 /* 428 * Pop least recently used config from the fifo 429 * in order to make room for the new one 430 */ 431 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg); 432 if (ret <= 0) 433 return NULL; 434 435 lru_cfg->live = false; 436 437 /* mark slot as free */ 438 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0); 439 440 /* invalidate all other configs that pointed to this one */ 441 for (i = 0; i < st->num_channels; i++) { 442 cfg = &st->channels[i].cfg; 443 444 if (cfg->cfg_slot == lru_cfg->cfg_slot) 445 cfg->live = false; 446 } 447 448 return lru_cfg; 449 } 450 451 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg) 452 { 453 struct ad7124_channel_config *lru_cfg; 454 int free_cfg_slot; 455 456 free_cfg_slot = ad7124_find_free_config_slot(st); 457 if (free_cfg_slot >= 0) { 458 /* push the new config in configs queue */ 459 kfifo_put(&st->live_cfgs_fifo, cfg); 460 } else { 461 /* pop one config to make room for the new one */ 462 lru_cfg = ad7124_pop_config(st); 463 if (!lru_cfg) 464 return -EINVAL; 465 466 /* push the new config in configs queue */ 467 free_cfg_slot = lru_cfg->cfg_slot; 468 kfifo_put(&st->live_cfgs_fifo, cfg); 469 } 470 471 /* mark slot as used */ 472 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1); 473 474 return ad7124_write_config(st, cfg, free_cfg_slot); 475 } 476 477 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch) 478 { 479 ch->cfg.live = true; 480 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain | 481 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1)); 482 } 483 484 static int ad7124_prepare_read(struct ad7124_state *st, int address) 485 { 486 struct ad7124_channel_config *cfg = &st->channels[address].cfg; 487 struct ad7124_channel_config *live_cfg; 488 489 /* 490 * Before doing any reads assign the channel a configuration. 491 * Check if channel's config is on the device 492 */ 493 if (!cfg->live) { 494 /* check if config matches another one */ 495 live_cfg = ad7124_find_similar_live_cfg(st, cfg); 496 if (!live_cfg) 497 ad7124_push_config(st, cfg); 498 else 499 cfg->cfg_slot = live_cfg->cfg_slot; 500 } 501 502 /* point channel to the config slot and enable */ 503 return ad7124_enable_channel(st, &st->channels[address]); 504 } 505 506 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 507 { 508 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 509 510 return ad7124_prepare_read(st, channel); 511 } 512 513 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 514 { 515 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 516 int ret; 517 518 mutex_lock(&st->cfgs_lock); 519 ret = __ad7124_set_channel(sd, channel); 520 mutex_unlock(&st->cfgs_lock); 521 522 return ret; 523 } 524 525 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append) 526 { 527 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 528 unsigned int adc_control = st->adc_control; 529 int ret; 530 531 adc_control &= ~AD7124_ADC_STATUS_EN_MSK; 532 adc_control |= AD7124_ADC_STATUS_EN(append); 533 534 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control); 535 if (ret < 0) 536 return ret; 537 538 st->adc_control = adc_control; 539 540 return 0; 541 } 542 543 static int ad7124_disable_all(struct ad_sigma_delta *sd) 544 { 545 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 546 int ret; 547 int i; 548 549 for (i = 0; i < st->num_channels; i++) { 550 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2); 551 if (ret < 0) 552 return ret; 553 } 554 555 return 0; 556 } 557 558 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 559 { 560 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 561 562 return ad7124_spi_write_mask(st, AD7124_CHANNEL(chan), AD7124_CHANNEL_EN_MSK, 0, 2); 563 } 564 565 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = { 566 .set_channel = ad7124_set_channel, 567 .append_status = ad7124_append_status, 568 .disable_all = ad7124_disable_all, 569 .disable_one = ad7124_disable_one, 570 .set_mode = ad7124_set_mode, 571 .has_registers = true, 572 .addr_shift = 0, 573 .read_mask = BIT(6), 574 .status_ch_mask = GENMASK(3, 0), 575 .data_reg = AD7124_DATA, 576 .num_slots = 8, 577 .irq_flags = IRQF_TRIGGER_FALLING, 578 }; 579 580 static int ad7124_read_raw(struct iio_dev *indio_dev, 581 struct iio_chan_spec const *chan, 582 int *val, int *val2, long info) 583 { 584 struct ad7124_state *st = iio_priv(indio_dev); 585 int idx, ret; 586 587 switch (info) { 588 case IIO_CHAN_INFO_RAW: 589 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 590 if (ret < 0) 591 return ret; 592 593 return IIO_VAL_INT; 594 case IIO_CHAN_INFO_SCALE: 595 mutex_lock(&st->cfgs_lock); 596 597 idx = st->channels[chan->address].cfg.pga_bits; 598 *val = st->channels[chan->address].cfg.vref_mv; 599 if (st->channels[chan->address].cfg.bipolar) 600 *val2 = chan->scan_type.realbits - 1 + idx; 601 else 602 *val2 = chan->scan_type.realbits + idx; 603 604 mutex_unlock(&st->cfgs_lock); 605 return IIO_VAL_FRACTIONAL_LOG2; 606 case IIO_CHAN_INFO_OFFSET: 607 mutex_lock(&st->cfgs_lock); 608 if (st->channels[chan->address].cfg.bipolar) 609 *val = -(1 << (chan->scan_type.realbits - 1)); 610 else 611 *val = 0; 612 613 mutex_unlock(&st->cfgs_lock); 614 return IIO_VAL_INT; 615 case IIO_CHAN_INFO_SAMP_FREQ: 616 mutex_lock(&st->cfgs_lock); 617 *val = st->channels[chan->address].cfg.odr; 618 mutex_unlock(&st->cfgs_lock); 619 620 return IIO_VAL_INT; 621 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 622 mutex_lock(&st->cfgs_lock); 623 *val = ad7124_get_3db_filter_freq(st, chan->scan_index); 624 mutex_unlock(&st->cfgs_lock); 625 626 return IIO_VAL_INT; 627 default: 628 return -EINVAL; 629 } 630 } 631 632 static int ad7124_write_raw(struct iio_dev *indio_dev, 633 struct iio_chan_spec const *chan, 634 int val, int val2, long info) 635 { 636 struct ad7124_state *st = iio_priv(indio_dev); 637 unsigned int res, gain, full_scale, vref; 638 int ret = 0; 639 640 mutex_lock(&st->cfgs_lock); 641 642 switch (info) { 643 case IIO_CHAN_INFO_SAMP_FREQ: 644 if (val2 != 0) { 645 ret = -EINVAL; 646 break; 647 } 648 649 ad7124_set_channel_odr(st, chan->address, val); 650 break; 651 case IIO_CHAN_INFO_SCALE: 652 if (val != 0) { 653 ret = -EINVAL; 654 break; 655 } 656 657 if (st->channels[chan->address].cfg.bipolar) 658 full_scale = 1 << (chan->scan_type.realbits - 1); 659 else 660 full_scale = 1 << chan->scan_type.realbits; 661 662 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL; 663 res = DIV_ROUND_CLOSEST(vref, full_scale); 664 gain = DIV_ROUND_CLOSEST(res, val2); 665 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain); 666 667 if (st->channels[chan->address].cfg.pga_bits != res) 668 st->channels[chan->address].cfg.live = false; 669 670 st->channels[chan->address].cfg.pga_bits = res; 671 break; 672 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 673 if (val2 != 0) { 674 ret = -EINVAL; 675 break; 676 } 677 678 ad7124_set_3db_filter_freq(st, chan->address, val); 679 break; 680 default: 681 ret = -EINVAL; 682 } 683 684 mutex_unlock(&st->cfgs_lock); 685 return ret; 686 } 687 688 static int ad7124_reg_access(struct iio_dev *indio_dev, 689 unsigned int reg, 690 unsigned int writeval, 691 unsigned int *readval) 692 { 693 struct ad7124_state *st = iio_priv(indio_dev); 694 int ret; 695 696 if (reg >= ARRAY_SIZE(ad7124_reg_size)) 697 return -EINVAL; 698 699 if (readval) 700 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg], 701 readval); 702 else 703 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg], 704 writeval); 705 706 return ret; 707 } 708 709 static IIO_CONST_ATTR(in_voltage_scale_available, 710 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023"); 711 712 static struct attribute *ad7124_attributes[] = { 713 &iio_const_attr_in_voltage_scale_available.dev_attr.attr, 714 NULL, 715 }; 716 717 static const struct attribute_group ad7124_attrs_group = { 718 .attrs = ad7124_attributes, 719 }; 720 721 static int ad7124_update_scan_mode(struct iio_dev *indio_dev, 722 const unsigned long *scan_mask) 723 { 724 struct ad7124_state *st = iio_priv(indio_dev); 725 bool bit_set; 726 int ret; 727 int i; 728 729 mutex_lock(&st->cfgs_lock); 730 for (i = 0; i < st->num_channels; i++) { 731 bit_set = test_bit(i, scan_mask); 732 if (bit_set) 733 ret = __ad7124_set_channel(&st->sd, i); 734 else 735 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 736 0, 2); 737 if (ret < 0) { 738 mutex_unlock(&st->cfgs_lock); 739 740 return ret; 741 } 742 } 743 744 mutex_unlock(&st->cfgs_lock); 745 746 return 0; 747 } 748 749 static const struct iio_info ad7124_info = { 750 .read_raw = ad7124_read_raw, 751 .write_raw = ad7124_write_raw, 752 .debugfs_reg_access = &ad7124_reg_access, 753 .validate_trigger = ad_sd_validate_trigger, 754 .update_scan_mode = ad7124_update_scan_mode, 755 .attrs = &ad7124_attrs_group, 756 }; 757 758 static int ad7124_soft_reset(struct ad7124_state *st) 759 { 760 unsigned int readval, timeout; 761 int ret; 762 763 ret = ad_sd_reset(&st->sd, 64); 764 if (ret < 0) 765 return ret; 766 767 timeout = 100; 768 do { 769 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval); 770 if (ret < 0) 771 return ret; 772 773 if (!(readval & AD7124_STATUS_POR_FLAG_MSK)) 774 return 0; 775 776 /* The AD7124 requires typically 2ms to power up and settle */ 777 usleep_range(100, 2000); 778 } while (--timeout); 779 780 dev_err(&st->sd.spi->dev, "Soft reset failed\n"); 781 782 return -EIO; 783 } 784 785 static int ad7124_check_chip_id(struct ad7124_state *st) 786 { 787 unsigned int readval, chip_id, silicon_rev; 788 int ret; 789 790 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval); 791 if (ret < 0) 792 return ret; 793 794 chip_id = AD7124_DEVICE_ID_GET(readval); 795 silicon_rev = AD7124_SILICON_REV_GET(readval); 796 797 if (chip_id != st->chip_info->chip_id) { 798 dev_err(&st->sd.spi->dev, 799 "Chip ID mismatch: expected %u, got %u\n", 800 st->chip_info->chip_id, chip_id); 801 return -ENODEV; 802 } 803 804 if (silicon_rev == 0) { 805 dev_err(&st->sd.spi->dev, 806 "Silicon revision empty. Chip may not be present\n"); 807 return -ENODEV; 808 } 809 810 return 0; 811 } 812 813 static int ad7124_parse_channel_config(struct iio_dev *indio_dev, 814 struct device *dev) 815 { 816 struct ad7124_state *st = iio_priv(indio_dev); 817 struct ad7124_channel_config *cfg; 818 struct ad7124_channel *channels; 819 struct iio_chan_spec *chan; 820 unsigned int ain[2], channel = 0, tmp; 821 int ret; 822 823 st->num_channels = device_get_child_node_count(dev); 824 if (!st->num_channels) 825 return dev_err_probe(dev, -ENODEV, "no channel children\n"); 826 827 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels, 828 sizeof(*chan), GFP_KERNEL); 829 if (!chan) 830 return -ENOMEM; 831 832 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels), 833 GFP_KERNEL); 834 if (!channels) 835 return -ENOMEM; 836 837 indio_dev->channels = chan; 838 indio_dev->num_channels = st->num_channels; 839 st->channels = channels; 840 841 device_for_each_child_node_scoped(dev, child) { 842 cfg = &st->channels[channel].cfg; 843 844 ret = fwnode_property_read_u32(child, "reg", &channel); 845 if (ret) 846 return ret; 847 848 if (channel >= indio_dev->num_channels) 849 return dev_err_probe(dev, -EINVAL, 850 "Channel index >= number of channels\n"); 851 852 ret = fwnode_property_read_u32_array(child, "diff-channels", 853 ain, 2); 854 if (ret) 855 return ret; 856 857 st->channels[channel].nr = channel; 858 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) | 859 AD7124_CHANNEL_AINM(ain[1]); 860 861 cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 862 863 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp); 864 if (ret) 865 cfg->refsel = AD7124_INT_REF; 866 else 867 cfg->refsel = tmp; 868 869 cfg->buf_positive = 870 fwnode_property_read_bool(child, "adi,buffered-positive"); 871 cfg->buf_negative = 872 fwnode_property_read_bool(child, "adi,buffered-negative"); 873 874 chan[channel] = ad7124_channel_template; 875 chan[channel].address = channel; 876 chan[channel].scan_index = channel; 877 chan[channel].channel = ain[0]; 878 chan[channel].channel2 = ain[1]; 879 } 880 881 return 0; 882 } 883 884 static int ad7124_setup(struct ad7124_state *st) 885 { 886 unsigned int fclk, power_mode; 887 int i, ret; 888 889 fclk = clk_get_rate(st->mclk); 890 if (!fclk) 891 return -EINVAL; 892 893 /* The power mode changes the master clock frequency */ 894 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz, 895 ARRAY_SIZE(ad7124_master_clk_freq_hz), 896 fclk); 897 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { 898 ret = clk_set_rate(st->mclk, fclk); 899 if (ret) 900 return ret; 901 } 902 903 /* Set the power mode */ 904 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK; 905 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode); 906 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 907 if (ret < 0) 908 return ret; 909 910 mutex_init(&st->cfgs_lock); 911 INIT_KFIFO(st->live_cfgs_fifo); 912 for (i = 0; i < st->num_channels; i++) { 913 914 ret = ad7124_init_config_vref(st, &st->channels[i].cfg); 915 if (ret < 0) 916 return ret; 917 918 /* 919 * 9.38 SPS is the minimum output data rate supported 920 * regardless of the selected power mode. Round it up to 10 and 921 * set all channels to this default value. 922 */ 923 ad7124_set_channel_odr(st, i, 10); 924 } 925 926 return ret; 927 } 928 929 static void ad7124_reg_disable(void *r) 930 { 931 regulator_disable(r); 932 } 933 934 static int ad7124_probe(struct spi_device *spi) 935 { 936 const struct ad7124_chip_info *info; 937 struct ad7124_state *st; 938 struct iio_dev *indio_dev; 939 int i, ret; 940 941 info = spi_get_device_match_data(spi); 942 if (!info) 943 return -ENODEV; 944 945 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 946 if (!indio_dev) 947 return -ENOMEM; 948 949 st = iio_priv(indio_dev); 950 951 st->chip_info = info; 952 953 indio_dev->name = st->chip_info->name; 954 indio_dev->modes = INDIO_DIRECT_MODE; 955 indio_dev->info = &ad7124_info; 956 957 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info); 958 if (ret < 0) 959 return ret; 960 961 ret = ad7124_parse_channel_config(indio_dev, &spi->dev); 962 if (ret < 0) 963 return ret; 964 965 for (i = 0; i < ARRAY_SIZE(st->vref); i++) { 966 if (i == AD7124_INT_REF) 967 continue; 968 969 st->vref[i] = devm_regulator_get_optional(&spi->dev, 970 ad7124_ref_names[i]); 971 if (PTR_ERR(st->vref[i]) == -ENODEV) 972 continue; 973 else if (IS_ERR(st->vref[i])) 974 return PTR_ERR(st->vref[i]); 975 976 ret = regulator_enable(st->vref[i]); 977 if (ret) 978 return ret; 979 980 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable, 981 st->vref[i]); 982 if (ret) 983 return ret; 984 } 985 986 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 987 if (IS_ERR(st->mclk)) 988 return PTR_ERR(st->mclk); 989 990 ret = ad7124_soft_reset(st); 991 if (ret < 0) 992 return ret; 993 994 ret = ad7124_check_chip_id(st); 995 if (ret) 996 return ret; 997 998 ret = ad7124_setup(st); 999 if (ret < 0) 1000 return ret; 1001 1002 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 1003 if (ret < 0) 1004 return ret; 1005 1006 return devm_iio_device_register(&spi->dev, indio_dev); 1007 1008 } 1009 1010 static const struct of_device_id ad7124_of_match[] = { 1011 { .compatible = "adi,ad7124-4", 1012 .data = &ad7124_chip_info_tbl[ID_AD7124_4], }, 1013 { .compatible = "adi,ad7124-8", 1014 .data = &ad7124_chip_info_tbl[ID_AD7124_8], }, 1015 { }, 1016 }; 1017 MODULE_DEVICE_TABLE(of, ad7124_of_match); 1018 1019 static const struct spi_device_id ad71124_ids[] = { 1020 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] }, 1021 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] }, 1022 {} 1023 }; 1024 MODULE_DEVICE_TABLE(spi, ad71124_ids); 1025 1026 static struct spi_driver ad71124_driver = { 1027 .driver = { 1028 .name = "ad7124", 1029 .of_match_table = ad7124_of_match, 1030 }, 1031 .probe = ad7124_probe, 1032 .id_table = ad71124_ids, 1033 }; 1034 module_spi_driver(ad71124_driver); 1035 1036 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1037 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver"); 1038 MODULE_LICENSE("GPL"); 1039 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1040