1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7124 SPI ADC driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/kfifo.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/property.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 22 #include <linux/iio/iio.h> 23 #include <linux/iio/adc/ad_sigma_delta.h> 24 #include <linux/iio/sysfs.h> 25 26 /* AD7124 registers */ 27 #define AD7124_COMMS 0x00 28 #define AD7124_STATUS 0x00 29 #define AD7124_ADC_CONTROL 0x01 30 #define AD7124_DATA 0x02 31 #define AD7124_IO_CONTROL_1 0x03 32 #define AD7124_IO_CONTROL_2 0x04 33 #define AD7124_ID 0x05 34 #define AD7124_ERROR 0x06 35 #define AD7124_ERROR_EN 0x07 36 #define AD7124_MCLK_COUNT 0x08 37 #define AD7124_CHANNEL(x) (0x09 + (x)) 38 #define AD7124_CONFIG(x) (0x19 + (x)) 39 #define AD7124_FILTER(x) (0x21 + (x)) 40 #define AD7124_OFFSET(x) (0x29 + (x)) 41 #define AD7124_GAIN(x) (0x31 + (x)) 42 43 /* AD7124_STATUS */ 44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4) 45 46 /* AD7124_ADC_CONTROL */ 47 #define AD7124_ADC_STATUS_EN_MSK BIT(10) 48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x) 49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8) 50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x) 51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6) 52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x) 53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2) 54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x) 55 56 #define AD7124_MODE_CAL_INT_ZERO 0x5 /* Internal Zero-Scale Calibration */ 57 #define AD7124_MODE_CAL_INT_FULL 0x6 /* Internal Full-Scale Calibration */ 58 #define AD7124_MODE_CAL_SYS_ZERO 0x7 /* System Zero-Scale Calibration */ 59 #define AD7124_MODE_CAL_SYS_FULL 0x8 /* System Full-Scale Calibration */ 60 61 /* AD7124 ID */ 62 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4) 63 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x) 64 #define AD7124_SILICON_REV_MSK GENMASK(3, 0) 65 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x) 66 67 #define CHIPID_AD7124_4 0x0 68 #define CHIPID_AD7124_8 0x1 69 70 /* AD7124_CHANNEL_X */ 71 #define AD7124_CHANNEL_EN_MSK BIT(15) 72 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x) 73 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12) 74 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x) 75 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5) 76 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x) 77 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0) 78 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x) 79 80 /* AD7124_CONFIG_X */ 81 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11) 82 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x) 83 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3) 84 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x) 85 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0) 86 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x) 87 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5) 88 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x) 89 90 /* AD7124_FILTER_X */ 91 #define AD7124_FILTER_FS_MSK GENMASK(10, 0) 92 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x) 93 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21) 94 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x) 95 96 #define AD7124_SINC3_FILTER 2 97 #define AD7124_SINC4_FILTER 0 98 99 #define AD7124_CONF_ADDR_OFFSET 20 100 #define AD7124_MAX_CONFIGS 8 101 #define AD7124_MAX_CHANNELS 16 102 103 /* AD7124 input sources */ 104 #define AD7124_INPUT_TEMPSENSOR 16 105 #define AD7124_INPUT_AVSS 17 106 107 enum ad7124_ids { 108 ID_AD7124_4, 109 ID_AD7124_8, 110 }; 111 112 enum ad7124_ref_sel { 113 AD7124_REFIN1, 114 AD7124_REFIN2, 115 AD7124_INT_REF, 116 AD7124_AVDD_REF, 117 }; 118 119 enum ad7124_power_mode { 120 AD7124_LOW_POWER, 121 AD7124_MID_POWER, 122 AD7124_FULL_POWER, 123 }; 124 125 static const unsigned int ad7124_gain[8] = { 126 1, 2, 4, 8, 16, 32, 64, 128 127 }; 128 129 static const unsigned int ad7124_reg_size[] = { 130 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2, 131 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 132 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 133 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 134 3, 3, 3, 3, 3 135 }; 136 137 static const int ad7124_master_clk_freq_hz[3] = { 138 [AD7124_LOW_POWER] = 76800, 139 [AD7124_MID_POWER] = 153600, 140 [AD7124_FULL_POWER] = 614400, 141 }; 142 143 static const char * const ad7124_ref_names[] = { 144 [AD7124_REFIN1] = "refin1", 145 [AD7124_REFIN2] = "refin2", 146 [AD7124_INT_REF] = "int", 147 [AD7124_AVDD_REF] = "avdd", 148 }; 149 150 struct ad7124_chip_info { 151 const char *name; 152 unsigned int chip_id; 153 unsigned int num_inputs; 154 }; 155 156 struct ad7124_channel_config { 157 bool live; 158 unsigned int cfg_slot; 159 /* 160 * Following fields are used to compare for equality. If you 161 * make adaptations in it, you most likely also have to adapt 162 * ad7124_find_similar_live_cfg(), too. 163 */ 164 struct_group(config_props, 165 enum ad7124_ref_sel refsel; 166 bool bipolar; 167 bool buf_positive; 168 bool buf_negative; 169 unsigned int vref_mv; 170 unsigned int pga_bits; 171 unsigned int odr; 172 unsigned int odr_sel_bits; 173 unsigned int filter_type; 174 unsigned int calibration_offset; 175 unsigned int calibration_gain; 176 ); 177 }; 178 179 struct ad7124_channel { 180 unsigned int nr; 181 struct ad7124_channel_config cfg; 182 unsigned int ain; 183 unsigned int slot; 184 u8 syscalib_mode; 185 }; 186 187 struct ad7124_state { 188 const struct ad7124_chip_info *chip_info; 189 struct ad_sigma_delta sd; 190 struct ad7124_channel *channels; 191 struct regulator *vref[4]; 192 struct clk *mclk; 193 unsigned int adc_control; 194 unsigned int num_channels; 195 struct mutex cfgs_lock; /* lock for configs access */ 196 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */ 197 198 /* 199 * Stores the power-on reset value for the GAIN(x) registers which are 200 * needed for measurements at gain 1 (i.e. CONFIG(x).PGA == 0) 201 */ 202 unsigned int gain_default; 203 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); 204 }; 205 206 static struct ad7124_chip_info ad7124_chip_info_tbl[] = { 207 [ID_AD7124_4] = { 208 .name = "ad7124-4", 209 .chip_id = CHIPID_AD7124_4, 210 .num_inputs = 8, 211 }, 212 [ID_AD7124_8] = { 213 .name = "ad7124-8", 214 .chip_id = CHIPID_AD7124_8, 215 .num_inputs = 16, 216 }, 217 }; 218 219 static int ad7124_find_closest_match(const int *array, 220 unsigned int size, int val) 221 { 222 int i, idx; 223 unsigned int diff_new, diff_old; 224 225 diff_old = U32_MAX; 226 idx = 0; 227 228 for (i = 0; i < size; i++) { 229 diff_new = abs(val - array[i]); 230 if (diff_new < diff_old) { 231 diff_old = diff_new; 232 idx = i; 233 } 234 } 235 236 return idx; 237 } 238 239 static int ad7124_spi_write_mask(struct ad7124_state *st, 240 unsigned int addr, 241 unsigned long mask, 242 unsigned int val, 243 unsigned int bytes) 244 { 245 unsigned int readval; 246 int ret; 247 248 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval); 249 if (ret < 0) 250 return ret; 251 252 readval &= ~mask; 253 readval |= val; 254 255 return ad_sd_write_reg(&st->sd, addr, bytes, readval); 256 } 257 258 static int ad7124_set_mode(struct ad_sigma_delta *sd, 259 enum ad_sigma_delta_mode mode) 260 { 261 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 262 263 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK; 264 st->adc_control |= AD7124_ADC_CTRL_MODE(mode); 265 266 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 267 } 268 269 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr) 270 { 271 unsigned int fclk, odr_sel_bits; 272 273 fclk = clk_get_rate(st->mclk); 274 /* 275 * FS[10:0] = fCLK / (fADC x 32) where: 276 * fADC is the output data rate 277 * fCLK is the master clock frequency 278 * FS[10:0] are the bits in the filter register 279 * FS[10:0] can have a value from 1 to 2047 280 */ 281 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); 282 if (odr_sel_bits < 1) 283 odr_sel_bits = 1; 284 else if (odr_sel_bits > 2047) 285 odr_sel_bits = 2047; 286 287 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits) 288 st->channels[channel].cfg.live = false; 289 290 /* fADC = fCLK / (FS[10:0] x 32) */ 291 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); 292 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits; 293 } 294 295 static int ad7124_get_3db_filter_freq(struct ad7124_state *st, 296 unsigned int channel) 297 { 298 unsigned int fadc; 299 300 fadc = st->channels[channel].cfg.odr; 301 302 switch (st->channels[channel].cfg.filter_type) { 303 case AD7124_SINC3_FILTER: 304 return DIV_ROUND_CLOSEST(fadc * 230, 1000); 305 case AD7124_SINC4_FILTER: 306 return DIV_ROUND_CLOSEST(fadc * 262, 1000); 307 default: 308 return -EINVAL; 309 } 310 } 311 312 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel, 313 unsigned int freq) 314 { 315 unsigned int sinc4_3db_odr; 316 unsigned int sinc3_3db_odr; 317 unsigned int new_filter; 318 unsigned int new_odr; 319 320 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230); 321 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262); 322 323 if (sinc4_3db_odr > sinc3_3db_odr) { 324 new_filter = AD7124_SINC3_FILTER; 325 new_odr = sinc4_3db_odr; 326 } else { 327 new_filter = AD7124_SINC4_FILTER; 328 new_odr = sinc3_3db_odr; 329 } 330 331 if (new_odr != st->channels[channel].cfg.odr) 332 st->channels[channel].cfg.live = false; 333 334 st->channels[channel].cfg.filter_type = new_filter; 335 st->channels[channel].cfg.odr = new_odr; 336 } 337 338 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st, 339 struct ad7124_channel_config *cfg) 340 { 341 struct ad7124_channel_config *cfg_aux; 342 int i; 343 344 /* 345 * This is just to make sure that the comparison is adapted after 346 * struct ad7124_channel_config was changed. 347 */ 348 static_assert(sizeof_field(struct ad7124_channel_config, config_props) == 349 sizeof(struct { 350 enum ad7124_ref_sel refsel; 351 bool bipolar; 352 bool buf_positive; 353 bool buf_negative; 354 unsigned int vref_mv; 355 unsigned int pga_bits; 356 unsigned int odr; 357 unsigned int odr_sel_bits; 358 unsigned int filter_type; 359 unsigned int calibration_offset; 360 unsigned int calibration_gain; 361 })); 362 363 for (i = 0; i < st->num_channels; i++) { 364 cfg_aux = &st->channels[i].cfg; 365 366 if (cfg_aux->live && 367 cfg->refsel == cfg_aux->refsel && 368 cfg->bipolar == cfg_aux->bipolar && 369 cfg->buf_positive == cfg_aux->buf_positive && 370 cfg->buf_negative == cfg_aux->buf_negative && 371 cfg->vref_mv == cfg_aux->vref_mv && 372 cfg->pga_bits == cfg_aux->pga_bits && 373 cfg->odr == cfg_aux->odr && 374 cfg->odr_sel_bits == cfg_aux->odr_sel_bits && 375 cfg->filter_type == cfg_aux->filter_type && 376 cfg->calibration_offset == cfg_aux->calibration_offset && 377 cfg->calibration_gain == cfg_aux->calibration_gain) 378 return cfg_aux; 379 } 380 381 return NULL; 382 } 383 384 static int ad7124_find_free_config_slot(struct ad7124_state *st) 385 { 386 unsigned int free_cfg_slot; 387 388 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS); 389 if (free_cfg_slot == AD7124_MAX_CONFIGS) 390 return -1; 391 392 return free_cfg_slot; 393 } 394 395 /* Only called during probe, so dev_err_probe() can be used */ 396 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg) 397 { 398 struct device *dev = &st->sd.spi->dev; 399 unsigned int refsel = cfg->refsel; 400 401 switch (refsel) { 402 case AD7124_REFIN1: 403 case AD7124_REFIN2: 404 case AD7124_AVDD_REF: 405 if (IS_ERR(st->vref[refsel])) 406 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]), 407 "Error, trying to use external voltage reference without a %s regulator.\n", 408 ad7124_ref_names[refsel]); 409 410 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]); 411 /* Conversion from uV to mV */ 412 cfg->vref_mv /= 1000; 413 return 0; 414 case AD7124_INT_REF: 415 cfg->vref_mv = 2500; 416 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK; 417 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1); 418 return 0; 419 default: 420 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel); 421 } 422 } 423 424 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg, 425 unsigned int cfg_slot) 426 { 427 unsigned int tmp; 428 unsigned int val; 429 int ret; 430 431 cfg->cfg_slot = cfg_slot; 432 433 ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg->cfg_slot), 3, cfg->calibration_offset); 434 if (ret) 435 return ret; 436 437 ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg->cfg_slot), 3, cfg->calibration_gain); 438 if (ret) 439 return ret; 440 441 tmp = (cfg->buf_positive << 1) + cfg->buf_negative; 442 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) | 443 AD7124_CONFIG_IN_BUFF(tmp) | AD7124_CONFIG_PGA(cfg->pga_bits); 444 445 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val); 446 if (ret < 0) 447 return ret; 448 449 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type) | 450 AD7124_FILTER_FS(cfg->odr_sel_bits); 451 return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), 452 AD7124_FILTER_TYPE_MSK | AD7124_FILTER_FS_MSK, 453 tmp, 3); 454 } 455 456 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st) 457 { 458 struct ad7124_channel_config *lru_cfg; 459 struct ad7124_channel_config *cfg; 460 int ret; 461 int i; 462 463 /* 464 * Pop least recently used config from the fifo 465 * in order to make room for the new one 466 */ 467 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg); 468 if (ret <= 0) 469 return NULL; 470 471 lru_cfg->live = false; 472 473 /* mark slot as free */ 474 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0); 475 476 /* invalidate all other configs that pointed to this one */ 477 for (i = 0; i < st->num_channels; i++) { 478 cfg = &st->channels[i].cfg; 479 480 if (cfg->cfg_slot == lru_cfg->cfg_slot) 481 cfg->live = false; 482 } 483 484 return lru_cfg; 485 } 486 487 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg) 488 { 489 struct ad7124_channel_config *lru_cfg; 490 int free_cfg_slot; 491 492 free_cfg_slot = ad7124_find_free_config_slot(st); 493 if (free_cfg_slot >= 0) { 494 /* push the new config in configs queue */ 495 kfifo_put(&st->live_cfgs_fifo, cfg); 496 } else { 497 /* pop one config to make room for the new one */ 498 lru_cfg = ad7124_pop_config(st); 499 if (!lru_cfg) 500 return -EINVAL; 501 502 /* push the new config in configs queue */ 503 free_cfg_slot = lru_cfg->cfg_slot; 504 kfifo_put(&st->live_cfgs_fifo, cfg); 505 } 506 507 /* mark slot as used */ 508 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1); 509 510 return ad7124_write_config(st, cfg, free_cfg_slot); 511 } 512 513 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch) 514 { 515 ch->cfg.live = true; 516 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain | 517 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1)); 518 } 519 520 static int ad7124_prepare_read(struct ad7124_state *st, int address) 521 { 522 struct ad7124_channel_config *cfg = &st->channels[address].cfg; 523 struct ad7124_channel_config *live_cfg; 524 525 /* 526 * Before doing any reads assign the channel a configuration. 527 * Check if channel's config is on the device 528 */ 529 if (!cfg->live) { 530 /* check if config matches another one */ 531 live_cfg = ad7124_find_similar_live_cfg(st, cfg); 532 if (!live_cfg) 533 ad7124_push_config(st, cfg); 534 else 535 cfg->cfg_slot = live_cfg->cfg_slot; 536 } 537 538 /* point channel to the config slot and enable */ 539 return ad7124_enable_channel(st, &st->channels[address]); 540 } 541 542 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 543 { 544 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 545 546 return ad7124_prepare_read(st, channel); 547 } 548 549 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 550 { 551 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 552 int ret; 553 554 mutex_lock(&st->cfgs_lock); 555 ret = __ad7124_set_channel(sd, channel); 556 mutex_unlock(&st->cfgs_lock); 557 558 return ret; 559 } 560 561 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append) 562 { 563 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 564 unsigned int adc_control = st->adc_control; 565 int ret; 566 567 adc_control &= ~AD7124_ADC_STATUS_EN_MSK; 568 adc_control |= AD7124_ADC_STATUS_EN(append); 569 570 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control); 571 if (ret < 0) 572 return ret; 573 574 st->adc_control = adc_control; 575 576 return 0; 577 } 578 579 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 580 { 581 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 582 583 /* The relevant thing here is that AD7124_CHANNEL_EN_MSK is cleared. */ 584 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0); 585 } 586 587 static int ad7124_disable_all(struct ad_sigma_delta *sd) 588 { 589 int ret; 590 int i; 591 592 for (i = 0; i < 16; i++) { 593 ret = ad7124_disable_one(sd, i); 594 if (ret < 0) 595 return ret; 596 } 597 598 return 0; 599 } 600 601 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = { 602 .set_channel = ad7124_set_channel, 603 .append_status = ad7124_append_status, 604 .disable_all = ad7124_disable_all, 605 .disable_one = ad7124_disable_one, 606 .set_mode = ad7124_set_mode, 607 .has_registers = true, 608 .addr_shift = 0, 609 .read_mask = BIT(6), 610 .status_ch_mask = GENMASK(3, 0), 611 .data_reg = AD7124_DATA, 612 .num_slots = 8, 613 .irq_flags = IRQF_TRIGGER_FALLING, 614 .num_resetclks = 64, 615 }; 616 617 static int ad7124_read_raw(struct iio_dev *indio_dev, 618 struct iio_chan_spec const *chan, 619 int *val, int *val2, long info) 620 { 621 struct ad7124_state *st = iio_priv(indio_dev); 622 int idx, ret; 623 624 switch (info) { 625 case IIO_CHAN_INFO_RAW: 626 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 627 if (ret < 0) 628 return ret; 629 630 return IIO_VAL_INT; 631 case IIO_CHAN_INFO_SCALE: 632 switch (chan->type) { 633 case IIO_VOLTAGE: 634 mutex_lock(&st->cfgs_lock); 635 636 idx = st->channels[chan->address].cfg.pga_bits; 637 *val = st->channels[chan->address].cfg.vref_mv; 638 if (st->channels[chan->address].cfg.bipolar) 639 *val2 = chan->scan_type.realbits - 1 + idx; 640 else 641 *val2 = chan->scan_type.realbits + idx; 642 643 mutex_unlock(&st->cfgs_lock); 644 return IIO_VAL_FRACTIONAL_LOG2; 645 646 case IIO_TEMP: 647 /* 648 * According to the data sheet 649 * Temperature (°C) 650 * = ((Conversion − 0x800000)/13584) − 272.5 651 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584 652 * = (Conversion − 12090248) / 13584 653 * So scale with 1000/13584 to yield °mC. Reduce by 8 to 654 * 125/1698. 655 */ 656 *val = 125; 657 *val2 = 1698; 658 return IIO_VAL_FRACTIONAL; 659 660 default: 661 return -EINVAL; 662 } 663 664 case IIO_CHAN_INFO_OFFSET: 665 switch (chan->type) { 666 case IIO_VOLTAGE: 667 mutex_lock(&st->cfgs_lock); 668 if (st->channels[chan->address].cfg.bipolar) 669 *val = -(1 << (chan->scan_type.realbits - 1)); 670 else 671 *val = 0; 672 673 mutex_unlock(&st->cfgs_lock); 674 return IIO_VAL_INT; 675 676 case IIO_TEMP: 677 /* see calculation above */ 678 *val = -12090248; 679 return IIO_VAL_INT; 680 681 default: 682 return -EINVAL; 683 } 684 685 case IIO_CHAN_INFO_SAMP_FREQ: 686 mutex_lock(&st->cfgs_lock); 687 *val = st->channels[chan->address].cfg.odr; 688 mutex_unlock(&st->cfgs_lock); 689 690 return IIO_VAL_INT; 691 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 692 mutex_lock(&st->cfgs_lock); 693 *val = ad7124_get_3db_filter_freq(st, chan->scan_index); 694 mutex_unlock(&st->cfgs_lock); 695 696 return IIO_VAL_INT; 697 default: 698 return -EINVAL; 699 } 700 } 701 702 static int ad7124_write_raw(struct iio_dev *indio_dev, 703 struct iio_chan_spec const *chan, 704 int val, int val2, long info) 705 { 706 struct ad7124_state *st = iio_priv(indio_dev); 707 unsigned int res, gain, full_scale, vref; 708 int ret = 0; 709 710 mutex_lock(&st->cfgs_lock); 711 712 switch (info) { 713 case IIO_CHAN_INFO_SAMP_FREQ: 714 if (val2 != 0 || val == 0) { 715 ret = -EINVAL; 716 break; 717 } 718 719 ad7124_set_channel_odr(st, chan->address, val); 720 break; 721 case IIO_CHAN_INFO_SCALE: 722 if (val != 0) { 723 ret = -EINVAL; 724 break; 725 } 726 727 if (st->channels[chan->address].cfg.bipolar) 728 full_scale = 1 << (chan->scan_type.realbits - 1); 729 else 730 full_scale = 1 << chan->scan_type.realbits; 731 732 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL; 733 res = DIV_ROUND_CLOSEST(vref, full_scale); 734 gain = DIV_ROUND_CLOSEST(res, val2); 735 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain); 736 737 if (st->channels[chan->address].cfg.pga_bits != res) 738 st->channels[chan->address].cfg.live = false; 739 740 st->channels[chan->address].cfg.pga_bits = res; 741 break; 742 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 743 if (val2 != 0) { 744 ret = -EINVAL; 745 break; 746 } 747 748 ad7124_set_3db_filter_freq(st, chan->address, val); 749 break; 750 default: 751 ret = -EINVAL; 752 } 753 754 mutex_unlock(&st->cfgs_lock); 755 return ret; 756 } 757 758 static int ad7124_reg_access(struct iio_dev *indio_dev, 759 unsigned int reg, 760 unsigned int writeval, 761 unsigned int *readval) 762 { 763 struct ad7124_state *st = iio_priv(indio_dev); 764 int ret; 765 766 if (reg >= ARRAY_SIZE(ad7124_reg_size)) 767 return -EINVAL; 768 769 if (readval) 770 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg], 771 readval); 772 else 773 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg], 774 writeval); 775 776 return ret; 777 } 778 779 static IIO_CONST_ATTR(in_voltage_scale_available, 780 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023"); 781 782 static struct attribute *ad7124_attributes[] = { 783 &iio_const_attr_in_voltage_scale_available.dev_attr.attr, 784 NULL, 785 }; 786 787 static const struct attribute_group ad7124_attrs_group = { 788 .attrs = ad7124_attributes, 789 }; 790 791 static int ad7124_update_scan_mode(struct iio_dev *indio_dev, 792 const unsigned long *scan_mask) 793 { 794 struct ad7124_state *st = iio_priv(indio_dev); 795 bool bit_set; 796 int ret; 797 int i; 798 799 mutex_lock(&st->cfgs_lock); 800 for (i = 0; i < st->num_channels; i++) { 801 bit_set = test_bit(i, scan_mask); 802 if (bit_set) 803 ret = __ad7124_set_channel(&st->sd, i); 804 else 805 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 806 0, 2); 807 if (ret < 0) { 808 mutex_unlock(&st->cfgs_lock); 809 810 return ret; 811 } 812 } 813 814 mutex_unlock(&st->cfgs_lock); 815 816 return 0; 817 } 818 819 static const struct iio_info ad7124_info = { 820 .read_raw = ad7124_read_raw, 821 .write_raw = ad7124_write_raw, 822 .debugfs_reg_access = &ad7124_reg_access, 823 .validate_trigger = ad_sd_validate_trigger, 824 .update_scan_mode = ad7124_update_scan_mode, 825 .attrs = &ad7124_attrs_group, 826 }; 827 828 /* Only called during probe, so dev_err_probe() can be used */ 829 static int ad7124_soft_reset(struct ad7124_state *st) 830 { 831 struct device *dev = &st->sd.spi->dev; 832 unsigned int readval, timeout; 833 int ret; 834 835 ret = ad_sd_reset(&st->sd); 836 if (ret < 0) 837 return ret; 838 839 fsleep(200); 840 timeout = 100; 841 do { 842 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval); 843 if (ret < 0) 844 return dev_err_probe(dev, ret, "Error reading status register\n"); 845 846 if (!(readval & AD7124_STATUS_POR_FLAG_MSK)) 847 break; 848 849 /* The AD7124 requires typically 2ms to power up and settle */ 850 usleep_range(100, 2000); 851 } while (--timeout); 852 853 if (readval & AD7124_STATUS_POR_FLAG_MSK) 854 return dev_err_probe(dev, -EIO, "Soft reset failed\n"); 855 856 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &st->gain_default); 857 if (ret < 0) 858 return dev_err_probe(dev, ret, "Error reading gain register\n"); 859 860 dev_dbg(dev, "Reset value of GAIN register is 0x%x\n", st->gain_default); 861 862 return 0; 863 } 864 865 static int ad7124_check_chip_id(struct ad7124_state *st) 866 { 867 struct device *dev = &st->sd.spi->dev; 868 unsigned int readval, chip_id, silicon_rev; 869 int ret; 870 871 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval); 872 if (ret < 0) 873 return dev_err_probe(dev, ret, "Failure to read ID register\n"); 874 875 chip_id = AD7124_DEVICE_ID_GET(readval); 876 silicon_rev = AD7124_SILICON_REV_GET(readval); 877 878 if (chip_id != st->chip_info->chip_id) 879 return dev_err_probe(dev, -ENODEV, 880 "Chip ID mismatch: expected %u, got %u\n", 881 st->chip_info->chip_id, chip_id); 882 883 if (silicon_rev == 0) 884 return dev_err_probe(dev, -ENODEV, 885 "Silicon revision empty. Chip may not be present\n"); 886 887 return 0; 888 } 889 890 enum { 891 AD7124_SYSCALIB_ZERO_SCALE, 892 AD7124_SYSCALIB_FULL_SCALE, 893 }; 894 895 static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan_spec *chan) 896 { 897 struct device *dev = &st->sd.spi->dev; 898 struct ad7124_channel *ch = &st->channels[chan->channel]; 899 int ret; 900 901 if (ch->syscalib_mode == AD7124_SYSCALIB_ZERO_SCALE) { 902 ch->cfg.calibration_offset = 0x800000; 903 904 ret = ad_sd_calibrate(&st->sd, AD7124_MODE_CAL_SYS_ZERO, 905 chan->address); 906 if (ret < 0) 907 return ret; 908 909 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(ch->cfg.cfg_slot), 3, 910 &ch->cfg.calibration_offset); 911 if (ret < 0) 912 return ret; 913 914 dev_dbg(dev, "offset for channel %d after zero-scale calibration: 0x%x\n", 915 chan->channel, ch->cfg.calibration_offset); 916 } else { 917 ch->cfg.calibration_gain = st->gain_default; 918 919 ret = ad_sd_calibrate(&st->sd, AD7124_MODE_CAL_SYS_FULL, 920 chan->address); 921 if (ret < 0) 922 return ret; 923 924 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(ch->cfg.cfg_slot), 3, 925 &ch->cfg.calibration_gain); 926 if (ret < 0) 927 return ret; 928 929 dev_dbg(dev, "gain for channel %d after full-scale calibration: 0x%x\n", 930 chan->channel, ch->cfg.calibration_gain); 931 } 932 933 return 0; 934 } 935 936 static ssize_t ad7124_write_syscalib(struct iio_dev *indio_dev, 937 uintptr_t private, 938 const struct iio_chan_spec *chan, 939 const char *buf, size_t len) 940 { 941 struct ad7124_state *st = iio_priv(indio_dev); 942 bool sys_calib; 943 int ret; 944 945 ret = kstrtobool(buf, &sys_calib); 946 if (ret) 947 return ret; 948 949 if (!sys_calib) 950 return len; 951 952 if (!iio_device_claim_direct(indio_dev)) 953 return -EBUSY; 954 955 ret = ad7124_syscalib_locked(st, chan); 956 957 iio_device_release_direct(indio_dev); 958 959 return ret ?: len; 960 } 961 962 static const char * const ad7124_syscalib_modes[] = { 963 [AD7124_SYSCALIB_ZERO_SCALE] = "zero_scale", 964 [AD7124_SYSCALIB_FULL_SCALE] = "full_scale", 965 }; 966 967 static int ad7124_set_syscalib_mode(struct iio_dev *indio_dev, 968 const struct iio_chan_spec *chan, 969 unsigned int mode) 970 { 971 struct ad7124_state *st = iio_priv(indio_dev); 972 973 st->channels[chan->channel].syscalib_mode = mode; 974 975 return 0; 976 } 977 978 static int ad7124_get_syscalib_mode(struct iio_dev *indio_dev, 979 const struct iio_chan_spec *chan) 980 { 981 struct ad7124_state *st = iio_priv(indio_dev); 982 983 return st->channels[chan->channel].syscalib_mode; 984 } 985 986 static const struct iio_enum ad7124_syscalib_mode_enum = { 987 .items = ad7124_syscalib_modes, 988 .num_items = ARRAY_SIZE(ad7124_syscalib_modes), 989 .set = ad7124_set_syscalib_mode, 990 .get = ad7124_get_syscalib_mode 991 }; 992 993 static const struct iio_chan_spec_ext_info ad7124_calibsys_ext_info[] = { 994 { 995 .name = "sys_calibration", 996 .write = ad7124_write_syscalib, 997 .shared = IIO_SEPARATE, 998 }, 999 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 1000 &ad7124_syscalib_mode_enum), 1001 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 1002 &ad7124_syscalib_mode_enum), 1003 { } 1004 }; 1005 1006 static const struct iio_chan_spec ad7124_channel_template = { 1007 .type = IIO_VOLTAGE, 1008 .indexed = 1, 1009 .differential = 1, 1010 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1011 BIT(IIO_CHAN_INFO_SCALE) | 1012 BIT(IIO_CHAN_INFO_OFFSET) | 1013 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 1014 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 1015 .scan_type = { 1016 .sign = 'u', 1017 .realbits = 24, 1018 .storagebits = 32, 1019 .endianness = IIO_BE, 1020 }, 1021 .ext_info = ad7124_calibsys_ext_info, 1022 }; 1023 1024 /* 1025 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4 1026 * while they are fine for ad7124-8. Values above 31 don't fit 1027 * into the register field and so are invalid for sure. 1028 */ 1029 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info) 1030 { 1031 if (ain >= info->num_inputs && ain < 16) 1032 return false; 1033 1034 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM_MSK); 1035 } 1036 1037 static int ad7124_parse_channel_config(struct iio_dev *indio_dev, 1038 struct device *dev) 1039 { 1040 struct ad7124_state *st = iio_priv(indio_dev); 1041 struct ad7124_channel_config *cfg; 1042 struct ad7124_channel *channels; 1043 struct iio_chan_spec *chan; 1044 unsigned int ain[2], channel = 0, tmp; 1045 unsigned int num_channels; 1046 int ret; 1047 1048 num_channels = device_get_child_node_count(dev); 1049 1050 /* 1051 * The driver assigns each logical channel defined in the device tree 1052 * statically one channel register. So only accept 16 such logical 1053 * channels to not treat CONFIG_0 (i.e. the register following 1054 * CHANNEL_15) as an additional channel register. The driver could be 1055 * improved to lift this limitation. 1056 */ 1057 if (num_channels > AD7124_MAX_CHANNELS) 1058 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n"); 1059 1060 /* Add one for temperature */ 1061 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS); 1062 1063 chan = devm_kcalloc(dev, st->num_channels, 1064 sizeof(*chan), GFP_KERNEL); 1065 if (!chan) 1066 return -ENOMEM; 1067 1068 channels = devm_kcalloc(dev, st->num_channels, sizeof(*channels), 1069 GFP_KERNEL); 1070 if (!channels) 1071 return -ENOMEM; 1072 1073 indio_dev->channels = chan; 1074 indio_dev->num_channels = st->num_channels; 1075 st->channels = channels; 1076 1077 device_for_each_child_node_scoped(dev, child) { 1078 ret = fwnode_property_read_u32(child, "reg", &channel); 1079 if (ret) 1080 return dev_err_probe(dev, ret, 1081 "Failed to parse reg property of %pfwP\n", child); 1082 1083 if (channel >= num_channels) 1084 return dev_err_probe(dev, -EINVAL, 1085 "Channel index >= number of channels in %pfwP\n", child); 1086 1087 ret = fwnode_property_read_u32_array(child, "diff-channels", 1088 ain, 2); 1089 if (ret) 1090 return dev_err_probe(dev, ret, 1091 "Failed to parse diff-channels property of %pfwP\n", child); 1092 1093 if (!ad7124_valid_input_select(ain[0], st->chip_info) || 1094 !ad7124_valid_input_select(ain[1], st->chip_info)) 1095 return dev_err_probe(dev, -EINVAL, 1096 "diff-channels property of %pfwP contains invalid data\n", child); 1097 1098 st->channels[channel].nr = channel; 1099 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) | 1100 AD7124_CHANNEL_AINM(ain[1]); 1101 1102 cfg = &st->channels[channel].cfg; 1103 cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 1104 1105 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp); 1106 if (ret) 1107 cfg->refsel = AD7124_INT_REF; 1108 else 1109 cfg->refsel = tmp; 1110 1111 cfg->buf_positive = 1112 fwnode_property_read_bool(child, "adi,buffered-positive"); 1113 cfg->buf_negative = 1114 fwnode_property_read_bool(child, "adi,buffered-negative"); 1115 1116 chan[channel] = ad7124_channel_template; 1117 chan[channel].address = channel; 1118 chan[channel].scan_index = channel; 1119 chan[channel].channel = ain[0]; 1120 chan[channel].channel2 = ain[1]; 1121 } 1122 1123 if (num_channels < AD7124_MAX_CHANNELS) { 1124 st->channels[num_channels] = (struct ad7124_channel) { 1125 .nr = num_channels, 1126 .ain = AD7124_CHANNEL_AINP(AD7124_INPUT_TEMPSENSOR) | 1127 AD7124_CHANNEL_AINM(AD7124_INPUT_AVSS), 1128 .cfg = { 1129 .bipolar = true, 1130 }, 1131 }; 1132 1133 chan[num_channels] = (struct iio_chan_spec) { 1134 .type = IIO_TEMP, 1135 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1136 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1137 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1138 .scan_type = { 1139 /* 1140 * You might find it strange that a bipolar 1141 * measurement yields an unsigned value, but 1142 * this matches the device's manual. 1143 */ 1144 .sign = 'u', 1145 .realbits = 24, 1146 .storagebits = 32, 1147 .endianness = IIO_BE, 1148 }, 1149 .address = num_channels, 1150 .scan_index = num_channels, 1151 }; 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int ad7124_setup(struct ad7124_state *st) 1158 { 1159 struct device *dev = &st->sd.spi->dev; 1160 unsigned int fclk, power_mode; 1161 int i, ret; 1162 1163 fclk = clk_get_rate(st->mclk); 1164 if (!fclk) 1165 return dev_err_probe(dev, -EINVAL, "Failed to get mclk rate\n"); 1166 1167 /* The power mode changes the master clock frequency */ 1168 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz, 1169 ARRAY_SIZE(ad7124_master_clk_freq_hz), 1170 fclk); 1171 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { 1172 ret = clk_set_rate(st->mclk, fclk); 1173 if (ret) 1174 return dev_err_probe(dev, ret, "Failed to set mclk rate\n"); 1175 } 1176 1177 /* Set the power mode */ 1178 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK; 1179 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode); 1180 1181 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK; 1182 st->adc_control |= AD7124_ADC_CTRL_MODE(AD_SD_MODE_IDLE); 1183 1184 mutex_init(&st->cfgs_lock); 1185 INIT_KFIFO(st->live_cfgs_fifo); 1186 for (i = 0; i < st->num_channels; i++) { 1187 1188 ret = ad7124_init_config_vref(st, &st->channels[i].cfg); 1189 if (ret < 0) 1190 return ret; 1191 1192 /* 1193 * 9.38 SPS is the minimum output data rate supported 1194 * regardless of the selected power mode. Round it up to 10 and 1195 * set all channels to this default value. 1196 */ 1197 ad7124_set_channel_odr(st, i, 10); 1198 } 1199 1200 ad7124_disable_all(&st->sd); 1201 1202 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 1203 if (ret < 0) 1204 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n"); 1205 1206 return ret; 1207 } 1208 1209 static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev) 1210 { 1211 struct device *dev = &st->sd.spi->dev; 1212 int ret, i; 1213 1214 for (i = 0; i < st->num_channels; i++) { 1215 1216 if (indio_dev->channels[i].type != IIO_VOLTAGE) 1217 continue; 1218 1219 /* 1220 * For calibration the OFFSET register should hold its reset default 1221 * value. For the GAIN register there is no such requirement but 1222 * for gain 1 it should hold the reset default value, too. So to 1223 * simplify matters use the reset default value for both. 1224 */ 1225 st->channels[i].cfg.calibration_offset = 0x800000; 1226 st->channels[i].cfg.calibration_gain = st->gain_default; 1227 1228 /* 1229 * Full-scale calibration isn't supported at gain 1, so skip in 1230 * that case. Note that untypically full-scale calibration has 1231 * to happen before zero-scale calibration. This only applies to 1232 * the internal calibration. For system calibration it's as 1233 * usual: first zero-scale then full-scale calibration. 1234 */ 1235 if (st->channels[i].cfg.pga_bits > 0) { 1236 ret = ad_sd_calibrate(&st->sd, AD7124_MODE_CAL_INT_FULL, i); 1237 if (ret < 0) 1238 return ret; 1239 1240 /* 1241 * read out the resulting value of GAIN 1242 * after full-scale calibration because the next 1243 * ad_sd_calibrate() call overwrites this via 1244 * ad_sigma_delta_set_channel() -> ad7124_set_channel() 1245 * ... -> ad7124_enable_channel(). 1246 */ 1247 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(st->channels[i].cfg.cfg_slot), 3, 1248 &st->channels[i].cfg.calibration_gain); 1249 if (ret < 0) 1250 return ret; 1251 } 1252 1253 ret = ad_sd_calibrate(&st->sd, AD7124_MODE_CAL_INT_ZERO, i); 1254 if (ret < 0) 1255 return ret; 1256 1257 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(st->channels[i].cfg.cfg_slot), 3, 1258 &st->channels[i].cfg.calibration_offset); 1259 if (ret < 0) 1260 return ret; 1261 1262 dev_dbg(dev, "offset and gain for channel %d = 0x%x + 0x%x\n", i, 1263 st->channels[i].cfg.calibration_offset, 1264 st->channels[i].cfg.calibration_gain); 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev) 1271 { 1272 int ret; 1273 unsigned int adc_control = st->adc_control; 1274 1275 /* 1276 * Calibration isn't supported at full power, so speed down a bit. 1277 * Setting .adc_control is enough here because the control register is 1278 * written as part of ad_sd_calibrate() -> ad_sigma_delta_set_mode(). 1279 * The resulting calibration is then also valid for high-speed, so just 1280 * restore adc_control afterwards. 1281 */ 1282 if (FIELD_GET(AD7124_ADC_CTRL_PWR_MSK, adc_control) >= AD7124_FULL_POWER) { 1283 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK; 1284 st->adc_control |= AD7124_ADC_CTRL_PWR(AD7124_MID_POWER); 1285 } 1286 1287 ret = __ad7124_calibrate_all(st, indio_dev); 1288 1289 st->adc_control = adc_control; 1290 1291 return ret; 1292 } 1293 1294 static void ad7124_reg_disable(void *r) 1295 { 1296 regulator_disable(r); 1297 } 1298 1299 static int ad7124_probe(struct spi_device *spi) 1300 { 1301 const struct ad7124_chip_info *info; 1302 struct device *dev = &spi->dev; 1303 struct ad7124_state *st; 1304 struct iio_dev *indio_dev; 1305 int i, ret; 1306 1307 info = spi_get_device_match_data(spi); 1308 if (!info) 1309 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n"); 1310 1311 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1312 if (!indio_dev) 1313 return -ENOMEM; 1314 1315 st = iio_priv(indio_dev); 1316 1317 st->chip_info = info; 1318 1319 indio_dev->name = st->chip_info->name; 1320 indio_dev->modes = INDIO_DIRECT_MODE; 1321 indio_dev->info = &ad7124_info; 1322 1323 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info); 1324 if (ret < 0) 1325 return ret; 1326 1327 ret = ad7124_parse_channel_config(indio_dev, &spi->dev); 1328 if (ret < 0) 1329 return ret; 1330 1331 for (i = 0; i < ARRAY_SIZE(st->vref); i++) { 1332 if (i == AD7124_INT_REF) 1333 continue; 1334 1335 st->vref[i] = devm_regulator_get_optional(&spi->dev, 1336 ad7124_ref_names[i]); 1337 if (PTR_ERR(st->vref[i]) == -ENODEV) 1338 continue; 1339 else if (IS_ERR(st->vref[i])) 1340 return PTR_ERR(st->vref[i]); 1341 1342 ret = regulator_enable(st->vref[i]); 1343 if (ret) 1344 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i); 1345 1346 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable, 1347 st->vref[i]); 1348 if (ret) 1349 return dev_err_probe(dev, ret, "Failed to register disable handler for regulator #%d\n", i); 1350 } 1351 1352 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 1353 if (IS_ERR(st->mclk)) 1354 return dev_err_probe(dev, PTR_ERR(st->mclk), "Failed to get mclk\n"); 1355 1356 ret = ad7124_soft_reset(st); 1357 if (ret < 0) 1358 return ret; 1359 1360 ret = ad7124_check_chip_id(st); 1361 if (ret) 1362 return ret; 1363 1364 ret = ad7124_setup(st); 1365 if (ret < 0) 1366 return ret; 1367 1368 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 1369 if (ret < 0) 1370 return dev_err_probe(dev, ret, "Failed to setup triggers\n"); 1371 1372 ret = ad7124_calibrate_all(st, indio_dev); 1373 if (ret) 1374 return ret; 1375 1376 ret = devm_iio_device_register(&spi->dev, indio_dev); 1377 if (ret < 0) 1378 return dev_err_probe(dev, ret, "Failed to register iio device\n"); 1379 1380 return 0; 1381 } 1382 1383 static const struct of_device_id ad7124_of_match[] = { 1384 { .compatible = "adi,ad7124-4", 1385 .data = &ad7124_chip_info_tbl[ID_AD7124_4], }, 1386 { .compatible = "adi,ad7124-8", 1387 .data = &ad7124_chip_info_tbl[ID_AD7124_8], }, 1388 { } 1389 }; 1390 MODULE_DEVICE_TABLE(of, ad7124_of_match); 1391 1392 static const struct spi_device_id ad71124_ids[] = { 1393 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] }, 1394 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] }, 1395 { } 1396 }; 1397 MODULE_DEVICE_TABLE(spi, ad71124_ids); 1398 1399 static struct spi_driver ad71124_driver = { 1400 .driver = { 1401 .name = "ad7124", 1402 .of_match_table = ad7124_of_match, 1403 }, 1404 .probe = ad7124_probe, 1405 .id_table = ad71124_ids, 1406 }; 1407 module_spi_driver(ad71124_driver); 1408 1409 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1410 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver"); 1411 MODULE_LICENSE("GPL"); 1412 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1413