1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI ADC driver for Analog Devices Inc. AD4695 and similar chips 4 * 5 * https://www.analog.com/en/products/ad4695.html 6 * https://www.analog.com/en/products/ad4696.html 7 * https://www.analog.com/en/products/ad4697.html 8 * https://www.analog.com/en/products/ad4698.html 9 * 10 * Copyright 2024 Analog Devices Inc. 11 * Copyright 2024 BayLibre, SAS 12 */ 13 14 #include <linux/align.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/compiler.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/err.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/triggered_buffer.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/minmax.h> 27 #include <linux/property.h> 28 #include <linux/regmap.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/spi/spi.h> 31 #include <linux/units.h> 32 33 #include <dt-bindings/iio/adi,ad4695.h> 34 35 /* AD4695 registers */ 36 #define AD4695_REG_SPI_CONFIG_A 0x0000 37 #define AD4695_REG_SPI_CONFIG_A_SW_RST (BIT(7) | BIT(0)) 38 #define AD4695_REG_SPI_CONFIG_A_ADDR_DIR BIT(5) 39 #define AD4695_REG_SPI_CONFIG_B 0x0001 40 #define AD4695_REG_SPI_CONFIG_B_INST_MODE BIT(7) 41 #define AD4695_REG_DEVICE_TYPE 0x0003 42 #define AD4695_REG_SCRATCH_PAD 0x000A 43 #define AD4695_REG_VENDOR_L 0x000C 44 #define AD4695_REG_VENDOR_H 0x000D 45 #define AD4695_REG_LOOP_MODE 0x000E 46 #define AD4695_REG_SPI_CONFIG_C 0x0010 47 #define AD4695_REG_SPI_CONFIG_C_MB_STRICT BIT(7) 48 #define AD4695_REG_SPI_STATUS 0x0011 49 #define AD4695_REG_STATUS 0x0014 50 #define AD4695_REG_ALERT_STATUS1 0x0015 51 #define AD4695_REG_ALERT_STATUS2 0x0016 52 #define AD4695_REG_CLAMP_STATUS 0x001A 53 #define AD4695_REG_SETUP 0x0020 54 #define AD4695_REG_SETUP_LDO_EN BIT(4) 55 #define AD4695_REG_SETUP_SPI_MODE BIT(2) 56 #define AD4695_REG_SETUP_SPI_CYC_CTRL BIT(1) 57 #define AD4695_REG_REF_CTRL 0x0021 58 #define AD4695_REG_REF_CTRL_OV_MODE BIT(7) 59 #define AD4695_REG_REF_CTRL_VREF_SET GENMASK(4, 2) 60 #define AD4695_REG_REF_CTRL_REFHIZ_EN BIT(1) 61 #define AD4695_REG_REF_CTRL_REFBUF_EN BIT(0) 62 #define AD4695_REG_SEQ_CTRL 0x0022 63 #define AD4695_REG_SEQ_CTRL_STD_SEQ_EN BIT(7) 64 #define AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS GENMASK(6, 0) 65 #define AD4695_REG_AC_CTRL 0x0023 66 #define AD4695_REG_STD_SEQ_CONFIG 0x0024 67 #define AD4695_REG_GPIO_CTRL 0x0026 68 #define AD4695_REG_GP_MODE 0x0027 69 #define AD4695_REG_TEMP_CTRL 0x0029 70 #define AD4695_REG_TEMP_CTRL_TEMP_EN BIT(0) 71 #define AD4695_REG_CONFIG_IN(n) (0x0030 | (n)) 72 #define AD4695_REG_CONFIG_IN_MODE BIT(6) 73 #define AD4695_REG_CONFIG_IN_PAIR GENMASK(5, 4) 74 #define AD4695_REG_CONFIG_IN_AINHIGHZ_EN BIT(3) 75 #define AD4695_REG_UPPER_IN(n) (0x0040 | (2 * (n))) 76 #define AD4695_REG_LOWER_IN(n) (0x0060 | (2 * (n))) 77 #define AD4695_REG_HYST_IN(n) (0x0080 | (2 * (n))) 78 #define AD4695_REG_OFFSET_IN(n) (0x00A0 | (2 * (n))) 79 #define AD4695_REG_GAIN_IN(n) (0x00C0 | (2 * (n))) 80 #define AD4695_REG_AS_SLOT(n) (0x0100 | (n)) 81 #define AD4695_REG_AS_SLOT_INX GENMASK(3, 0) 82 83 /* Conversion mode commands */ 84 #define AD4695_CMD_EXIT_CNV_MODE 0x0A 85 #define AD4695_CMD_TEMP_CHAN 0x0F 86 #define AD4695_CMD_VOLTAGE_CHAN(n) (0x10 | (n)) 87 88 /* timing specs */ 89 #define AD4695_T_CONVERT_NS 415 90 #define AD4695_T_WAKEUP_HW_MS 3 91 #define AD4695_T_WAKEUP_SW_MS 3 92 #define AD4695_T_REFBUF_MS 100 93 #define AD4695_T_REGCONFIG_NS 20 94 #define AD4695_T_SCK_CNV_DELAY_NS 80 95 #define AD4695_REG_ACCESS_SCLK_HZ (10 * MEGA) 96 97 /* Max number of voltage input channels. */ 98 #define AD4695_MAX_CHANNELS 16 99 /* Max size of 1 raw sample in bytes. */ 100 #define AD4695_MAX_CHANNEL_SIZE 2 101 102 enum ad4695_in_pair { 103 AD4695_IN_PAIR_REFGND, 104 AD4695_IN_PAIR_COM, 105 AD4695_IN_PAIR_EVEN_ODD, 106 }; 107 108 struct ad4695_chip_info { 109 const char *name; 110 int max_sample_rate; 111 u32 t_acq_ns; 112 u8 num_voltage_inputs; 113 }; 114 115 struct ad4695_channel_config { 116 unsigned int channel; 117 bool highz_en; 118 bool bipolar; 119 enum ad4695_in_pair pin_pairing; 120 unsigned int common_mode_mv; 121 }; 122 123 struct ad4695_state { 124 struct spi_device *spi; 125 struct regmap *regmap; 126 struct regmap *regmap16; 127 struct gpio_desc *reset_gpio; 128 /* voltages channels plus temperature and timestamp */ 129 struct iio_chan_spec iio_chan[AD4695_MAX_CHANNELS + 2]; 130 struct ad4695_channel_config channels_cfg[AD4695_MAX_CHANNELS]; 131 const struct ad4695_chip_info *chip_info; 132 /* Reference voltage. */ 133 unsigned int vref_mv; 134 /* Common mode input pin voltage. */ 135 unsigned int com_mv; 136 /* 137 * 2 per voltage and temperature chan plus 1 xfer to trigger 1st 138 * CNV. Excluding the trigger xfer, every 2nd xfer only serves 139 * to control CS and add a delay between the last SCLK and next 140 * CNV rising edges. 141 */ 142 struct spi_transfer buf_read_xfer[AD4695_MAX_CHANNELS * 2 + 3]; 143 struct spi_message buf_read_msg; 144 /* Raw conversion data received. */ 145 u8 buf[ALIGN((AD4695_MAX_CHANNELS + 2) * AD4695_MAX_CHANNEL_SIZE, 146 sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); 147 u16 raw_data; 148 /* Commands to send for single conversion. */ 149 u16 cnv_cmd; 150 u8 cnv_cmd2; 151 }; 152 153 static const struct regmap_range ad4695_regmap_rd_ranges[] = { 154 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B), 155 regmap_reg_range(AD4695_REG_DEVICE_TYPE, AD4695_REG_DEVICE_TYPE), 156 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD), 157 regmap_reg_range(AD4695_REG_VENDOR_L, AD4695_REG_LOOP_MODE), 158 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS), 159 regmap_reg_range(AD4695_REG_STATUS, AD4695_REG_ALERT_STATUS2), 160 regmap_reg_range(AD4695_REG_CLAMP_STATUS, AD4695_REG_CLAMP_STATUS), 161 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL), 162 regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL), 163 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)), 164 regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)), 165 }; 166 167 static const struct regmap_access_table ad4695_regmap_rd_table = { 168 .yes_ranges = ad4695_regmap_rd_ranges, 169 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_rd_ranges), 170 }; 171 172 static const struct regmap_range ad4695_regmap_wr_ranges[] = { 173 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B), 174 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD), 175 regmap_reg_range(AD4695_REG_LOOP_MODE, AD4695_REG_LOOP_MODE), 176 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS), 177 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL), 178 regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL), 179 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)), 180 regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)), 181 }; 182 183 static const struct regmap_access_table ad4695_regmap_wr_table = { 184 .yes_ranges = ad4695_regmap_wr_ranges, 185 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_wr_ranges), 186 }; 187 188 static const struct regmap_config ad4695_regmap_config = { 189 .name = "ad4695-8", 190 .reg_bits = 16, 191 .val_bits = 8, 192 .max_register = AD4695_REG_AS_SLOT(127), 193 .rd_table = &ad4695_regmap_rd_table, 194 .wr_table = &ad4695_regmap_wr_table, 195 .can_multi_write = true, 196 }; 197 198 static const struct regmap_range ad4695_regmap16_rd_ranges[] = { 199 regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG), 200 regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)), 201 }; 202 203 static const struct regmap_access_table ad4695_regmap16_rd_table = { 204 .yes_ranges = ad4695_regmap16_rd_ranges, 205 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap16_rd_ranges), 206 }; 207 208 static const struct regmap_range ad4695_regmap16_wr_ranges[] = { 209 regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG), 210 regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)), 211 }; 212 213 static const struct regmap_access_table ad4695_regmap16_wr_table = { 214 .yes_ranges = ad4695_regmap16_wr_ranges, 215 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap16_wr_ranges), 216 }; 217 218 static const struct regmap_config ad4695_regmap16_config = { 219 .name = "ad4695-16", 220 .reg_bits = 16, 221 .reg_stride = 2, 222 .val_bits = 16, 223 .val_format_endian = REGMAP_ENDIAN_LITTLE, 224 .max_register = AD4695_REG_GAIN_IN(15), 225 .rd_table = &ad4695_regmap16_rd_table, 226 .wr_table = &ad4695_regmap16_wr_table, 227 .can_multi_write = true, 228 }; 229 230 static const struct iio_chan_spec ad4695_channel_template = { 231 .type = IIO_VOLTAGE, 232 .indexed = 1, 233 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 234 BIT(IIO_CHAN_INFO_SCALE) | 235 BIT(IIO_CHAN_INFO_OFFSET) | 236 BIT(IIO_CHAN_INFO_CALIBSCALE) | 237 BIT(IIO_CHAN_INFO_CALIBBIAS), 238 .info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBSCALE) | 239 BIT(IIO_CHAN_INFO_CALIBBIAS), 240 .scan_type = { 241 .sign = 'u', 242 .realbits = 16, 243 .storagebits = 16, 244 }, 245 }; 246 247 static const struct iio_chan_spec ad4695_temp_channel_template = { 248 .address = AD4695_CMD_TEMP_CHAN, 249 .type = IIO_TEMP, 250 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 251 BIT(IIO_CHAN_INFO_SCALE) | 252 BIT(IIO_CHAN_INFO_OFFSET), 253 .scan_type = { 254 .sign = 's', 255 .realbits = 16, 256 .storagebits = 16, 257 }, 258 }; 259 260 static const struct iio_chan_spec ad4695_soft_timestamp_channel_template = 261 IIO_CHAN_SOFT_TIMESTAMP(0); 262 263 static const char * const ad4695_power_supplies[] = { 264 "avdd", "vio" 265 }; 266 267 static const struct ad4695_chip_info ad4695_chip_info = { 268 .name = "ad4695", 269 .max_sample_rate = 500 * KILO, 270 .t_acq_ns = 1715, 271 .num_voltage_inputs = 16, 272 }; 273 274 static const struct ad4695_chip_info ad4696_chip_info = { 275 .name = "ad4696", 276 .max_sample_rate = 1 * MEGA, 277 .t_acq_ns = 715, 278 .num_voltage_inputs = 16, 279 }; 280 281 static const struct ad4695_chip_info ad4697_chip_info = { 282 .name = "ad4697", 283 .max_sample_rate = 500 * KILO, 284 .t_acq_ns = 1715, 285 .num_voltage_inputs = 8, 286 }; 287 288 static const struct ad4695_chip_info ad4698_chip_info = { 289 .name = "ad4698", 290 .max_sample_rate = 1 * MEGA, 291 .t_acq_ns = 715, 292 .num_voltage_inputs = 8, 293 }; 294 295 /** 296 * ad4695_set_single_cycle_mode - Set the device in single cycle mode 297 * @st: The AD4695 state 298 * @channel: The first channel to read 299 * 300 * As per the datasheet, to enable single cycle mode, we need to set 301 * STD_SEQ_EN=0, NUM_SLOTS_AS=0 and CYC_CTRL=1 (Table 15). Setting SPI_MODE=1 302 * triggers the first conversion using the channel in AS_SLOT0. 303 * 304 * Context: can sleep, must be called with iio_device_claim_direct held 305 * Return: 0 on success, a negative error code on failure 306 */ 307 static int ad4695_set_single_cycle_mode(struct ad4695_state *st, 308 unsigned int channel) 309 { 310 int ret; 311 312 ret = regmap_clear_bits(st->regmap, AD4695_REG_SEQ_CTRL, 313 AD4695_REG_SEQ_CTRL_STD_SEQ_EN | 314 AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS); 315 if (ret) 316 return ret; 317 318 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(0), 319 FIELD_PREP(AD4695_REG_AS_SLOT_INX, channel)); 320 if (ret) 321 return ret; 322 323 return regmap_set_bits(st->regmap, AD4695_REG_SETUP, 324 AD4695_REG_SETUP_SPI_MODE | 325 AD4695_REG_SETUP_SPI_CYC_CTRL); 326 } 327 328 /** 329 * ad4695_enter_advanced_sequencer_mode - Put the ADC in advanced sequencer mode 330 * @st: The driver state 331 * @n: The number of slots to use - must be >= 2, <= 128 332 * 333 * As per the datasheet, to enable advanced sequencer, we need to set 334 * STD_SEQ_EN=0, NUM_SLOTS_AS=n-1 and CYC_CTRL=0 (Table 15). Setting SPI_MODE=1 335 * triggers the first conversion using the channel in AS_SLOT0. 336 * 337 * Return: 0 on success, a negative error code on failure 338 */ 339 static int ad4695_enter_advanced_sequencer_mode(struct ad4695_state *st, u32 n) 340 { 341 int ret; 342 343 ret = regmap_update_bits(st->regmap, AD4695_REG_SEQ_CTRL, 344 AD4695_REG_SEQ_CTRL_STD_SEQ_EN | 345 AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS, 346 FIELD_PREP(AD4695_REG_SEQ_CTRL_STD_SEQ_EN, 0) | 347 FIELD_PREP(AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS, n - 1)); 348 if (ret) 349 return ret; 350 351 return regmap_update_bits(st->regmap, AD4695_REG_SETUP, 352 AD4695_REG_SETUP_SPI_MODE | AD4695_REG_SETUP_SPI_CYC_CTRL, 353 FIELD_PREP(AD4695_REG_SETUP_SPI_MODE, 1) | 354 FIELD_PREP(AD4695_REG_SETUP_SPI_CYC_CTRL, 0)); 355 } 356 357 /** 358 * ad4695_exit_conversion_mode - Exit conversion mode 359 * @st: The AD4695 state 360 * 361 * Sends SPI command to exit conversion mode. 362 * 363 * Return: 0 on success, a negative error code on failure 364 */ 365 static int ad4695_exit_conversion_mode(struct ad4695_state *st) 366 { 367 struct spi_transfer xfer = { 368 .tx_buf = &st->cnv_cmd2, 369 .len = 1, 370 .delay.value = AD4695_T_REGCONFIG_NS, 371 .delay.unit = SPI_DELAY_UNIT_NSECS, 372 }; 373 374 /* 375 * Technically, could do a 5-bit transfer, but shifting to start of 376 * 8 bits instead for better SPI controller support. 377 */ 378 st->cnv_cmd2 = AD4695_CMD_EXIT_CNV_MODE << 3; 379 380 return spi_sync_transfer(st->spi, &xfer, 1); 381 } 382 383 static int ad4695_set_ref_voltage(struct ad4695_state *st, int vref_mv) 384 { 385 u8 val; 386 387 if (vref_mv >= 2400 && vref_mv <= 2750) 388 val = 0; 389 else if (vref_mv > 2750 && vref_mv <= 3250) 390 val = 1; 391 else if (vref_mv > 3250 && vref_mv <= 3750) 392 val = 2; 393 else if (vref_mv > 3750 && vref_mv <= 4500) 394 val = 3; 395 else if (vref_mv > 4500 && vref_mv <= 5100) 396 val = 4; 397 else 398 return -EINVAL; 399 400 return regmap_update_bits(st->regmap, AD4695_REG_REF_CTRL, 401 AD4695_REG_REF_CTRL_VREF_SET, 402 FIELD_PREP(AD4695_REG_REF_CTRL_VREF_SET, val)); 403 } 404 405 static int ad4695_write_chn_cfg(struct ad4695_state *st, 406 struct ad4695_channel_config *cfg) 407 { 408 u32 mask, val; 409 410 mask = AD4695_REG_CONFIG_IN_MODE; 411 val = FIELD_PREP(AD4695_REG_CONFIG_IN_MODE, cfg->bipolar ? 1 : 0); 412 413 mask |= AD4695_REG_CONFIG_IN_PAIR; 414 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_PAIR, cfg->pin_pairing); 415 416 mask |= AD4695_REG_CONFIG_IN_AINHIGHZ_EN; 417 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_AINHIGHZ_EN, 418 cfg->highz_en ? 1 : 0); 419 420 return regmap_update_bits(st->regmap, 421 AD4695_REG_CONFIG_IN(cfg->channel), 422 mask, val); 423 } 424 425 static int ad4695_buffer_preenable(struct iio_dev *indio_dev) 426 { 427 struct ad4695_state *st = iio_priv(indio_dev); 428 struct spi_transfer *xfer; 429 u8 temp_chan_bit = st->chip_info->num_voltage_inputs; 430 u32 bit, num_xfer, num_slots; 431 u32 temp_en = 0; 432 int ret, rx_buf_offset = 0; 433 434 /* 435 * We are using the advanced sequencer since it is the only way to read 436 * multiple channels that allows individual configuration of each 437 * voltage input channel. Slot 0 in the advanced sequencer is used to 438 * account for the gap between trigger polls - we don't read data from 439 * this slot. Each enabled voltage channel is assigned a slot starting 440 * with slot 1. 441 */ 442 num_slots = 1; 443 444 memset(st->buf_read_xfer, 0, sizeof(st->buf_read_xfer)); 445 446 /* First xfer is only to trigger conversion of slot 1, so no rx. */ 447 xfer = &st->buf_read_xfer[0]; 448 xfer->cs_change = 1; 449 xfer->delay.value = st->chip_info->t_acq_ns; 450 xfer->delay.unit = SPI_DELAY_UNIT_NSECS; 451 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS; 452 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 453 num_xfer = 1; 454 455 iio_for_each_active_channel(indio_dev, bit) { 456 xfer = &st->buf_read_xfer[num_xfer]; 457 xfer->bits_per_word = 16; 458 xfer->rx_buf = &st->buf[rx_buf_offset]; 459 xfer->len = 2; 460 rx_buf_offset += xfer->len; 461 462 if (bit == temp_chan_bit) { 463 temp_en = 1; 464 } else { 465 ret = regmap_write(st->regmap, 466 AD4695_REG_AS_SLOT(num_slots), 467 FIELD_PREP(AD4695_REG_AS_SLOT_INX, bit)); 468 if (ret) 469 return ret; 470 471 num_slots++; 472 } 473 474 num_xfer++; 475 476 /* 477 * We need to add a blank xfer in data reads, to meet the timing 478 * requirement of a minimum delay between the last SCLK rising 479 * edge and the CS deassert. 480 */ 481 xfer = &st->buf_read_xfer[num_xfer]; 482 xfer->delay.value = AD4695_T_SCK_CNV_DELAY_NS; 483 xfer->delay.unit = SPI_DELAY_UNIT_NSECS; 484 xfer->cs_change = 1; 485 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS; 486 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 487 488 num_xfer++; 489 } 490 491 /* 492 * The advanced sequencer requires that at least 2 slots are enabled. 493 * Since slot 0 is always used for other purposes, we need only 1 494 * enabled voltage channel to meet this requirement. If the temperature 495 * channel is the only enabled channel, we need to add one more slot in 496 * the sequence but not read from it. This is because the temperature 497 * sensor is sampled at the end of the channel sequence in advanced 498 * sequencer mode (see datasheet page 38). 499 * 500 * From the iio_for_each_active_channel() block above, we now have an 501 * xfer with data followed by a blank xfer to allow us to meet the 502 * timing spec, so move both of those up before adding an extra to 503 * handle the temperature-only case. 504 */ 505 if (num_slots < 2) { 506 /* Move last two xfers */ 507 st->buf_read_xfer[num_xfer] = st->buf_read_xfer[num_xfer - 1]; 508 st->buf_read_xfer[num_xfer - 1] = st->buf_read_xfer[num_xfer - 2]; 509 num_xfer++; 510 511 /* Modify inserted xfer for extra slot. */ 512 xfer = &st->buf_read_xfer[num_xfer - 3]; 513 memset(xfer, 0, sizeof(*xfer)); 514 xfer->cs_change = 1; 515 xfer->delay.value = st->chip_info->t_acq_ns; 516 xfer->delay.unit = SPI_DELAY_UNIT_NSECS; 517 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS; 518 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 519 xfer++; 520 521 /* and add the extra slot in the sequencer */ 522 ret = regmap_write(st->regmap, 523 AD4695_REG_AS_SLOT(num_slots), 524 FIELD_PREP(AD4695_REG_AS_SLOT_INX, 0)); 525 if (ret) 526 return ret; 527 528 num_slots++; 529 530 /* 531 * We still want to point at the last xfer when finished, so 532 * update the pointer. 533 */ 534 xfer = &st->buf_read_xfer[num_xfer - 1]; 535 } 536 537 /* 538 * Don't keep CS asserted after last xfer. Also triggers conversion of 539 * slot 0. 540 */ 541 xfer->cs_change = 0; 542 543 /* 544 * Temperature channel isn't included in the sequence, but rather 545 * controlled by setting a bit in the TEMP_CTRL register. 546 */ 547 548 ret = regmap_update_bits(st->regmap, AD4695_REG_TEMP_CTRL, 549 AD4695_REG_TEMP_CTRL_TEMP_EN, 550 FIELD_PREP(AD4695_REG_TEMP_CTRL_TEMP_EN, temp_en)); 551 if (ret) 552 return ret; 553 554 spi_message_init_with_transfers(&st->buf_read_msg, st->buf_read_xfer, 555 num_xfer); 556 557 ret = spi_optimize_message(st->spi, &st->buf_read_msg); 558 if (ret) 559 return ret; 560 561 /* This triggers conversion of slot 0. */ 562 ret = ad4695_enter_advanced_sequencer_mode(st, num_slots); 563 if (ret) 564 spi_unoptimize_message(&st->buf_read_msg); 565 566 return ret; 567 } 568 569 static int ad4695_buffer_postdisable(struct iio_dev *indio_dev) 570 { 571 struct ad4695_state *st = iio_priv(indio_dev); 572 int ret; 573 574 ret = ad4695_exit_conversion_mode(st); 575 if (ret) 576 return ret; 577 578 spi_unoptimize_message(&st->buf_read_msg); 579 580 return 0; 581 } 582 583 static const struct iio_buffer_setup_ops ad4695_buffer_setup_ops = { 584 .preenable = ad4695_buffer_preenable, 585 .postdisable = ad4695_buffer_postdisable, 586 }; 587 588 static irqreturn_t ad4695_trigger_handler(int irq, void *p) 589 { 590 struct iio_poll_func *pf = p; 591 struct iio_dev *indio_dev = pf->indio_dev; 592 struct ad4695_state *st = iio_priv(indio_dev); 593 int ret; 594 595 ret = spi_sync(st->spi, &st->buf_read_msg); 596 if (ret) 597 goto out; 598 599 iio_push_to_buffers_with_timestamp(indio_dev, st->buf, pf->timestamp); 600 601 out: 602 iio_trigger_notify_done(indio_dev->trig); 603 604 return IRQ_HANDLED; 605 } 606 607 /** 608 * ad4695_read_one_sample - Read a single sample using single-cycle mode 609 * @st: The AD4695 state 610 * @address: The address of the channel to read 611 * 612 * Upon successful return, the sample will be stored in `st->raw_data`. 613 * 614 * Context: can sleep, must be called with iio_device_claim_direct held 615 * Return: 0 on success, a negative error code on failure 616 */ 617 static int ad4695_read_one_sample(struct ad4695_state *st, unsigned int address) 618 { 619 struct spi_transfer xfers[2] = { 620 { 621 .speed_hz = AD4695_REG_ACCESS_SCLK_HZ, 622 .bits_per_word = 16, 623 .tx_buf = &st->cnv_cmd, 624 .len = 2, 625 }, 626 { 627 /* Required delay between last SCLK and CNV/CS */ 628 .delay.value = AD4695_T_SCK_CNV_DELAY_NS, 629 .delay.unit = SPI_DELAY_UNIT_NSECS, 630 } 631 }; 632 int ret; 633 634 ret = ad4695_set_single_cycle_mode(st, address); 635 if (ret) 636 return ret; 637 638 /* 639 * Setting the first channel to the temperature channel isn't supported 640 * in single-cycle mode, so we have to do an extra conversion to read 641 * the temperature. 642 */ 643 if (address == AD4695_CMD_TEMP_CHAN) { 644 st->cnv_cmd = AD4695_CMD_TEMP_CHAN << 11; 645 646 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 647 if (ret) 648 return ret; 649 } 650 651 /* Then read the result and exit conversion mode. */ 652 st->cnv_cmd = AD4695_CMD_EXIT_CNV_MODE << 11; 653 xfers[0].rx_buf = &st->raw_data; 654 655 return spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 656 } 657 658 static int ad4695_read_raw(struct iio_dev *indio_dev, 659 struct iio_chan_spec const *chan, 660 int *val, int *val2, long mask) 661 { 662 struct ad4695_state *st = iio_priv(indio_dev); 663 struct ad4695_channel_config *cfg = &st->channels_cfg[chan->scan_index]; 664 u8 realbits = chan->scan_type.realbits; 665 unsigned int reg_val; 666 int ret, tmp; 667 668 switch (mask) { 669 case IIO_CHAN_INFO_RAW: 670 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 671 ret = ad4695_read_one_sample(st, chan->address); 672 if (ret) 673 return ret; 674 675 if (chan->scan_type.sign == 's') 676 *val = sign_extend32(st->raw_data, realbits - 1); 677 else 678 *val = st->raw_data; 679 680 return IIO_VAL_INT; 681 } 682 unreachable(); 683 case IIO_CHAN_INFO_SCALE: 684 switch (chan->type) { 685 case IIO_VOLTAGE: 686 *val = st->vref_mv; 687 *val2 = chan->scan_type.realbits; 688 return IIO_VAL_FRACTIONAL_LOG2; 689 case IIO_TEMP: 690 /* T_scale (°C) = raw * V_REF (mV) / (-1.8 mV/°C * 2^16) */ 691 *val = st->vref_mv * -556; 692 *val2 = 16; 693 return IIO_VAL_FRACTIONAL_LOG2; 694 default: 695 return -EINVAL; 696 } 697 case IIO_CHAN_INFO_OFFSET: 698 switch (chan->type) { 699 case IIO_VOLTAGE: 700 if (cfg->pin_pairing == AD4695_IN_PAIR_COM) 701 *val = st->com_mv * (1 << realbits) / st->vref_mv; 702 else if (cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) 703 *val = cfg->common_mode_mv * (1 << realbits) / st->vref_mv; 704 else 705 *val = 0; 706 707 return IIO_VAL_INT; 708 case IIO_TEMP: 709 /* T_offset (°C) = -725 mV / (-1.8 mV/°C) */ 710 /* T_offset (raw) = T_offset (°C) * (-1.8 mV/°C) * 2^16 / V_REF (mV) */ 711 *val = -47513600; 712 *val2 = st->vref_mv; 713 return IIO_VAL_FRACTIONAL; 714 default: 715 return -EINVAL; 716 } 717 case IIO_CHAN_INFO_CALIBSCALE: 718 switch (chan->type) { 719 case IIO_VOLTAGE: 720 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 721 ret = regmap_read(st->regmap16, 722 AD4695_REG_GAIN_IN(chan->scan_index), 723 ®_val); 724 if (ret) 725 return ret; 726 727 *val = reg_val; 728 *val2 = 15; 729 730 return IIO_VAL_FRACTIONAL_LOG2; 731 } 732 unreachable(); 733 default: 734 return -EINVAL; 735 } 736 case IIO_CHAN_INFO_CALIBBIAS: 737 switch (chan->type) { 738 case IIO_VOLTAGE: 739 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 740 ret = regmap_read(st->regmap16, 741 AD4695_REG_OFFSET_IN(chan->scan_index), 742 ®_val); 743 if (ret) 744 return ret; 745 746 tmp = sign_extend32(reg_val, 15); 747 748 *val = tmp / 4; 749 *val2 = abs(tmp) % 4 * MICRO / 4; 750 751 if (tmp < 0 && *val2) { 752 *val *= -1; 753 *val2 *= -1; 754 } 755 756 return IIO_VAL_INT_PLUS_MICRO; 757 } 758 unreachable(); 759 default: 760 return -EINVAL; 761 } 762 default: 763 return -EINVAL; 764 } 765 } 766 767 static int ad4695_write_raw(struct iio_dev *indio_dev, 768 struct iio_chan_spec const *chan, 769 int val, int val2, long mask) 770 { 771 struct ad4695_state *st = iio_priv(indio_dev); 772 unsigned int reg_val; 773 774 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 775 switch (mask) { 776 case IIO_CHAN_INFO_CALIBSCALE: 777 switch (chan->type) { 778 case IIO_VOLTAGE: 779 if (val < 0 || val2 < 0) 780 reg_val = 0; 781 else if (val > 1) 782 reg_val = U16_MAX; 783 else 784 reg_val = (val * (1 << 16) + 785 mul_u64_u32_div(val2, 1 << 16, 786 MICRO)) / 2; 787 788 return regmap_write(st->regmap16, 789 AD4695_REG_GAIN_IN(chan->scan_index), 790 reg_val); 791 default: 792 return -EINVAL; 793 } 794 case IIO_CHAN_INFO_CALIBBIAS: 795 switch (chan->type) { 796 case IIO_VOLTAGE: 797 if (val2 >= 0 && val > S16_MAX / 4) 798 reg_val = S16_MAX; 799 else if ((val2 < 0 ? -val : val) < S16_MIN / 4) 800 reg_val = S16_MIN; 801 else if (val2 < 0) 802 reg_val = clamp_t(int, 803 -(val * 4 + -val2 * 4 / MICRO), 804 S16_MIN, S16_MAX); 805 else if (val < 0) 806 reg_val = clamp_t(int, 807 val * 4 - val2 * 4 / MICRO, 808 S16_MIN, S16_MAX); 809 else 810 reg_val = clamp_t(int, 811 val * 4 + val2 * 4 / MICRO, 812 S16_MIN, S16_MAX); 813 814 return regmap_write(st->regmap16, 815 AD4695_REG_OFFSET_IN(chan->scan_index), 816 reg_val); 817 default: 818 return -EINVAL; 819 } 820 default: 821 return -EINVAL; 822 } 823 } 824 unreachable(); 825 } 826 827 static int ad4695_read_avail(struct iio_dev *indio_dev, 828 struct iio_chan_spec const *chan, 829 const int **vals, int *type, int *length, 830 long mask) 831 { 832 static const int ad4695_calibscale_available[6] = { 833 /* Range of 0 (inclusive) to 2 (exclusive) */ 834 0, 15, 1, 15, U16_MAX, 15 835 }; 836 static const int ad4695_calibbias_available[6] = { 837 /* 838 * Datasheet says FSR/8 which translates to signed/4. The step 839 * depends on oversampling ratio which is always 1 for now. 840 */ 841 S16_MIN / 4, 0, 0, MICRO / 4, S16_MAX / 4, S16_MAX % 4 * MICRO / 4 842 }; 843 844 switch (mask) { 845 case IIO_CHAN_INFO_CALIBSCALE: 846 switch (chan->type) { 847 case IIO_VOLTAGE: 848 *vals = ad4695_calibscale_available; 849 *type = IIO_VAL_FRACTIONAL_LOG2; 850 return IIO_AVAIL_RANGE; 851 default: 852 return -EINVAL; 853 } 854 case IIO_CHAN_INFO_CALIBBIAS: 855 switch (chan->type) { 856 case IIO_VOLTAGE: 857 *vals = ad4695_calibbias_available; 858 *type = IIO_VAL_INT_PLUS_MICRO; 859 return IIO_AVAIL_RANGE; 860 default: 861 return -EINVAL; 862 } 863 default: 864 return -EINVAL; 865 } 866 } 867 868 static int ad4695_debugfs_reg_access(struct iio_dev *indio_dev, 869 unsigned int reg, 870 unsigned int writeval, 871 unsigned int *readval) 872 { 873 struct ad4695_state *st = iio_priv(indio_dev); 874 875 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 876 if (readval) { 877 if (regmap_check_range_table(st->regmap, reg, 878 &ad4695_regmap_rd_table)) 879 return regmap_read(st->regmap, reg, readval); 880 if (regmap_check_range_table(st->regmap16, reg, 881 &ad4695_regmap16_rd_table)) 882 return regmap_read(st->regmap16, reg, readval); 883 } else { 884 if (regmap_check_range_table(st->regmap, reg, 885 &ad4695_regmap_wr_table)) 886 return regmap_write(st->regmap, reg, writeval); 887 if (regmap_check_range_table(st->regmap16, reg, 888 &ad4695_regmap16_wr_table)) 889 return regmap_write(st->regmap16, reg, writeval); 890 } 891 } 892 893 return -EINVAL; 894 } 895 896 static const struct iio_info ad4695_info = { 897 .read_raw = &ad4695_read_raw, 898 .write_raw = &ad4695_write_raw, 899 .read_avail = &ad4695_read_avail, 900 .debugfs_reg_access = &ad4695_debugfs_reg_access, 901 }; 902 903 static int ad4695_parse_channel_cfg(struct ad4695_state *st) 904 { 905 struct device *dev = &st->spi->dev; 906 struct ad4695_channel_config *chan_cfg; 907 struct iio_chan_spec *iio_chan; 908 int ret, i; 909 910 /* populate defaults */ 911 for (i = 0; i < st->chip_info->num_voltage_inputs; i++) { 912 chan_cfg = &st->channels_cfg[i]; 913 iio_chan = &st->iio_chan[i]; 914 915 chan_cfg->highz_en = true; 916 chan_cfg->channel = i; 917 918 *iio_chan = ad4695_channel_template; 919 iio_chan->channel = i; 920 iio_chan->scan_index = i; 921 iio_chan->address = AD4695_CMD_VOLTAGE_CHAN(i); 922 } 923 924 /* modify based on firmware description */ 925 device_for_each_child_node_scoped(dev, child) { 926 u32 reg, val; 927 928 ret = fwnode_property_read_u32(child, "reg", ®); 929 if (ret) 930 return dev_err_probe(dev, ret, 931 "failed to read reg property (%s)\n", 932 fwnode_get_name(child)); 933 934 if (reg >= st->chip_info->num_voltage_inputs) 935 return dev_err_probe(dev, -EINVAL, 936 "reg out of range (%s)\n", 937 fwnode_get_name(child)); 938 939 iio_chan = &st->iio_chan[reg]; 940 chan_cfg = &st->channels_cfg[reg]; 941 942 chan_cfg->highz_en = 943 !fwnode_property_read_bool(child, "adi,no-high-z"); 944 chan_cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 945 946 ret = fwnode_property_read_u32(child, "common-mode-channel", 947 &val); 948 if (ret && ret != -EINVAL) 949 return dev_err_probe(dev, ret, 950 "failed to read common-mode-channel (%s)\n", 951 fwnode_get_name(child)); 952 953 if (ret == -EINVAL || val == AD4695_COMMON_MODE_REFGND) 954 chan_cfg->pin_pairing = AD4695_IN_PAIR_REFGND; 955 else if (val == AD4695_COMMON_MODE_COM) 956 chan_cfg->pin_pairing = AD4695_IN_PAIR_COM; 957 else 958 chan_cfg->pin_pairing = AD4695_IN_PAIR_EVEN_ODD; 959 960 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD && 961 val % 2 == 0) 962 return dev_err_probe(dev, -EINVAL, 963 "common-mode-channel must be odd number (%s)\n", 964 fwnode_get_name(child)); 965 966 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD && 967 val != reg + 1) 968 return dev_err_probe(dev, -EINVAL, 969 "common-mode-channel must be next consecutive channel (%s)\n", 970 fwnode_get_name(child)); 971 972 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) { 973 char name[5]; 974 975 snprintf(name, sizeof(name), "in%d", reg + 1); 976 977 ret = devm_regulator_get_enable_read_voltage(dev, name); 978 if (ret < 0) 979 return dev_err_probe(dev, ret, 980 "failed to get %s voltage (%s)\n", 981 name, fwnode_get_name(child)); 982 983 chan_cfg->common_mode_mv = ret / 1000; 984 } 985 986 if (chan_cfg->bipolar && 987 chan_cfg->pin_pairing == AD4695_IN_PAIR_REFGND) 988 return dev_err_probe(dev, -EINVAL, 989 "bipolar mode is not available for inputs paired with REFGND (%s).\n", 990 fwnode_get_name(child)); 991 992 if (chan_cfg->bipolar) 993 iio_chan->scan_type.sign = 's'; 994 995 ret = ad4695_write_chn_cfg(st, chan_cfg); 996 if (ret) 997 return ret; 998 } 999 1000 /* Temperature channel must be next scan index after voltage channels. */ 1001 st->iio_chan[i] = ad4695_temp_channel_template; 1002 st->iio_chan[i].scan_index = i; 1003 i++; 1004 1005 st->iio_chan[i] = ad4695_soft_timestamp_channel_template; 1006 st->iio_chan[i].scan_index = i; 1007 1008 return 0; 1009 } 1010 1011 static int ad4695_probe(struct spi_device *spi) 1012 { 1013 struct device *dev = &spi->dev; 1014 struct ad4695_state *st; 1015 struct iio_dev *indio_dev; 1016 struct gpio_desc *cnv_gpio; 1017 bool use_internal_ldo_supply; 1018 bool use_internal_ref_buffer; 1019 int ret; 1020 1021 cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW); 1022 if (IS_ERR(cnv_gpio)) 1023 return dev_err_probe(dev, PTR_ERR(cnv_gpio), 1024 "Failed to get CNV GPIO\n"); 1025 1026 /* Driver currently requires CNV pin to be connected to SPI CS */ 1027 if (cnv_gpio) 1028 return dev_err_probe(dev, -ENODEV, 1029 "CNV GPIO is not supported\n"); 1030 1031 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1032 if (!indio_dev) 1033 return -ENOMEM; 1034 1035 st = iio_priv(indio_dev); 1036 st->spi = spi; 1037 1038 st->chip_info = spi_get_device_match_data(spi); 1039 if (!st->chip_info) 1040 return -EINVAL; 1041 1042 /* Registers cannot be read at the max allowable speed */ 1043 spi->max_speed_hz = AD4695_REG_ACCESS_SCLK_HZ; 1044 1045 st->regmap = devm_regmap_init_spi(spi, &ad4695_regmap_config); 1046 if (IS_ERR(st->regmap)) 1047 return dev_err_probe(dev, PTR_ERR(st->regmap), 1048 "Failed to initialize regmap\n"); 1049 1050 st->regmap16 = devm_regmap_init_spi(spi, &ad4695_regmap16_config); 1051 if (IS_ERR(st->regmap16)) 1052 return dev_err_probe(dev, PTR_ERR(st->regmap16), 1053 "Failed to initialize regmap16\n"); 1054 1055 ret = devm_regulator_bulk_get_enable(dev, 1056 ARRAY_SIZE(ad4695_power_supplies), 1057 ad4695_power_supplies); 1058 if (ret) 1059 return dev_err_probe(dev, ret, 1060 "Failed to enable power supplies\n"); 1061 1062 /* If LDO_IN supply is present, then we are using internal LDO. */ 1063 ret = devm_regulator_get_enable_optional(dev, "ldo-in"); 1064 if (ret < 0 && ret != -ENODEV) 1065 return dev_err_probe(dev, ret, 1066 "Failed to enable LDO_IN supply\n"); 1067 1068 use_internal_ldo_supply = ret == 0; 1069 1070 if (!use_internal_ldo_supply) { 1071 /* Otherwise we need an external VDD supply. */ 1072 ret = devm_regulator_get_enable(dev, "vdd"); 1073 if (ret < 0) 1074 return dev_err_probe(dev, ret, 1075 "Failed to enable VDD supply\n"); 1076 } 1077 1078 /* If REFIN supply is given, then we are using internal buffer */ 1079 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 1080 if (ret < 0 && ret != -ENODEV) 1081 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n"); 1082 1083 if (ret != -ENODEV) { 1084 st->vref_mv = ret / 1000; 1085 use_internal_ref_buffer = true; 1086 } else { 1087 /* Otherwise, we need an external reference. */ 1088 ret = devm_regulator_get_enable_read_voltage(dev, "ref"); 1089 if (ret < 0) 1090 return dev_err_probe(dev, ret, 1091 "Failed to get REF voltage\n"); 1092 1093 st->vref_mv = ret / 1000; 1094 use_internal_ref_buffer = false; 1095 } 1096 1097 ret = devm_regulator_get_enable_read_voltage(dev, "com"); 1098 if (ret < 0 && ret != -ENODEV) 1099 return dev_err_probe(dev, ret, "Failed to get COM voltage\n"); 1100 1101 st->com_mv = ret == -ENODEV ? 0 : ret / 1000; 1102 1103 /* 1104 * Reset the device using hardware reset if available or fall back to 1105 * software reset. 1106 */ 1107 1108 st->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1109 if (IS_ERR(st->reset_gpio)) 1110 return PTR_ERR(st->reset_gpio); 1111 1112 if (st->reset_gpio) { 1113 gpiod_set_value(st->reset_gpio, 0); 1114 msleep(AD4695_T_WAKEUP_HW_MS); 1115 } else { 1116 ret = regmap_write(st->regmap, AD4695_REG_SPI_CONFIG_A, 1117 AD4695_REG_SPI_CONFIG_A_SW_RST); 1118 if (ret) 1119 return ret; 1120 1121 msleep(AD4695_T_WAKEUP_SW_MS); 1122 } 1123 1124 /* Needed for regmap16 to be able to work correctly. */ 1125 ret = regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_A, 1126 AD4695_REG_SPI_CONFIG_A_ADDR_DIR); 1127 if (ret) 1128 return ret; 1129 1130 /* Disable internal LDO if it isn't needed. */ 1131 ret = regmap_update_bits(st->regmap, AD4695_REG_SETUP, 1132 AD4695_REG_SETUP_LDO_EN, 1133 FIELD_PREP(AD4695_REG_SETUP_LDO_EN, 1134 use_internal_ldo_supply ? 1 : 0)); 1135 if (ret) 1136 return ret; 1137 1138 /* configure reference supply */ 1139 1140 if (device_property_present(dev, "adi,no-ref-current-limit")) { 1141 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL, 1142 AD4695_REG_REF_CTRL_OV_MODE); 1143 if (ret) 1144 return ret; 1145 } 1146 1147 if (device_property_present(dev, "adi,no-ref-high-z")) { 1148 if (use_internal_ref_buffer) 1149 return dev_err_probe(dev, -EINVAL, 1150 "Cannot disable high-Z mode for internal reference buffer\n"); 1151 1152 ret = regmap_clear_bits(st->regmap, AD4695_REG_REF_CTRL, 1153 AD4695_REG_REF_CTRL_REFHIZ_EN); 1154 if (ret) 1155 return ret; 1156 } 1157 1158 ret = ad4695_set_ref_voltage(st, st->vref_mv); 1159 if (ret) 1160 return ret; 1161 1162 if (use_internal_ref_buffer) { 1163 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL, 1164 AD4695_REG_REF_CTRL_REFBUF_EN); 1165 if (ret) 1166 return ret; 1167 1168 /* Give the capacitor some time to charge up. */ 1169 msleep(AD4695_T_REFBUF_MS); 1170 } 1171 1172 ret = ad4695_parse_channel_cfg(st); 1173 if (ret) 1174 return ret; 1175 1176 indio_dev->name = st->chip_info->name; 1177 indio_dev->info = &ad4695_info; 1178 indio_dev->modes = INDIO_DIRECT_MODE; 1179 indio_dev->channels = st->iio_chan; 1180 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 2; 1181 1182 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1183 iio_pollfunc_store_time, 1184 ad4695_trigger_handler, 1185 &ad4695_buffer_setup_ops); 1186 if (ret) 1187 return ret; 1188 1189 return devm_iio_device_register(dev, indio_dev); 1190 } 1191 1192 static const struct spi_device_id ad4695_spi_id_table[] = { 1193 { .name = "ad4695", .driver_data = (kernel_ulong_t)&ad4695_chip_info }, 1194 { .name = "ad4696", .driver_data = (kernel_ulong_t)&ad4696_chip_info }, 1195 { .name = "ad4697", .driver_data = (kernel_ulong_t)&ad4697_chip_info }, 1196 { .name = "ad4698", .driver_data = (kernel_ulong_t)&ad4698_chip_info }, 1197 { } 1198 }; 1199 MODULE_DEVICE_TABLE(spi, ad4695_spi_id_table); 1200 1201 static const struct of_device_id ad4695_of_match_table[] = { 1202 { .compatible = "adi,ad4695", .data = &ad4695_chip_info, }, 1203 { .compatible = "adi,ad4696", .data = &ad4696_chip_info, }, 1204 { .compatible = "adi,ad4697", .data = &ad4697_chip_info, }, 1205 { .compatible = "adi,ad4698", .data = &ad4698_chip_info, }, 1206 { } 1207 }; 1208 MODULE_DEVICE_TABLE(of, ad4695_of_match_table); 1209 1210 static struct spi_driver ad4695_driver = { 1211 .driver = { 1212 .name = "ad4695", 1213 .of_match_table = ad4695_of_match_table, 1214 }, 1215 .probe = ad4695_probe, 1216 .id_table = ad4695_spi_id_table, 1217 }; 1218 module_spi_driver(ad4695_driver); 1219 1220 MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>"); 1221 MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>"); 1222 MODULE_DESCRIPTION("Analog Devices AD4695 ADC driver"); 1223 MODULE_LICENSE("GPL"); 1224