1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2022 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/spi/spi.h> 25 #include <linux/types.h> 26 #include <linux/units.h> 27 28 #include <asm/div64.h> 29 #include <linux/unaligned.h> 30 31 #include <linux/iio/buffer.h> 32 #include <linux/iio/iio.h> 33 #include <linux/iio/kfifo_buf.h> 34 #include <linux/iio/sysfs.h> 35 #include <linux/iio/trigger.h> 36 #include <linux/iio/trigger_consumer.h> 37 #include <linux/iio/triggered_buffer.h> 38 39 #define AD4130_NAME "ad4130" 40 41 #define AD4130_COMMS_READ_MASK BIT(6) 42 43 #define AD4130_STATUS_REG 0x00 44 45 #define AD4130_ADC_CONTROL_REG 0x01 46 #define AD4130_ADC_CONTROL_BIPOLAR_MASK BIT(14) 47 #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13) 48 #define AD4130_ADC_CONTROL_CONT_READ_MASK BIT(11) 49 #define AD4130_INT_REF_2_5V 2500000 50 #define AD4130_INT_REF_1_25V 1250000 51 #define AD4130_ADC_CONTROL_CSB_EN_MASK BIT(9) 52 #define AD4130_ADC_CONTROL_INT_REF_EN_MASK BIT(8) 53 #define AD4130_ADC_CONTROL_MODE_MASK GENMASK(5, 2) 54 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0) 55 #define AD4130_MCLK_FREQ_76_8KHZ 76800 56 #define AD4130_MCLK_FREQ_153_6KHZ 153600 57 58 #define AD4130_DATA_REG 0x02 59 60 #define AD4130_IO_CONTROL_REG 0x03 61 #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8) 62 #define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4) 63 #define AD4130_4_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 6) 64 #define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0) 65 #define AD4130_4_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 2) 66 67 #define AD4130_VBIAS_REG 0x04 68 69 #define AD4130_ID_REG 0x05 70 71 #define AD4130_ERROR_REG 0x06 72 73 #define AD4130_ERROR_EN_REG 0x07 74 75 #define AD4130_MCLK_COUNT_REG 0x08 76 77 #define AD4130_CHANNEL_X_REG(x) (0x09 + (x)) 78 #define AD4130_CHANNEL_EN_MASK BIT(23) 79 #define AD4130_CHANNEL_SETUP_MASK GENMASK(22, 20) 80 #define AD4130_CHANNEL_AINP_MASK GENMASK(17, 13) 81 #define AD4130_CHANNEL_AINM_MASK GENMASK(12, 8) 82 #define AD4130_CHANNEL_IOUT1_MASK GENMASK(7, 4) 83 #define AD4130_CHANNEL_IOUT2_MASK GENMASK(3, 0) 84 85 #define AD4130_CONFIG_X_REG(x) (0x19 + (x)) 86 #define AD4130_CONFIG_IOUT1_VAL_MASK GENMASK(15, 13) 87 #define AD4130_CONFIG_IOUT2_VAL_MASK GENMASK(12, 10) 88 #define AD4130_CONFIG_BURNOUT_MASK GENMASK(9, 8) 89 #define AD4130_CONFIG_REF_BUFP_MASK BIT(7) 90 #define AD4130_CONFIG_REF_BUFM_MASK BIT(6) 91 #define AD4130_CONFIG_REF_SEL_MASK GENMASK(5, 4) 92 #define AD4130_CONFIG_PGA_MASK GENMASK(3, 1) 93 94 #define AD4130_FILTER_X_REG(x) (0x21 + (x)) 95 #define AD4130_FILTER_MODE_MASK GENMASK(15, 12) 96 #define AD4130_FILTER_SELECT_MASK GENMASK(10, 0) 97 #define AD4130_FILTER_SELECT_MIN 1 98 99 #define AD4130_OFFSET_X_REG(x) (0x29 + (x)) 100 101 #define AD4130_GAIN_X_REG(x) (0x31 + (x)) 102 103 #define AD4130_MISC_REG 0x39 104 105 #define AD4130_FIFO_CONTROL_REG 0x3a 106 #define AD4130_FIFO_CONTROL_HEADER_MASK BIT(18) 107 #define AD4130_FIFO_CONTROL_MODE_MASK GENMASK(17, 16) 108 #define AD4130_FIFO_CONTROL_WM_INT_EN_MASK BIT(9) 109 #define AD4130_FIFO_CONTROL_WM_MASK GENMASK(7, 0) 110 #define AD4130_WATERMARK_256 0 111 112 #define AD4130_FIFO_STATUS_REG 0x3b 113 114 #define AD4130_FIFO_THRESHOLD_REG 0x3c 115 116 #define AD4130_FIFO_DATA_REG 0x3d 117 #define AD4130_FIFO_SIZE 256 118 #define AD4130_FIFO_MAX_SAMPLE_SIZE 3 119 120 #define AD4130_MAX_ANALOG_PINS 16 121 #define AD4130_MAX_CHANNELS 16 122 #define AD4130_MAX_DIFF_INPUTS 30 123 #define AD4130_MAX_GPIOS 4 124 #define AD4130_MAX_ODR 2400 125 #define AD4130_MAX_PGA 8 126 #define AD4130_MAX_SETUPS 8 127 128 #define AD4130_AIN2_P1 0x2 129 #define AD4130_AIN3_P2 0x3 130 131 #define AD4130_RESET_BUF_SIZE 8 132 #define AD4130_RESET_SLEEP_US (160 * MICRO / AD4130_MCLK_FREQ_76_8KHZ) 133 134 #define AD4130_INVALID_SLOT -1 135 136 static const unsigned int ad4129_reg_size[] = { 137 [AD4130_STATUS_REG] = 1, 138 [AD4130_ADC_CONTROL_REG] = 2, 139 [AD4130_DATA_REG] = 2, 140 [AD4130_IO_CONTROL_REG] = 2, 141 [AD4130_VBIAS_REG] = 2, 142 [AD4130_ID_REG] = 1, 143 [AD4130_ERROR_REG] = 2, 144 [AD4130_ERROR_EN_REG] = 2, 145 [AD4130_MCLK_COUNT_REG] = 1, 146 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3, 147 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 148 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 149 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 150 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 151 [AD4130_MISC_REG] = 2, 152 [AD4130_FIFO_CONTROL_REG] = 3, 153 [AD4130_FIFO_STATUS_REG] = 1, 154 [AD4130_FIFO_THRESHOLD_REG] = 3, 155 [AD4130_FIFO_DATA_REG] = 2, 156 }; 157 158 static const unsigned int ad4130_reg_size[] = { 159 [AD4130_STATUS_REG] = 1, 160 [AD4130_ADC_CONTROL_REG] = 2, 161 [AD4130_DATA_REG] = 3, 162 [AD4130_IO_CONTROL_REG] = 2, 163 [AD4130_VBIAS_REG] = 2, 164 [AD4130_ID_REG] = 1, 165 [AD4130_ERROR_REG] = 2, 166 [AD4130_ERROR_EN_REG] = 2, 167 [AD4130_MCLK_COUNT_REG] = 1, 168 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3, 169 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 170 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 171 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 172 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 173 [AD4130_MISC_REG] = 2, 174 [AD4130_FIFO_CONTROL_REG] = 3, 175 [AD4130_FIFO_STATUS_REG] = 1, 176 [AD4130_FIFO_THRESHOLD_REG] = 3, 177 [AD4130_FIFO_DATA_REG] = 3, 178 }; 179 180 static const unsigned int ad4131_reg_size[] = { 181 [AD4130_STATUS_REG] = 1, 182 [AD4130_ADC_CONTROL_REG] = 2, 183 [AD4130_DATA_REG] = 2, 184 [AD4130_IO_CONTROL_REG] = 2, 185 [AD4130_VBIAS_REG] = 2, 186 [AD4130_ID_REG] = 1, 187 [AD4130_ERROR_REG] = 2, 188 [AD4130_ERROR_EN_REG] = 2, 189 [AD4130_MCLK_COUNT_REG] = 1, 190 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3, 191 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 192 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 193 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 194 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 195 [AD4130_MISC_REG] = 2, 196 }; 197 198 enum ad4130_int_ref_val { 199 AD4130_INT_REF_VAL_2_5V, 200 AD4130_INT_REF_VAL_1_25V, 201 }; 202 203 enum ad4130_mclk_sel { 204 AD4130_MCLK_76_8KHZ, 205 AD4130_MCLK_76_8KHZ_OUT, 206 AD4130_MCLK_76_8KHZ_EXT, 207 AD4130_MCLK_153_6KHZ_EXT, 208 }; 209 210 enum ad4130_int_pin_sel { 211 AD4130_INT_PIN_INT, 212 AD4130_INT_PIN_CLK, 213 AD4130_INT_PIN_P2, 214 AD4130_INT_PIN_DOUT, 215 }; 216 217 enum ad4130_iout { 218 AD4130_IOUT_OFF, 219 AD4130_IOUT_10000NA, 220 AD4130_IOUT_20000NA, 221 AD4130_IOUT_50000NA, 222 AD4130_IOUT_100000NA, 223 AD4130_IOUT_150000NA, 224 AD4130_IOUT_200000NA, 225 AD4130_IOUT_100NA, 226 AD4130_IOUT_MAX 227 }; 228 229 enum ad4130_burnout { 230 AD4130_BURNOUT_OFF, 231 AD4130_BURNOUT_500NA, 232 AD4130_BURNOUT_2000NA, 233 AD4130_BURNOUT_4000NA, 234 AD4130_BURNOUT_MAX 235 }; 236 237 enum ad4130_ref_sel { 238 AD4130_REF_REFIN1, 239 AD4130_REF_REFIN2, 240 AD4130_REF_REFOUT_AVSS, 241 AD4130_REF_AVDD_AVSS, 242 AD4130_REF_SEL_MAX 243 }; 244 245 enum ad4130_fifo_mode { 246 AD4130_FIFO_MODE_DISABLED = 0b00, 247 AD4130_FIFO_MODE_WM = 0b01, 248 }; 249 250 enum ad4130_mode { 251 AD4130_MODE_CONTINUOUS = 0b0000, 252 AD4130_MODE_IDLE = 0b0100, 253 }; 254 255 enum ad4130_filter_type { 256 AD4130_FILTER_SINC4, 257 AD4130_FILTER_SINC4_SINC1, 258 AD4130_FILTER_SINC3, 259 AD4130_FILTER_SINC3_REJ60, 260 AD4130_FILTER_SINC3_SINC1, 261 AD4130_FILTER_SINC3_PF1, 262 AD4130_FILTER_SINC3_PF2, 263 AD4130_FILTER_SINC3_PF3, 264 AD4130_FILTER_SINC3_PF4, 265 }; 266 267 enum ad4130_pin_function { 268 AD4130_PIN_FN_NONE, 269 AD4130_PIN_FN_SPECIAL = BIT(0), 270 AD4130_PIN_FN_DIFF = BIT(1), 271 AD4130_PIN_FN_EXCITATION = BIT(2), 272 AD4130_PIN_FN_VBIAS = BIT(3), 273 }; 274 275 /* Pin mapping for AIN0..AIN7, VBIAS_0..VBIAS_7 */ 276 static const u8 ad4130_4_pin_map[] = { 277 0x00, 0x01, 0x04, 0x05, 0x0A, 0x0B, 0x0E, 0x0F, /* 0 - 7 */ 278 }; 279 280 /* Pin mapping for AIN0..AIN15, VBIAS_0..VBIAS_15 */ 281 static const u8 ad4130_8_pin_map[] = { 282 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 0 - 7 */ 283 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, /* 8 - 15 */ 284 }; 285 286 struct ad4130_chip_info { 287 const char *name; 288 unsigned int max_analog_pins; 289 unsigned int num_gpios; 290 const struct iio_info *info; 291 const unsigned int *reg_size; 292 const unsigned int reg_size_length; 293 const u8 *pin_map; 294 bool has_fifo; 295 }; 296 297 /* 298 * If you make adaptations in this struct, you most likely also have to adapt 299 * ad4130_setup_info_eq(), too. 300 */ 301 struct ad4130_setup_info { 302 unsigned int iout0_val; 303 unsigned int iout1_val; 304 unsigned int burnout; 305 unsigned int pga; 306 unsigned int fs; 307 u32 ref_sel; 308 enum ad4130_filter_type filter_type; 309 bool ref_bufp; 310 bool ref_bufm; 311 }; 312 313 struct ad4130_slot_info { 314 struct ad4130_setup_info setup; 315 unsigned int enabled_channels; 316 unsigned int channels; 317 }; 318 319 struct ad4130_chan_info { 320 struct ad4130_setup_info setup; 321 u32 iout0; 322 u32 iout1; 323 int slot; 324 bool enabled; 325 bool initialized; 326 }; 327 328 struct ad4130_filter_config { 329 enum ad4130_filter_type filter_type; 330 unsigned int odr_div; 331 unsigned int fs_max; 332 enum iio_available_type samp_freq_avail_type; 333 int samp_freq_avail_len; 334 int samp_freq_avail[3][2]; 335 }; 336 337 struct ad4130_state { 338 struct regmap *regmap; 339 struct spi_device *spi; 340 struct clk *mclk; 341 const struct ad4130_chip_info *chip_info; 342 struct regulator_bulk_data regulators[4]; 343 u32 irq_trigger; 344 u32 inv_irq_trigger; 345 346 /* 347 * Synchronize access to members the of driver state, and ensure 348 * atomicity of consecutive regmap operations. 349 */ 350 struct mutex lock; 351 struct completion completion; 352 353 struct iio_chan_spec chans[AD4130_MAX_CHANNELS]; 354 struct ad4130_chan_info chans_info[AD4130_MAX_CHANNELS]; 355 struct ad4130_slot_info slots_info[AD4130_MAX_SETUPS]; 356 enum ad4130_pin_function pins_fn[AD4130_MAX_ANALOG_PINS]; 357 u32 vbias_pins[AD4130_MAX_ANALOG_PINS]; 358 u32 num_vbias_pins; 359 int scale_tbls[AD4130_REF_SEL_MAX][AD4130_MAX_PGA][2]; 360 struct gpio_chip gc; 361 struct clk_hw int_clk_hw; 362 363 u32 int_pin_sel; 364 u32 int_ref_uv; 365 u32 mclk_sel; 366 bool int_ref_en; 367 bool bipolar; 368 bool buffer_wait_for_irq; 369 370 unsigned int num_enabled_channels; 371 unsigned int effective_watermark; 372 unsigned int watermark; 373 374 struct spi_message fifo_msg; 375 struct spi_transfer fifo_xfer[2]; 376 struct iio_trigger *trig; 377 378 /* 379 * DMA (thus cache coherency maintenance) requires any transfer 380 * buffers to live in their own cache lines. As the use of these 381 * buffers is synchronous, all of the buffers used for DMA in this 382 * driver may share a cache line. 383 */ 384 u8 reset_buf[AD4130_RESET_BUF_SIZE] __aligned(IIO_DMA_MINALIGN); 385 u8 reg_write_tx_buf[4]; 386 u8 reg_read_tx_buf[1]; 387 u8 reg_read_rx_buf[3]; 388 union { 389 struct { 390 u8 fifo_tx_buf[2]; 391 u8 fifo_rx_buf[AD4130_FIFO_SIZE * AD4130_FIFO_MAX_SAMPLE_SIZE]; 392 }; 393 IIO_DECLARE_BUFFER_WITH_TS(u32, scan_channels, AD4130_MAX_CHANNELS); 394 }; 395 }; 396 397 static const char * const ad4130_int_pin_names[] = { 398 [AD4130_INT_PIN_INT] = "int", 399 [AD4130_INT_PIN_CLK] = "clk", 400 [AD4130_INT_PIN_P2] = "p2", 401 [AD4130_INT_PIN_DOUT] = "dout", 402 }; 403 404 static const unsigned int ad4130_iout_current_na_tbl[AD4130_IOUT_MAX] = { 405 [AD4130_IOUT_OFF] = 0, 406 [AD4130_IOUT_100NA] = 100, 407 [AD4130_IOUT_10000NA] = 10000, 408 [AD4130_IOUT_20000NA] = 20000, 409 [AD4130_IOUT_50000NA] = 50000, 410 [AD4130_IOUT_100000NA] = 100000, 411 [AD4130_IOUT_150000NA] = 150000, 412 [AD4130_IOUT_200000NA] = 200000, 413 }; 414 415 static const unsigned int ad4130_burnout_current_na_tbl[AD4130_BURNOUT_MAX] = { 416 [AD4130_BURNOUT_OFF] = 0, 417 [AD4130_BURNOUT_500NA] = 500, 418 [AD4130_BURNOUT_2000NA] = 2000, 419 [AD4130_BURNOUT_4000NA] = 4000, 420 }; 421 422 #define AD4130_VARIABLE_ODR_CONFIG(_filter_type, _odr_div, _fs_max) \ 423 { \ 424 .filter_type = (_filter_type), \ 425 .odr_div = (_odr_div), \ 426 .fs_max = (_fs_max), \ 427 .samp_freq_avail_type = IIO_AVAIL_RANGE, \ 428 .samp_freq_avail = { \ 429 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \ 430 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \ 431 { AD4130_MAX_ODR, (_odr_div) }, \ 432 }, \ 433 } 434 435 #define AD4130_FIXED_ODR_CONFIG(_filter_type, _odr_div) \ 436 { \ 437 .filter_type = (_filter_type), \ 438 .odr_div = (_odr_div), \ 439 .fs_max = AD4130_FILTER_SELECT_MIN, \ 440 .samp_freq_avail_type = IIO_AVAIL_LIST, \ 441 .samp_freq_avail_len = 1, \ 442 .samp_freq_avail = { \ 443 { AD4130_MAX_ODR, (_odr_div) }, \ 444 }, \ 445 } 446 447 static const struct ad4130_filter_config ad4130_filter_configs[] = { 448 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4, 1, 10), 449 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4_SINC1, 11, 10), 450 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3, 1, 2047), 451 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1, 2047), 452 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_SINC1, 10, 2047), 453 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF1, 92), 454 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF2, 100), 455 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF3, 124), 456 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF4, 148), 457 }; 458 459 static const char * const ad4130_filter_types_str[] = { 460 [AD4130_FILTER_SINC4] = "sinc4", 461 [AD4130_FILTER_SINC4_SINC1] = "sinc4+sinc1", 462 [AD4130_FILTER_SINC3] = "sinc3", 463 [AD4130_FILTER_SINC3_REJ60] = "sinc3+rej60", 464 [AD4130_FILTER_SINC3_SINC1] = "sinc3+sinc1", 465 [AD4130_FILTER_SINC3_PF1] = "sinc3+pf1", 466 [AD4130_FILTER_SINC3_PF2] = "sinc3+pf2", 467 [AD4130_FILTER_SINC3_PF3] = "sinc3+pf3", 468 [AD4130_FILTER_SINC3_PF4] = "sinc3+pf4", 469 }; 470 471 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg, 472 unsigned int *size) 473 { 474 if (reg >= st->chip_info->reg_size_length) 475 return -EINVAL; 476 477 *size = st->chip_info->reg_size[reg]; 478 479 return 0; 480 } 481 482 static unsigned int ad4130_data_reg_size(struct ad4130_state *st) 483 { 484 unsigned int data_reg_size; 485 int ret; 486 487 ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size); 488 if (ret) 489 return 0; 490 491 return data_reg_size; 492 } 493 494 static unsigned int ad4130_resolution(struct ad4130_state *st) 495 { 496 return ad4130_data_reg_size(st) * BITS_PER_BYTE; 497 } 498 499 static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val) 500 { 501 struct ad4130_state *st = context; 502 unsigned int size; 503 int ret; 504 505 ret = ad4130_get_reg_size(st, reg, &size); 506 if (ret) 507 return ret; 508 509 st->reg_write_tx_buf[0] = reg; 510 511 switch (size) { 512 case 3: 513 put_unaligned_be24(val, &st->reg_write_tx_buf[1]); 514 break; 515 case 2: 516 put_unaligned_be16(val, &st->reg_write_tx_buf[1]); 517 break; 518 case 1: 519 st->reg_write_tx_buf[1] = val; 520 break; 521 default: 522 return -EINVAL; 523 } 524 525 return spi_write(st->spi, st->reg_write_tx_buf, size + 1); 526 } 527 528 static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val) 529 { 530 struct ad4130_state *st = context; 531 struct spi_transfer t[] = { 532 { 533 .tx_buf = st->reg_read_tx_buf, 534 .len = sizeof(st->reg_read_tx_buf), 535 }, 536 { 537 .rx_buf = st->reg_read_rx_buf, 538 }, 539 }; 540 unsigned int size; 541 int ret; 542 543 ret = ad4130_get_reg_size(st, reg, &size); 544 if (ret) 545 return ret; 546 547 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg; 548 t[1].len = size; 549 550 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 551 if (ret) 552 return ret; 553 554 switch (size) { 555 case 3: 556 *val = get_unaligned_be24(st->reg_read_rx_buf); 557 break; 558 case 2: 559 *val = get_unaligned_be16(st->reg_read_rx_buf); 560 break; 561 case 1: 562 *val = st->reg_read_rx_buf[0]; 563 break; 564 default: 565 return -EINVAL; 566 } 567 568 return 0; 569 } 570 571 static const struct regmap_config ad4130_regmap_config = { 572 .reg_read = ad4130_reg_read, 573 .reg_write = ad4130_reg_write, 574 }; 575 576 static int ad4130_gpio_init_valid_mask(struct gpio_chip *gc, 577 unsigned long *valid_mask, 578 unsigned int ngpios) 579 { 580 struct ad4130_state *st = gpiochip_get_data(gc); 581 unsigned int i; 582 583 /* 584 * Output-only GPIO functionality is available on pins AIN2 through 585 * AIN5 for some parts and AIN2 through AIN3 for others. If these pins 586 * are used for anything else, do not expose them. 587 */ 588 for (i = 0; i < ngpios; i++) { 589 unsigned int pin = i + AD4130_AIN2_P1; 590 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE; 591 592 __assign_bit(i, valid_mask, valid); 593 } 594 595 return 0; 596 } 597 598 static int ad4130_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 599 { 600 return GPIO_LINE_DIRECTION_OUT; 601 } 602 603 static int ad4130_gpio_set(struct gpio_chip *gc, unsigned int offset, 604 int value) 605 { 606 struct ad4130_state *st = gpiochip_get_data(gc); 607 unsigned int mask; 608 609 if (st->chip_info->num_gpios == AD4130_MAX_GPIOS) 610 mask = FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK, 611 BIT(offset)); 612 else 613 mask = FIELD_PREP(AD4130_4_IO_CONTROL_GPIO_DATA_MASK, 614 BIT(offset)); 615 616 return regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, 617 value ? mask : 0); 618 } 619 620 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode) 621 { 622 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, 623 AD4130_ADC_CONTROL_MODE_MASK, 624 FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, mode)); 625 } 626 627 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en) 628 { 629 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 630 AD4130_FIFO_CONTROL_WM_INT_EN_MASK, 631 FIELD_PREP(AD4130_FIFO_CONTROL_WM_INT_EN_MASK, en)); 632 } 633 634 static unsigned int ad4130_watermark_reg_val(unsigned int val) 635 { 636 if (val == AD4130_FIFO_SIZE) 637 val = AD4130_WATERMARK_256; 638 639 return val; 640 } 641 642 static int ad4130_set_fifo_mode(struct ad4130_state *st, 643 enum ad4130_fifo_mode mode) 644 { 645 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 646 AD4130_FIFO_CONTROL_MODE_MASK, 647 FIELD_PREP(AD4130_FIFO_CONTROL_MODE_MASK, mode)); 648 } 649 650 static void ad4130_push_fifo_data(struct iio_dev *indio_dev) 651 { 652 struct ad4130_state *st = iio_priv(indio_dev); 653 unsigned int data_reg_size = ad4130_data_reg_size(st); 654 unsigned int transfer_len = st->effective_watermark * data_reg_size; 655 unsigned int set_size = st->num_enabled_channels * data_reg_size; 656 unsigned int i; 657 int ret; 658 659 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark); 660 st->fifo_xfer[1].len = transfer_len; 661 662 ret = spi_sync(st->spi, &st->fifo_msg); 663 if (ret) 664 return; 665 666 for (i = 0; i < transfer_len; i += set_size) 667 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]); 668 } 669 670 static irqreturn_t ad4130_irq_handler(int irq, void *private) 671 { 672 struct iio_dev *indio_dev = private; 673 struct ad4130_state *st = iio_priv(indio_dev); 674 675 if (iio_buffer_enabled(indio_dev)) { 676 if (st->chip_info->has_fifo) 677 ad4130_push_fifo_data(indio_dev); 678 else if (st->buffer_wait_for_irq) 679 complete(&st->completion); 680 else 681 iio_trigger_poll(st->trig); 682 } else { 683 complete(&st->completion); 684 } 685 686 return IRQ_HANDLED; 687 } 688 689 static irqreturn_t ad4130_trigger_handler(int irq, void *p) 690 { 691 struct iio_poll_func *pf = p; 692 struct iio_dev *indio_dev = pf->indio_dev; 693 struct ad4130_state *st = iio_priv(indio_dev); 694 unsigned int data_reg_size = ad4130_data_reg_size(st); 695 struct spi_transfer xfer = { }; 696 unsigned int num_en_chn; 697 int ret; 698 699 num_en_chn = bitmap_weight(indio_dev->active_scan_mask, 700 iio_get_masklength(indio_dev)); 701 xfer.rx_buf = st->scan_channels; 702 xfer.len = data_reg_size * num_en_chn; 703 ret = spi_sync_transfer(st->spi, &xfer, 1); 704 if (ret < 0) 705 goto err_out; 706 707 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_channels, 708 iio_get_time_ns(indio_dev)); 709 710 err_out: 711 iio_trigger_notify_done(indio_dev->trig); 712 713 return IRQ_HANDLED; 714 } 715 716 static bool ad4130_setup_info_eq(struct ad4130_setup_info *a, 717 struct ad4130_setup_info *b) 718 { 719 /* 720 * This is just to make sure that the comparison is adapted after 721 * struct ad4130_setup_info was changed. 722 */ 723 static_assert(sizeof(*a) == 724 sizeof(struct { 725 unsigned int iout0_val; 726 unsigned int iout1_val; 727 unsigned int burnout; 728 unsigned int pga; 729 unsigned int fs; 730 u32 ref_sel; 731 enum ad4130_filter_type filter_type; 732 bool ref_bufp; 733 bool ref_bufm; 734 })); 735 736 if (a->iout0_val != b->iout0_val || 737 a->iout1_val != b->iout1_val || 738 a->burnout != b->burnout || 739 a->pga != b->pga || 740 a->fs != b->fs || 741 a->ref_sel != b->ref_sel || 742 a->filter_type != b->filter_type || 743 a->ref_bufp != b->ref_bufp || 744 a->ref_bufm != b->ref_bufm) 745 return false; 746 747 return true; 748 } 749 750 static int ad4130_find_slot(struct ad4130_state *st, 751 struct ad4130_setup_info *target_setup_info, 752 unsigned int *slot, bool *overwrite) 753 { 754 unsigned int i; 755 756 *slot = AD4130_INVALID_SLOT; 757 *overwrite = false; 758 759 for (i = 0; i < AD4130_MAX_SETUPS; i++) { 760 struct ad4130_slot_info *slot_info = &st->slots_info[i]; 761 762 /* Immediately accept a matching setup info. */ 763 if (ad4130_setup_info_eq(target_setup_info, &slot_info->setup)) { 764 *slot = i; 765 return 0; 766 } 767 768 /* Ignore all setups which are used by enabled channels. */ 769 if (slot_info->enabled_channels) 770 continue; 771 772 /* Find the least used slot. */ 773 if (*slot == AD4130_INVALID_SLOT || 774 slot_info->channels < st->slots_info[*slot].channels) 775 *slot = i; 776 } 777 778 if (*slot == AD4130_INVALID_SLOT) 779 return -EINVAL; 780 781 *overwrite = true; 782 783 return 0; 784 } 785 786 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel) 787 { 788 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 789 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot]; 790 791 chan_info->slot = AD4130_INVALID_SLOT; 792 slot_info->channels--; 793 } 794 795 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot) 796 { 797 unsigned int i; 798 799 for (i = 0; i < AD4130_MAX_CHANNELS; i++) { 800 struct ad4130_chan_info *chan_info = &st->chans_info[i]; 801 802 if (!chan_info->initialized || chan_info->slot != slot) 803 continue; 804 805 ad4130_unlink_channel(st, i); 806 } 807 808 return 0; 809 } 810 811 static int ad4130_link_channel_slot(struct ad4130_state *st, 812 unsigned int channel, unsigned int slot) 813 { 814 struct ad4130_slot_info *slot_info = &st->slots_info[slot]; 815 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 816 int ret; 817 818 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), 819 AD4130_CHANNEL_SETUP_MASK, 820 FIELD_PREP(AD4130_CHANNEL_SETUP_MASK, slot)); 821 if (ret) 822 return ret; 823 824 chan_info->slot = slot; 825 slot_info->channels++; 826 827 return 0; 828 } 829 830 static int ad4130_write_slot_setup(struct ad4130_state *st, 831 unsigned int slot, 832 struct ad4130_setup_info *setup_info) 833 { 834 unsigned int val; 835 int ret; 836 837 val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) | 838 FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) | 839 FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) | 840 FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) | 841 FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) | 842 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) | 843 FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga); 844 845 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val); 846 if (ret) 847 return ret; 848 849 val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_type) | 850 FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs); 851 852 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val); 853 if (ret) 854 return ret; 855 856 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info)); 857 858 return 0; 859 } 860 861 static int ad4130_write_channel_setup(struct ad4130_state *st, 862 unsigned int channel, bool on_enable) 863 { 864 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 865 struct ad4130_setup_info *setup_info = &chan_info->setup; 866 bool overwrite; 867 int slot; 868 int ret; 869 870 /* 871 * The following cases need to be handled. 872 * 873 * 1. Enabled and linked channel with setup changes: 874 * - Find a slot. If not possible, return error. 875 * - Unlink channel from current slot. 876 * - If the slot has channels linked to it, unlink all channels, and 877 * write the new setup to it. 878 * - Link channel to new slot. 879 * 880 * 2. Soon to be enabled and unlinked channel: 881 * - Find a slot. If not possible, return error. 882 * - If the slot has channels linked to it, unlink all channels, and 883 * write the new setup to it. 884 * - Link channel to the slot. 885 * 886 * 3. Disabled and linked channel with setup changes: 887 * - Unlink channel from current slot. 888 * 889 * 4. Soon to be enabled and linked channel: 890 * 5. Disabled and unlinked channel with setup changes: 891 * - Do nothing. 892 */ 893 894 /* Case 4 */ 895 if (on_enable && chan_info->slot != AD4130_INVALID_SLOT) 896 return 0; 897 898 if (!on_enable && !chan_info->enabled) { 899 if (chan_info->slot != AD4130_INVALID_SLOT) 900 /* Case 3 */ 901 ad4130_unlink_channel(st, channel); 902 903 /* Cases 3 & 5 */ 904 return 0; 905 } 906 907 /* Cases 1 & 2 */ 908 ret = ad4130_find_slot(st, setup_info, &slot, &overwrite); 909 if (ret) 910 return ret; 911 912 if (chan_info->slot != AD4130_INVALID_SLOT) 913 /* Case 1 */ 914 ad4130_unlink_channel(st, channel); 915 916 if (overwrite) { 917 ret = ad4130_unlink_slot(st, slot); 918 if (ret) 919 return ret; 920 921 ret = ad4130_write_slot_setup(st, slot, setup_info); 922 if (ret) 923 return ret; 924 } 925 926 return ad4130_link_channel_slot(st, channel, slot); 927 } 928 929 static int ad4130_set_channel_enable(struct ad4130_state *st, 930 unsigned int channel, bool status) 931 { 932 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 933 struct ad4130_slot_info *slot_info; 934 int ret; 935 936 if (chan_info->enabled == status) 937 return 0; 938 939 if (status) { 940 ret = ad4130_write_channel_setup(st, channel, true); 941 if (ret) 942 return ret; 943 } 944 945 slot_info = &st->slots_info[chan_info->slot]; 946 947 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), 948 AD4130_CHANNEL_EN_MASK, 949 FIELD_PREP(AD4130_CHANNEL_EN_MASK, status)); 950 if (ret) 951 return ret; 952 953 slot_info->enabled_channels += status ? 1 : -1; 954 chan_info->enabled = status; 955 956 return 0; 957 } 958 959 /* 960 * Table 58. FILTER_MODE_n bits and Filter Types of the datasheet describes 961 * the relation between filter mode, ODR and FS. 962 * 963 * Notice that the max ODR of each filter mode is not necessarily the 964 * absolute max ODR supported by the chip. 965 * 966 * The ODR divider is not explicitly specified, but it can be deduced based 967 * on the ODR range of each filter mode. 968 * 969 * For example, for Sinc4+Sinc1, max ODR is 218.18. That means that the 970 * absolute max ODR is divided by 11 to achieve the max ODR of this filter 971 * mode. 972 * 973 * The formulas for converting between ODR and FS for a specific filter 974 * mode can be deduced from the same table. 975 * 976 * Notice that FS = 1 actually means max ODR, and that ODR decreases by 977 * (maximum ODR / maximum FS) for each increment of FS. 978 * 979 * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=> 980 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=> 981 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=> 982 * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div) 983 * (used in ad4130_fs_to_freq) 984 * 985 * For the opposite formula, FS can be extracted from the last one. 986 * 987 * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=> 988 * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=> 989 * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR 990 * (used in ad4130_fs_to_freq) 991 */ 992 993 static void ad4130_freq_to_fs(enum ad4130_filter_type filter_type, 994 int val, int val2, unsigned int *fs) 995 { 996 const struct ad4130_filter_config *filter_config = 997 &ad4130_filter_configs[filter_type]; 998 u64 dividend, divisor; 999 int temp; 1000 1001 dividend = filter_config->fs_max * filter_config->odr_div * 1002 ((u64)val * NANO + val2); 1003 divisor = (u64)AD4130_MAX_ODR * NANO; 1004 1005 temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max - 1006 DIV64_U64_ROUND_CLOSEST(dividend, divisor); 1007 1008 if (temp < AD4130_FILTER_SELECT_MIN) 1009 temp = AD4130_FILTER_SELECT_MIN; 1010 else if (temp > filter_config->fs_max) 1011 temp = filter_config->fs_max; 1012 1013 *fs = temp; 1014 } 1015 1016 static void ad4130_fs_to_freq(enum ad4130_filter_type filter_type, 1017 unsigned int fs, int *val, int *val2) 1018 { 1019 const struct ad4130_filter_config *filter_config = 1020 &ad4130_filter_configs[filter_type]; 1021 unsigned int dividend, divisor; 1022 u64 temp; 1023 1024 dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) * 1025 AD4130_MAX_ODR; 1026 divisor = filter_config->fs_max * filter_config->odr_div; 1027 1028 temp = div_u64((u64)dividend * NANO, divisor); 1029 *val = div_u64_rem(temp, NANO, val2); 1030 } 1031 1032 static int ad4130_set_filter_type(struct iio_dev *indio_dev, 1033 const struct iio_chan_spec *chan, 1034 unsigned int val) 1035 { 1036 struct ad4130_state *st = iio_priv(indio_dev); 1037 unsigned int channel = chan->scan_index; 1038 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 1039 struct ad4130_setup_info *setup_info = &chan_info->setup; 1040 enum ad4130_filter_type old_filter_type; 1041 int freq_val, freq_val2; 1042 unsigned int old_fs; 1043 int ret = 0; 1044 1045 guard(mutex)(&st->lock); 1046 if (setup_info->filter_type == val) 1047 return 0; 1048 1049 old_fs = setup_info->fs; 1050 old_filter_type = setup_info->filter_type; 1051 1052 /* 1053 * When switching between filter modes, try to match the ODR as 1054 * close as possible. To do this, convert the current FS into ODR 1055 * using the old filter mode, then convert it back into FS using 1056 * the new filter mode. 1057 */ 1058 ad4130_fs_to_freq(setup_info->filter_type, setup_info->fs, 1059 &freq_val, &freq_val2); 1060 1061 ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs); 1062 1063 setup_info->filter_type = val; 1064 1065 ret = ad4130_write_channel_setup(st, channel, false); 1066 if (ret) { 1067 setup_info->fs = old_fs; 1068 setup_info->filter_type = old_filter_type; 1069 return ret; 1070 } 1071 1072 return 0; 1073 } 1074 1075 static int ad4130_get_filter_type(struct iio_dev *indio_dev, 1076 const struct iio_chan_spec *chan) 1077 { 1078 struct ad4130_state *st = iio_priv(indio_dev); 1079 unsigned int channel = chan->scan_index; 1080 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; 1081 enum ad4130_filter_type filter_type; 1082 1083 guard(mutex)(&st->lock); 1084 filter_type = setup_info->filter_type; 1085 1086 return filter_type; 1087 } 1088 1089 static const struct iio_enum ad4130_filter_type_enum = { 1090 .items = ad4130_filter_types_str, 1091 .num_items = ARRAY_SIZE(ad4130_filter_types_str), 1092 .set = ad4130_set_filter_type, 1093 .get = ad4130_get_filter_type, 1094 }; 1095 1096 static const struct iio_chan_spec_ext_info ad4130_ext_info[] = { 1097 /* 1098 * `filter_type` is the standardized IIO ABI for digital filtering. 1099 * `filter_mode` is just kept for backwards compatibility. 1100 */ 1101 IIO_ENUM("filter_mode", IIO_SEPARATE, &ad4130_filter_type_enum), 1102 IIO_ENUM_AVAILABLE("filter_mode", IIO_SHARED_BY_TYPE, 1103 &ad4130_filter_type_enum), 1104 IIO_ENUM("filter_type", IIO_SEPARATE, &ad4130_filter_type_enum), 1105 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE, 1106 &ad4130_filter_type_enum), 1107 { } 1108 }; 1109 1110 static const struct iio_chan_spec ad4130_channel_template = { 1111 .type = IIO_VOLTAGE, 1112 .indexed = 1, 1113 .differential = 1, 1114 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1115 BIT(IIO_CHAN_INFO_SCALE) | 1116 BIT(IIO_CHAN_INFO_OFFSET) | 1117 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1118 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) | 1119 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1120 .ext_info = ad4130_ext_info, 1121 .scan_type = { 1122 .sign = 'u', 1123 .endianness = IIO_BE, 1124 }, 1125 }; 1126 1127 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel, 1128 int val, int val2) 1129 { 1130 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 1131 struct ad4130_setup_info *setup_info = &chan_info->setup; 1132 unsigned int pga, old_pga; 1133 int ret; 1134 1135 for (pga = 0; pga < AD4130_MAX_PGA; pga++) 1136 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && 1137 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) 1138 break; 1139 1140 if (pga == AD4130_MAX_PGA) 1141 return -EINVAL; 1142 1143 guard(mutex)(&st->lock); 1144 if (pga == setup_info->pga) 1145 return 0; 1146 1147 old_pga = setup_info->pga; 1148 setup_info->pga = pga; 1149 1150 ret = ad4130_write_channel_setup(st, channel, false); 1151 if (ret) { 1152 setup_info->pga = old_pga; 1153 return ret; 1154 } 1155 1156 return 0; 1157 } 1158 1159 static int ad4130_set_channel_freq(struct ad4130_state *st, 1160 unsigned int channel, int val, int val2) 1161 { 1162 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 1163 struct ad4130_setup_info *setup_info = &chan_info->setup; 1164 unsigned int fs, old_fs; 1165 int ret; 1166 1167 guard(mutex)(&st->lock); 1168 old_fs = setup_info->fs; 1169 1170 ad4130_freq_to_fs(setup_info->filter_type, val, val2, &fs); 1171 1172 if (fs == setup_info->fs) 1173 return 0; 1174 1175 setup_info->fs = fs; 1176 1177 ret = ad4130_write_channel_setup(st, channel, false); 1178 if (ret) { 1179 setup_info->fs = old_fs; 1180 return ret; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int _ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel, 1187 int *val) 1188 { 1189 struct ad4130_state *st = iio_priv(indio_dev); 1190 int ret; 1191 1192 ret = ad4130_set_channel_enable(st, channel, true); 1193 if (ret) 1194 return ret; 1195 1196 reinit_completion(&st->completion); 1197 1198 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); 1199 if (ret) 1200 return ret; 1201 1202 ret = wait_for_completion_timeout(&st->completion, 1203 msecs_to_jiffies(1000)); 1204 if (!ret) 1205 return -ETIMEDOUT; 1206 1207 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); 1208 if (ret) 1209 return ret; 1210 1211 ret = regmap_read(st->regmap, AD4130_DATA_REG, val); 1212 if (ret) 1213 return ret; 1214 1215 ret = ad4130_set_channel_enable(st, channel, false); 1216 if (ret) 1217 return ret; 1218 1219 return IIO_VAL_INT; 1220 } 1221 1222 static int ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel, 1223 int *val) 1224 { 1225 struct ad4130_state *st = iio_priv(indio_dev); 1226 1227 guard(mutex)(&st->lock); 1228 1229 return _ad4130_read_sample(indio_dev, channel, val); 1230 } 1231 1232 static int ad4130_read_raw(struct iio_dev *indio_dev, 1233 struct iio_chan_spec const *chan, 1234 int *val, int *val2, long info) 1235 { 1236 struct ad4130_state *st = iio_priv(indio_dev); 1237 unsigned int channel = chan->scan_index; 1238 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; 1239 int ret; 1240 1241 switch (info) { 1242 case IIO_CHAN_INFO_RAW: 1243 if (!iio_device_claim_direct(indio_dev)) 1244 return -EBUSY; 1245 1246 ret = ad4130_read_sample(indio_dev, channel, val); 1247 iio_device_release_direct(indio_dev); 1248 return ret; 1249 case IIO_CHAN_INFO_SCALE: { 1250 guard(mutex)(&st->lock); 1251 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; 1252 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; 1253 1254 return IIO_VAL_INT_PLUS_NANO; 1255 } 1256 case IIO_CHAN_INFO_OFFSET: 1257 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0; 1258 1259 return IIO_VAL_INT; 1260 case IIO_CHAN_INFO_SAMP_FREQ: { 1261 guard(mutex)(&st->lock); 1262 ad4130_fs_to_freq(setup_info->filter_type, setup_info->fs, 1263 val, val2); 1264 1265 return IIO_VAL_INT_PLUS_NANO; 1266 } 1267 default: 1268 return -EINVAL; 1269 } 1270 } 1271 1272 static int ad4130_read_avail(struct iio_dev *indio_dev, 1273 struct iio_chan_spec const *chan, 1274 const int **vals, int *type, int *length, 1275 long info) 1276 { 1277 struct ad4130_state *st = iio_priv(indio_dev); 1278 unsigned int channel = chan->scan_index; 1279 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; 1280 const struct ad4130_filter_config *filter_config; 1281 1282 switch (info) { 1283 case IIO_CHAN_INFO_SCALE: 1284 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; 1285 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; 1286 1287 *type = IIO_VAL_INT_PLUS_NANO; 1288 1289 return IIO_AVAIL_LIST; 1290 case IIO_CHAN_INFO_SAMP_FREQ: 1291 scoped_guard(mutex, &st->lock) { 1292 filter_config = &ad4130_filter_configs[setup_info->filter_type]; 1293 } 1294 1295 *vals = (int *)filter_config->samp_freq_avail; 1296 *length = filter_config->samp_freq_avail_len * 2; 1297 *type = IIO_VAL_FRACTIONAL; 1298 1299 return filter_config->samp_freq_avail_type; 1300 default: 1301 return -EINVAL; 1302 } 1303 } 1304 1305 static int ad4130_write_raw_get_fmt(struct iio_dev *indio_dev, 1306 struct iio_chan_spec const *chan, 1307 long info) 1308 { 1309 switch (info) { 1310 case IIO_CHAN_INFO_SCALE: 1311 case IIO_CHAN_INFO_SAMP_FREQ: 1312 return IIO_VAL_INT_PLUS_NANO; 1313 default: 1314 return -EINVAL; 1315 } 1316 } 1317 1318 static int ad4130_write_raw(struct iio_dev *indio_dev, 1319 struct iio_chan_spec const *chan, 1320 int val, int val2, long info) 1321 { 1322 struct ad4130_state *st = iio_priv(indio_dev); 1323 unsigned int channel = chan->scan_index; 1324 1325 switch (info) { 1326 case IIO_CHAN_INFO_SCALE: 1327 return ad4130_set_channel_pga(st, channel, val, val2); 1328 case IIO_CHAN_INFO_SAMP_FREQ: 1329 return ad4130_set_channel_freq(st, channel, val, val2); 1330 default: 1331 return -EINVAL; 1332 } 1333 } 1334 1335 static int ad4130_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1336 unsigned int writeval, unsigned int *readval) 1337 { 1338 struct ad4130_state *st = iio_priv(indio_dev); 1339 1340 if (readval) 1341 return regmap_read(st->regmap, reg, readval); 1342 1343 return regmap_write(st->regmap, reg, writeval); 1344 } 1345 1346 static int ad4130_update_scan_mode(struct iio_dev *indio_dev, 1347 const unsigned long *scan_mask) 1348 { 1349 struct ad4130_state *st = iio_priv(indio_dev); 1350 unsigned int channel; 1351 unsigned int val = 0; 1352 int ret; 1353 1354 guard(mutex)(&st->lock); 1355 1356 for_each_set_bit(channel, scan_mask, indio_dev->num_channels) { 1357 ret = ad4130_set_channel_enable(st, channel, true); 1358 if (ret) 1359 return ret; 1360 1361 val++; 1362 } 1363 1364 st->num_enabled_channels = val; 1365 1366 return 0; 1367 } 1368 1369 static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val) 1370 { 1371 struct ad4130_state *st = iio_priv(indio_dev); 1372 unsigned int eff; 1373 int ret; 1374 1375 if (val > AD4130_FIFO_SIZE) 1376 return -EINVAL; 1377 1378 eff = val * st->num_enabled_channels; 1379 if (eff > AD4130_FIFO_SIZE) 1380 /* 1381 * Always set watermark to a multiple of the number of 1382 * enabled channels to avoid making the FIFO unaligned. 1383 */ 1384 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels); 1385 1386 guard(mutex)(&st->lock); 1387 1388 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 1389 AD4130_FIFO_CONTROL_WM_MASK, 1390 FIELD_PREP(AD4130_FIFO_CONTROL_WM_MASK, 1391 ad4130_watermark_reg_val(eff))); 1392 if (ret) 1393 return ret; 1394 1395 st->effective_watermark = eff; 1396 st->watermark = val; 1397 1398 return 0; 1399 } 1400 1401 static const struct iio_info ad4130_info = { 1402 .read_raw = ad4130_read_raw, 1403 .read_avail = ad4130_read_avail, 1404 .write_raw_get_fmt = ad4130_write_raw_get_fmt, 1405 .write_raw = ad4130_write_raw, 1406 .update_scan_mode = ad4130_update_scan_mode, 1407 .hwfifo_set_watermark = ad4130_set_fifo_watermark, 1408 .debugfs_reg_access = ad4130_reg_access, 1409 }; 1410 1411 static const struct iio_info ad4131_info = { 1412 .read_raw = ad4130_read_raw, 1413 .read_avail = ad4130_read_avail, 1414 .write_raw_get_fmt = ad4130_write_raw_get_fmt, 1415 .write_raw = ad4130_write_raw, 1416 .update_scan_mode = ad4130_update_scan_mode, 1417 .debugfs_reg_access = ad4130_reg_access, 1418 }; 1419 1420 static const struct ad4130_chip_info ad4129_4_chip_info = { 1421 .name = "ad4129-4", 1422 .max_analog_pins = 8, 1423 .num_gpios = 2, 1424 .info = &ad4130_info, 1425 .reg_size = ad4129_reg_size, 1426 .reg_size_length = ARRAY_SIZE(ad4129_reg_size), 1427 .has_fifo = true, 1428 .pin_map = ad4130_4_pin_map, 1429 }; 1430 1431 static const struct ad4130_chip_info ad4129_8_chip_info = { 1432 .name = "ad4129-8", 1433 .max_analog_pins = 16, 1434 .num_gpios = 4, 1435 .info = &ad4130_info, 1436 .reg_size = ad4129_reg_size, 1437 .reg_size_length = ARRAY_SIZE(ad4129_reg_size), 1438 .has_fifo = true, 1439 .pin_map = ad4130_8_pin_map, 1440 }; 1441 1442 static const struct ad4130_chip_info ad4130_4_chip_info = { 1443 .name = "ad4130-4", 1444 .max_analog_pins = 16, 1445 .num_gpios = 2, 1446 .info = &ad4130_info, 1447 .reg_size = ad4130_reg_size, 1448 .reg_size_length = ARRAY_SIZE(ad4130_reg_size), 1449 .has_fifo = true, 1450 .pin_map = ad4130_4_pin_map, 1451 }; 1452 1453 static const struct ad4130_chip_info ad4130_8_chip_info = { 1454 .name = "ad4130-8", 1455 .max_analog_pins = 16, 1456 .num_gpios = 4, 1457 .info = &ad4130_info, 1458 .reg_size = ad4130_reg_size, 1459 .reg_size_length = ARRAY_SIZE(ad4130_reg_size), 1460 .has_fifo = true, 1461 .pin_map = ad4130_8_pin_map, 1462 }; 1463 1464 static const struct ad4130_chip_info ad4131_4_chip_info = { 1465 .name = "ad4131-4", 1466 .max_analog_pins = 8, 1467 .num_gpios = 2, 1468 .info = &ad4131_info, 1469 .reg_size = ad4131_reg_size, 1470 .reg_size_length = ARRAY_SIZE(ad4131_reg_size), 1471 .pin_map = ad4130_4_pin_map, 1472 }; 1473 1474 static const struct ad4130_chip_info ad4131_8_chip_info = { 1475 .name = "ad4131-8", 1476 .max_analog_pins = 16, 1477 .num_gpios = 4, 1478 .info = &ad4131_info, 1479 .reg_size = ad4131_reg_size, 1480 .reg_size_length = ARRAY_SIZE(ad4131_reg_size), 1481 .pin_map = ad4130_8_pin_map, 1482 }; 1483 1484 static int ad4130_buffer_postenable(struct iio_dev *indio_dev) 1485 { 1486 struct ad4130_state *st = iio_priv(indio_dev); 1487 int ret; 1488 1489 guard(mutex)(&st->lock); 1490 1491 if (st->chip_info->has_fifo) { 1492 ret = ad4130_set_watermark_interrupt_en(st, true); 1493 if (ret) 1494 return ret; 1495 1496 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); 1497 if (ret) 1498 return ret; 1499 1500 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); 1501 if (ret) 1502 return ret; 1503 } 1504 1505 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); 1506 if (ret) 1507 return ret; 1508 1509 /* 1510 * When using triggered buffer, Entering continuous read mode must 1511 * be the last command sent. No configuration changes are allowed until 1512 * exiting this mode. 1513 */ 1514 if (!st->chip_info->has_fifo) { 1515 ret = regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, 1516 AD4130_ADC_CONTROL_CONT_READ_MASK, 1517 FIELD_PREP(AD4130_ADC_CONTROL_CONT_READ_MASK, 1)); 1518 if (ret) 1519 return ret; 1520 } 1521 1522 return 0; 1523 } 1524 1525 static int ad4130_buffer_predisable(struct iio_dev *indio_dev) 1526 { 1527 struct ad4130_state *st = iio_priv(indio_dev); 1528 unsigned int i; 1529 u32 temp; 1530 int ret; 1531 1532 guard(mutex)(&st->lock); 1533 1534 if (!st->chip_info->has_fifo) { 1535 temp = 0x42; 1536 reinit_completion(&st->completion); 1537 1538 /* 1539 * In continuous read mode, when all samples are read, the data 1540 * ready signal returns high until the next conversion result is 1541 * ready. To exit this mode, the command must be sent when data 1542 * ready is low. In order to ensure that condition, wait for the 1543 * next interrupt (when the new conversion is finished), allowing 1544 * data ready to return low before sending the exit command. 1545 */ 1546 st->buffer_wait_for_irq = true; 1547 if (!wait_for_completion_timeout(&st->completion, msecs_to_jiffies(1000))) 1548 dev_warn(&st->spi->dev, "Conversion timed out\n"); 1549 st->buffer_wait_for_irq = false; 1550 1551 /* Perform a read data command to exit continuous read mode (0x42) */ 1552 ret = spi_write(st->spi, &temp, 1); 1553 if (ret) 1554 return ret; 1555 } 1556 1557 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); 1558 if (ret) 1559 return ret; 1560 1561 if (st->chip_info->has_fifo) { 1562 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger); 1563 if (ret) 1564 return ret; 1565 1566 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); 1567 if (ret) 1568 return ret; 1569 1570 ret = ad4130_set_watermark_interrupt_en(st, false); 1571 if (ret) 1572 return ret; 1573 } 1574 1575 /* 1576 * update_scan_mode() is not called in the disable path, disable all 1577 * channels here. 1578 */ 1579 for (i = 0; i < indio_dev->num_channels; i++) { 1580 ret = ad4130_set_channel_enable(st, i, false); 1581 if (ret) 1582 return ret; 1583 } 1584 1585 return 0; 1586 } 1587 1588 static const struct iio_buffer_setup_ops ad4130_buffer_ops = { 1589 .postenable = ad4130_buffer_postenable, 1590 .predisable = ad4130_buffer_predisable, 1591 }; 1592 1593 static ssize_t hwfifo_watermark_show(struct device *dev, 1594 struct device_attribute *attr, char *buf) 1595 { 1596 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); 1597 unsigned int val; 1598 1599 guard(mutex)(&st->lock); 1600 val = st->watermark; 1601 1602 return sysfs_emit(buf, "%d\n", val); 1603 } 1604 1605 static ssize_t hwfifo_enabled_show(struct device *dev, 1606 struct device_attribute *attr, char *buf) 1607 { 1608 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); 1609 unsigned int val; 1610 int ret; 1611 1612 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val); 1613 if (ret) 1614 return ret; 1615 1616 val = FIELD_GET(AD4130_FIFO_CONTROL_MODE_MASK, val); 1617 1618 return sysfs_emit(buf, "%d\n", val != AD4130_FIFO_MODE_DISABLED); 1619 } 1620 1621 static ssize_t hwfifo_watermark_min_show(struct device *dev, 1622 struct device_attribute *attr, 1623 char *buf) 1624 { 1625 return sysfs_emit(buf, "%s\n", "1"); 1626 } 1627 1628 static ssize_t hwfifo_watermark_max_show(struct device *dev, 1629 struct device_attribute *attr, 1630 char *buf) 1631 { 1632 return sysfs_emit(buf, "%s\n", __stringify(AD4130_FIFO_SIZE)); 1633 } 1634 1635 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 1636 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 1637 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0); 1638 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0); 1639 1640 static const struct iio_dev_attr *ad4130_fifo_attributes[] = { 1641 &iio_dev_attr_hwfifo_watermark_min, 1642 &iio_dev_attr_hwfifo_watermark_max, 1643 &iio_dev_attr_hwfifo_watermark, 1644 &iio_dev_attr_hwfifo_enabled, 1645 NULL 1646 }; 1647 1648 static const struct iio_trigger_ops ad4130_trigger_ops = { 1649 .validate_device = iio_trigger_validate_own_device, 1650 }; 1651 1652 static int ad4130_triggered_buffer_setup(struct iio_dev *indio_dev) 1653 { 1654 struct ad4130_state *st = iio_priv(indio_dev); 1655 int ret; 1656 1657 st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", 1658 indio_dev->name, iio_device_id(indio_dev)); 1659 if (!st->trig) 1660 return -ENOMEM; 1661 1662 st->trig->ops = &ad4130_trigger_ops; 1663 iio_trigger_set_drvdata(st->trig, indio_dev); 1664 ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig); 1665 if (ret) 1666 return ret; 1667 1668 indio_dev->trig = iio_trigger_get(st->trig); 1669 1670 return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, 1671 &iio_pollfunc_store_time, 1672 &ad4130_trigger_handler, 1673 &ad4130_buffer_ops); 1674 } 1675 1676 static int _ad4130_find_table_index(const unsigned int *tbl, size_t len, 1677 unsigned int val) 1678 { 1679 unsigned int i; 1680 1681 for (i = 0; i < len; i++) 1682 if (tbl[i] == val) 1683 return i; 1684 1685 return -EINVAL; 1686 } 1687 1688 #define ad4130_find_table_index(table, val) \ 1689 _ad4130_find_table_index(table, ARRAY_SIZE(table), val) 1690 1691 static int ad4130_get_ref_voltage(struct ad4130_state *st, 1692 enum ad4130_ref_sel ref_sel) 1693 { 1694 switch (ref_sel) { 1695 case AD4130_REF_REFIN1: 1696 return regulator_get_voltage(st->regulators[2].consumer); 1697 case AD4130_REF_REFIN2: 1698 return regulator_get_voltage(st->regulators[3].consumer); 1699 case AD4130_REF_AVDD_AVSS: 1700 return regulator_get_voltage(st->regulators[0].consumer); 1701 case AD4130_REF_REFOUT_AVSS: 1702 return st->int_ref_uv; 1703 default: 1704 return -EINVAL; 1705 } 1706 } 1707 1708 static int ad4130_parse_fw_setup(struct ad4130_state *st, 1709 struct fwnode_handle *child, 1710 struct ad4130_setup_info *setup_info) 1711 { 1712 struct device *dev = &st->spi->dev; 1713 u32 tmp; 1714 int ret; 1715 1716 tmp = 0; 1717 fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp); 1718 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp); 1719 if (ret < 0) 1720 return dev_err_probe(dev, ret, 1721 "Invalid excitation current %unA\n", tmp); 1722 setup_info->iout0_val = ret; 1723 1724 tmp = 0; 1725 fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp); 1726 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp); 1727 if (ret < 0) 1728 return dev_err_probe(dev, ret, 1729 "Invalid excitation current %unA\n", tmp); 1730 setup_info->iout1_val = ret; 1731 1732 tmp = 0; 1733 fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp); 1734 ret = ad4130_find_table_index(ad4130_burnout_current_na_tbl, tmp); 1735 if (ret < 0) 1736 return dev_err_probe(dev, ret, 1737 "Invalid burnout current %unA\n", tmp); 1738 setup_info->burnout = ret; 1739 1740 setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive"); 1741 setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative"); 1742 1743 setup_info->ref_sel = AD4130_REF_REFIN1; 1744 fwnode_property_read_u32(child, "adi,reference-select", 1745 &setup_info->ref_sel); 1746 if (setup_info->ref_sel >= AD4130_REF_SEL_MAX) 1747 return dev_err_probe(dev, -EINVAL, 1748 "Invalid reference selected %u\n", 1749 setup_info->ref_sel); 1750 1751 if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS) 1752 st->int_ref_en = true; 1753 1754 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel); 1755 if (ret < 0) 1756 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1757 setup_info->ref_sel); 1758 1759 return 0; 1760 } 1761 1762 static unsigned int ad4130_translate_pin(struct ad4130_state *st, 1763 unsigned int logical_pin) 1764 { 1765 /* For analog input pins, use the chip-specific pin mapping */ 1766 if (logical_pin < st->chip_info->max_analog_pins) 1767 return st->chip_info->pin_map[logical_pin]; 1768 1769 /* For internal channels, pass through unchanged */ 1770 return logical_pin; 1771 } 1772 1773 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin) 1774 { 1775 struct device *dev = &st->spi->dev; 1776 1777 if (pin >= AD4130_MAX_DIFF_INPUTS) 1778 return dev_err_probe(dev, -EINVAL, 1779 "Invalid differential channel %u\n", pin); 1780 1781 if (pin >= st->chip_info->max_analog_pins) 1782 return 0; 1783 1784 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) 1785 return dev_err_probe(dev, -EINVAL, 1786 "Pin %u already used with fn %u\n", pin, 1787 st->pins_fn[pin]); 1788 1789 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF; 1790 1791 return 0; 1792 } 1793 1794 static int ad4130_validate_diff_channels(struct ad4130_state *st, 1795 u32 *pins, unsigned int len) 1796 { 1797 unsigned int i; 1798 int ret; 1799 1800 for (i = 0; i < len; i++) { 1801 ret = ad4130_validate_diff_channel(st, pins[i]); 1802 if (ret) 1803 return ret; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin) 1810 { 1811 struct device *dev = &st->spi->dev; 1812 1813 if (pin >= st->chip_info->max_analog_pins) 1814 return dev_err_probe(dev, -EINVAL, 1815 "Invalid excitation pin %u\n", pin); 1816 1817 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) 1818 return dev_err_probe(dev, -EINVAL, 1819 "Pin %u already used with fn %u\n", pin, 1820 st->pins_fn[pin]); 1821 1822 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION; 1823 1824 return 0; 1825 } 1826 1827 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin) 1828 { 1829 struct device *dev = &st->spi->dev; 1830 1831 if (pin >= st->chip_info->max_analog_pins) 1832 return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n", 1833 pin); 1834 1835 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) 1836 return dev_err_probe(dev, -EINVAL, 1837 "Pin %u already used with fn %u\n", pin, 1838 st->pins_fn[pin]); 1839 1840 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS; 1841 1842 return 0; 1843 } 1844 1845 static int ad4130_validate_vbias_pins(struct ad4130_state *st, 1846 u32 *pins, unsigned int len) 1847 { 1848 unsigned int i; 1849 int ret; 1850 1851 for (i = 0; i < st->num_vbias_pins; i++) { 1852 ret = ad4130_validate_vbias_pin(st, pins[i]); 1853 if (ret) 1854 return ret; 1855 } 1856 1857 return 0; 1858 } 1859 1860 static int ad4130_parse_fw_channel(struct iio_dev *indio_dev, 1861 struct fwnode_handle *child) 1862 { 1863 struct ad4130_state *st = iio_priv(indio_dev); 1864 unsigned int resolution = ad4130_resolution(st); 1865 unsigned int index = indio_dev->num_channels++; 1866 struct device *dev = &st->spi->dev; 1867 struct ad4130_chan_info *chan_info; 1868 struct iio_chan_spec *chan; 1869 u32 pins[2]; 1870 int ret; 1871 1872 if (index >= AD4130_MAX_CHANNELS) 1873 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 1874 1875 chan = &st->chans[index]; 1876 chan_info = &st->chans_info[index]; 1877 1878 *chan = ad4130_channel_template; 1879 chan->scan_type.realbits = resolution; 1880 chan->scan_type.storagebits = resolution; 1881 chan->scan_index = index; 1882 1883 chan_info->slot = AD4130_INVALID_SLOT; 1884 chan_info->setup.fs = AD4130_FILTER_SELECT_MIN; 1885 chan_info->initialized = true; 1886 1887 ret = fwnode_property_read_u32_array(child, "diff-channels", pins, 1888 ARRAY_SIZE(pins)); 1889 if (ret) 1890 return ret; 1891 1892 ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins)); 1893 if (ret) 1894 return ret; 1895 1896 chan->channel = pins[0]; 1897 chan->channel2 = pins[1]; 1898 1899 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup); 1900 if (ret) 1901 return ret; 1902 1903 fwnode_property_read_u32(child, "adi,excitation-pin-0", 1904 &chan_info->iout0); 1905 if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) { 1906 ret = ad4130_validate_excitation_pin(st, chan_info->iout0); 1907 if (ret) 1908 return ret; 1909 } 1910 1911 fwnode_property_read_u32(child, "adi,excitation-pin-1", 1912 &chan_info->iout1); 1913 if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) { 1914 ret = ad4130_validate_excitation_pin(st, chan_info->iout1); 1915 if (ret) 1916 return ret; 1917 } 1918 1919 return 0; 1920 } 1921 1922 static int ad4130_parse_fw_children(struct iio_dev *indio_dev) 1923 { 1924 struct ad4130_state *st = iio_priv(indio_dev); 1925 struct device *dev = &st->spi->dev; 1926 int ret; 1927 1928 indio_dev->channels = st->chans; 1929 1930 device_for_each_child_node_scoped(dev, child) { 1931 ret = ad4130_parse_fw_channel(indio_dev, child); 1932 if (ret) 1933 return ret; 1934 } 1935 1936 return 0; 1937 } 1938 1939 static int ad4310_parse_fw(struct iio_dev *indio_dev) 1940 { 1941 struct ad4130_state *st = iio_priv(indio_dev); 1942 struct device *dev = &st->spi->dev; 1943 u32 ext_clk_freq = AD4130_MCLK_FREQ_76_8KHZ; 1944 unsigned int i; 1945 int avdd_uv; 1946 int irq; 1947 int ret; 1948 1949 st->mclk = devm_clk_get_optional(dev, "mclk"); 1950 if (IS_ERR(st->mclk)) 1951 return dev_err_probe(dev, PTR_ERR(st->mclk), 1952 "Failed to get mclk\n"); 1953 1954 st->int_pin_sel = AD4130_INT_PIN_INT; 1955 1956 for (i = 0; i < ARRAY_SIZE(ad4130_int_pin_names); i++) { 1957 irq = fwnode_irq_get_byname(dev_fwnode(dev), 1958 ad4130_int_pin_names[i]); 1959 if (irq > 0) { 1960 st->int_pin_sel = i; 1961 break; 1962 } 1963 } 1964 1965 if (st->int_pin_sel == AD4130_INT_PIN_DOUT) 1966 return dev_err_probe(dev, -EINVAL, 1967 "Cannot use DOUT as interrupt pin\n"); 1968 1969 if (st->int_pin_sel == AD4130_INT_PIN_P2) 1970 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL; 1971 1972 device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq); 1973 if (ext_clk_freq != AD4130_MCLK_FREQ_153_6KHZ && 1974 ext_clk_freq != AD4130_MCLK_FREQ_76_8KHZ) 1975 return dev_err_probe(dev, -EINVAL, 1976 "Invalid external clock frequency %u\n", 1977 ext_clk_freq); 1978 1979 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ) 1980 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT; 1981 else if (st->mclk) 1982 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT; 1983 else 1984 st->mclk_sel = AD4130_MCLK_76_8KHZ; 1985 1986 if (st->int_pin_sel == AD4130_INT_PIN_CLK && 1987 st->mclk_sel != AD4130_MCLK_76_8KHZ) 1988 return dev_err_probe(dev, -EINVAL, 1989 "Invalid clock %u for interrupt pin %u\n", 1990 st->mclk_sel, st->int_pin_sel); 1991 1992 st->int_ref_uv = AD4130_INT_REF_2_5V; 1993 1994 /* 1995 * When the AVDD supply is set to below 2.5V the internal reference of 1996 * 1.25V should be selected. 1997 * See datasheet page 37, section ADC REFERENCE. 1998 */ 1999 avdd_uv = regulator_get_voltage(st->regulators[0].consumer); 2000 if (avdd_uv > 0 && avdd_uv < AD4130_INT_REF_2_5V) 2001 st->int_ref_uv = AD4130_INT_REF_1_25V; 2002 2003 st->bipolar = device_property_read_bool(dev, "adi,bipolar"); 2004 2005 ret = device_property_count_u32(dev, "adi,vbias-pins"); 2006 if (ret > 0) { 2007 if (ret > st->chip_info->max_analog_pins) 2008 return dev_err_probe(dev, -EINVAL, 2009 "Too many vbias pins %u\n", ret); 2010 2011 st->num_vbias_pins = ret; 2012 2013 ret = device_property_read_u32_array(dev, "adi,vbias-pins", 2014 st->vbias_pins, 2015 st->num_vbias_pins); 2016 if (ret) 2017 return dev_err_probe(dev, ret, 2018 "Failed to read vbias pins\n"); 2019 2020 ret = ad4130_validate_vbias_pins(st, st->vbias_pins, 2021 st->num_vbias_pins); 2022 if (ret) 2023 return ret; 2024 } 2025 2026 ret = ad4130_parse_fw_children(indio_dev); 2027 if (ret) 2028 return ret; 2029 2030 return 0; 2031 } 2032 2033 static void ad4130_fill_scale_tbls(struct ad4130_state *st) 2034 { 2035 unsigned int pow = ad4130_resolution(st) - st->bipolar; 2036 unsigned int i, j; 2037 2038 for (i = 0; i < AD4130_REF_SEL_MAX; i++) { 2039 int ret; 2040 u64 nv; 2041 2042 ret = ad4130_get_ref_voltage(st, i); 2043 if (ret < 0) 2044 continue; 2045 2046 nv = (u64)ret * NANO; 2047 2048 for (j = 0; j < AD4130_MAX_PGA; j++) 2049 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI); 2050 } 2051 } 2052 2053 static void ad4130_clk_disable_unprepare(void *clk) 2054 { 2055 clk_disable_unprepare(clk); 2056 } 2057 2058 static int ad4130_set_mclk_sel(struct ad4130_state *st, 2059 enum ad4130_mclk_sel mclk_sel) 2060 { 2061 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, 2062 AD4130_ADC_CONTROL_MCLK_SEL_MASK, 2063 FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, 2064 mclk_sel)); 2065 } 2066 2067 static unsigned long ad4130_int_clk_recalc_rate(struct clk_hw *hw, 2068 unsigned long parent_rate) 2069 { 2070 return AD4130_MCLK_FREQ_76_8KHZ; 2071 } 2072 2073 static int ad4130_int_clk_is_enabled(struct clk_hw *hw) 2074 { 2075 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); 2076 2077 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT; 2078 } 2079 2080 static int ad4130_int_clk_prepare(struct clk_hw *hw) 2081 { 2082 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); 2083 int ret; 2084 2085 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT); 2086 if (ret) 2087 return ret; 2088 2089 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT; 2090 2091 return 0; 2092 } 2093 2094 static void ad4130_int_clk_unprepare(struct clk_hw *hw) 2095 { 2096 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); 2097 int ret; 2098 2099 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ); 2100 if (ret) 2101 return; 2102 2103 st->mclk_sel = AD4130_MCLK_76_8KHZ; 2104 } 2105 2106 static const struct clk_ops ad4130_int_clk_ops = { 2107 .recalc_rate = ad4130_int_clk_recalc_rate, 2108 .is_enabled = ad4130_int_clk_is_enabled, 2109 .prepare = ad4130_int_clk_prepare, 2110 .unprepare = ad4130_int_clk_unprepare, 2111 }; 2112 2113 static int ad4130_setup_int_clk(struct ad4130_state *st) 2114 { 2115 struct device *dev = &st->spi->dev; 2116 struct device_node *of_node = dev_of_node(dev); 2117 struct clk_init_data init = {}; 2118 const char *clk_name; 2119 int ret; 2120 2121 if (st->int_pin_sel == AD4130_INT_PIN_CLK || 2122 st->mclk_sel != AD4130_MCLK_76_8KHZ) 2123 return 0; 2124 2125 if (!of_node) 2126 return 0; 2127 2128 clk_name = of_node->name; 2129 of_property_read_string(of_node, "clock-output-names", &clk_name); 2130 2131 init.name = clk_name; 2132 init.ops = &ad4130_int_clk_ops; 2133 2134 st->int_clk_hw.init = &init; 2135 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 2136 if (ret) 2137 return ret; 2138 2139 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2140 &st->int_clk_hw); 2141 } 2142 2143 static int ad4130_setup(struct iio_dev *indio_dev) 2144 { 2145 struct ad4130_state *st = iio_priv(indio_dev); 2146 struct device *dev = &st->spi->dev; 2147 unsigned int int_ref_val; 2148 unsigned long rate = AD4130_MCLK_FREQ_76_8KHZ; 2149 unsigned int val; 2150 unsigned int i; 2151 int ret; 2152 2153 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT) 2154 rate = AD4130_MCLK_FREQ_153_6KHZ; 2155 2156 ret = clk_set_rate(st->mclk, rate); 2157 if (ret) 2158 return ret; 2159 2160 ret = clk_prepare_enable(st->mclk); 2161 if (ret) 2162 return ret; 2163 2164 ret = devm_add_action_or_reset(dev, ad4130_clk_disable_unprepare, 2165 st->mclk); 2166 if (ret) 2167 return ret; 2168 2169 if (st->int_ref_uv == AD4130_INT_REF_2_5V) 2170 int_ref_val = AD4130_INT_REF_VAL_2_5V; 2171 else 2172 int_ref_val = AD4130_INT_REF_VAL_1_25V; 2173 2174 /* Switch to SPI 4-wire mode. */ 2175 val = FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1); 2176 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar); 2177 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en); 2178 val |= FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, AD4130_MODE_IDLE); 2179 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel); 2180 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_VAL_MASK, int_ref_val); 2181 2182 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val); 2183 if (ret) 2184 return ret; 2185 2186 /* 2187 * Configure unused GPIOs for output. If configured, the interrupt 2188 * function of P2 takes priority over the GPIO out function. 2189 */ 2190 val = 0; 2191 for (i = 0; i < st->chip_info->num_gpios; i++) { 2192 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE) { 2193 if (st->chip_info->num_gpios == 2) 2194 val |= FIELD_PREP(AD4130_4_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); 2195 else 2196 val |= FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i)); 2197 } 2198 } 2199 2200 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); 2201 2202 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val); 2203 if (ret) 2204 return ret; 2205 2206 val = 0; 2207 for (i = 0; i < st->num_vbias_pins; i++) 2208 val |= BIT(ad4130_translate_pin(st, st->vbias_pins[i])); 2209 2210 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val); 2211 if (ret) 2212 return ret; 2213 2214 if (st->chip_info->has_fifo) { 2215 ret = regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 2216 AD4130_FIFO_CONTROL_HEADER_MASK); 2217 if (ret) 2218 return ret; 2219 2220 /* FIFO watermark interrupt starts out as enabled, disable it. */ 2221 ret = ad4130_set_watermark_interrupt_en(st, false); 2222 if (ret) 2223 return ret; 2224 } 2225 2226 /* Setup channels. */ 2227 for (i = 0; i < indio_dev->num_channels; i++) { 2228 struct ad4130_chan_info *chan_info = &st->chans_info[i]; 2229 struct iio_chan_spec *chan = &st->chans[i]; 2230 unsigned int val; 2231 2232 val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, 2233 ad4130_translate_pin(st, chan->channel)) | 2234 FIELD_PREP(AD4130_CHANNEL_AINM_MASK, 2235 ad4130_translate_pin(st, chan->channel2)) | 2236 FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, 2237 ad4130_translate_pin(st, chan_info->iout0)) | 2238 FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, 2239 ad4130_translate_pin(st, chan_info->iout1)); 2240 2241 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); 2242 if (ret) 2243 return ret; 2244 } 2245 2246 return 0; 2247 } 2248 2249 static int ad4130_soft_reset(struct ad4130_state *st) 2250 { 2251 int ret; 2252 2253 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf)); 2254 if (ret) 2255 return ret; 2256 2257 fsleep(AD4130_RESET_SLEEP_US); 2258 2259 return 0; 2260 } 2261 2262 static void ad4130_disable_regulators(void *data) 2263 { 2264 struct ad4130_state *st = data; 2265 2266 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 2267 } 2268 2269 static int ad4130_probe(struct spi_device *spi) 2270 { 2271 struct device *dev = &spi->dev; 2272 struct iio_dev *indio_dev; 2273 struct ad4130_state *st; 2274 int ret; 2275 2276 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 2277 if (!indio_dev) 2278 return -ENOMEM; 2279 2280 st = iio_priv(indio_dev); 2281 2282 st->chip_info = device_get_match_data(dev); 2283 2284 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); 2285 init_completion(&st->completion); 2286 mutex_init(&st->lock); 2287 st->spi = spi; 2288 2289 if (st->chip_info->has_fifo) { 2290 /* 2291 * Xfer: [ XFR1 ] [ XFR2 ] 2292 * Master: 0x7D N ...................... 2293 * Slave: ...... DATA1 DATA2 ... DATAN 2294 */ 2295 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; 2296 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf; 2297 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf); 2298 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf; 2299 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, 2300 ARRAY_SIZE(st->fifo_xfer)); 2301 } 2302 2303 indio_dev->name = st->chip_info->name; 2304 indio_dev->modes = INDIO_DIRECT_MODE; 2305 indio_dev->info = st->chip_info->info; 2306 2307 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); 2308 if (IS_ERR(st->regmap)) 2309 return PTR_ERR(st->regmap); 2310 2311 st->regulators[0].supply = "avdd"; 2312 st->regulators[1].supply = "iovdd"; 2313 st->regulators[2].supply = "refin1"; 2314 st->regulators[3].supply = "refin2"; 2315 2316 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 2317 st->regulators); 2318 if (ret) 2319 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 2320 2321 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 2322 if (ret) 2323 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 2324 2325 ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st); 2326 if (ret) 2327 return ret; 2328 2329 ret = ad4130_soft_reset(st); 2330 if (ret) 2331 return ret; 2332 2333 ret = ad4310_parse_fw(indio_dev); 2334 if (ret) 2335 return ret; 2336 2337 ret = ad4130_setup(indio_dev); 2338 if (ret) 2339 return ret; 2340 2341 ret = ad4130_setup_int_clk(st); 2342 if (ret) 2343 return ret; 2344 2345 ad4130_fill_scale_tbls(st); 2346 2347 st->gc.owner = THIS_MODULE; 2348 st->gc.label = st->chip_info->name; 2349 st->gc.base = -1; 2350 st->gc.ngpio = st->chip_info->num_gpios; 2351 st->gc.parent = dev; 2352 st->gc.can_sleep = true; 2353 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask; 2354 st->gc.get_direction = ad4130_gpio_get_direction; 2355 st->gc.set = ad4130_gpio_set; 2356 2357 ret = devm_gpiochip_add_data(dev, &st->gc, st); 2358 if (ret) 2359 return ret; 2360 2361 if (st->chip_info->has_fifo) 2362 ret = devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, 2363 &ad4130_buffer_ops, 2364 ad4130_fifo_attributes); 2365 else 2366 ret = ad4130_triggered_buffer_setup(indio_dev); 2367 if (ret) 2368 return ret; 2369 2370 ret = devm_request_threaded_irq(dev, spi->irq, NULL, 2371 ad4130_irq_handler, IRQF_ONESHOT, 2372 indio_dev->name, indio_dev); 2373 if (ret) 2374 return dev_err_probe(dev, ret, "Failed to request irq\n"); 2375 2376 if (st->chip_info->has_fifo) { 2377 /* 2378 * When the chip enters FIFO mode, IRQ polarity is inverted. 2379 * When the chip exits FIFO mode, IRQ polarity returns to normal. 2380 * See datasheet pages: 65, FIFO Watermark Interrupt section, 2381 * and 71, Bit Descriptions for STATUS Register, RDYB. 2382 * Cache the normal and inverted IRQ triggers to set them when 2383 * entering and exiting FIFO mode. 2384 */ 2385 st->irq_trigger = irq_get_trigger_type(spi->irq); 2386 if (st->irq_trigger & IRQF_TRIGGER_RISING) 2387 st->inv_irq_trigger = IRQF_TRIGGER_FALLING; 2388 else if (st->irq_trigger & IRQF_TRIGGER_FALLING) 2389 st->inv_irq_trigger = IRQF_TRIGGER_RISING; 2390 else 2391 return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", 2392 st->irq_trigger); 2393 } 2394 2395 return devm_iio_device_register(dev, indio_dev); 2396 } 2397 2398 static const struct of_device_id ad4130_of_match[] = { 2399 { 2400 .compatible = "adi,ad4129-4", 2401 .data = &ad4129_4_chip_info 2402 }, 2403 { 2404 .compatible = "adi,ad4129-8", 2405 .data = &ad4129_8_chip_info 2406 }, 2407 { 2408 .compatible = "adi,ad4130-4", 2409 .data = &ad4130_4_chip_info 2410 }, 2411 { 2412 .compatible = "adi,ad4130", 2413 .data = &ad4130_8_chip_info 2414 }, 2415 { 2416 .compatible = "adi,ad4131-4", 2417 .data = &ad4131_4_chip_info 2418 }, 2419 { 2420 .compatible = "adi,ad4131-8", 2421 .data = &ad4131_8_chip_info 2422 }, 2423 { } 2424 }; 2425 MODULE_DEVICE_TABLE(of, ad4130_of_match); 2426 2427 static const struct spi_device_id ad4130_id_table[] = { 2428 { .name = "ad4129-4", .driver_data = (kernel_ulong_t)&ad4129_4_chip_info }, 2429 { .name = "ad4129-8", .driver_data = (kernel_ulong_t)&ad4129_8_chip_info }, 2430 { .name = "ad4130-4", .driver_data = (kernel_ulong_t)&ad4130_4_chip_info }, 2431 { .name = "ad4130", .driver_data = (kernel_ulong_t)&ad4130_8_chip_info }, 2432 { .name = "ad4131-4", .driver_data = (kernel_ulong_t)&ad4131_4_chip_info }, 2433 { .name = "ad4131-8", .driver_data = (kernel_ulong_t)&ad4131_8_chip_info }, 2434 { } 2435 }; 2436 MODULE_DEVICE_TABLE(spi, ad4130_id_table); 2437 2438 static struct spi_driver ad4130_driver = { 2439 .driver = { 2440 .name = AD4130_NAME, 2441 .of_match_table = ad4130_of_match, 2442 }, 2443 .probe = ad4130_probe, 2444 .id_table = ad4130_id_table, 2445 }; 2446 module_spi_driver(ad4130_driver); 2447 2448 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 2449 MODULE_DESCRIPTION("Analog Devices AD4130 SPI driver"); 2450 MODULE_LICENSE("GPL"); 2451