1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD4080 SPI ADC driver 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/iio/backend.h> 15 #include <linux/iio/iio.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/spi/spi.h> 22 #include <linux/types.h> 23 #include <linux/unaligned.h> 24 #include <linux/units.h> 25 26 /* Register Definition */ 27 #define AD4080_REG_INTERFACE_CONFIG_A 0x00 28 #define AD4080_REG_INTERFACE_CONFIG_B 0x01 29 #define AD4080_REG_DEVICE_CONFIG 0x02 30 #define AD4080_REG_CHIP_TYPE 0x03 31 #define AD4080_REG_PRODUCT_ID_L 0x04 32 #define AD4080_REG_PRODUCT_ID_H 0x05 33 #define AD4080_REG_CHIP_GRADE 0x06 34 #define AD4080_REG_SCRATCH_PAD 0x0A 35 #define AD4080_REG_SPI_REVISION 0x0B 36 #define AD4080_REG_VENDOR_L 0x0C 37 #define AD4080_REG_VENDOR_H 0x0D 38 #define AD4080_REG_STREAM_MODE 0x0E 39 #define AD4080_REG_TRANSFER_CONFIG 0x0F 40 #define AD4080_REG_INTERFACE_CONFIG_C 0x10 41 #define AD4080_REG_INTERFACE_STATUS_A 0x11 42 #define AD4080_REG_DEVICE_STATUS 0x14 43 #define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15 44 #define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16 45 #define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17 46 #define AD4080_REG_PWR_CTRL 0x18 47 #define AD4080_REG_GPIO_CONFIG_A 0x19 48 #define AD4080_REG_GPIO_CONFIG_B 0x1A 49 #define AD4080_REG_GPIO_CONFIG_C 0x1B 50 #define AD4080_REG_GENERAL_CONFIG 0x1C 51 #define AD4080_REG_FIFO_WATERMARK_LSB 0x1D 52 #define AD4080_REG_FIFO_WATERMARK_MSB 0x1E 53 #define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F 54 #define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20 55 #define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21 56 #define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22 57 #define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23 58 #define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24 59 #define AD4080_REG_OFFSET_LSB 0x25 60 #define AD4080_REG_OFFSET_MSB 0x26 61 #define AD4080_REG_GAIN_LSB 0x27 62 #define AD4080_REG_GAIN_MSB 0x28 63 #define AD4080_REG_FILTER_CONFIG 0x29 64 65 /* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */ 66 #define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) 67 #define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5) 68 #define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) 69 70 /* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */ 71 #define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7) 72 #define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3) 73 74 /* AD4080_REG_DEVICE_CONFIG Bit Definition */ 75 #define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0) 76 77 /* AD4080_REG_TRANSFER_CONFIG Bit Definition */ 78 #define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2) 79 80 /* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */ 81 #define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5) 82 83 /* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */ 84 #define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6) 85 #define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4) 86 #define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2) 87 #define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0) 88 89 /* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */ 90 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4) 91 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3) 92 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0) 93 94 /* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */ 95 #define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4) 96 97 /* AD4080_REG_PWR_CTRL Bit Definition */ 98 #define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1) 99 #define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0) 100 101 /* AD4080_REG_GPIO_CONFIG_A Bit Definition */ 102 #define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1) 103 #define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0) 104 105 /* AD4080_REG_GPIO_CONFIG_B Bit Definition */ 106 #define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4) 107 #define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0) 108 #define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO 0 109 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL 1 110 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE 2 111 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY 3 112 #define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH 4 113 #define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH 5 114 #define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT 6 115 #define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA 7 116 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC 8 117 #define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT 9 118 119 /* AD4080_REG_FIFO_CONFIG Bit Definition */ 120 #define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0) 121 122 /* AD4080_REG_FILTER_CONFIG Bit Definition */ 123 #define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3) 124 #define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0) 125 126 /* Miscellaneous Definitions */ 127 #define AD4080_SPI_READ BIT(7) 128 #define AD4080_CHIP_ID 0x0050 129 #define AD4081_CHIP_ID 0x0051 130 #define AD4082_CHIP_ID 0x0052 131 #define AD4083_CHIP_ID 0x0053 132 #define AD4084_CHIP_ID 0x0054 133 #define AD4085_CHIP_ID 0x0055 134 #define AD4086_CHIP_ID 0x0056 135 #define AD4087_CHIP_ID 0x0057 136 #define AD4088_CHIP_ID 0x0058 137 #define AD4880_CHIP_ID 0x0059 138 #define AD4884_CHIP_ID 0x005C 139 140 #define AD4080_MAX_CHANNELS 2 141 142 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 143 144 #define AD4080_MAX_SAMP_FREQ 40000000 145 #define AD4080_MIN_SAMP_FREQ 1250000 146 147 enum ad4080_filter_type { 148 FILTER_NONE, 149 SINC_1, 150 SINC_5, 151 SINC_5_COMP 152 }; 153 154 static const unsigned int ad4080_scale_table[][2] = { 155 { 6000, 0 }, 156 }; 157 158 static const char *const ad4080_filter_type_iio_enum[] = { 159 [FILTER_NONE] = "none", 160 [SINC_1] = "sinc1", 161 [SINC_5] = "sinc5", 162 [SINC_5_COMP] = "sinc5+pf1", 163 }; 164 165 static const int ad4080_dec_rate_avail[] = { 166 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 167 }; 168 169 static const int ad4080_dec_rate_none[] = { 1 }; 170 171 static const char * const ad4080_power_supplies[] = { 172 "vdd33", "vdd11", "vddldo", "iovdd", "vrefin", 173 }; 174 175 struct ad4080_chip_info { 176 const char *name; 177 unsigned int product_id; 178 int num_scales; 179 const unsigned int (*scale_table)[2]; 180 const struct iio_chan_spec *channels; 181 unsigned int num_channels; 182 unsigned int lvds_cnv_clk_cnt_max; 183 }; 184 185 struct ad4080_state { 186 struct spi_device *spi[AD4080_MAX_CHANNELS]; 187 struct regmap *regmap[AD4080_MAX_CHANNELS]; 188 struct iio_backend *back[AD4080_MAX_CHANNELS]; 189 const struct ad4080_chip_info *info; 190 /* 191 * Synchronize access to members the of driver state, and ensure 192 * atomicity of consecutive regmap operations. 193 */ 194 struct mutex lock; 195 unsigned int num_lanes; 196 unsigned long clk_rate; 197 enum ad4080_filter_type filter_type[AD4080_MAX_CHANNELS]; 198 bool lvds_cnv_en; 199 }; 200 201 static const struct regmap_config ad4080_regmap_config = { 202 .reg_bits = 16, 203 .val_bits = 8, 204 .read_flag_mask = BIT(7), 205 .max_register = 0x29, 206 }; 207 208 static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg, 209 unsigned int writeval, unsigned int *readval) 210 { 211 struct ad4080_state *st = iio_priv(indio_dev); 212 213 if (readval) 214 return regmap_read(st->regmap[0], reg, readval); 215 216 return regmap_write(st->regmap[0], reg, writeval); 217 } 218 219 static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) 220 { 221 unsigned int tmp; 222 223 tmp = (st->info->scale_table[0][0] * 1000000ULL) >> 224 st->info->channels[0].scan_type.realbits; 225 *val = tmp / 1000000; 226 *val2 = tmp % 1000000; 227 228 return IIO_VAL_INT_PLUS_NANO; 229 } 230 231 static unsigned int ad4080_get_dec_rate(struct iio_dev *dev, 232 const struct iio_chan_spec *chan) 233 { 234 struct ad4080_state *st = iio_priv(dev); 235 int ret; 236 unsigned int data; 237 unsigned int ch = chan->channel; 238 239 ret = regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); 240 if (ret) 241 return ret; 242 243 return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1); 244 } 245 246 static int ad4080_set_dec_rate(struct iio_dev *dev, 247 const struct iio_chan_spec *chan, 248 unsigned int mode) 249 { 250 struct ad4080_state *st = iio_priv(dev); 251 unsigned int ch = chan->channel; 252 253 guard(mutex)(&st->lock); 254 255 if ((st->filter_type[ch] >= SINC_5 && mode >= 512) || mode < 2) 256 return -EINVAL; 257 258 return regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, 259 AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 260 FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 261 (ilog2(mode) - 1))); 262 } 263 264 static int ad4080_read_raw(struct iio_dev *indio_dev, 265 struct iio_chan_spec const *chan, 266 int *val, int *val2, long m) 267 { 268 struct ad4080_state *st = iio_priv(indio_dev); 269 int dec_rate; 270 271 switch (m) { 272 case IIO_CHAN_INFO_SCALE: 273 return ad4080_get_scale(st, val, val2); 274 case IIO_CHAN_INFO_SAMP_FREQ: 275 dec_rate = ad4080_get_dec_rate(indio_dev, chan); 276 if (dec_rate < 0) 277 return dec_rate; 278 if (st->filter_type[chan->channel] == SINC_5_COMP) 279 dec_rate *= 2; 280 if (st->filter_type[chan->channel]) 281 *val = DIV_ROUND_CLOSEST(st->clk_rate, dec_rate); 282 else 283 *val = st->clk_rate; 284 return IIO_VAL_INT; 285 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 286 if (st->filter_type[chan->channel] == FILTER_NONE) { 287 *val = 1; 288 } else { 289 *val = ad4080_get_dec_rate(indio_dev, chan); 290 if (*val < 0) 291 return *val; 292 } 293 return IIO_VAL_INT; 294 default: 295 return -EINVAL; 296 } 297 } 298 299 static int ad4080_write_raw(struct iio_dev *indio_dev, 300 struct iio_chan_spec const *chan, 301 int val, int val2, long mask) 302 { 303 struct ad4080_state *st = iio_priv(indio_dev); 304 305 switch (mask) { 306 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 307 if (st->filter_type[chan->channel] == FILTER_NONE && val > 1) 308 return -EINVAL; 309 310 return ad4080_set_dec_rate(indio_dev, chan, val); 311 default: 312 return -EINVAL; 313 } 314 } 315 316 static int ad4080_lvds_sync_write(struct ad4080_state *st, unsigned int ch) 317 { 318 struct device *dev = regmap_get_device(st->regmap[ch]); 319 int ret; 320 321 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, 322 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 323 if (ret) 324 return ret; 325 326 ret = iio_backend_interface_data_align(st->back[ch], 10000); 327 if (ret) 328 return dev_err_probe(dev, ret, 329 "Data alignment process failed\n"); 330 331 dev_dbg(dev, "Success: Pattern correct and Locked!\n"); 332 return regmap_clear_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, 333 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 334 } 335 336 static int ad4080_get_filter_type(struct iio_dev *dev, 337 const struct iio_chan_spec *chan) 338 { 339 struct ad4080_state *st = iio_priv(dev); 340 unsigned int data; 341 unsigned int ch = chan->channel; 342 int ret; 343 344 ret = regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); 345 if (ret) 346 return ret; 347 348 return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data); 349 } 350 351 static int ad4080_set_filter_type(struct iio_dev *dev, 352 const struct iio_chan_spec *chan, 353 unsigned int mode) 354 { 355 struct ad4080_state *st = iio_priv(dev); 356 unsigned int ch = chan->channel; 357 int dec_rate; 358 int ret; 359 360 guard(mutex)(&st->lock); 361 362 dec_rate = ad4080_get_dec_rate(dev, chan); 363 if (dec_rate < 0) 364 return dec_rate; 365 366 if (mode >= SINC_5 && dec_rate >= 512) 367 return -EINVAL; 368 369 ret = iio_backend_filter_type_set(st->back[ch], mode); 370 if (ret) 371 return ret; 372 373 ret = regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, 374 AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 375 FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 376 mode)); 377 if (ret) 378 return ret; 379 380 st->filter_type[ch] = mode; 381 382 return 0; 383 } 384 385 static int ad4080_read_avail(struct iio_dev *indio_dev, 386 struct iio_chan_spec const *chan, 387 const int **vals, int *type, int *length, 388 long mask) 389 { 390 struct ad4080_state *st = iio_priv(indio_dev); 391 392 switch (mask) { 393 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 394 switch (st->filter_type[chan->channel]) { 395 case FILTER_NONE: 396 *vals = ad4080_dec_rate_none; 397 *length = ARRAY_SIZE(ad4080_dec_rate_none); 398 break; 399 default: 400 *vals = ad4080_dec_rate_avail; 401 *length = st->filter_type[chan->channel] >= SINC_5 ? 402 (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) : 403 ARRAY_SIZE(ad4080_dec_rate_avail); 404 break; 405 } 406 *type = IIO_VAL_INT; 407 return IIO_AVAIL_LIST; 408 default: 409 return -EINVAL; 410 } 411 } 412 413 static int ad4880_update_scan_mode(struct iio_dev *indio_dev, 414 const unsigned long *scan_mask) 415 { 416 struct ad4080_state *st = iio_priv(indio_dev); 417 int ret; 418 419 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) { 420 /* 421 * Each backend has a single channel (channel 0 from the 422 * backend's perspective), so always use channel index 0. 423 */ 424 if (test_bit(ch, scan_mask)) 425 ret = iio_backend_chan_enable(st->back[ch], 0); 426 else 427 ret = iio_backend_chan_disable(st->back[ch], 0); 428 if (ret) 429 return ret; 430 } 431 432 return 0; 433 } 434 435 static const struct iio_info ad4080_iio_info = { 436 .debugfs_reg_access = ad4080_reg_access, 437 .read_raw = ad4080_read_raw, 438 .write_raw = ad4080_write_raw, 439 .read_avail = ad4080_read_avail, 440 }; 441 442 /* 443 * AD4880 needs update_scan_mode to enable/disable individual backend channels. 444 * Single-channel devices don't need this as their backends may not implement 445 * chan_enable/chan_disable operations. 446 */ 447 static const struct iio_info ad4880_iio_info = { 448 .debugfs_reg_access = ad4080_reg_access, 449 .read_raw = ad4080_read_raw, 450 .write_raw = ad4080_write_raw, 451 .read_avail = ad4080_read_avail, 452 .update_scan_mode = ad4880_update_scan_mode, 453 }; 454 455 static const struct iio_enum ad4080_filter_type_enum = { 456 .items = ad4080_filter_type_iio_enum, 457 .num_items = ARRAY_SIZE(ad4080_filter_type_iio_enum), 458 .set = ad4080_set_filter_type, 459 .get = ad4080_get_filter_type, 460 }; 461 462 static struct iio_chan_spec_ext_info ad4080_ext_info[] = { 463 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum), 464 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, 465 &ad4080_filter_type_enum), 466 { } 467 }; 468 469 /* 470 * AD4880 needs per-channel filter configuration since each channel has 471 * its own independent ADC with separate SPI interface. 472 */ 473 static struct iio_chan_spec_ext_info ad4880_ext_info[] = { 474 IIO_ENUM("filter_type", IIO_SEPARATE, &ad4080_filter_type_enum), 475 IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, 476 &ad4080_filter_type_enum), 477 { } 478 }; 479 480 #define AD4080_CHANNEL_DEFINE(bits, storage, idx) { \ 481 .type = IIO_VOLTAGE, \ 482 .indexed = 1, \ 483 .channel = (idx), \ 484 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \ 485 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 486 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 487 .info_mask_shared_by_all_available = \ 488 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 489 .ext_info = ad4080_ext_info, \ 490 .scan_index = (idx), \ 491 .scan_type = { \ 492 .sign = 's', \ 493 .realbits = (bits), \ 494 .storagebits = (storage), \ 495 }, \ 496 } 497 498 /* 499 * AD4880 has per-channel attributes (filter_type, oversampling_ratio, 500 * sampling_frequency) since each channel has its own independent ADC 501 * with separate SPI configuration interface. 502 */ 503 #define AD4880_CHANNEL_DEFINE(bits, storage, idx) { \ 504 .type = IIO_VOLTAGE, \ 505 .indexed = 1, \ 506 .channel = (idx), \ 507 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \ 508 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 509 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 510 .info_mask_separate_available = \ 511 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 512 .ext_info = ad4880_ext_info, \ 513 .scan_index = (idx), \ 514 .scan_type = { \ 515 .sign = 's', \ 516 .realbits = (bits), \ 517 .storagebits = (storage), \ 518 }, \ 519 } 520 521 static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32, 0); 522 523 static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32, 0); 524 525 static const struct iio_chan_spec ad4082_channel = AD4080_CHANNEL_DEFINE(20, 32, 0); 526 527 static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16, 0); 528 529 static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16, 0); 530 531 static const struct iio_chan_spec ad4085_channel = AD4080_CHANNEL_DEFINE(16, 16, 0); 532 533 static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16, 0); 534 535 static const struct iio_chan_spec ad4087_channel = AD4080_CHANNEL_DEFINE(14, 16, 0); 536 537 static const struct iio_chan_spec ad4088_channel = AD4080_CHANNEL_DEFINE(14, 16, 0); 538 539 static const struct iio_chan_spec ad4880_channels[] = { 540 AD4880_CHANNEL_DEFINE(20, 32, 0), 541 AD4880_CHANNEL_DEFINE(20, 32, 1), 542 }; 543 544 static const struct iio_chan_spec ad4884_channels[] = { 545 AD4880_CHANNEL_DEFINE(16, 16, 0), 546 AD4880_CHANNEL_DEFINE(16, 16, 1), 547 }; 548 549 static const struct ad4080_chip_info ad4080_chip_info = { 550 .name = "ad4080", 551 .product_id = AD4080_CHIP_ID, 552 .scale_table = ad4080_scale_table, 553 .num_scales = ARRAY_SIZE(ad4080_scale_table), 554 .num_channels = 1, 555 .channels = &ad4080_channel, 556 .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX, 557 }; 558 559 static const struct ad4080_chip_info ad4081_chip_info = { 560 .name = "ad4081", 561 .product_id = AD4081_CHIP_ID, 562 .scale_table = ad4080_scale_table, 563 .num_scales = ARRAY_SIZE(ad4080_scale_table), 564 .num_channels = 1, 565 .channels = &ad4081_channel, 566 .lvds_cnv_clk_cnt_max = 2, 567 }; 568 569 static const struct ad4080_chip_info ad4082_chip_info = { 570 .name = "ad4082", 571 .product_id = AD4082_CHIP_ID, 572 .scale_table = ad4080_scale_table, 573 .num_scales = ARRAY_SIZE(ad4080_scale_table), 574 .num_channels = 1, 575 .channels = &ad4082_channel, 576 .lvds_cnv_clk_cnt_max = 8, 577 }; 578 579 static const struct ad4080_chip_info ad4083_chip_info = { 580 .name = "ad4083", 581 .product_id = AD4083_CHIP_ID, 582 .scale_table = ad4080_scale_table, 583 .num_scales = ARRAY_SIZE(ad4080_scale_table), 584 .num_channels = 1, 585 .channels = &ad4083_channel, 586 .lvds_cnv_clk_cnt_max = 5, 587 }; 588 589 static const struct ad4080_chip_info ad4084_chip_info = { 590 .name = "ad4084", 591 .product_id = AD4084_CHIP_ID, 592 .scale_table = ad4080_scale_table, 593 .num_scales = ARRAY_SIZE(ad4080_scale_table), 594 .num_channels = 1, 595 .channels = &ad4084_channel, 596 .lvds_cnv_clk_cnt_max = 2, 597 }; 598 599 static const struct ad4080_chip_info ad4085_chip_info = { 600 .name = "ad4085", 601 .product_id = AD4085_CHIP_ID, 602 .scale_table = ad4080_scale_table, 603 .num_scales = ARRAY_SIZE(ad4080_scale_table), 604 .num_channels = 1, 605 .channels = &ad4085_channel, 606 .lvds_cnv_clk_cnt_max = 8, 607 }; 608 609 static const struct ad4080_chip_info ad4086_chip_info = { 610 .name = "ad4086", 611 .product_id = AD4086_CHIP_ID, 612 .scale_table = ad4080_scale_table, 613 .num_scales = ARRAY_SIZE(ad4080_scale_table), 614 .num_channels = 1, 615 .channels = &ad4086_channel, 616 .lvds_cnv_clk_cnt_max = 4, 617 }; 618 619 static const struct ad4080_chip_info ad4087_chip_info = { 620 .name = "ad4087", 621 .product_id = AD4087_CHIP_ID, 622 .scale_table = ad4080_scale_table, 623 .num_scales = ARRAY_SIZE(ad4080_scale_table), 624 .num_channels = 1, 625 .channels = &ad4087_channel, 626 .lvds_cnv_clk_cnt_max = 1, 627 }; 628 629 static const struct ad4080_chip_info ad4088_chip_info = { 630 .name = "ad4088", 631 .product_id = AD4088_CHIP_ID, 632 .scale_table = ad4080_scale_table, 633 .num_scales = ARRAY_SIZE(ad4080_scale_table), 634 .num_channels = 1, 635 .channels = &ad4088_channel, 636 .lvds_cnv_clk_cnt_max = 8, 637 }; 638 639 static const struct ad4080_chip_info ad4880_chip_info = { 640 .name = "ad4880", 641 .product_id = AD4880_CHIP_ID, 642 .scale_table = ad4080_scale_table, 643 .num_scales = ARRAY_SIZE(ad4080_scale_table), 644 .num_channels = 2, 645 .channels = ad4880_channels, 646 .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX, 647 }; 648 649 static const struct ad4080_chip_info ad4884_chip_info = { 650 .name = "ad4884", 651 .product_id = AD4884_CHIP_ID, 652 .scale_table = ad4080_scale_table, 653 .num_scales = ARRAY_SIZE(ad4080_scale_table), 654 .num_channels = 2, 655 .channels = ad4884_channels, 656 .lvds_cnv_clk_cnt_max = 2, 657 }; 658 659 static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch) 660 { 661 struct device *dev = regmap_get_device(st->regmap[ch]); 662 __le16 id_le; 663 u16 id; 664 int ret; 665 666 ret = regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, 667 AD4080_INTERFACE_CONFIG_A_SW_RESET); 668 if (ret) 669 return ret; 670 671 ret = regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, 672 AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); 673 if (ret) 674 return ret; 675 676 ret = regmap_bulk_read(st->regmap[ch], AD4080_REG_PRODUCT_ID_L, &id_le, 677 sizeof(id_le)); 678 if (ret) 679 return ret; 680 681 id = le16_to_cpu(id_le); 682 if (id != st->info->product_id) 683 dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); 684 685 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_GPIO_CONFIG_A, 686 AD4080_GPIO_CONFIG_A_GPO_1_EN); 687 if (ret) 688 return ret; 689 690 ret = regmap_write(st->regmap[ch], AD4080_REG_GPIO_CONFIG_B, 691 FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, 692 AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY)); 693 if (ret) 694 return ret; 695 696 ret = iio_backend_num_lanes_set(st->back[ch], st->num_lanes); 697 if (ret) 698 return ret; 699 700 if (!st->lvds_cnv_en) 701 return 0; 702 703 /* Set maximum LVDS Data Transfer Latency */ 704 ret = regmap_update_bits(st->regmap[ch], 705 AD4080_REG_ADC_DATA_INTF_CONFIG_B, 706 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 707 FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 708 st->info->lvds_cnv_clk_cnt_max)); 709 if (ret) 710 return ret; 711 712 if (st->num_lanes > 1) { 713 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, 714 AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); 715 if (ret) 716 return ret; 717 } 718 719 ret = regmap_set_bits(st->regmap[ch], 720 AD4080_REG_ADC_DATA_INTF_CONFIG_B, 721 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); 722 if (ret) 723 return ret; 724 725 return ad4080_lvds_sync_write(st, ch); 726 } 727 728 static int ad4080_setup(struct iio_dev *indio_dev) 729 { 730 struct ad4080_state *st = iio_priv(indio_dev); 731 int ret; 732 733 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) { 734 ret = ad4080_setup_channel(st, ch); 735 if (ret) 736 return ret; 737 } 738 739 return 0; 740 } 741 742 static int ad4080_properties_parse(struct ad4080_state *st, 743 struct device *dev) 744 { 745 746 st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable"); 747 748 st->num_lanes = 1; 749 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); 750 if (!st->num_lanes || st->num_lanes > 2) 751 return dev_err_probe(dev, -EINVAL, 752 "Invalid 'adi,num-lanes' value: %u", 753 st->num_lanes); 754 755 return 0; 756 } 757 758 static int ad4080_probe(struct spi_device *spi) 759 { 760 struct iio_dev *indio_dev; 761 struct device *dev = &spi->dev; 762 struct ad4080_state *st; 763 struct clk *clk; 764 int ret; 765 766 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 767 if (!indio_dev) 768 return -ENOMEM; 769 770 st = iio_priv(indio_dev); 771 772 ret = devm_regulator_bulk_get_enable(dev, 773 ARRAY_SIZE(ad4080_power_supplies), 774 ad4080_power_supplies); 775 if (ret) 776 return dev_err_probe(dev, ret, 777 "failed to get and enable supplies\n"); 778 779 /* Setup primary SPI device (channel 0) */ 780 st->spi[0] = spi; 781 st->regmap[0] = devm_regmap_init_spi(spi, &ad4080_regmap_config); 782 if (IS_ERR(st->regmap[0])) 783 return PTR_ERR(st->regmap[0]); 784 785 st->info = spi_get_device_match_data(spi); 786 if (!st->info) 787 return -ENODEV; 788 789 /* Setup ancillary SPI devices for additional channels */ 790 for (unsigned int ch = 1; ch < st->info->num_channels; ch++) { 791 st->spi[ch] = devm_spi_new_ancillary_device(spi, spi_get_chipselect(spi, ch)); 792 if (IS_ERR(st->spi[ch])) 793 return dev_err_probe(dev, PTR_ERR(st->spi[ch]), 794 "failed to register ancillary device\n"); 795 796 st->regmap[ch] = devm_regmap_init_spi(st->spi[ch], &ad4080_regmap_config); 797 if (IS_ERR(st->regmap[ch])) 798 return PTR_ERR(st->regmap[ch]); 799 } 800 801 ret = devm_mutex_init(dev, &st->lock); 802 if (ret) 803 return ret; 804 805 indio_dev->name = st->info->name; 806 indio_dev->channels = st->info->channels; 807 indio_dev->num_channels = st->info->num_channels; 808 indio_dev->info = st->info->num_channels > 1 ? 809 &ad4880_iio_info : &ad4080_iio_info; 810 811 ret = ad4080_properties_parse(st, dev); 812 if (ret) 813 return ret; 814 815 clk = devm_clk_get_enabled(&spi->dev, "cnv"); 816 if (IS_ERR(clk)) 817 return PTR_ERR(clk); 818 819 st->clk_rate = clk_get_rate(clk); 820 821 /* Get backends for all channels */ 822 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) { 823 st->back[ch] = devm_iio_backend_get_by_index(dev, ch); 824 if (IS_ERR(st->back[ch])) 825 return PTR_ERR(st->back[ch]); 826 827 ret = devm_iio_backend_enable(dev, st->back[ch]); 828 if (ret) 829 return ret; 830 } 831 832 /* 833 * Request buffer from the first backend only. For multi-channel 834 * devices (e.g., AD4880), the FPGA uses two axi_ad408x IP instances 835 * (one per ADC channel) whose outputs are combined by a packer block 836 * that interleaves all channel data into a single DMA stream routed 837 * through the first backend's clock domain. 838 */ 839 ret = devm_iio_backend_request_buffer(dev, st->back[0], indio_dev); 840 if (ret) 841 return ret; 842 843 ret = ad4080_setup(indio_dev); 844 if (ret) 845 return ret; 846 847 return devm_iio_device_register(&spi->dev, indio_dev); 848 } 849 850 static const struct spi_device_id ad4080_id[] = { 851 { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, 852 { "ad4081", (kernel_ulong_t)&ad4081_chip_info }, 853 { "ad4082", (kernel_ulong_t)&ad4082_chip_info }, 854 { "ad4083", (kernel_ulong_t)&ad4083_chip_info }, 855 { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, 856 { "ad4085", (kernel_ulong_t)&ad4085_chip_info }, 857 { "ad4086", (kernel_ulong_t)&ad4086_chip_info }, 858 { "ad4087", (kernel_ulong_t)&ad4087_chip_info }, 859 { "ad4088", (kernel_ulong_t)&ad4088_chip_info }, 860 { "ad4880", (kernel_ulong_t)&ad4880_chip_info }, 861 { "ad4884", (kernel_ulong_t)&ad4884_chip_info }, 862 { } 863 }; 864 MODULE_DEVICE_TABLE(spi, ad4080_id); 865 866 static const struct of_device_id ad4080_of_match[] = { 867 { .compatible = "adi,ad4080", &ad4080_chip_info }, 868 { .compatible = "adi,ad4081", &ad4081_chip_info }, 869 { .compatible = "adi,ad4082", &ad4082_chip_info }, 870 { .compatible = "adi,ad4083", &ad4083_chip_info }, 871 { .compatible = "adi,ad4084", &ad4084_chip_info }, 872 { .compatible = "adi,ad4085", &ad4085_chip_info }, 873 { .compatible = "adi,ad4086", &ad4086_chip_info }, 874 { .compatible = "adi,ad4087", &ad4087_chip_info }, 875 { .compatible = "adi,ad4088", &ad4088_chip_info }, 876 { .compatible = "adi,ad4880", &ad4880_chip_info }, 877 { .compatible = "adi,ad4884", &ad4884_chip_info }, 878 { } 879 }; 880 MODULE_DEVICE_TABLE(of, ad4080_of_match); 881 882 static struct spi_driver ad4080_driver = { 883 .driver = { 884 .name = "ad4080", 885 .of_match_table = ad4080_of_match, 886 }, 887 .probe = ad4080_probe, 888 .id_table = ad4080_id, 889 }; 890 module_spi_driver(ad4080_driver); 891 892 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 893 MODULE_DESCRIPTION("Analog Devices AD4080"); 894 MODULE_LICENSE("GPL"); 895 MODULE_IMPORT_NS("IIO_BACKEND"); 896