1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD4080 SPI ADC driver 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/iio/backend.h> 15 #include <linux/iio/iio.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/spi/spi.h> 22 #include <linux/types.h> 23 #include <linux/unaligned.h> 24 #include <linux/units.h> 25 26 /* Register Definition */ 27 #define AD4080_REG_INTERFACE_CONFIG_A 0x00 28 #define AD4080_REG_INTERFACE_CONFIG_B 0x01 29 #define AD4080_REG_DEVICE_CONFIG 0x02 30 #define AD4080_REG_CHIP_TYPE 0x03 31 #define AD4080_REG_PRODUCT_ID_L 0x04 32 #define AD4080_REG_PRODUCT_ID_H 0x05 33 #define AD4080_REG_CHIP_GRADE 0x06 34 #define AD4080_REG_SCRATCH_PAD 0x0A 35 #define AD4080_REG_SPI_REVISION 0x0B 36 #define AD4080_REG_VENDOR_L 0x0C 37 #define AD4080_REG_VENDOR_H 0x0D 38 #define AD4080_REG_STREAM_MODE 0x0E 39 #define AD4080_REG_TRANSFER_CONFIG 0x0F 40 #define AD4080_REG_INTERFACE_CONFIG_C 0x10 41 #define AD4080_REG_INTERFACE_STATUS_A 0x11 42 #define AD4080_REG_DEVICE_STATUS 0x14 43 #define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15 44 #define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16 45 #define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17 46 #define AD4080_REG_PWR_CTRL 0x18 47 #define AD4080_REG_GPIO_CONFIG_A 0x19 48 #define AD4080_REG_GPIO_CONFIG_B 0x1A 49 #define AD4080_REG_GPIO_CONFIG_C 0x1B 50 #define AD4080_REG_GENERAL_CONFIG 0x1C 51 #define AD4080_REG_FIFO_WATERMARK_LSB 0x1D 52 #define AD4080_REG_FIFO_WATERMARK_MSB 0x1E 53 #define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F 54 #define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20 55 #define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21 56 #define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22 57 #define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23 58 #define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24 59 #define AD4080_REG_OFFSET_LSB 0x25 60 #define AD4080_REG_OFFSET_MSB 0x26 61 #define AD4080_REG_GAIN_LSB 0x27 62 #define AD4080_REG_GAIN_MSB 0x28 63 #define AD4080_REG_FILTER_CONFIG 0x29 64 65 /* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */ 66 #define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) 67 #define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5) 68 #define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) 69 70 /* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */ 71 #define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7) 72 #define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3) 73 74 /* AD4080_REG_DEVICE_CONFIG Bit Definition */ 75 #define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0) 76 77 /* AD4080_REG_TRANSFER_CONFIG Bit Definition */ 78 #define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2) 79 80 /* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */ 81 #define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5) 82 83 /* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */ 84 #define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6) 85 #define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4) 86 #define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2) 87 #define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0) 88 89 /* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */ 90 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4) 91 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3) 92 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0) 93 94 /* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */ 95 #define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4) 96 97 /* AD4080_REG_PWR_CTRL Bit Definition */ 98 #define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1) 99 #define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0) 100 101 /* AD4080_REG_GPIO_CONFIG_A Bit Definition */ 102 #define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1) 103 #define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0) 104 105 /* AD4080_REG_GPIO_CONFIG_B Bit Definition */ 106 #define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4) 107 #define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0) 108 #define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO 0 109 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL 1 110 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE 2 111 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY 3 112 #define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH 4 113 #define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH 5 114 #define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT 6 115 #define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA 7 116 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC 8 117 #define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT 9 118 119 /* AD4080_REG_FIFO_CONFIG Bit Definition */ 120 #define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0) 121 122 /* AD4080_REG_FILTER_CONFIG Bit Definition */ 123 #define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3) 124 #define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0) 125 126 /* Miscellaneous Definitions */ 127 #define AD4080_SPI_READ BIT(7) 128 #define AD4080_CHIP_ID GENMASK(2, 0) 129 130 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 131 132 #define AD4080_MAX_SAMP_FREQ 40000000 133 #define AD4080_MIN_SAMP_FREQ 1250000 134 135 enum ad4080_filter_type { 136 FILTER_NONE, 137 SINC_1, 138 SINC_5, 139 SINC_5_COMP 140 }; 141 142 static const unsigned int ad4080_scale_table[][2] = { 143 { 6000, 0 }, 144 }; 145 146 static const char *const ad4080_filter_type_iio_enum[] = { 147 [FILTER_NONE] = "none", 148 [SINC_1] = "sinc1", 149 [SINC_5] = "sinc5", 150 [SINC_5_COMP] = "sinc5+pf1", 151 }; 152 153 static const int ad4080_dec_rate_avail[] = { 154 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 155 }; 156 157 static const int ad4080_dec_rate_none[] = { 1 }; 158 159 static const char * const ad4080_power_supplies[] = { 160 "vdd33", "vdd11", "vddldo", "iovdd", "vrefin", 161 }; 162 163 struct ad4080_chip_info { 164 const char *name; 165 unsigned int product_id; 166 int num_scales; 167 const unsigned int (*scale_table)[2]; 168 const struct iio_chan_spec *channels; 169 unsigned int num_channels; 170 }; 171 172 struct ad4080_state { 173 struct regmap *regmap; 174 struct iio_backend *back; 175 const struct ad4080_chip_info *info; 176 /* 177 * Synchronize access to members the of driver state, and ensure 178 * atomicity of consecutive regmap operations. 179 */ 180 struct mutex lock; 181 unsigned int num_lanes; 182 unsigned int dec_rate; 183 unsigned long clk_rate; 184 enum ad4080_filter_type filter_type; 185 bool lvds_cnv_en; 186 }; 187 188 static const struct regmap_config ad4080_regmap_config = { 189 .reg_bits = 16, 190 .val_bits = 8, 191 .read_flag_mask = BIT(7), 192 .max_register = 0x29, 193 }; 194 195 static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg, 196 unsigned int writeval, unsigned int *readval) 197 { 198 struct ad4080_state *st = iio_priv(indio_dev); 199 200 if (readval) 201 return regmap_read(st->regmap, reg, readval); 202 203 return regmap_write(st->regmap, reg, writeval); 204 } 205 206 static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) 207 { 208 unsigned int tmp; 209 210 tmp = (st->info->scale_table[0][0] * 1000000ULL) >> 211 st->info->channels[0].scan_type.realbits; 212 *val = tmp / 1000000; 213 *val2 = tmp % 1000000; 214 215 return IIO_VAL_INT_PLUS_NANO; 216 } 217 218 static unsigned int ad4080_get_dec_rate(struct iio_dev *dev, 219 const struct iio_chan_spec *chan) 220 { 221 struct ad4080_state *st = iio_priv(dev); 222 int ret; 223 unsigned int data; 224 225 ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); 226 if (ret) 227 return ret; 228 229 return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1); 230 } 231 232 static int ad4080_set_dec_rate(struct iio_dev *dev, 233 const struct iio_chan_spec *chan, 234 unsigned int mode) 235 { 236 struct ad4080_state *st = iio_priv(dev); 237 238 guard(mutex)(&st->lock); 239 240 if ((st->filter_type >= SINC_5 && mode >= 512) || mode < 2) 241 return -EINVAL; 242 243 return regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, 244 AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 245 FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, 246 (ilog2(mode) - 1))); 247 } 248 249 static int ad4080_read_raw(struct iio_dev *indio_dev, 250 struct iio_chan_spec const *chan, 251 int *val, int *val2, long m) 252 { 253 struct ad4080_state *st = iio_priv(indio_dev); 254 int dec_rate; 255 256 switch (m) { 257 case IIO_CHAN_INFO_SCALE: 258 return ad4080_get_scale(st, val, val2); 259 case IIO_CHAN_INFO_SAMP_FREQ: 260 dec_rate = ad4080_get_dec_rate(indio_dev, chan); 261 if (dec_rate < 0) 262 return dec_rate; 263 if (st->filter_type == SINC_5_COMP) 264 dec_rate *= 2; 265 if (st->filter_type) 266 *val = DIV_ROUND_CLOSEST(st->clk_rate, dec_rate); 267 else 268 *val = st->clk_rate; 269 return IIO_VAL_INT; 270 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 271 if (st->filter_type == FILTER_NONE) { 272 *val = 1; 273 } else { 274 *val = ad4080_get_dec_rate(indio_dev, chan); 275 if (*val < 0) 276 return *val; 277 } 278 return IIO_VAL_INT; 279 default: 280 return -EINVAL; 281 } 282 } 283 284 static int ad4080_write_raw(struct iio_dev *indio_dev, 285 struct iio_chan_spec const *chan, 286 int val, int val2, long mask) 287 { 288 struct ad4080_state *st = iio_priv(indio_dev); 289 290 switch (mask) { 291 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 292 if (st->filter_type == FILTER_NONE && val > 1) 293 return -EINVAL; 294 295 return ad4080_set_dec_rate(indio_dev, chan, val); 296 default: 297 return -EINVAL; 298 } 299 } 300 301 static int ad4080_lvds_sync_write(struct ad4080_state *st) 302 { 303 struct device *dev = regmap_get_device(st->regmap); 304 int ret; 305 306 ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, 307 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 308 if (ret) 309 return ret; 310 311 ret = iio_backend_interface_data_align(st->back, 10000); 312 if (ret) 313 return dev_err_probe(dev, ret, 314 "Data alignment process failed\n"); 315 316 dev_dbg(dev, "Success: Pattern correct and Locked!\n"); 317 return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, 318 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); 319 } 320 321 static int ad4080_get_filter_type(struct iio_dev *dev, 322 const struct iio_chan_spec *chan) 323 { 324 struct ad4080_state *st = iio_priv(dev); 325 unsigned int data; 326 int ret; 327 328 ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); 329 if (ret) 330 return ret; 331 332 return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data); 333 } 334 335 static int ad4080_set_filter_type(struct iio_dev *dev, 336 const struct iio_chan_spec *chan, 337 unsigned int mode) 338 { 339 struct ad4080_state *st = iio_priv(dev); 340 int dec_rate; 341 int ret; 342 343 guard(mutex)(&st->lock); 344 345 dec_rate = ad4080_get_dec_rate(dev, chan); 346 if (dec_rate < 0) 347 return dec_rate; 348 349 if (mode >= SINC_5 && dec_rate >= 512) 350 return -EINVAL; 351 352 ret = iio_backend_filter_type_set(st->back, mode); 353 if (ret) 354 return ret; 355 356 ret = regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, 357 AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 358 FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, 359 mode)); 360 if (ret) 361 return ret; 362 363 st->filter_type = mode; 364 365 return 0; 366 } 367 368 static int ad4080_read_avail(struct iio_dev *indio_dev, 369 struct iio_chan_spec const *chan, 370 const int **vals, int *type, int *length, 371 long mask) 372 { 373 struct ad4080_state *st = iio_priv(indio_dev); 374 375 switch (mask) { 376 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 377 switch (st->filter_type) { 378 case FILTER_NONE: 379 *vals = ad4080_dec_rate_none; 380 *length = ARRAY_SIZE(ad4080_dec_rate_none); 381 break; 382 default: 383 *vals = ad4080_dec_rate_avail; 384 *length = st->filter_type >= SINC_5 ? 385 (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) : 386 ARRAY_SIZE(ad4080_dec_rate_avail); 387 break; 388 } 389 *type = IIO_VAL_INT; 390 return IIO_AVAIL_LIST; 391 default: 392 return -EINVAL; 393 } 394 } 395 396 static const struct iio_info ad4080_iio_info = { 397 .debugfs_reg_access = ad4080_reg_access, 398 .read_raw = ad4080_read_raw, 399 .write_raw = ad4080_write_raw, 400 .read_avail = ad4080_read_avail, 401 }; 402 403 static const struct iio_enum ad4080_filter_type_enum = { 404 .items = ad4080_filter_type_iio_enum, 405 .num_items = ARRAY_SIZE(ad4080_filter_type_iio_enum), 406 .set = ad4080_set_filter_type, 407 .get = ad4080_get_filter_type, 408 }; 409 410 static struct iio_chan_spec_ext_info ad4080_ext_info[] = { 411 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum), 412 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, 413 &ad4080_filter_type_enum), 414 { } 415 }; 416 417 static const struct iio_chan_spec ad4080_channel = { 418 .type = IIO_VOLTAGE, 419 .indexed = 1, 420 .channel = 0, 421 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), 422 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | 423 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 424 .info_mask_shared_by_all_available = 425 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 426 .ext_info = ad4080_ext_info, 427 .scan_index = 0, 428 .scan_type = { 429 .sign = 's', 430 .realbits = 20, 431 .storagebits = 32, 432 }, 433 }; 434 435 static const struct ad4080_chip_info ad4080_chip_info = { 436 .name = "ad4080", 437 .product_id = AD4080_CHIP_ID, 438 .scale_table = ad4080_scale_table, 439 .num_scales = ARRAY_SIZE(ad4080_scale_table), 440 .num_channels = 1, 441 .channels = &ad4080_channel, 442 }; 443 444 static int ad4080_setup(struct iio_dev *indio_dev) 445 { 446 struct ad4080_state *st = iio_priv(indio_dev); 447 struct device *dev = regmap_get_device(st->regmap); 448 unsigned int id; 449 int ret; 450 451 ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, 452 AD4080_INTERFACE_CONFIG_A_SW_RESET); 453 if (ret) 454 return ret; 455 456 ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, 457 AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); 458 if (ret) 459 return ret; 460 461 ret = regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id); 462 if (ret) 463 return ret; 464 465 if (id != AD4080_CHIP_ID) 466 dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); 467 468 ret = regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, 469 AD4080_GPIO_CONFIG_A_GPO_1_EN); 470 if (ret) 471 return ret; 472 473 ret = regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B, 474 FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, 475 AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY)); 476 if (ret) 477 return ret; 478 479 ret = iio_backend_num_lanes_set(st->back, st->num_lanes); 480 if (ret) 481 return ret; 482 483 if (!st->lvds_cnv_en) 484 return 0; 485 486 /* Set maximum LVDS Data Transfer Latency */ 487 ret = regmap_update_bits(st->regmap, 488 AD4080_REG_ADC_DATA_INTF_CONFIG_B, 489 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 490 FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, 491 AD4080_LVDS_CNV_CLK_CNT_MAX)); 492 if (ret) 493 return ret; 494 495 if (st->num_lanes > 1) { 496 ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, 497 AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); 498 if (ret) 499 return ret; 500 } 501 502 ret = regmap_set_bits(st->regmap, 503 AD4080_REG_ADC_DATA_INTF_CONFIG_B, 504 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); 505 if (ret) 506 return ret; 507 508 return ad4080_lvds_sync_write(st); 509 } 510 511 static int ad4080_properties_parse(struct ad4080_state *st) 512 { 513 struct device *dev = regmap_get_device(st->regmap); 514 515 st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable"); 516 517 st->num_lanes = 1; 518 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); 519 if (!st->num_lanes || st->num_lanes > 2) 520 return dev_err_probe(dev, -EINVAL, 521 "Invalid 'adi,num-lanes' value: %u", 522 st->num_lanes); 523 524 return 0; 525 } 526 527 static int ad4080_probe(struct spi_device *spi) 528 { 529 struct iio_dev *indio_dev; 530 struct device *dev = &spi->dev; 531 struct ad4080_state *st; 532 struct clk *clk; 533 int ret; 534 535 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 536 if (!indio_dev) 537 return -ENOMEM; 538 539 st = iio_priv(indio_dev); 540 541 ret = devm_regulator_bulk_get_enable(dev, 542 ARRAY_SIZE(ad4080_power_supplies), 543 ad4080_power_supplies); 544 if (ret) 545 return dev_err_probe(dev, ret, 546 "failed to get and enable supplies\n"); 547 548 st->regmap = devm_regmap_init_spi(spi, &ad4080_regmap_config); 549 if (IS_ERR(st->regmap)) 550 return PTR_ERR(st->regmap); 551 552 st->info = spi_get_device_match_data(spi); 553 if (!st->info) 554 return -ENODEV; 555 556 ret = devm_mutex_init(dev, &st->lock); 557 if (ret) 558 return ret; 559 560 indio_dev->name = st->info->name; 561 indio_dev->channels = st->info->channels; 562 indio_dev->num_channels = st->info->num_channels; 563 indio_dev->info = &ad4080_iio_info; 564 565 ret = ad4080_properties_parse(st); 566 if (ret) 567 return ret; 568 569 clk = devm_clk_get_enabled(&spi->dev, "cnv"); 570 if (IS_ERR(clk)) 571 return PTR_ERR(clk); 572 573 st->clk_rate = clk_get_rate(clk); 574 575 st->back = devm_iio_backend_get(dev, NULL); 576 if (IS_ERR(st->back)) 577 return PTR_ERR(st->back); 578 579 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 580 if (ret) 581 return ret; 582 583 ret = devm_iio_backend_enable(dev, st->back); 584 if (ret) 585 return ret; 586 587 ret = ad4080_setup(indio_dev); 588 if (ret) 589 return ret; 590 591 return devm_iio_device_register(&spi->dev, indio_dev); 592 } 593 594 static const struct spi_device_id ad4080_id[] = { 595 { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, 596 { } 597 }; 598 MODULE_DEVICE_TABLE(spi, ad4080_id); 599 600 static const struct of_device_id ad4080_of_match[] = { 601 { .compatible = "adi,ad4080", &ad4080_chip_info }, 602 { } 603 }; 604 MODULE_DEVICE_TABLE(of, ad4080_of_match); 605 606 static struct spi_driver ad4080_driver = { 607 .driver = { 608 .name = "ad4080", 609 .of_match_table = ad4080_of_match, 610 }, 611 .probe = ad4080_probe, 612 .id_table = ad4080_id, 613 }; 614 module_spi_driver(ad4080_driver); 615 616 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 617 MODULE_DESCRIPTION("Analog Devices AD4080"); 618 MODULE_LICENSE("GPL"); 619 MODULE_IMPORT_NS("IIO_BACKEND"); 620