1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD4062 I3C ADC driver 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/devm-helpers.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i3c/device.h> 16 #include <linux/i3c/master.h> 17 #include <linux/iio/buffer.h> 18 #include <linux/iio/events.h> 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/trigger.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/interrupt.h> 25 #include <linux/jiffies.h> 26 #include <linux/math.h> 27 #include <linux/minmax.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/string.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 #include <linux/unaligned.h> 36 #include <linux/util_macros.h> 37 38 #define AD4062_REG_INTERFACE_CONFIG_A 0x00 39 #define AD4062_REG_DEVICE_CONFIG 0x02 40 #define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK GENMASK(1, 0) 41 #define AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE 3 42 #define AD4062_REG_PROD_ID_1 0x05 43 #define AD4062_REG_DEVICE_GRADE 0x06 44 #define AD4062_REG_SCRATCH_PAD 0x0A 45 #define AD4062_REG_VENDOR_H 0x0D 46 #define AD4062_REG_STREAM_MODE 0x0E 47 #define AD4062_REG_INTERFACE_STATUS 0x11 48 #define AD4062_REG_MODE_SET 0x20 49 #define AD4062_REG_MODE_SET_ENTER_ADC BIT(0) 50 #define AD4062_REG_ADC_MODES 0x21 51 #define AD4062_REG_ADC_MODES_MODE_MSK GENMASK(1, 0) 52 #define AD4062_REG_ADC_CONFIG 0x22 53 #define AD4062_REG_ADC_CONFIG_REF_EN_MSK BIT(5) 54 #define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK BIT(4) 55 #define AD4062_REG_AVG_CONFIG 0x23 56 #define AD4062_REG_GP_CONF 0x24 57 #define AD4062_REG_GP_CONF_MODE_MSK_0 GENMASK(2, 0) 58 #define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4) 59 #define AD4062_REG_INTR_CONF 0x25 60 #define AD4062_REG_INTR_CONF_EN_MSK_0 GENMASK(1, 0) 61 #define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4) 62 #define AD4062_REG_TIMER_CONFIG 0x27 63 #define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4) 64 #define AD4062_REG_MAX_LIMIT 0x29 65 #define AD4062_REG_MIN_LIMIT 0x2B 66 #define AD4062_REG_MAX_HYST 0x2C 67 #define AD4062_REG_MIN_HYST 0x2D 68 #define AD4062_REG_MON_VAL 0x2F 69 #define AD4062_REG_ADC_IBI_EN 0x31 70 #define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER BIT(2) 71 #define AD4062_REG_ADC_IBI_EN_MAX BIT(1) 72 #define AD4062_REG_ADC_IBI_EN_MIN BIT(0) 73 #define AD4062_REG_FUSE_CRC 0x40 74 #define AD4062_REG_DEVICE_STATUS 0x41 75 #define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6) 76 #define AD4062_REG_IBI_STATUS 0x48 77 #define AD4062_REG_CONV_READ_LSB 0x50 78 #define AD4062_REG_CONV_READ_16BITS 0x51 79 #define AD4062_REG_CONV_READ_32BITS 0x53 80 #define AD4062_REG_CONV_TRIGGER_16BITS 0x57 81 #define AD4062_REG_CONV_TRIGGER_32BITS 0x59 82 #define AD4062_REG_CONV_AUTO 0x61 83 #define AD4062_MAX_REG AD4062_REG_CONV_AUTO 84 85 #define AD4062_MON_VAL_MIDDLE_POINT 0x8000 86 87 #define AD4062_I3C_VENDOR 0x0177 88 #define AD4062_SOFT_RESET 0x81 89 #define AD4060_PROD_ID 0x7A 90 #define AD4062_PROD_ID 0x7C 91 92 #define AD4062_GP_DISABLED 0x0 93 #define AD4062_GP_INTR 0x1 94 #define AD4062_GP_DRDY 0x2 95 #define AD4062_GP_STATIC_LOW 0x5 96 #define AD4062_GP_STATIC_HIGH 0x6 97 98 #define AD4062_LIMIT_BITS 12 99 100 #define AD4062_INTR_EN_NEITHER 0x0 101 #define AD4062_INTR_EN_EITHER 0x3 102 103 #define AD4062_TCONV_NS 270 104 105 enum ad4062_operation_mode { 106 AD4062_SAMPLE_MODE = 0x0, 107 AD4062_BURST_AVERAGING_MODE = 0x1, 108 AD4062_MONITOR_MODE = 0x3, 109 }; 110 111 struct ad4062_chip_info { 112 const struct iio_chan_spec channels[1]; 113 const char *name; 114 u16 prod_id; 115 u16 avg_max; 116 }; 117 118 enum { 119 AD4062_SCAN_TYPE_SAMPLE, 120 AD4062_SCAN_TYPE_BURST_AVG, 121 }; 122 123 static const struct iio_scan_type ad4062_scan_type_12_s[] = { 124 [AD4062_SCAN_TYPE_SAMPLE] = { 125 .sign = 's', 126 .realbits = 12, 127 .storagebits = 16, 128 .endianness = IIO_BE, 129 }, 130 [AD4062_SCAN_TYPE_BURST_AVG] = { 131 .sign = 's', 132 .realbits = 14, 133 .storagebits = 16, 134 .endianness = IIO_BE, 135 }, 136 }; 137 138 static const struct iio_scan_type ad4062_scan_type_16_s[] = { 139 [AD4062_SCAN_TYPE_SAMPLE] = { 140 .sign = 's', 141 .realbits = 16, 142 .storagebits = 16, 143 .endianness = IIO_BE, 144 }, 145 [AD4062_SCAN_TYPE_BURST_AVG] = { 146 .sign = 's', 147 .realbits = 20, 148 .storagebits = 32, 149 .endianness = IIO_BE, 150 }, 151 }; 152 153 static const unsigned int ad4062_conversion_freqs[] = { 154 2000000, 1000000, 300000, 100000, /* 0 - 3 */ 155 33300, 10000, 3000, 500, /* 4 - 7 */ 156 333, 250, 200, 166, /* 8 - 11 */ 157 140, 124, 111, /* 12 - 15 */ 158 }; 159 160 struct ad4062_state { 161 const struct ad4062_chip_info *chip; 162 const struct ad4062_bus_ops *ops; 163 enum ad4062_operation_mode mode; 164 struct work_struct trig_conv; 165 struct completion completion; 166 struct iio_trigger *trigger; 167 struct iio_dev *indio_dev; 168 struct i3c_device *i3cdev; 169 struct regmap *regmap; 170 bool wait_event; 171 int vref_uV; 172 unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)]; 173 bool gpo_irq[2]; 174 u16 sampling_frequency; 175 u16 events_frequency; 176 u8 oversamp_ratio; 177 u8 conv_sizeof; 178 u8 conv_addr; 179 union { 180 __be32 be32; 181 __be16 be16; 182 } buf __aligned(IIO_DMA_MINALIGN); 183 }; 184 185 static const struct regmap_range ad4062_regmap_rd_ranges[] = { 186 regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_GRADE), 187 regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_INTERFACE_STATUS), 188 regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), 189 regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_IBI_STATUS), 190 regmap_reg_range(AD4062_REG_CONV_READ_LSB, AD4062_REG_CONV_AUTO), 191 }; 192 193 static const struct regmap_access_table ad4062_regmap_rd_table = { 194 .yes_ranges = ad4062_regmap_rd_ranges, 195 .n_yes_ranges = ARRAY_SIZE(ad4062_regmap_rd_ranges), 196 }; 197 198 static const struct regmap_range ad4062_regmap_wr_ranges[] = { 199 regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_CONFIG), 200 regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_SCRATCH_PAD), 201 regmap_reg_range(AD4062_REG_STREAM_MODE, AD4062_REG_INTERFACE_STATUS), 202 regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), 203 regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_DEVICE_STATUS), 204 }; 205 206 static const struct regmap_access_table ad4062_regmap_wr_table = { 207 .yes_ranges = ad4062_regmap_wr_ranges, 208 .n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges), 209 }; 210 211 static const struct iio_event_spec ad4062_events[] = { 212 { 213 .type = IIO_EV_TYPE_THRESH, 214 .dir = IIO_EV_DIR_EITHER, 215 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 216 }, 217 { 218 .type = IIO_EV_TYPE_THRESH, 219 .dir = IIO_EV_DIR_RISING, 220 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 221 BIT(IIO_EV_INFO_HYSTERESIS), 222 }, 223 { 224 .type = IIO_EV_TYPE_THRESH, 225 .dir = IIO_EV_DIR_FALLING, 226 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 227 BIT(IIO_EV_INFO_HYSTERESIS), 228 }, 229 }; 230 231 #define AD4062_CHAN(bits) { \ 232 .type = IIO_VOLTAGE, \ 233 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ 234 BIT(IIO_CHAN_INFO_SCALE) | \ 235 BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 236 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 237 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 238 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 239 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 240 .indexed = 1, \ 241 .channel = 0, \ 242 .event_spec = ad4062_events, \ 243 .num_event_specs = ARRAY_SIZE(ad4062_events), \ 244 .has_ext_scan_type = 1, \ 245 .ext_scan_type = ad4062_scan_type_##bits##_s, \ 246 .num_ext_scan_type = ARRAY_SIZE(ad4062_scan_type_##bits##_s), \ 247 } 248 249 static const struct ad4062_chip_info ad4060_chip_info = { 250 .name = "ad4060", 251 .channels = { AD4062_CHAN(12) }, 252 .prod_id = AD4060_PROD_ID, 253 .avg_max = 256, 254 }; 255 256 static const struct ad4062_chip_info ad4062_chip_info = { 257 .name = "ad4062", 258 .channels = { AD4062_CHAN(16) }, 259 .prod_id = AD4062_PROD_ID, 260 .avg_max = 4096, 261 }; 262 263 static ssize_t sampling_frequency_show(struct device *dev, 264 struct device_attribute *attr, char *buf) 265 { 266 struct ad4062_state *st = iio_priv(dev_to_iio_dev(dev)); 267 268 return sysfs_emit(buf, "%d\n", ad4062_conversion_freqs[st->events_frequency]); 269 } 270 271 static int sampling_frequency_store_dispatch(struct iio_dev *indio_dev, 272 const char *buf) 273 { 274 struct ad4062_state *st = iio_priv(indio_dev); 275 int val, ret; 276 277 if (st->wait_event) 278 return -EBUSY; 279 280 ret = kstrtoint(buf, 10, &val); 281 if (ret) 282 return ret; 283 284 st->events_frequency = find_closest_descending(val, ad4062_conversion_freqs, 285 ARRAY_SIZE(ad4062_conversion_freqs)); 286 return 0; 287 } 288 289 static ssize_t sampling_frequency_store(struct device *dev, 290 struct device_attribute *attr, 291 const char *buf, size_t len) 292 { 293 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 294 int ret; 295 296 if (!iio_device_claim_direct(indio_dev)) 297 return -EBUSY; 298 299 ret = sampling_frequency_store_dispatch(indio_dev, buf); 300 iio_device_release_direct(indio_dev); 301 return ret ?: len; 302 } 303 304 static IIO_DEVICE_ATTR_RW(sampling_frequency, 0); 305 306 static ssize_t sampling_frequency_available_show(struct device *dev, 307 struct device_attribute *attr, 308 char *buf) 309 { 310 int ret = 0; 311 312 for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) 313 ret += sysfs_emit_at(buf, ret, "%d%s", ad4062_conversion_freqs[i], 314 i != (ARRAY_SIZE(ad4062_conversion_freqs) - 1) ? " " : "\n"); 315 return ret; 316 } 317 318 static IIO_DEVICE_ATTR_RO(sampling_frequency_available, 0); 319 320 static struct attribute *ad4062_event_attributes[] = { 321 &iio_dev_attr_sampling_frequency.dev_attr.attr, 322 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 323 NULL 324 }; 325 326 static const struct attribute_group ad4062_event_attribute_group = { 327 .attrs = ad4062_event_attributes, 328 }; 329 330 static int ad4062_set_oversampling_ratio(struct ad4062_state *st, int val, int val2) 331 { 332 const u32 _max = st->chip->avg_max; 333 const u32 _min = 1; 334 int ret; 335 336 if (!in_range(val, _min, _max) || val2 != 0) 337 return -EINVAL; 338 339 /* 1 disables oversampling */ 340 val = ilog2(val); 341 if (val == 0) { 342 st->mode = AD4062_SAMPLE_MODE; 343 } else { 344 st->mode = AD4062_BURST_AVERAGING_MODE; 345 ret = regmap_write(st->regmap, AD4062_REG_AVG_CONFIG, val - 1); 346 if (ret) 347 return ret; 348 } 349 st->oversamp_ratio = val; 350 351 return 0; 352 } 353 354 static int ad4062_get_oversampling_ratio(struct ad4062_state *st, int *val) 355 { 356 int ret, buf; 357 358 if (st->mode == AD4062_SAMPLE_MODE) { 359 *val = 1; 360 return 0; 361 } 362 363 ret = regmap_read(st->regmap, AD4062_REG_AVG_CONFIG, &buf); 364 if (ret) 365 return ret; 366 367 *val = BIT(buf + 1); 368 return 0; 369 } 370 371 static int ad4062_calc_sampling_frequency(unsigned int fosc, unsigned int oversamp_ratio) 372 { 373 /* From datasheet p.31: (n_avg - 1)/fosc + tconv */ 374 u32 n_avg = BIT(oversamp_ratio) - 1; 375 u32 period_ns = NSEC_PER_SEC / fosc; 376 377 /* Result is less than 1 Hz */ 378 if (n_avg >= fosc) 379 return 1; 380 381 return NSEC_PER_SEC / (n_avg * period_ns + AD4062_TCONV_NS); 382 } 383 384 static int ad4062_populate_sampling_frequency(struct ad4062_state *st) 385 { 386 for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) 387 st->samp_freqs[i] = 388 ad4062_calc_sampling_frequency(ad4062_conversion_freqs[i], 389 st->oversamp_ratio); 390 return 0; 391 } 392 393 static int ad4062_get_sampling_frequency(struct ad4062_state *st, int *val) 394 { 395 int freq = ad4062_conversion_freqs[st->sampling_frequency]; 396 397 *val = ad4062_calc_sampling_frequency(freq, st->oversamp_ratio); 398 return IIO_VAL_INT; 399 } 400 401 static int ad4062_set_sampling_frequency(struct ad4062_state *st, int val, int val2) 402 { 403 int ret; 404 405 if (val2 != 0) 406 return -EINVAL; 407 408 ret = ad4062_populate_sampling_frequency(st); 409 if (ret) 410 return ret; 411 412 st->sampling_frequency = 413 find_closest_descending(val, st->samp_freqs, 414 ARRAY_SIZE(ad4062_conversion_freqs)); 415 return 0; 416 } 417 418 static int ad4062_check_ids(struct ad4062_state *st) 419 { 420 struct device *dev = &st->i3cdev->dev; 421 int ret; 422 u16 val; 423 424 ret = regmap_bulk_read(st->regmap, AD4062_REG_PROD_ID_1, 425 &st->buf.be16, sizeof(st->buf.be16)); 426 if (ret) 427 return ret; 428 429 val = be16_to_cpu(st->buf.be16); 430 if (val != st->chip->prod_id) 431 dev_warn(dev, "Production ID x%x does not match known values", val); 432 433 ret = regmap_bulk_read(st->regmap, AD4062_REG_VENDOR_H, 434 &st->buf.be16, sizeof(st->buf.be16)); 435 if (ret) 436 return ret; 437 438 val = be16_to_cpu(st->buf.be16); 439 if (val != AD4062_I3C_VENDOR) { 440 dev_err(dev, "Vendor ID x%x does not match expected value\n", val); 441 return -ENODEV; 442 } 443 444 return 0; 445 } 446 447 static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val) 448 { 449 return regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG, 450 FIELD_PREP(AD4062_REG_TIMER_CONFIG_FS_MASK, val)); 451 } 452 453 static int ad4062_set_operation_mode(struct ad4062_state *st, 454 enum ad4062_operation_mode mode) 455 { 456 const unsigned int samp_freq = mode == AD4062_MONITOR_MODE ? 457 st->events_frequency : st->sampling_frequency; 458 int ret; 459 460 ret = ad4062_conversion_frequency_set(st, samp_freq); 461 if (ret) 462 return ret; 463 464 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_MODES, 465 AD4062_REG_ADC_MODES_MODE_MSK, mode); 466 if (ret) 467 return ret; 468 469 if (mode == AD4062_MONITOR_MODE) { 470 /* Change address pointer to enter monitor mode */ 471 struct i3c_xfer xfer_trigger = { 472 .data.out = &st->conv_addr, 473 .len = sizeof(st->conv_addr), 474 .rnw = false, 475 }; 476 st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS; 477 return i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR); 478 } 479 480 return regmap_write(st->regmap, AD4062_REG_MODE_SET, 481 AD4062_REG_MODE_SET_ENTER_ADC); 482 } 483 484 static int ad4062_soft_reset(struct ad4062_state *st) 485 { 486 u8 val = AD4062_SOFT_RESET; 487 int ret; 488 489 ret = regmap_write(st->regmap, AD4062_REG_INTERFACE_CONFIG_A, val); 490 if (ret) 491 return ret; 492 493 /* Wait AD4062 treset time, datasheet p8 */ 494 ndelay(60); 495 496 return 0; 497 } 498 499 static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 500 const bool *ref_sel) 501 { 502 struct ad4062_state *st = iio_priv(indio_dev); 503 const struct iio_scan_type *scan_type; 504 int ret; 505 506 scan_type = iio_get_current_scan_type(indio_dev, chan); 507 if (IS_ERR(scan_type)) 508 return PTR_ERR(scan_type); 509 510 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 511 AD4062_REG_GP_CONF_MODE_MSK_0, 512 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, 513 AD4062_GP_INTR)); 514 if (ret) 515 return ret; 516 517 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 518 AD4062_REG_GP_CONF_MODE_MSK_1, 519 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, 520 AD4062_GP_DRDY)); 521 if (ret) 522 return ret; 523 524 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, 525 AD4062_REG_ADC_CONFIG_REF_EN_MSK, 526 FIELD_PREP(AD4062_REG_ADC_CONFIG_REF_EN_MSK, 527 *ref_sel)); 528 if (ret) 529 return ret; 530 531 ret = regmap_write(st->regmap, AD4062_REG_DEVICE_STATUS, 532 AD4062_REG_DEVICE_STATUS_DEVICE_RESET); 533 if (ret) 534 return ret; 535 536 ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, 537 AD4062_REG_INTR_CONF_EN_MSK_0, 538 FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_0, 539 AD4062_INTR_EN_EITHER)); 540 if (ret) 541 return ret; 542 543 ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, 544 AD4062_REG_INTR_CONF_EN_MSK_1, 545 FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1, 546 AD4062_INTR_EN_NEITHER)); 547 if (ret) 548 return ret; 549 550 st->buf.be16 = cpu_to_be16(AD4062_MON_VAL_MIDDLE_POINT); 551 return regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, 552 &st->buf.be16, sizeof(st->buf.be16)); 553 } 554 555 static irqreturn_t ad4062_irq_handler_thresh(int irq, void *private) 556 { 557 struct iio_dev *indio_dev = private; 558 559 iio_push_event(indio_dev, 560 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 561 IIO_EV_TYPE_THRESH, 562 IIO_EV_DIR_EITHER), 563 iio_get_time_ns(indio_dev)); 564 565 return IRQ_HANDLED; 566 } 567 568 static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private) 569 { 570 struct iio_dev *indio_dev = private; 571 struct ad4062_state *st = iio_priv(indio_dev); 572 573 if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev)) 574 iio_trigger_poll(st->trigger); 575 else 576 complete(&st->completion); 577 578 return IRQ_HANDLED; 579 } 580 581 static void ad4062_ibi_handler(struct i3c_device *i3cdev, 582 const struct i3c_ibi_payload *payload) 583 { 584 struct ad4062_state *st = i3cdev_get_drvdata(i3cdev); 585 586 if (st->wait_event) { 587 iio_push_event(st->indio_dev, 588 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 589 IIO_EV_TYPE_THRESH, 590 IIO_EV_DIR_EITHER), 591 iio_get_time_ns(st->indio_dev)); 592 return; 593 } 594 if (iio_buffer_enabled(st->indio_dev)) 595 iio_trigger_poll_nested(st->trigger); 596 else 597 complete(&st->completion); 598 } 599 600 static void ad4062_trigger_work(struct work_struct *work) 601 { 602 struct ad4062_state *st = 603 container_of(work, struct ad4062_state, trig_conv); 604 int ret; 605 606 /* 607 * Read current conversion, if at reg CONV_READ, stop bit triggers 608 * next sample and does not need writing the address. 609 */ 610 struct i3c_xfer xfer_sample = { 611 .data.in = &st->buf.be32, 612 .len = st->conv_sizeof, 613 .rnw = true, 614 }; 615 struct i3c_xfer xfer_trigger = { 616 .data.out = &st->conv_addr, 617 .len = sizeof(st->conv_addr), 618 .rnw = false, 619 }; 620 621 ret = i3c_device_do_xfers(st->i3cdev, &xfer_sample, 1, I3C_SDR); 622 if (ret) 623 return; 624 625 iio_push_to_buffers_with_ts(st->indio_dev, &st->buf.be32, st->conv_sizeof, 626 iio_get_time_ns(st->indio_dev)); 627 if (st->gpo_irq[1]) 628 return; 629 630 i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR); 631 } 632 633 static irqreturn_t ad4062_poll_handler(int irq, void *p) 634 { 635 struct iio_poll_func *pf = p; 636 struct iio_dev *indio_dev = pf->indio_dev; 637 struct ad4062_state *st = iio_priv(indio_dev); 638 639 iio_trigger_notify_done(indio_dev->trig); 640 schedule_work(&st->trig_conv); 641 642 return IRQ_HANDLED; 643 } 644 645 static void ad4062_disable_ibi(void *data) 646 { 647 struct i3c_device *i3cdev = data; 648 649 i3c_device_disable_ibi(i3cdev); 650 } 651 652 static void ad4062_free_ibi(void *data) 653 { 654 struct i3c_device *i3cdev = data; 655 656 i3c_device_free_ibi(i3cdev); 657 } 658 659 static int ad4062_request_ibi(struct i3c_device *i3cdev) 660 { 661 const struct i3c_ibi_setup ibireq = { 662 .max_payload_len = 1, 663 .num_slots = 1, 664 .handler = ad4062_ibi_handler, 665 }; 666 int ret; 667 668 ret = i3c_device_request_ibi(i3cdev, &ibireq); 669 if (ret) 670 return ret; 671 672 ret = devm_add_action_or_reset(&i3cdev->dev, ad4062_free_ibi, i3cdev); 673 if (ret) 674 return ret; 675 676 ret = i3c_device_enable_ibi(i3cdev); 677 if (ret) 678 return ret; 679 680 return devm_add_action_or_reset(&i3cdev->dev, ad4062_disable_ibi, i3cdev); 681 } 682 683 static int ad4062_request_irq(struct iio_dev *indio_dev) 684 { 685 struct ad4062_state *st = iio_priv(indio_dev); 686 struct device *dev = &st->i3cdev->dev; 687 int ret; 688 689 ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp0"); 690 if (ret == -EPROBE_DEFER) 691 return ret; 692 693 if (ret < 0) { 694 st->gpo_irq[0] = false; 695 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, 696 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN, 697 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN); 698 if (ret) 699 return ret; 700 } else { 701 st->gpo_irq[0] = true; 702 ret = devm_request_threaded_irq(dev, ret, NULL, 703 ad4062_irq_handler_thresh, 704 IRQF_ONESHOT, indio_dev->name, 705 indio_dev); 706 if (ret) 707 return ret; 708 } 709 710 ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp1"); 711 if (ret == -EPROBE_DEFER) 712 return ret; 713 714 if (ret < 0) { 715 st->gpo_irq[1] = false; 716 return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, 717 AD4062_REG_ADC_IBI_EN_CONV_TRIGGER, 718 AD4062_REG_ADC_IBI_EN_CONV_TRIGGER); 719 } 720 st->gpo_irq[1] = true; 721 722 return devm_request_irq(dev, ret, ad4062_irq_handler_drdy, 723 IRQF_NO_THREAD, indio_dev->name, indio_dev); 724 } 725 726 static const struct iio_trigger_ops ad4062_trigger_ops = { 727 .validate_device = &iio_trigger_validate_own_device, 728 }; 729 730 static int ad4062_request_trigger(struct iio_dev *indio_dev) 731 { 732 struct ad4062_state *st = iio_priv(indio_dev); 733 struct device *dev = &st->i3cdev->dev; 734 int ret; 735 736 st->trigger = devm_iio_trigger_alloc(dev, "%s-dev%d", 737 indio_dev->name, 738 iio_device_id(indio_dev)); 739 if (!st->trigger) 740 return -ENOMEM; 741 742 st->trigger->ops = &ad4062_trigger_ops; 743 iio_trigger_set_drvdata(st->trigger, indio_dev); 744 745 ret = devm_iio_trigger_register(dev, st->trigger); 746 if (ret) 747 return ret; 748 749 indio_dev->trig = iio_trigger_get(st->trigger); 750 751 return 0; 752 } 753 754 static const int ad4062_oversampling_avail[] = { 755 1, 2, 4, 8, 16, 32, 64, 128, /* 0 - 7 */ 756 256, 512, 1024, 2048, 4096, /* 8 - 12 */ 757 }; 758 759 static int ad4062_read_avail(struct iio_dev *indio_dev, 760 struct iio_chan_spec const *chan, const int **vals, 761 int *type, int *len, long mask) 762 { 763 struct ad4062_state *st = iio_priv(indio_dev); 764 int ret; 765 766 switch (mask) { 767 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 768 *vals = ad4062_oversampling_avail; 769 *len = ARRAY_SIZE(ad4062_oversampling_avail); 770 *len -= st->chip->avg_max == 256 ? 4 : 0; 771 *type = IIO_VAL_INT; 772 773 return IIO_AVAIL_LIST; 774 case IIO_CHAN_INFO_SAMP_FREQ: 775 ret = ad4062_populate_sampling_frequency(st); 776 if (ret) 777 return ret; 778 *vals = st->samp_freqs; 779 *len = st->oversamp_ratio ? ARRAY_SIZE(ad4062_conversion_freqs) : 1; 780 *type = IIO_VAL_INT; 781 782 return IIO_AVAIL_LIST; 783 default: 784 return -EINVAL; 785 } 786 } 787 788 static int ad4062_get_chan_scale(struct iio_dev *indio_dev, int *val, int *val2) 789 { 790 struct ad4062_state *st = iio_priv(indio_dev); 791 const struct iio_scan_type *scan_type; 792 793 /* 794 * In burst averaging mode the averaging filter accumulates resulting 795 * in a sample with increased precision. 796 */ 797 scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels); 798 if (IS_ERR(scan_type)) 799 return PTR_ERR(scan_type); 800 801 *val = (st->vref_uV * 2) / (MICRO / MILLI); /* signed */ 802 *val2 = scan_type->realbits - 1; 803 804 return IIO_VAL_FRACTIONAL_LOG2; 805 } 806 807 static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2) 808 { 809 int ret; 810 811 ret = regmap_bulk_read(st->regmap, AD4062_REG_MON_VAL, 812 &st->buf.be16, sizeof(st->buf.be16)); 813 if (ret) 814 return ret; 815 816 /* From datasheet: code out = code in × mon_val/0x8000 */ 817 *val = be16_to_cpu(st->buf.be16) * 2; 818 *val2 = 16; 819 820 return IIO_VAL_FRACTIONAL_LOG2; 821 } 822 823 static int ad4062_set_chan_calibscale(struct ad4062_state *st, int gain_int, 824 int gain_frac) 825 { 826 /* Divide numerator and denumerator by known great common divider */ 827 const u32 mon_val = AD4062_MON_VAL_MIDDLE_POINT / 64; 828 const u32 micro = MICRO / 64; 829 const u32 gain_fp = gain_int * MICRO + gain_frac; 830 const u32 reg_val = DIV_ROUND_CLOSEST(gain_fp * mon_val, micro); 831 int ret; 832 833 /* Checks if the gain is in range and the value fits the field */ 834 if (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1) 835 return -EINVAL; 836 837 st->buf.be16 = cpu_to_be16(reg_val); 838 ret = regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, 839 &st->buf.be16, sizeof(st->buf.be16)); 840 if (ret) 841 return ret; 842 843 /* Enable scale if gain is not equal to one */ 844 return regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, 845 AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, 846 FIELD_PREP(AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, 847 !(gain_int == 1 && gain_frac == 0))); 848 } 849 850 static int ad4062_read_chan_raw(struct ad4062_state *st, int *val) 851 { 852 struct i3c_device *i3cdev = st->i3cdev; 853 struct i3c_xfer xfer_trigger = { 854 .data.out = &st->conv_addr, 855 .len = sizeof(st->conv_addr), 856 .rnw = false, 857 }; 858 struct i3c_xfer xfer_sample = { 859 .data.in = &st->buf.be32, 860 .len = sizeof(st->buf.be32), 861 .rnw = true, 862 }; 863 int ret; 864 865 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 866 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 867 if (ret) 868 return ret; 869 870 ret = ad4062_set_operation_mode(st, st->mode); 871 if (ret) 872 return ret; 873 874 reinit_completion(&st->completion); 875 /* Change address pointer to trigger conversion */ 876 st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS; 877 ret = i3c_device_do_xfers(i3cdev, &xfer_trigger, 1, I3C_SDR); 878 if (ret) 879 return ret; 880 /* 881 * Single sample read should be used only for oversampling and 882 * sampling frequency pairs that take less than 1 sec. 883 */ 884 ret = wait_for_completion_timeout(&st->completion, 885 msecs_to_jiffies(1000)); 886 if (!ret) 887 return -ETIMEDOUT; 888 889 ret = i3c_device_do_xfers(i3cdev, &xfer_sample, 1, I3C_SDR); 890 if (ret) 891 return ret; 892 *val = be32_to_cpu(st->buf.be32); 893 return 0; 894 } 895 896 static int ad4062_read_raw_dispatch(struct ad4062_state *st, 897 int *val, int *val2, long info) 898 { 899 if (st->wait_event) 900 return -EBUSY; 901 902 switch (info) { 903 case IIO_CHAN_INFO_RAW: 904 return ad4062_read_chan_raw(st, val); 905 906 case IIO_CHAN_INFO_CALIBSCALE: 907 return ad4062_get_chan_calibscale(st, val, val2); 908 909 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 910 return ad4062_get_oversampling_ratio(st, val); 911 912 default: 913 return -EINVAL; 914 } 915 } 916 917 static int ad4062_read_raw(struct iio_dev *indio_dev, 918 struct iio_chan_spec const *chan, 919 int *val, int *val2, long info) 920 { 921 struct ad4062_state *st = iio_priv(indio_dev); 922 int ret; 923 924 switch (info) { 925 case IIO_CHAN_INFO_SCALE: 926 return ad4062_get_chan_scale(indio_dev, val, val2); 927 928 case IIO_CHAN_INFO_SAMP_FREQ: 929 return ad4062_get_sampling_frequency(st, val); 930 } 931 932 if (!iio_device_claim_direct(indio_dev)) 933 return -EBUSY; 934 935 ret = ad4062_read_raw_dispatch(st, val, val2, info); 936 iio_device_release_direct(indio_dev); 937 return ret ?: IIO_VAL_INT; 938 } 939 940 static int ad4062_write_raw_dispatch(struct ad4062_state *st, int val, int val2, 941 long info) 942 { 943 if (st->wait_event) 944 return -EBUSY; 945 946 switch (info) { 947 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 948 return ad4062_set_oversampling_ratio(st, val, val2); 949 950 case IIO_CHAN_INFO_CALIBSCALE: 951 return ad4062_set_chan_calibscale(st, val, val2); 952 953 default: 954 return -EINVAL; 955 } 956 } 957 958 static int ad4062_write_raw(struct iio_dev *indio_dev, 959 struct iio_chan_spec const *chan, int val, 960 int val2, long info) 961 { 962 struct ad4062_state *st = iio_priv(indio_dev); 963 int ret; 964 965 switch (info) { 966 case IIO_CHAN_INFO_SAMP_FREQ: 967 return ad4062_set_sampling_frequency(st, val, val2); 968 } 969 970 if (!iio_device_claim_direct(indio_dev)) 971 return -EBUSY; 972 973 ret = ad4062_write_raw_dispatch(st, val, val2, info); 974 iio_device_release_direct(indio_dev); 975 return ret; 976 } 977 978 static int pm_ad4062_monitor_mode_enable(struct ad4062_state *st) 979 { 980 int ret; 981 982 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 983 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 984 if (ret) 985 return ret; 986 987 return ad4062_set_operation_mode(st, AD4062_MONITOR_MODE); 988 } 989 990 static int ad4062_monitor_mode_enable(struct ad4062_state *st) 991 { 992 int ret; 993 994 ret = pm_ad4062_monitor_mode_enable(st); 995 if (ret) 996 return ret; 997 998 pm_runtime_get_noresume(&st->i3cdev->dev); 999 return 0; 1000 } 1001 1002 static int ad4062_monitor_mode_disable(struct ad4062_state *st) 1003 { 1004 pm_runtime_put_autosuspend(&st->i3cdev->dev); 1005 return 0; 1006 } 1007 1008 static int ad4062_read_event_config(struct iio_dev *indio_dev, 1009 const struct iio_chan_spec *chan, 1010 enum iio_event_type type, 1011 enum iio_event_direction dir) 1012 { 1013 struct ad4062_state *st = iio_priv(indio_dev); 1014 1015 return st->wait_event; 1016 } 1017 1018 static int ad4062_write_event_config_dispatch(struct iio_dev *indio_dev, 1019 bool state) 1020 { 1021 struct ad4062_state *st = iio_priv(indio_dev); 1022 int ret; 1023 1024 if (st->wait_event == state) 1025 ret = 0; 1026 else if (state) 1027 ret = ad4062_monitor_mode_enable(st); 1028 else 1029 ret = ad4062_monitor_mode_disable(st); 1030 if (ret) 1031 return ret; 1032 1033 st->wait_event = state; 1034 return 0; 1035 } 1036 1037 static int ad4062_write_event_config(struct iio_dev *indio_dev, 1038 const struct iio_chan_spec *chan, 1039 enum iio_event_type type, 1040 enum iio_event_direction dir, 1041 bool state) 1042 { 1043 int ret; 1044 1045 if (!iio_device_claim_direct(indio_dev)) 1046 return -EBUSY; 1047 1048 ret = ad4062_write_event_config_dispatch(indio_dev, state); 1049 iio_device_release_direct(indio_dev); 1050 return ret; 1051 } 1052 1053 static int __ad4062_read_event_info_value(struct ad4062_state *st, 1054 enum iio_event_direction dir, int *val) 1055 { 1056 int ret; 1057 u8 reg; 1058 1059 if (dir == IIO_EV_DIR_RISING) 1060 reg = AD4062_REG_MAX_LIMIT; 1061 else 1062 reg = AD4062_REG_MIN_LIMIT; 1063 1064 ret = regmap_bulk_read(st->regmap, reg, &st->buf.be16, 1065 sizeof(st->buf.be16)); 1066 if (ret) 1067 return ret; 1068 1069 *val = sign_extend32(be16_to_cpu(st->buf.be16), AD4062_LIMIT_BITS - 1); 1070 1071 return 0; 1072 } 1073 1074 static int __ad4062_read_event_info_hysteresis(struct ad4062_state *st, 1075 enum iio_event_direction dir, int *val) 1076 { 1077 u8 reg; 1078 1079 if (dir == IIO_EV_DIR_RISING) 1080 reg = AD4062_REG_MAX_HYST; 1081 else 1082 reg = AD4062_REG_MIN_HYST; 1083 return regmap_read(st->regmap, reg, val); 1084 } 1085 1086 static int ad4062_read_event_config_dispatch(struct iio_dev *indio_dev, 1087 enum iio_event_direction dir, 1088 enum iio_event_info info, int *val) 1089 { 1090 struct ad4062_state *st = iio_priv(indio_dev); 1091 1092 if (st->wait_event) 1093 return -EBUSY; 1094 1095 switch (info) { 1096 case IIO_EV_INFO_VALUE: 1097 return __ad4062_read_event_info_value(st, dir, val); 1098 case IIO_EV_INFO_HYSTERESIS: 1099 return __ad4062_read_event_info_hysteresis(st, dir, val); 1100 default: 1101 return -EINVAL; 1102 } 1103 } 1104 1105 static int ad4062_read_event_value(struct iio_dev *indio_dev, 1106 const struct iio_chan_spec *chan, 1107 enum iio_event_type type, 1108 enum iio_event_direction dir, 1109 enum iio_event_info info, int *val, 1110 int *val2) 1111 { 1112 int ret; 1113 1114 if (!iio_device_claim_direct(indio_dev)) 1115 return -EBUSY; 1116 1117 ret = ad4062_read_event_config_dispatch(indio_dev, dir, info, val); 1118 iio_device_release_direct(indio_dev); 1119 return ret ?: IIO_VAL_INT; 1120 } 1121 1122 static int __ad4062_write_event_info_value(struct ad4062_state *st, 1123 enum iio_event_direction dir, int val) 1124 { 1125 u8 reg; 1126 1127 if (val != sign_extend32(val, AD4062_LIMIT_BITS - 1)) 1128 return -EINVAL; 1129 if (dir == IIO_EV_DIR_RISING) 1130 reg = AD4062_REG_MAX_LIMIT; 1131 else 1132 reg = AD4062_REG_MIN_LIMIT; 1133 st->buf.be16 = cpu_to_be16(val); 1134 1135 return regmap_bulk_write(st->regmap, reg, &st->buf.be16, 1136 sizeof(st->buf.be16)); 1137 } 1138 1139 static int __ad4062_write_event_info_hysteresis(struct ad4062_state *st, 1140 enum iio_event_direction dir, int val) 1141 { 1142 u8 reg; 1143 1144 if (val > BIT(7) - 1) 1145 return -EINVAL; 1146 if (dir == IIO_EV_DIR_RISING) 1147 reg = AD4062_REG_MAX_HYST; 1148 else 1149 reg = AD4062_REG_MIN_HYST; 1150 1151 return regmap_write(st->regmap, reg, val); 1152 } 1153 1154 static int ad4062_write_event_value_dispatch(struct iio_dev *indio_dev, 1155 enum iio_event_type type, 1156 enum iio_event_direction dir, 1157 enum iio_event_info info, int val) 1158 { 1159 struct ad4062_state *st = iio_priv(indio_dev); 1160 1161 if (st->wait_event) 1162 return -EBUSY; 1163 1164 switch (type) { 1165 case IIO_EV_TYPE_THRESH: 1166 switch (info) { 1167 case IIO_EV_INFO_VALUE: 1168 return __ad4062_write_event_info_value(st, dir, val); 1169 case IIO_EV_INFO_HYSTERESIS: 1170 return __ad4062_write_event_info_hysteresis(st, dir, val); 1171 default: 1172 return -EINVAL; 1173 } 1174 default: 1175 return -EINVAL; 1176 } 1177 } 1178 1179 static int ad4062_write_event_value(struct iio_dev *indio_dev, 1180 const struct iio_chan_spec *chan, 1181 enum iio_event_type type, 1182 enum iio_event_direction dir, 1183 enum iio_event_info info, int val, 1184 int val2) 1185 { 1186 int ret; 1187 1188 if (!iio_device_claim_direct(indio_dev)) 1189 return -EBUSY; 1190 1191 ret = ad4062_write_event_value_dispatch(indio_dev, type, dir, info, val); 1192 iio_device_release_direct(indio_dev); 1193 return ret; 1194 } 1195 1196 /* 1197 * The AD4062 in burst averaging mode increases realbits from 16-bits to 1198 * 20-bits, increasing the storagebits from 16-bits to 32-bits. 1199 */ 1200 static inline size_t ad4062_sizeof_storagebits(struct ad4062_state *st) 1201 { 1202 const struct iio_scan_type *scan_type = 1203 iio_get_current_scan_type(st->indio_dev, st->chip->channels); 1204 1205 return BITS_TO_BYTES(scan_type->storagebits); 1206 } 1207 1208 /* Read registers only with realbits (no sign extension bytes) */ 1209 static inline size_t ad4062_get_conv_addr(struct ad4062_state *st, size_t _sizeof) 1210 { 1211 if (st->gpo_irq[1]) 1212 return _sizeof == sizeof(u32) ? AD4062_REG_CONV_READ_32BITS : 1213 AD4062_REG_CONV_READ_16BITS; 1214 return _sizeof == sizeof(u32) ? AD4062_REG_CONV_TRIGGER_32BITS : 1215 AD4062_REG_CONV_TRIGGER_16BITS; 1216 } 1217 1218 static int pm_ad4062_triggered_buffer_postenable(struct ad4062_state *st) 1219 { 1220 int ret; 1221 1222 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 1223 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 1224 if (ret) 1225 return ret; 1226 1227 if (st->wait_event) 1228 return -EBUSY; 1229 1230 ret = ad4062_set_operation_mode(st, st->mode); 1231 if (ret) 1232 return ret; 1233 1234 st->conv_sizeof = ad4062_sizeof_storagebits(st); 1235 st->conv_addr = ad4062_get_conv_addr(st, st->conv_sizeof); 1236 /* CONV_READ requires read to trigger first sample. */ 1237 struct i3c_xfer xfer_sample[2] = { 1238 { 1239 .data.out = &st->conv_addr, 1240 .len = sizeof(st->conv_addr), 1241 .rnw = false, 1242 }, 1243 { 1244 .data.in = &st->buf.be32, 1245 .len = sizeof(st->buf.be32), 1246 .rnw = true, 1247 } 1248 }; 1249 1250 return i3c_device_do_xfers(st->i3cdev, xfer_sample, 1251 st->gpo_irq[1] ? 2 : 1, I3C_SDR); 1252 } 1253 1254 static int ad4062_triggered_buffer_postenable(struct iio_dev *indio_dev) 1255 { 1256 struct ad4062_state *st = iio_priv(indio_dev); 1257 int ret; 1258 1259 ret = pm_ad4062_triggered_buffer_postenable(st); 1260 if (ret) 1261 return ret; 1262 1263 pm_runtime_get_noresume(&st->i3cdev->dev); 1264 return 0; 1265 } 1266 1267 static int ad4062_triggered_buffer_predisable(struct iio_dev *indio_dev) 1268 { 1269 struct ad4062_state *st = iio_priv(indio_dev); 1270 1271 pm_runtime_put_autosuspend(&st->i3cdev->dev); 1272 return 0; 1273 } 1274 1275 static const struct iio_buffer_setup_ops ad4062_triggered_buffer_setup_ops = { 1276 .postenable = &ad4062_triggered_buffer_postenable, 1277 .predisable = &ad4062_triggered_buffer_predisable, 1278 }; 1279 1280 static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1281 unsigned int writeval, unsigned int *readval) 1282 { 1283 struct ad4062_state *st = iio_priv(indio_dev); 1284 1285 if (readval) 1286 return regmap_read(st->regmap, reg, readval); 1287 else 1288 return regmap_write(st->regmap, reg, writeval); 1289 } 1290 1291 static int ad4062_get_current_scan_type(const struct iio_dev *indio_dev, 1292 const struct iio_chan_spec *chan) 1293 { 1294 struct ad4062_state *st = iio_priv(indio_dev); 1295 1296 return st->mode == AD4062_BURST_AVERAGING_MODE ? 1297 AD4062_SCAN_TYPE_BURST_AVG : 1298 AD4062_SCAN_TYPE_SAMPLE; 1299 } 1300 1301 static const struct iio_info ad4062_info = { 1302 .read_raw = ad4062_read_raw, 1303 .write_raw = ad4062_write_raw, 1304 .read_avail = ad4062_read_avail, 1305 .read_event_config = ad4062_read_event_config, 1306 .write_event_config = ad4062_write_event_config, 1307 .read_event_value = ad4062_read_event_value, 1308 .write_event_value = ad4062_write_event_value, 1309 .event_attrs = &ad4062_event_attribute_group, 1310 .get_current_scan_type = ad4062_get_current_scan_type, 1311 .debugfs_reg_access = ad4062_debugfs_reg_access, 1312 }; 1313 1314 static const struct regmap_config ad4062_regmap_config = { 1315 .name = "ad4062", 1316 .reg_bits = 8, 1317 .val_bits = 8, 1318 .max_register = AD4062_MAX_REG, 1319 .rd_table = &ad4062_regmap_rd_table, 1320 .wr_table = &ad4062_regmap_wr_table, 1321 .can_sleep = true, 1322 }; 1323 1324 static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel) 1325 { 1326 struct device *dev = &st->i3cdev->dev; 1327 int ret; 1328 1329 ret = devm_regulator_get_enable(dev, "vio"); 1330 if (ret) 1331 return dev_err_probe(dev, ret, "Failed to enable vio voltage\n"); 1332 1333 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref"); 1334 *ref_sel = st->vref_uV == -ENODEV; 1335 if (st->vref_uV < 0 && !*ref_sel) 1336 return dev_err_probe(dev, st->vref_uV, 1337 "Failed to enable and read ref voltage\n"); 1338 1339 if (*ref_sel) { 1340 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "vdd"); 1341 if (st->vref_uV < 0) 1342 return dev_err_probe(dev, st->vref_uV, 1343 "Failed to enable and read vdd voltage\n"); 1344 } else { 1345 ret = devm_regulator_get_enable(dev, "vdd"); 1346 if (ret) 1347 return dev_err_probe(dev, ret, 1348 "Failed to enable vdd regulator\n"); 1349 } 1350 1351 return 0; 1352 } 1353 1354 static int ad4062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1355 { 1356 return GPIO_LINE_DIRECTION_OUT; 1357 } 1358 1359 static int ad4062_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1360 { 1361 struct ad4062_state *st = gpiochip_get_data(gc); 1362 unsigned int reg_val = value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC_LOW; 1363 1364 if (offset) 1365 return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1366 AD4062_REG_GP_CONF_MODE_MSK_1, 1367 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val)); 1368 else 1369 return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1370 AD4062_REG_GP_CONF_MODE_MSK_0, 1371 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val)); 1372 } 1373 1374 static int ad4062_gpio_get(struct gpio_chip *gc, unsigned int offset) 1375 { 1376 struct ad4062_state *st = gpiochip_get_data(gc); 1377 unsigned int reg_val; 1378 int ret; 1379 1380 ret = regmap_read(st->regmap, AD4062_REG_GP_CONF, ®_val); 1381 if (ret) 1382 return ret; 1383 1384 if (offset) 1385 reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val); 1386 else 1387 reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val); 1388 1389 return reg_val == AD4062_GP_STATIC_HIGH; 1390 } 1391 1392 static void ad4062_gpio_disable(void *data) 1393 { 1394 struct ad4062_state *st = data; 1395 u8 val = FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_DISABLED) | 1396 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DISABLED); 1397 1398 regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1399 AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0, 1400 val); 1401 } 1402 1403 static int ad4062_gpio_init_valid_mask(struct gpio_chip *gc, 1404 unsigned long *valid_mask, 1405 unsigned int ngpios) 1406 { 1407 struct ad4062_state *st = gpiochip_get_data(gc); 1408 1409 bitmap_zero(valid_mask, ngpios); 1410 1411 for (unsigned int i = 0; i < ARRAY_SIZE(st->gpo_irq); i++) 1412 __assign_bit(i, valid_mask, !st->gpo_irq[i]); 1413 1414 return 0; 1415 } 1416 1417 static int ad4062_gpio_init(struct ad4062_state *st) 1418 { 1419 struct device *dev = &st->i3cdev->dev; 1420 struct gpio_chip *gc; 1421 u8 val, mask; 1422 int ret; 1423 1424 if (!device_property_read_bool(dev, "gpio-controller")) 1425 return 0; 1426 1427 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1428 if (!gc) 1429 return -ENOMEM; 1430 1431 val = 0; 1432 mask = 0; 1433 if (!st->gpo_irq[0]) { 1434 mask |= AD4062_REG_GP_CONF_MODE_MSK_0; 1435 val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_STATIC_LOW); 1436 } 1437 if (!st->gpo_irq[1]) { 1438 mask |= AD4062_REG_GP_CONF_MODE_MSK_1; 1439 val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_STATIC_LOW); 1440 } 1441 1442 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1443 mask, val); 1444 if (ret) 1445 return ret; 1446 1447 ret = devm_add_action_or_reset(dev, ad4062_gpio_disable, st); 1448 if (ret) 1449 return ret; 1450 1451 gc->parent = dev; 1452 gc->label = st->chip->name; 1453 gc->owner = THIS_MODULE; 1454 gc->base = -1; 1455 gc->ngpio = 2; 1456 gc->init_valid_mask = ad4062_gpio_init_valid_mask; 1457 gc->get_direction = ad4062_gpio_get_direction; 1458 gc->set = ad4062_gpio_set; 1459 gc->get = ad4062_gpio_get; 1460 gc->can_sleep = true; 1461 1462 ret = devm_gpiochip_add_data(dev, gc, st); 1463 if (ret) 1464 return dev_err_probe(dev, ret, "Unable to register GPIO chip\n"); 1465 1466 return 0; 1467 } 1468 1469 static const struct i3c_device_id ad4062_id_table[] = { 1470 I3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info), 1471 I3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info), 1472 { } 1473 }; 1474 MODULE_DEVICE_TABLE(i3c, ad4062_id_table); 1475 1476 static int ad4062_probe(struct i3c_device *i3cdev) 1477 { 1478 const struct i3c_device_id *id = i3c_device_match_id(i3cdev, ad4062_id_table); 1479 const struct ad4062_chip_info *chip = id->data; 1480 struct device *dev = &i3cdev->dev; 1481 struct iio_dev *indio_dev; 1482 struct ad4062_state *st; 1483 bool ref_sel; 1484 int ret; 1485 1486 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1487 if (!indio_dev) 1488 return -ENOMEM; 1489 1490 st = iio_priv(indio_dev); 1491 st->i3cdev = i3cdev; 1492 i3cdev_set_drvdata(i3cdev, st); 1493 init_completion(&st->completion); 1494 1495 ret = ad4062_regulators_get(st, &ref_sel); 1496 if (ret) 1497 return ret; 1498 1499 st->regmap = devm_regmap_init_i3c(i3cdev, &ad4062_regmap_config); 1500 if (IS_ERR(st->regmap)) 1501 return dev_err_probe(dev, PTR_ERR(st->regmap), 1502 "Failed to initialize regmap\n"); 1503 1504 st->mode = AD4062_SAMPLE_MODE; 1505 st->wait_event = false; 1506 st->chip = chip; 1507 st->sampling_frequency = 0; 1508 st->events_frequency = 0; 1509 st->oversamp_ratio = 0; 1510 st->indio_dev = indio_dev; 1511 1512 indio_dev->modes = INDIO_DIRECT_MODE; 1513 indio_dev->num_channels = 1; 1514 indio_dev->info = &ad4062_info; 1515 indio_dev->name = chip->name; 1516 indio_dev->channels = chip->channels; 1517 1518 ret = ad4062_soft_reset(st); 1519 if (ret) 1520 return dev_err_probe(dev, ret, "AD4062 failed to soft reset\n"); 1521 1522 ret = ad4062_check_ids(st); 1523 if (ret) 1524 return ret; 1525 1526 ret = ad4062_setup(indio_dev, indio_dev->channels, &ref_sel); 1527 if (ret) 1528 return ret; 1529 1530 ret = ad4062_request_irq(indio_dev); 1531 if (ret) 1532 return ret; 1533 1534 ret = ad4062_request_trigger(indio_dev); 1535 if (ret) 1536 return ret; 1537 1538 ret = devm_iio_triggered_buffer_setup(&i3cdev->dev, indio_dev, 1539 iio_pollfunc_store_time, 1540 ad4062_poll_handler, 1541 &ad4062_triggered_buffer_setup_ops); 1542 if (ret) 1543 return ret; 1544 1545 pm_runtime_set_active(dev); 1546 ret = devm_pm_runtime_enable(dev); 1547 if (ret) 1548 return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n"); 1549 1550 pm_runtime_set_autosuspend_delay(dev, 1000); 1551 pm_runtime_use_autosuspend(dev); 1552 1553 ret = ad4062_request_ibi(i3cdev); 1554 if (ret) 1555 return dev_err_probe(dev, ret, "Failed to request i3c ibi\n"); 1556 1557 ret = ad4062_gpio_init(st); 1558 if (ret) 1559 return ret; 1560 1561 ret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work); 1562 if (ret) 1563 return ret; 1564 1565 return devm_iio_device_register(dev, indio_dev); 1566 } 1567 1568 static int ad4062_runtime_suspend(struct device *dev) 1569 { 1570 struct ad4062_state *st = dev_get_drvdata(dev); 1571 1572 return regmap_write(st->regmap, AD4062_REG_DEVICE_CONFIG, 1573 FIELD_PREP(AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK, 1574 AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE)); 1575 } 1576 1577 static int ad4062_runtime_resume(struct device *dev) 1578 { 1579 struct ad4062_state *st = dev_get_drvdata(dev); 1580 int ret; 1581 1582 ret = regmap_clear_bits(st->regmap, AD4062_REG_DEVICE_CONFIG, 1583 AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK); 1584 if (ret) 1585 return ret; 1586 1587 /* Wait device functional blocks to power up */ 1588 fsleep(3 * USEC_PER_MSEC); 1589 return 0; 1590 } 1591 1592 static DEFINE_RUNTIME_DEV_PM_OPS(ad4062_pm_ops, 1593 ad4062_runtime_suspend, ad4062_runtime_resume, NULL); 1594 1595 static struct i3c_driver ad4062_driver = { 1596 .driver = { 1597 .name = "ad4062", 1598 .pm = pm_ptr(&ad4062_pm_ops), 1599 }, 1600 .probe = ad4062_probe, 1601 .id_table = ad4062_id_table, 1602 }; 1603 module_i3c_driver(ad4062_driver); 1604 1605 MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); 1606 MODULE_DESCRIPTION("Analog Devices AD4062"); 1607 MODULE_LICENSE("GPL"); 1608