1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD4062 I3C ADC driver 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/devm-helpers.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i3c/device.h> 16 #include <linux/i3c/master.h> 17 #include <linux/iio/buffer.h> 18 #include <linux/iio/events.h> 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/trigger.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/interrupt.h> 25 #include <linux/jiffies.h> 26 #include <linux/math.h> 27 #include <linux/minmax.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/string.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 #include <linux/unaligned.h> 36 #include <linux/util_macros.h> 37 38 #define AD4062_REG_INTERFACE_CONFIG_A 0x00 39 #define AD4062_REG_DEVICE_CONFIG 0x02 40 #define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK GENMASK(1, 0) 41 #define AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE 3 42 #define AD4062_REG_PROD_ID_1 0x05 43 #define AD4062_REG_DEVICE_GRADE 0x06 44 #define AD4062_REG_SCRATCH_PAD 0x0A 45 #define AD4062_REG_VENDOR_H 0x0D 46 #define AD4062_REG_STREAM_MODE 0x0E 47 #define AD4062_REG_INTERFACE_STATUS 0x11 48 #define AD4062_REG_MODE_SET 0x20 49 #define AD4062_REG_MODE_SET_ENTER_ADC BIT(0) 50 #define AD4062_REG_ADC_MODES 0x21 51 #define AD4062_REG_ADC_MODES_MODE_MSK GENMASK(1, 0) 52 #define AD4062_REG_ADC_CONFIG 0x22 53 #define AD4062_REG_ADC_CONFIG_REF_EN_MSK BIT(5) 54 #define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK BIT(4) 55 #define AD4062_REG_AVG_CONFIG 0x23 56 #define AD4062_REG_GP_CONF 0x24 57 #define AD4062_REG_GP_CONF_MODE_MSK_0 GENMASK(2, 0) 58 #define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4) 59 #define AD4062_REG_INTR_CONF 0x25 60 #define AD4062_REG_INTR_CONF_EN_MSK_0 GENMASK(1, 0) 61 #define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4) 62 #define AD4062_REG_TIMER_CONFIG 0x27 63 #define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4) 64 #define AD4062_REG_MAX_LIMIT 0x29 65 #define AD4062_REG_MIN_LIMIT 0x2B 66 #define AD4062_REG_MAX_HYST 0x2C 67 #define AD4062_REG_MIN_HYST 0x2D 68 #define AD4062_REG_MON_VAL 0x2F 69 #define AD4062_REG_ADC_IBI_EN 0x31 70 #define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER BIT(2) 71 #define AD4062_REG_ADC_IBI_EN_MAX BIT(1) 72 #define AD4062_REG_ADC_IBI_EN_MIN BIT(0) 73 #define AD4062_REG_FUSE_CRC 0x40 74 #define AD4062_REG_DEVICE_STATUS 0x41 75 #define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6) 76 #define AD4062_REG_IBI_STATUS 0x48 77 #define AD4062_REG_CONV_READ_LSB 0x50 78 #define AD4062_REG_CONV_READ_16BITS 0x51 79 #define AD4062_REG_CONV_READ_32BITS 0x53 80 #define AD4062_REG_CONV_TRIGGER_16BITS 0x57 81 #define AD4062_REG_CONV_TRIGGER_32BITS 0x59 82 #define AD4062_REG_CONV_AUTO 0x61 83 #define AD4062_MAX_REG AD4062_REG_CONV_AUTO 84 85 #define AD4062_MON_VAL_MIDDLE_POINT 0x8000 86 87 #define AD4062_I3C_VENDOR 0x0177 88 #define AD4062_SOFT_RESET 0x81 89 #define AD4060_PROD_ID 0x7A 90 #define AD4062_PROD_ID 0x7C 91 92 #define AD4062_GP_DISABLED 0x0 93 #define AD4062_GP_INTR 0x1 94 #define AD4062_GP_DRDY 0x2 95 #define AD4062_GP_STATIC_LOW 0x5 96 #define AD4062_GP_STATIC_HIGH 0x6 97 98 #define AD4062_LIMIT_BITS 12 99 100 #define AD4062_INTR_EN_NEITHER 0x0 101 #define AD4062_INTR_EN_EITHER 0x3 102 103 #define AD4062_TCONV_NS 270 104 105 enum ad4062_operation_mode { 106 AD4062_SAMPLE_MODE = 0x0, 107 AD4062_BURST_AVERAGING_MODE = 0x1, 108 AD4062_MONITOR_MODE = 0x3, 109 }; 110 111 struct ad4062_chip_info { 112 const struct iio_chan_spec channels[1]; 113 const char *name; 114 u16 prod_id; 115 u16 avg_max; 116 }; 117 118 enum { 119 AD4062_SCAN_TYPE_SAMPLE, 120 AD4062_SCAN_TYPE_BURST_AVG, 121 }; 122 123 static const struct iio_scan_type ad4062_scan_type_12_s[] = { 124 [AD4062_SCAN_TYPE_SAMPLE] = { 125 .sign = 's', 126 .realbits = 12, 127 .storagebits = 16, 128 .endianness = IIO_BE, 129 }, 130 [AD4062_SCAN_TYPE_BURST_AVG] = { 131 .sign = 's', 132 .realbits = 14, 133 .storagebits = 16, 134 .endianness = IIO_BE, 135 }, 136 }; 137 138 static const struct iio_scan_type ad4062_scan_type_16_s[] = { 139 [AD4062_SCAN_TYPE_SAMPLE] = { 140 .sign = 's', 141 .realbits = 16, 142 .storagebits = 16, 143 .endianness = IIO_BE, 144 }, 145 [AD4062_SCAN_TYPE_BURST_AVG] = { 146 .sign = 's', 147 .realbits = 20, 148 .storagebits = 32, 149 .endianness = IIO_BE, 150 }, 151 }; 152 153 static const unsigned int ad4062_conversion_freqs[] = { 154 2000000, 1000000, 300000, 100000, /* 0 - 3 */ 155 33300, 10000, 3000, 500, /* 4 - 7 */ 156 333, 250, 200, 166, /* 8 - 11 */ 157 140, 124, 111, /* 12 - 15 */ 158 }; 159 160 struct ad4062_state { 161 const struct ad4062_chip_info *chip; 162 const struct ad4062_bus_ops *ops; 163 enum ad4062_operation_mode mode; 164 struct work_struct trig_conv; 165 struct completion completion; 166 struct iio_trigger *trigger; 167 struct iio_dev *indio_dev; 168 struct i3c_device *i3cdev; 169 struct regmap *regmap; 170 bool wait_event; 171 int vref_uV; 172 unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)]; 173 bool gpo_irq[2]; 174 u16 sampling_frequency; 175 u16 events_frequency; 176 u8 oversamp_ratio; 177 u8 conv_sizeof; 178 u8 conv_addr; 179 union { 180 __be32 be32; 181 __be16 be16; 182 } buf __aligned(IIO_DMA_MINALIGN); 183 }; 184 185 static const struct regmap_range ad4062_regmap_rd_ranges[] = { 186 regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_GRADE), 187 regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_INTERFACE_STATUS), 188 regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), 189 regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_IBI_STATUS), 190 regmap_reg_range(AD4062_REG_CONV_READ_LSB, AD4062_REG_CONV_AUTO), 191 }; 192 193 static const struct regmap_access_table ad4062_regmap_rd_table = { 194 .yes_ranges = ad4062_regmap_rd_ranges, 195 .n_yes_ranges = ARRAY_SIZE(ad4062_regmap_rd_ranges), 196 }; 197 198 static const struct regmap_range ad4062_regmap_wr_ranges[] = { 199 regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_CONFIG), 200 regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_SCRATCH_PAD), 201 regmap_reg_range(AD4062_REG_STREAM_MODE, AD4062_REG_INTERFACE_STATUS), 202 regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), 203 regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_DEVICE_STATUS), 204 }; 205 206 static const struct regmap_access_table ad4062_regmap_wr_table = { 207 .yes_ranges = ad4062_regmap_wr_ranges, 208 .n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges), 209 }; 210 211 static const struct iio_event_spec ad4062_events[] = { 212 { 213 .type = IIO_EV_TYPE_THRESH, 214 .dir = IIO_EV_DIR_EITHER, 215 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 216 }, 217 { 218 .type = IIO_EV_TYPE_THRESH, 219 .dir = IIO_EV_DIR_RISING, 220 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 221 BIT(IIO_EV_INFO_HYSTERESIS), 222 }, 223 { 224 .type = IIO_EV_TYPE_THRESH, 225 .dir = IIO_EV_DIR_FALLING, 226 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 227 BIT(IIO_EV_INFO_HYSTERESIS), 228 }, 229 }; 230 231 #define AD4062_CHAN(bits) { \ 232 .type = IIO_VOLTAGE, \ 233 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ 234 BIT(IIO_CHAN_INFO_SCALE) | \ 235 BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 236 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 237 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 238 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 239 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 240 .indexed = 1, \ 241 .channel = 0, \ 242 .event_spec = ad4062_events, \ 243 .num_event_specs = ARRAY_SIZE(ad4062_events), \ 244 .has_ext_scan_type = 1, \ 245 .ext_scan_type = ad4062_scan_type_##bits##_s, \ 246 .num_ext_scan_type = ARRAY_SIZE(ad4062_scan_type_##bits##_s), \ 247 } 248 249 static const struct ad4062_chip_info ad4060_chip_info = { 250 .name = "ad4060", 251 .channels = { AD4062_CHAN(12) }, 252 .prod_id = AD4060_PROD_ID, 253 .avg_max = 256, 254 }; 255 256 static const struct ad4062_chip_info ad4062_chip_info = { 257 .name = "ad4062", 258 .channels = { AD4062_CHAN(16) }, 259 .prod_id = AD4062_PROD_ID, 260 .avg_max = 4096, 261 }; 262 263 static ssize_t sampling_frequency_show(struct device *dev, 264 struct device_attribute *attr, char *buf) 265 { 266 struct ad4062_state *st = iio_priv(dev_to_iio_dev(dev)); 267 268 return sysfs_emit(buf, "%d\n", ad4062_conversion_freqs[st->events_frequency]); 269 } 270 271 static int sampling_frequency_store_dispatch(struct iio_dev *indio_dev, 272 const char *buf) 273 { 274 struct ad4062_state *st = iio_priv(indio_dev); 275 int val, ret; 276 277 if (st->wait_event) 278 return -EBUSY; 279 280 ret = kstrtoint(buf, 10, &val); 281 if (ret) 282 return ret; 283 284 st->events_frequency = find_closest_descending(val, ad4062_conversion_freqs, 285 ARRAY_SIZE(ad4062_conversion_freqs)); 286 return 0; 287 } 288 289 static ssize_t sampling_frequency_store(struct device *dev, 290 struct device_attribute *attr, 291 const char *buf, size_t len) 292 { 293 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 294 int ret; 295 296 if (!iio_device_claim_direct(indio_dev)) 297 return -EBUSY; 298 299 ret = sampling_frequency_store_dispatch(indio_dev, buf); 300 iio_device_release_direct(indio_dev); 301 return ret ?: len; 302 } 303 304 static IIO_DEVICE_ATTR_RW(sampling_frequency, 0); 305 306 static ssize_t sampling_frequency_available_show(struct device *dev, 307 struct device_attribute *attr, 308 char *buf) 309 { 310 int ret = 0; 311 312 for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) 313 ret += sysfs_emit_at(buf, ret, "%d%s", ad4062_conversion_freqs[i], 314 i != (ARRAY_SIZE(ad4062_conversion_freqs) - 1) ? " " : "\n"); 315 return ret; 316 } 317 318 static IIO_DEVICE_ATTR_RO(sampling_frequency_available, 0); 319 320 static struct attribute *ad4062_event_attributes[] = { 321 &iio_dev_attr_sampling_frequency.dev_attr.attr, 322 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 323 NULL 324 }; 325 326 static const struct attribute_group ad4062_event_attribute_group = { 327 .attrs = ad4062_event_attributes, 328 }; 329 330 static int ad4062_set_oversampling_ratio(struct ad4062_state *st, int val, int val2) 331 { 332 const u32 _max = st->chip->avg_max; 333 const u32 _min = 1; 334 int ret; 335 336 if (!in_range(val, _min, _max) || val2 != 0) 337 return -EINVAL; 338 339 /* 1 disables oversampling */ 340 val = ilog2(val); 341 if (val == 0) { 342 st->mode = AD4062_SAMPLE_MODE; 343 } else { 344 st->mode = AD4062_BURST_AVERAGING_MODE; 345 ret = regmap_write(st->regmap, AD4062_REG_AVG_CONFIG, val - 1); 346 if (ret) 347 return ret; 348 } 349 st->oversamp_ratio = val; 350 351 return 0; 352 } 353 354 static int ad4062_get_oversampling_ratio(struct ad4062_state *st, int *val) 355 { 356 int ret, buf; 357 358 if (st->mode == AD4062_SAMPLE_MODE) { 359 *val = 1; 360 return 0; 361 } 362 363 ret = regmap_read(st->regmap, AD4062_REG_AVG_CONFIG, &buf); 364 if (ret) 365 return ret; 366 367 *val = BIT(buf + 1); 368 return 0; 369 } 370 371 static int ad4062_calc_sampling_frequency(unsigned int fosc, unsigned int oversamp_ratio) 372 { 373 /* From datasheet p.31: (n_avg - 1)/fosc + tconv */ 374 u32 n_avg = BIT(oversamp_ratio) - 1; 375 u32 period_ns = NSEC_PER_SEC / fosc; 376 377 /* Result is less than 1 Hz */ 378 if (n_avg >= fosc) 379 return 1; 380 381 return NSEC_PER_SEC / (n_avg * period_ns + AD4062_TCONV_NS); 382 } 383 384 static int ad4062_populate_sampling_frequency(struct ad4062_state *st) 385 { 386 for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) 387 st->samp_freqs[i] = 388 ad4062_calc_sampling_frequency(ad4062_conversion_freqs[i], 389 st->oversamp_ratio); 390 return 0; 391 } 392 393 static int ad4062_get_sampling_frequency(struct ad4062_state *st, int *val) 394 { 395 int freq = ad4062_conversion_freqs[st->sampling_frequency]; 396 397 *val = ad4062_calc_sampling_frequency(freq, st->oversamp_ratio); 398 return IIO_VAL_INT; 399 } 400 401 static int ad4062_set_sampling_frequency(struct ad4062_state *st, int val, int val2) 402 { 403 int ret; 404 405 if (val2 != 0) 406 return -EINVAL; 407 408 ret = ad4062_populate_sampling_frequency(st); 409 if (ret) 410 return ret; 411 412 st->sampling_frequency = 413 find_closest_descending(val, st->samp_freqs, 414 ARRAY_SIZE(ad4062_conversion_freqs)); 415 return 0; 416 } 417 418 static int ad4062_check_ids(struct ad4062_state *st) 419 { 420 struct device *dev = &st->i3cdev->dev; 421 int ret; 422 u16 val; 423 424 ret = regmap_bulk_read(st->regmap, AD4062_REG_PROD_ID_1, 425 &st->buf.be16, sizeof(st->buf.be16)); 426 if (ret) 427 return ret; 428 429 val = be16_to_cpu(st->buf.be16); 430 if (val != st->chip->prod_id) 431 dev_warn(dev, "Production ID x%x does not match known values", val); 432 433 ret = regmap_bulk_read(st->regmap, AD4062_REG_VENDOR_H, 434 &st->buf.be16, sizeof(st->buf.be16)); 435 if (ret) 436 return ret; 437 438 val = be16_to_cpu(st->buf.be16); 439 if (val != AD4062_I3C_VENDOR) { 440 dev_err(dev, "Vendor ID x%x does not match expected value\n", val); 441 return -ENODEV; 442 } 443 444 return 0; 445 } 446 447 static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val) 448 { 449 return regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG, 450 FIELD_PREP(AD4062_REG_TIMER_CONFIG_FS_MASK, val)); 451 } 452 453 static int ad4062_set_operation_mode(struct ad4062_state *st, 454 enum ad4062_operation_mode mode) 455 { 456 const unsigned int samp_freq = mode == AD4062_MONITOR_MODE ? 457 st->events_frequency : st->sampling_frequency; 458 int ret; 459 460 ret = ad4062_conversion_frequency_set(st, samp_freq); 461 if (ret) 462 return ret; 463 464 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_MODES, 465 AD4062_REG_ADC_MODES_MODE_MSK, mode); 466 if (ret) 467 return ret; 468 469 if (mode == AD4062_MONITOR_MODE) { 470 /* Change address pointer to enter monitor mode */ 471 struct i3c_xfer xfer_trigger = { 472 .data.out = &st->conv_addr, 473 .len = sizeof(st->conv_addr), 474 .rnw = false, 475 }; 476 st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS; 477 return i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR); 478 } 479 480 return regmap_write(st->regmap, AD4062_REG_MODE_SET, 481 AD4062_REG_MODE_SET_ENTER_ADC); 482 } 483 484 static int ad4062_soft_reset(struct ad4062_state *st) 485 { 486 u8 val = AD4062_SOFT_RESET; 487 int ret; 488 489 ret = regmap_write(st->regmap, AD4062_REG_INTERFACE_CONFIG_A, val); 490 if (ret) 491 return ret; 492 493 /* Wait AD4062 treset time, datasheet p8 */ 494 ndelay(60); 495 496 return 0; 497 } 498 499 static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 500 const bool *ref_sel) 501 { 502 struct ad4062_state *st = iio_priv(indio_dev); 503 const struct iio_scan_type *scan_type; 504 int ret; 505 506 scan_type = iio_get_current_scan_type(indio_dev, chan); 507 if (IS_ERR(scan_type)) 508 return PTR_ERR(scan_type); 509 510 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 511 AD4062_REG_GP_CONF_MODE_MSK_0, 512 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, 513 AD4062_GP_INTR)); 514 if (ret) 515 return ret; 516 517 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 518 AD4062_REG_GP_CONF_MODE_MSK_1, 519 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, 520 AD4062_GP_DRDY)); 521 if (ret) 522 return ret; 523 524 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, 525 AD4062_REG_ADC_CONFIG_REF_EN_MSK, 526 FIELD_PREP(AD4062_REG_ADC_CONFIG_REF_EN_MSK, 527 *ref_sel)); 528 if (ret) 529 return ret; 530 531 ret = regmap_write(st->regmap, AD4062_REG_DEVICE_STATUS, 532 AD4062_REG_DEVICE_STATUS_DEVICE_RESET); 533 if (ret) 534 return ret; 535 536 ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, 537 AD4062_REG_INTR_CONF_EN_MSK_0, 538 FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_0, 539 AD4062_INTR_EN_EITHER)); 540 if (ret) 541 return ret; 542 543 ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, 544 AD4062_REG_INTR_CONF_EN_MSK_1, 545 FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1, 546 AD4062_INTR_EN_NEITHER)); 547 if (ret) 548 return ret; 549 550 st->buf.be16 = cpu_to_be16(AD4062_MON_VAL_MIDDLE_POINT); 551 return regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, 552 &st->buf.be16, sizeof(st->buf.be16)); 553 } 554 555 static irqreturn_t ad4062_irq_handler_thresh(int irq, void *private) 556 { 557 struct iio_dev *indio_dev = private; 558 559 iio_push_event(indio_dev, 560 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 561 IIO_EV_TYPE_THRESH, 562 IIO_EV_DIR_EITHER), 563 iio_get_time_ns(indio_dev)); 564 565 return IRQ_HANDLED; 566 } 567 568 static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private) 569 { 570 struct iio_dev *indio_dev = private; 571 struct ad4062_state *st = iio_priv(indio_dev); 572 573 if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev)) 574 iio_trigger_poll(st->trigger); 575 else 576 complete(&st->completion); 577 578 return IRQ_HANDLED; 579 } 580 581 static void ad4062_ibi_handler(struct i3c_device *i3cdev, 582 const struct i3c_ibi_payload *payload) 583 { 584 struct ad4062_state *st = i3cdev_get_drvdata(i3cdev); 585 586 if (st->wait_event) { 587 iio_push_event(st->indio_dev, 588 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 589 IIO_EV_TYPE_THRESH, 590 IIO_EV_DIR_EITHER), 591 iio_get_time_ns(st->indio_dev)); 592 return; 593 } 594 if (iio_buffer_enabled(st->indio_dev)) 595 iio_trigger_poll_nested(st->trigger); 596 else 597 complete(&st->completion); 598 } 599 600 static void ad4062_trigger_work(struct work_struct *work) 601 { 602 struct ad4062_state *st = 603 container_of(work, struct ad4062_state, trig_conv); 604 int ret; 605 606 /* 607 * Read current conversion, if at reg CONV_READ, stop bit triggers 608 * next sample and does not need writing the address. 609 */ 610 struct i3c_xfer xfer_sample = { 611 .data.in = &st->buf.be32, 612 .len = st->conv_sizeof, 613 .rnw = true, 614 }; 615 struct i3c_xfer xfer_trigger = { 616 .data.out = &st->conv_addr, 617 .len = sizeof(st->conv_addr), 618 .rnw = false, 619 }; 620 621 ret = i3c_device_do_xfers(st->i3cdev, &xfer_sample, 1, I3C_SDR); 622 if (ret) 623 return; 624 625 iio_push_to_buffers_with_ts(st->indio_dev, &st->buf.be32, st->conv_sizeof, 626 iio_get_time_ns(st->indio_dev)); 627 if (st->gpo_irq[1]) 628 return; 629 630 i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR); 631 } 632 633 static irqreturn_t ad4062_poll_handler(int irq, void *p) 634 { 635 struct iio_poll_func *pf = p; 636 struct iio_dev *indio_dev = pf->indio_dev; 637 struct ad4062_state *st = iio_priv(indio_dev); 638 639 iio_trigger_notify_done(indio_dev->trig); 640 schedule_work(&st->trig_conv); 641 642 return IRQ_HANDLED; 643 } 644 645 static void ad4062_disable_ibi(void *data) 646 { 647 struct i3c_device *i3cdev = data; 648 649 i3c_device_disable_ibi(i3cdev); 650 } 651 652 static void ad4062_free_ibi(void *data) 653 { 654 struct i3c_device *i3cdev = data; 655 656 i3c_device_free_ibi(i3cdev); 657 } 658 659 static int ad4062_request_ibi(struct i3c_device *i3cdev) 660 { 661 const struct i3c_ibi_setup ibireq = { 662 .max_payload_len = 1, 663 .num_slots = 1, 664 .handler = ad4062_ibi_handler, 665 }; 666 int ret; 667 668 ret = i3c_device_request_ibi(i3cdev, &ibireq); 669 if (ret) 670 return ret; 671 672 ret = devm_add_action_or_reset(&i3cdev->dev, ad4062_free_ibi, i3cdev); 673 if (ret) 674 return ret; 675 676 ret = i3c_device_enable_ibi(i3cdev); 677 if (ret) 678 return ret; 679 680 return devm_add_action_or_reset(&i3cdev->dev, ad4062_disable_ibi, i3cdev); 681 } 682 683 static int ad4062_request_irq(struct iio_dev *indio_dev) 684 { 685 struct ad4062_state *st = iio_priv(indio_dev); 686 struct device *dev = &st->i3cdev->dev; 687 int ret; 688 689 ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp0"); 690 if (ret == -EPROBE_DEFER) 691 return ret; 692 693 if (ret < 0) { 694 st->gpo_irq[0] = false; 695 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, 696 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN, 697 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN); 698 if (ret) 699 return ret; 700 } else { 701 st->gpo_irq[0] = true; 702 ret = devm_request_threaded_irq(dev, ret, NULL, 703 ad4062_irq_handler_thresh, 704 IRQF_ONESHOT, indio_dev->name, 705 indio_dev); 706 if (ret) 707 return ret; 708 } 709 710 ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp1"); 711 if (ret == -EPROBE_DEFER) 712 return ret; 713 714 if (ret < 0) { 715 st->gpo_irq[1] = false; 716 return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, 717 AD4062_REG_ADC_IBI_EN_CONV_TRIGGER, 718 AD4062_REG_ADC_IBI_EN_CONV_TRIGGER); 719 } 720 st->gpo_irq[1] = true; 721 722 return devm_request_threaded_irq(dev, ret, 723 ad4062_irq_handler_drdy, 724 NULL, IRQF_ONESHOT, indio_dev->name, 725 indio_dev); 726 } 727 728 static const struct iio_trigger_ops ad4062_trigger_ops = { 729 .validate_device = &iio_trigger_validate_own_device, 730 }; 731 732 static int ad4062_request_trigger(struct iio_dev *indio_dev) 733 { 734 struct ad4062_state *st = iio_priv(indio_dev); 735 struct device *dev = &st->i3cdev->dev; 736 int ret; 737 738 st->trigger = devm_iio_trigger_alloc(dev, "%s-dev%d", 739 indio_dev->name, 740 iio_device_id(indio_dev)); 741 if (!st->trigger) 742 return -ENOMEM; 743 744 st->trigger->ops = &ad4062_trigger_ops; 745 iio_trigger_set_drvdata(st->trigger, indio_dev); 746 747 ret = devm_iio_trigger_register(dev, st->trigger); 748 if (ret) 749 return ret; 750 751 indio_dev->trig = iio_trigger_get(st->trigger); 752 753 return 0; 754 } 755 756 static const int ad4062_oversampling_avail[] = { 757 1, 2, 4, 8, 16, 32, 64, 128, /* 0 - 7 */ 758 256, 512, 1024, 2048, 4096, /* 8 - 12 */ 759 }; 760 761 static int ad4062_read_avail(struct iio_dev *indio_dev, 762 struct iio_chan_spec const *chan, const int **vals, 763 int *type, int *len, long mask) 764 { 765 struct ad4062_state *st = iio_priv(indio_dev); 766 int ret; 767 768 switch (mask) { 769 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 770 *vals = ad4062_oversampling_avail; 771 *len = ARRAY_SIZE(ad4062_oversampling_avail); 772 *len -= st->chip->avg_max == 256 ? 4 : 0; 773 *type = IIO_VAL_INT; 774 775 return IIO_AVAIL_LIST; 776 case IIO_CHAN_INFO_SAMP_FREQ: 777 ret = ad4062_populate_sampling_frequency(st); 778 if (ret) 779 return ret; 780 *vals = st->samp_freqs; 781 *len = st->oversamp_ratio ? ARRAY_SIZE(ad4062_conversion_freqs) : 1; 782 *type = IIO_VAL_INT; 783 784 return IIO_AVAIL_LIST; 785 default: 786 return -EINVAL; 787 } 788 } 789 790 static int ad4062_get_chan_scale(struct iio_dev *indio_dev, int *val, int *val2) 791 { 792 struct ad4062_state *st = iio_priv(indio_dev); 793 const struct iio_scan_type *scan_type; 794 795 /* 796 * In burst averaging mode the averaging filter accumulates resulting 797 * in a sample with increased precision. 798 */ 799 scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels); 800 if (IS_ERR(scan_type)) 801 return PTR_ERR(scan_type); 802 803 *val = (st->vref_uV * 2) / (MICRO / MILLI); /* signed */ 804 *val2 = scan_type->realbits - 1; 805 806 return IIO_VAL_FRACTIONAL_LOG2; 807 } 808 809 static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2) 810 { 811 int ret; 812 813 ret = regmap_bulk_read(st->regmap, AD4062_REG_MON_VAL, 814 &st->buf.be16, sizeof(st->buf.be16)); 815 if (ret) 816 return ret; 817 818 /* From datasheet: code out = code in × mon_val/0x8000 */ 819 *val = be16_to_cpu(st->buf.be16) * 2; 820 *val2 = 16; 821 822 return IIO_VAL_FRACTIONAL_LOG2; 823 } 824 825 static int ad4062_set_chan_calibscale(struct ad4062_state *st, int gain_int, 826 int gain_frac) 827 { 828 /* Divide numerator and denumerator by known great common divider */ 829 const u32 mon_val = AD4062_MON_VAL_MIDDLE_POINT / 64; 830 const u32 micro = MICRO / 64; 831 const u32 gain_fp = gain_int * MICRO + gain_frac; 832 const u32 reg_val = DIV_ROUND_CLOSEST(gain_fp * mon_val, micro); 833 int ret; 834 835 /* Checks if the gain is in range and the value fits the field */ 836 if (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1) 837 return -EINVAL; 838 839 st->buf.be16 = cpu_to_be16(reg_val); 840 ret = regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, 841 &st->buf.be16, sizeof(st->buf.be16)); 842 if (ret) 843 return ret; 844 845 /* Enable scale if gain is not equal to one */ 846 return regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, 847 AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, 848 FIELD_PREP(AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, 849 !(gain_int == 1 && gain_frac == 0))); 850 } 851 852 static int ad4062_read_chan_raw(struct ad4062_state *st, int *val) 853 { 854 struct i3c_device *i3cdev = st->i3cdev; 855 struct i3c_xfer xfer_trigger = { 856 .data.out = &st->conv_addr, 857 .len = sizeof(st->conv_addr), 858 .rnw = false, 859 }; 860 struct i3c_xfer xfer_sample = { 861 .data.in = &st->buf.be32, 862 .len = sizeof(st->buf.be32), 863 .rnw = true, 864 }; 865 int ret; 866 867 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 868 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 869 if (ret) 870 return ret; 871 872 ret = ad4062_set_operation_mode(st, st->mode); 873 if (ret) 874 return ret; 875 876 reinit_completion(&st->completion); 877 /* Change address pointer to trigger conversion */ 878 st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS; 879 ret = i3c_device_do_xfers(i3cdev, &xfer_trigger, 1, I3C_SDR); 880 if (ret) 881 return ret; 882 /* 883 * Single sample read should be used only for oversampling and 884 * sampling frequency pairs that take less than 1 sec. 885 */ 886 ret = wait_for_completion_timeout(&st->completion, 887 msecs_to_jiffies(1000)); 888 if (!ret) 889 return -ETIMEDOUT; 890 891 ret = i3c_device_do_xfers(i3cdev, &xfer_sample, 1, I3C_SDR); 892 if (ret) 893 return ret; 894 *val = be32_to_cpu(st->buf.be32); 895 return 0; 896 } 897 898 static int ad4062_read_raw_dispatch(struct ad4062_state *st, 899 int *val, int *val2, long info) 900 { 901 if (st->wait_event) 902 return -EBUSY; 903 904 switch (info) { 905 case IIO_CHAN_INFO_RAW: 906 return ad4062_read_chan_raw(st, val); 907 908 case IIO_CHAN_INFO_CALIBSCALE: 909 return ad4062_get_chan_calibscale(st, val, val2); 910 911 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 912 return ad4062_get_oversampling_ratio(st, val); 913 914 default: 915 return -EINVAL; 916 } 917 } 918 919 static int ad4062_read_raw(struct iio_dev *indio_dev, 920 struct iio_chan_spec const *chan, 921 int *val, int *val2, long info) 922 { 923 struct ad4062_state *st = iio_priv(indio_dev); 924 int ret; 925 926 switch (info) { 927 case IIO_CHAN_INFO_SCALE: 928 return ad4062_get_chan_scale(indio_dev, val, val2); 929 930 case IIO_CHAN_INFO_SAMP_FREQ: 931 return ad4062_get_sampling_frequency(st, val); 932 } 933 934 if (!iio_device_claim_direct(indio_dev)) 935 return -EBUSY; 936 937 ret = ad4062_read_raw_dispatch(st, val, val2, info); 938 iio_device_release_direct(indio_dev); 939 return ret ?: IIO_VAL_INT; 940 } 941 942 static int ad4062_write_raw_dispatch(struct ad4062_state *st, int val, int val2, 943 long info) 944 { 945 if (st->wait_event) 946 return -EBUSY; 947 948 switch (info) { 949 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 950 return ad4062_set_oversampling_ratio(st, val, val2); 951 952 case IIO_CHAN_INFO_CALIBSCALE: 953 return ad4062_set_chan_calibscale(st, val, val2); 954 955 default: 956 return -EINVAL; 957 } 958 }; 959 960 static int ad4062_write_raw(struct iio_dev *indio_dev, 961 struct iio_chan_spec const *chan, int val, 962 int val2, long info) 963 { 964 struct ad4062_state *st = iio_priv(indio_dev); 965 int ret; 966 967 switch (info) { 968 case IIO_CHAN_INFO_SAMP_FREQ: 969 return ad4062_set_sampling_frequency(st, val, val2); 970 } 971 972 if (!iio_device_claim_direct(indio_dev)) 973 return -EBUSY; 974 975 ret = ad4062_write_raw_dispatch(st, val, val2, info); 976 iio_device_release_direct(indio_dev); 977 return ret; 978 } 979 980 static int pm_ad4062_monitor_mode_enable(struct ad4062_state *st) 981 { 982 int ret; 983 984 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 985 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 986 if (ret) 987 return ret; 988 989 return ad4062_set_operation_mode(st, AD4062_MONITOR_MODE); 990 } 991 992 static int ad4062_monitor_mode_enable(struct ad4062_state *st) 993 { 994 int ret; 995 996 ret = pm_ad4062_monitor_mode_enable(st); 997 if (ret) 998 return ret; 999 1000 pm_runtime_get_noresume(&st->i3cdev->dev); 1001 return 0; 1002 } 1003 1004 static int ad4062_monitor_mode_disable(struct ad4062_state *st) 1005 { 1006 pm_runtime_put_autosuspend(&st->i3cdev->dev); 1007 return 0; 1008 } 1009 1010 static int ad4062_read_event_config(struct iio_dev *indio_dev, 1011 const struct iio_chan_spec *chan, 1012 enum iio_event_type type, 1013 enum iio_event_direction dir) 1014 { 1015 struct ad4062_state *st = iio_priv(indio_dev); 1016 1017 return st->wait_event; 1018 } 1019 1020 static int ad4062_write_event_config_dispatch(struct iio_dev *indio_dev, 1021 bool state) 1022 { 1023 struct ad4062_state *st = iio_priv(indio_dev); 1024 int ret; 1025 1026 if (st->wait_event == state) 1027 ret = 0; 1028 else if (state) 1029 ret = ad4062_monitor_mode_enable(st); 1030 else 1031 ret = ad4062_monitor_mode_disable(st); 1032 if (ret) 1033 return ret; 1034 1035 st->wait_event = state; 1036 return 0; 1037 } 1038 1039 static int ad4062_write_event_config(struct iio_dev *indio_dev, 1040 const struct iio_chan_spec *chan, 1041 enum iio_event_type type, 1042 enum iio_event_direction dir, 1043 bool state) 1044 { 1045 int ret; 1046 1047 if (!iio_device_claim_direct(indio_dev)) 1048 return -EBUSY; 1049 1050 ret = ad4062_write_event_config_dispatch(indio_dev, state); 1051 iio_device_release_direct(indio_dev); 1052 return ret; 1053 } 1054 1055 static int __ad4062_read_event_info_value(struct ad4062_state *st, 1056 enum iio_event_direction dir, int *val) 1057 { 1058 int ret; 1059 u8 reg; 1060 1061 if (dir == IIO_EV_DIR_RISING) 1062 reg = AD4062_REG_MAX_LIMIT; 1063 else 1064 reg = AD4062_REG_MIN_LIMIT; 1065 1066 ret = regmap_bulk_read(st->regmap, reg, &st->buf.be16, 1067 sizeof(st->buf.be16)); 1068 if (ret) 1069 return ret; 1070 1071 *val = sign_extend32(be16_to_cpu(st->buf.be16), AD4062_LIMIT_BITS - 1); 1072 1073 return 0; 1074 } 1075 1076 static int __ad4062_read_event_info_hysteresis(struct ad4062_state *st, 1077 enum iio_event_direction dir, int *val) 1078 { 1079 u8 reg; 1080 1081 if (dir == IIO_EV_DIR_RISING) 1082 reg = AD4062_REG_MAX_HYST; 1083 else 1084 reg = AD4062_REG_MIN_HYST; 1085 return regmap_read(st->regmap, reg, val); 1086 } 1087 1088 static int ad4062_read_event_config_dispatch(struct iio_dev *indio_dev, 1089 enum iio_event_direction dir, 1090 enum iio_event_info info, int *val) 1091 { 1092 struct ad4062_state *st = iio_priv(indio_dev); 1093 1094 if (st->wait_event) 1095 return -EBUSY; 1096 1097 switch (info) { 1098 case IIO_EV_INFO_VALUE: 1099 return __ad4062_read_event_info_value(st, dir, val); 1100 case IIO_EV_INFO_HYSTERESIS: 1101 return __ad4062_read_event_info_hysteresis(st, dir, val); 1102 default: 1103 return -EINVAL; 1104 } 1105 } 1106 1107 static int ad4062_read_event_value(struct iio_dev *indio_dev, 1108 const struct iio_chan_spec *chan, 1109 enum iio_event_type type, 1110 enum iio_event_direction dir, 1111 enum iio_event_info info, int *val, 1112 int *val2) 1113 { 1114 int ret; 1115 1116 if (!iio_device_claim_direct(indio_dev)) 1117 return -EBUSY; 1118 1119 ret = ad4062_read_event_config_dispatch(indio_dev, dir, info, val); 1120 iio_device_release_direct(indio_dev); 1121 return ret ?: IIO_VAL_INT; 1122 } 1123 1124 static int __ad4062_write_event_info_value(struct ad4062_state *st, 1125 enum iio_event_direction dir, int val) 1126 { 1127 u8 reg; 1128 1129 if (val != sign_extend32(val, AD4062_LIMIT_BITS - 1)) 1130 return -EINVAL; 1131 if (dir == IIO_EV_DIR_RISING) 1132 reg = AD4062_REG_MAX_LIMIT; 1133 else 1134 reg = AD4062_REG_MIN_LIMIT; 1135 st->buf.be16 = cpu_to_be16(val); 1136 1137 return regmap_bulk_write(st->regmap, reg, &st->buf.be16, 1138 sizeof(st->buf.be16)); 1139 } 1140 1141 static int __ad4062_write_event_info_hysteresis(struct ad4062_state *st, 1142 enum iio_event_direction dir, int val) 1143 { 1144 u8 reg; 1145 1146 if (val > BIT(7) - 1) 1147 return -EINVAL; 1148 if (dir == IIO_EV_DIR_RISING) 1149 reg = AD4062_REG_MAX_HYST; 1150 else 1151 reg = AD4062_REG_MIN_HYST; 1152 1153 return regmap_write(st->regmap, reg, val); 1154 } 1155 1156 static int ad4062_write_event_value_dispatch(struct iio_dev *indio_dev, 1157 enum iio_event_type type, 1158 enum iio_event_direction dir, 1159 enum iio_event_info info, int val) 1160 { 1161 struct ad4062_state *st = iio_priv(indio_dev); 1162 1163 if (st->wait_event) 1164 return -EBUSY; 1165 1166 switch (type) { 1167 case IIO_EV_TYPE_THRESH: 1168 switch (info) { 1169 case IIO_EV_INFO_VALUE: 1170 return __ad4062_write_event_info_value(st, dir, val); 1171 case IIO_EV_INFO_HYSTERESIS: 1172 return __ad4062_write_event_info_hysteresis(st, dir, val); 1173 default: 1174 return -EINVAL; 1175 } 1176 default: 1177 return -EINVAL; 1178 } 1179 } 1180 1181 static int ad4062_write_event_value(struct iio_dev *indio_dev, 1182 const struct iio_chan_spec *chan, 1183 enum iio_event_type type, 1184 enum iio_event_direction dir, 1185 enum iio_event_info info, int val, 1186 int val2) 1187 { 1188 int ret; 1189 1190 if (!iio_device_claim_direct(indio_dev)) 1191 return -EBUSY; 1192 1193 ret = ad4062_write_event_value_dispatch(indio_dev, type, dir, info, val); 1194 iio_device_release_direct(indio_dev); 1195 return ret; 1196 } 1197 1198 /* 1199 * The AD4062 in burst averaging mode increases realbits from 16-bits to 1200 * 20-bits, increasing the storagebits from 16-bits to 32-bits. 1201 */ 1202 static inline size_t ad4062_sizeof_storagebits(struct ad4062_state *st) 1203 { 1204 const struct iio_scan_type *scan_type = 1205 iio_get_current_scan_type(st->indio_dev, st->chip->channels); 1206 1207 return BITS_TO_BYTES(scan_type->storagebits); 1208 } 1209 1210 /* Read registers only with realbits (no sign extension bytes) */ 1211 static inline size_t ad4062_get_conv_addr(struct ad4062_state *st, size_t _sizeof) 1212 { 1213 if (st->gpo_irq[1]) 1214 return _sizeof == sizeof(u32) ? AD4062_REG_CONV_READ_32BITS : 1215 AD4062_REG_CONV_READ_16BITS; 1216 return _sizeof == sizeof(u32) ? AD4062_REG_CONV_TRIGGER_32BITS : 1217 AD4062_REG_CONV_TRIGGER_16BITS; 1218 } 1219 1220 static int pm_ad4062_triggered_buffer_postenable(struct ad4062_state *st) 1221 { 1222 int ret; 1223 1224 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 1225 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 1226 if (ret) 1227 return ret; 1228 1229 if (st->wait_event) 1230 return -EBUSY; 1231 1232 ret = ad4062_set_operation_mode(st, st->mode); 1233 if (ret) 1234 return ret; 1235 1236 st->conv_sizeof = ad4062_sizeof_storagebits(st); 1237 st->conv_addr = ad4062_get_conv_addr(st, st->conv_sizeof); 1238 /* CONV_READ requires read to trigger first sample. */ 1239 struct i3c_xfer xfer_sample[2] = { 1240 { 1241 .data.out = &st->conv_addr, 1242 .len = sizeof(st->conv_addr), 1243 .rnw = false, 1244 }, 1245 { 1246 .data.in = &st->buf.be32, 1247 .len = sizeof(st->buf.be32), 1248 .rnw = true, 1249 } 1250 }; 1251 1252 return i3c_device_do_xfers(st->i3cdev, xfer_sample, 1253 st->gpo_irq[1] ? 2 : 1, I3C_SDR); 1254 } 1255 1256 static int ad4062_triggered_buffer_postenable(struct iio_dev *indio_dev) 1257 { 1258 struct ad4062_state *st = iio_priv(indio_dev); 1259 int ret; 1260 1261 ret = pm_ad4062_triggered_buffer_postenable(st); 1262 if (ret) 1263 return ret; 1264 1265 pm_runtime_get_noresume(&st->i3cdev->dev); 1266 return 0; 1267 } 1268 1269 static int ad4062_triggered_buffer_predisable(struct iio_dev *indio_dev) 1270 { 1271 struct ad4062_state *st = iio_priv(indio_dev); 1272 1273 pm_runtime_put_autosuspend(&st->i3cdev->dev); 1274 return 0; 1275 } 1276 1277 static const struct iio_buffer_setup_ops ad4062_triggered_buffer_setup_ops = { 1278 .postenable = &ad4062_triggered_buffer_postenable, 1279 .predisable = &ad4062_triggered_buffer_predisable, 1280 }; 1281 1282 static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1283 unsigned int writeval, unsigned int *readval) 1284 { 1285 struct ad4062_state *st = iio_priv(indio_dev); 1286 1287 if (readval) 1288 return regmap_read(st->regmap, reg, readval); 1289 else 1290 return regmap_write(st->regmap, reg, writeval); 1291 } 1292 1293 static int ad4062_get_current_scan_type(const struct iio_dev *indio_dev, 1294 const struct iio_chan_spec *chan) 1295 { 1296 struct ad4062_state *st = iio_priv(indio_dev); 1297 1298 return st->mode == AD4062_BURST_AVERAGING_MODE ? 1299 AD4062_SCAN_TYPE_BURST_AVG : 1300 AD4062_SCAN_TYPE_SAMPLE; 1301 } 1302 1303 static const struct iio_info ad4062_info = { 1304 .read_raw = ad4062_read_raw, 1305 .write_raw = ad4062_write_raw, 1306 .read_avail = ad4062_read_avail, 1307 .read_event_config = ad4062_read_event_config, 1308 .write_event_config = ad4062_write_event_config, 1309 .read_event_value = ad4062_read_event_value, 1310 .write_event_value = ad4062_write_event_value, 1311 .event_attrs = &ad4062_event_attribute_group, 1312 .get_current_scan_type = ad4062_get_current_scan_type, 1313 .debugfs_reg_access = ad4062_debugfs_reg_access, 1314 }; 1315 1316 static const struct regmap_config ad4062_regmap_config = { 1317 .name = "ad4062", 1318 .reg_bits = 8, 1319 .val_bits = 8, 1320 .max_register = AD4062_MAX_REG, 1321 .rd_table = &ad4062_regmap_rd_table, 1322 .wr_table = &ad4062_regmap_wr_table, 1323 .can_sleep = true, 1324 }; 1325 1326 static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel) 1327 { 1328 struct device *dev = &st->i3cdev->dev; 1329 int ret; 1330 1331 ret = devm_regulator_get_enable(dev, "vio"); 1332 if (ret) 1333 return dev_err_probe(dev, ret, "Failed to enable vio voltage\n"); 1334 1335 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref"); 1336 *ref_sel = st->vref_uV == -ENODEV; 1337 if (st->vref_uV < 0 && !*ref_sel) 1338 return dev_err_probe(dev, st->vref_uV, 1339 "Failed to enable and read ref voltage\n"); 1340 1341 if (*ref_sel) { 1342 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "vdd"); 1343 if (st->vref_uV < 0) 1344 return dev_err_probe(dev, st->vref_uV, 1345 "Failed to enable and read vdd voltage\n"); 1346 } else { 1347 ret = devm_regulator_get_enable(dev, "vdd"); 1348 if (ret) 1349 return dev_err_probe(dev, ret, 1350 "Failed to enable vdd regulator\n"); 1351 } 1352 1353 return 0; 1354 } 1355 1356 static int ad4062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1357 { 1358 return GPIO_LINE_DIRECTION_OUT; 1359 } 1360 1361 static int ad4062_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1362 { 1363 struct ad4062_state *st = gpiochip_get_data(gc); 1364 unsigned int reg_val = value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC_LOW; 1365 1366 if (offset) 1367 return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1368 AD4062_REG_GP_CONF_MODE_MSK_1, 1369 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val)); 1370 else 1371 return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1372 AD4062_REG_GP_CONF_MODE_MSK_0, 1373 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val)); 1374 } 1375 1376 static int ad4062_gpio_get(struct gpio_chip *gc, unsigned int offset) 1377 { 1378 struct ad4062_state *st = gpiochip_get_data(gc); 1379 unsigned int reg_val; 1380 int ret; 1381 1382 ret = regmap_read(st->regmap, AD4062_REG_GP_CONF, ®_val); 1383 if (ret) 1384 return ret; 1385 1386 if (offset) 1387 reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val); 1388 else 1389 reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val); 1390 1391 return reg_val == AD4062_GP_STATIC_HIGH; 1392 } 1393 1394 static void ad4062_gpio_disable(void *data) 1395 { 1396 struct ad4062_state *st = data; 1397 u8 val = FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_DISABLED) | 1398 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DISABLED); 1399 1400 regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1401 AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0, 1402 val); 1403 } 1404 1405 static int ad4062_gpio_init_valid_mask(struct gpio_chip *gc, 1406 unsigned long *valid_mask, 1407 unsigned int ngpios) 1408 { 1409 struct ad4062_state *st = gpiochip_get_data(gc); 1410 1411 bitmap_zero(valid_mask, ngpios); 1412 1413 for (unsigned int i = 0; i < ARRAY_SIZE(st->gpo_irq); i++) 1414 __assign_bit(i, valid_mask, !st->gpo_irq[i]); 1415 1416 return 0; 1417 } 1418 1419 static int ad4062_gpio_init(struct ad4062_state *st) 1420 { 1421 struct device *dev = &st->i3cdev->dev; 1422 struct gpio_chip *gc; 1423 u8 val, mask; 1424 int ret; 1425 1426 if (!device_property_read_bool(dev, "gpio-controller")) 1427 return 0; 1428 1429 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1430 if (!gc) 1431 return -ENOMEM; 1432 1433 val = 0; 1434 mask = 0; 1435 if (!st->gpo_irq[0]) { 1436 mask |= AD4062_REG_GP_CONF_MODE_MSK_0; 1437 val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_STATIC_LOW); 1438 } 1439 if (!st->gpo_irq[1]) { 1440 mask |= AD4062_REG_GP_CONF_MODE_MSK_1; 1441 val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_STATIC_LOW); 1442 } 1443 1444 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1445 mask, val); 1446 if (ret) 1447 return ret; 1448 1449 ret = devm_add_action_or_reset(dev, ad4062_gpio_disable, st); 1450 if (ret) 1451 return ret; 1452 1453 gc->parent = dev; 1454 gc->label = st->chip->name; 1455 gc->owner = THIS_MODULE; 1456 gc->base = -1; 1457 gc->ngpio = 2; 1458 gc->init_valid_mask = ad4062_gpio_init_valid_mask; 1459 gc->get_direction = ad4062_gpio_get_direction; 1460 gc->set = ad4062_gpio_set; 1461 gc->get = ad4062_gpio_get; 1462 gc->can_sleep = true; 1463 1464 ret = devm_gpiochip_add_data(dev, gc, st); 1465 if (ret) 1466 return dev_err_probe(dev, ret, "Unable to register GPIO chip\n"); 1467 1468 return 0; 1469 } 1470 1471 static const struct i3c_device_id ad4062_id_table[] = { 1472 I3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info), 1473 I3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info), 1474 { } 1475 }; 1476 MODULE_DEVICE_TABLE(i3c, ad4062_id_table); 1477 1478 static int ad4062_probe(struct i3c_device *i3cdev) 1479 { 1480 const struct i3c_device_id *id = i3c_device_match_id(i3cdev, ad4062_id_table); 1481 const struct ad4062_chip_info *chip = id->data; 1482 struct device *dev = &i3cdev->dev; 1483 struct iio_dev *indio_dev; 1484 struct ad4062_state *st; 1485 bool ref_sel; 1486 int ret; 1487 1488 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1489 if (!indio_dev) 1490 return -ENOMEM; 1491 1492 st = iio_priv(indio_dev); 1493 st->i3cdev = i3cdev; 1494 i3cdev_set_drvdata(i3cdev, st); 1495 init_completion(&st->completion); 1496 1497 ret = ad4062_regulators_get(st, &ref_sel); 1498 if (ret) 1499 return ret; 1500 1501 st->regmap = devm_regmap_init_i3c(i3cdev, &ad4062_regmap_config); 1502 if (IS_ERR(st->regmap)) 1503 return dev_err_probe(dev, PTR_ERR(st->regmap), 1504 "Failed to initialize regmap\n"); 1505 1506 st->mode = AD4062_SAMPLE_MODE; 1507 st->wait_event = false; 1508 st->chip = chip; 1509 st->sampling_frequency = 0; 1510 st->events_frequency = 0; 1511 st->oversamp_ratio = 0; 1512 st->indio_dev = indio_dev; 1513 1514 indio_dev->modes = INDIO_DIRECT_MODE; 1515 indio_dev->num_channels = 1; 1516 indio_dev->info = &ad4062_info; 1517 indio_dev->name = chip->name; 1518 indio_dev->channels = chip->channels; 1519 1520 ret = ad4062_soft_reset(st); 1521 if (ret) 1522 return dev_err_probe(dev, ret, "AD4062 failed to soft reset\n"); 1523 1524 ret = ad4062_check_ids(st); 1525 if (ret) 1526 return ret; 1527 1528 ret = ad4062_setup(indio_dev, indio_dev->channels, &ref_sel); 1529 if (ret) 1530 return ret; 1531 1532 ret = ad4062_request_irq(indio_dev); 1533 if (ret) 1534 return ret; 1535 1536 ret = ad4062_request_trigger(indio_dev); 1537 if (ret) 1538 return ret; 1539 1540 ret = devm_iio_triggered_buffer_setup(&i3cdev->dev, indio_dev, 1541 iio_pollfunc_store_time, 1542 ad4062_poll_handler, 1543 &ad4062_triggered_buffer_setup_ops); 1544 if (ret) 1545 return ret; 1546 1547 pm_runtime_set_active(dev); 1548 ret = devm_pm_runtime_enable(dev); 1549 if (ret) 1550 return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n"); 1551 1552 pm_runtime_set_autosuspend_delay(dev, 1000); 1553 pm_runtime_use_autosuspend(dev); 1554 1555 ret = ad4062_request_ibi(i3cdev); 1556 if (ret) 1557 return dev_err_probe(dev, ret, "Failed to request i3c ibi\n"); 1558 1559 ret = ad4062_gpio_init(st); 1560 if (ret) 1561 return ret; 1562 1563 ret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work); 1564 if (ret) 1565 return ret; 1566 1567 return devm_iio_device_register(dev, indio_dev); 1568 } 1569 1570 static int ad4062_runtime_suspend(struct device *dev) 1571 { 1572 struct ad4062_state *st = dev_get_drvdata(dev); 1573 1574 return regmap_write(st->regmap, AD4062_REG_DEVICE_CONFIG, 1575 FIELD_PREP(AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK, 1576 AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE)); 1577 } 1578 1579 static int ad4062_runtime_resume(struct device *dev) 1580 { 1581 struct ad4062_state *st = dev_get_drvdata(dev); 1582 int ret; 1583 1584 ret = regmap_clear_bits(st->regmap, AD4062_REG_DEVICE_CONFIG, 1585 AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK); 1586 if (ret) 1587 return ret; 1588 1589 /* Wait device functional blocks to power up */ 1590 fsleep(3 * USEC_PER_MSEC); 1591 return 0; 1592 } 1593 1594 static DEFINE_RUNTIME_DEV_PM_OPS(ad4062_pm_ops, 1595 ad4062_runtime_suspend, ad4062_runtime_resume, NULL); 1596 1597 static struct i3c_driver ad4062_driver = { 1598 .driver = { 1599 .name = "ad4062", 1600 .pm = pm_ptr(&ad4062_pm_ops), 1601 }, 1602 .probe = ad4062_probe, 1603 .id_table = ad4062_id_table, 1604 }; 1605 module_i3c_driver(ad4062_driver); 1606 1607 MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); 1608 MODULE_DESCRIPTION("Analog Devices AD4062"); 1609 MODULE_LICENSE("GPL"); 1610