1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD4030 and AD4630 ADC family driver. 4 * 5 * Copyright 2024 Analog Devices, Inc. 6 * Copyright 2024 BayLibre, SAS 7 * 8 * based on code from: 9 * Analog Devices, Inc. 10 * Sergiu Cuciurean <sergiu.cuciurean@analog.com> 11 * Nuno Sa <nuno.sa@analog.com> 12 * Marcelo Schmitt <marcelo.schmitt@analog.com> 13 * Liviu Adace <liviu.adace@analog.com> 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/cleanup.h> 18 #include <linux/clk.h> 19 #include <linux/dmaengine.h> 20 #include <linux/limits.h> 21 #include <linux/log2.h> 22 #include <linux/math64.h> 23 #include <linux/minmax.h> 24 #include <linux/pwm.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/spi/offload/consumer.h> 28 #include <linux/spi/spi.h> 29 #include <linux/unaligned.h> 30 #include <linux/units.h> 31 #include <linux/types.h> 32 33 #include <linux/iio/buffer-dmaengine.h> 34 #include <linux/iio/iio.h> 35 #include <linux/iio/trigger_consumer.h> 36 #include <linux/iio/triggered_buffer.h> 37 38 #define AD4030_REG_INTERFACE_CONFIG_A 0x00 39 #define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7)) 40 #define AD4030_REG_INTERFACE_CONFIG_B 0x01 41 #define AD4030_REG_DEVICE_CONFIG 0x02 42 #define AD4030_REG_CHIP_TYPE 0x03 43 #define AD4030_REG_PRODUCT_ID_L 0x04 44 #define AD4030_REG_PRODUCT_ID_H 0x05 45 #define AD4030_REG_CHIP_GRADE 0x06 46 #define AD4030_REG_CHIP_GRADE_AD4030_24_GRADE 0x10 47 #define AD4030_REG_CHIP_GRADE_AD4630_16_GRADE 0x03 48 #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 49 #define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05 50 #define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02 51 #define AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE 0x1E 52 #define AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE 0x1C 53 #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) 54 #define AD4030_REG_SCRATCH_PAD 0x0A 55 #define AD4030_REG_SPI_REVISION 0x0B 56 #define AD4030_REG_VENDOR_L 0x0C 57 #define AD4030_REG_VENDOR_H 0x0D 58 #define AD4030_REG_STREAM_MODE 0x0E 59 #define AD4030_REG_INTERFACE_CONFIG_C 0x10 60 #define AD4030_REG_INTERFACE_STATUS_A 0x11 61 #define AD4030_REG_EXIT_CFG_MODE 0x14 62 #define AD4030_REG_EXIT_CFG_MODE_EXIT_MSK BIT(0) 63 #define AD4030_REG_AVG 0x15 64 #define AD4030_REG_AVG_MASK_AVG_SYNC BIT(7) 65 #define AD4030_REG_AVG_MASK_AVG_VAL GENMASK(4, 0) 66 #define AD4030_REG_OFFSET_X0_0 0x16 67 #define AD4030_REG_OFFSET_X0_1 0x17 68 #define AD4030_REG_OFFSET_X0_2 0x18 69 #define AD4030_REG_OFFSET_X1_0 0x19 70 #define AD4030_REG_OFFSET_X1_1 0x1A 71 #define AD4030_REG_OFFSET_X1_2 0x1B 72 #define AD4030_REG_OFFSET_BYTES_NB 3 73 #define AD4030_REG_OFFSET_CHAN(ch) \ 74 (AD4030_REG_OFFSET_X0_2 + (AD4030_REG_OFFSET_BYTES_NB * (ch))) 75 #define AD4030_REG_GAIN_X0_LSB 0x1C 76 #define AD4030_REG_GAIN_X0_MSB 0x1D 77 #define AD4030_REG_GAIN_X1_LSB 0x1E 78 #define AD4030_REG_GAIN_X1_MSB 0x1F 79 #define AD4030_REG_GAIN_MAX_GAIN 1999970 80 #define AD4030_REG_GAIN_BYTES_NB 2 81 #define AD4030_REG_GAIN_CHAN(ch) \ 82 (AD4030_REG_GAIN_X0_MSB + (AD4030_REG_GAIN_BYTES_NB * (ch))) 83 #define AD4030_REG_MODES 0x20 84 #define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0) 85 #define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6) 86 #define AD4030_REG_OSCILATOR 0x21 87 #define AD4030_REG_IO 0x22 88 #define AD4030_REG_IO_MASK_IO2X BIT(1) 89 #define AD4030_REG_PAT0 0x23 90 #define AD4030_REG_PAT1 0x24 91 #define AD4030_REG_PAT2 0x25 92 #define AD4030_REG_PAT3 0x26 93 #define AD4030_REG_DIG_DIAG 0x34 94 #define AD4030_REG_DIG_ERR 0x35 95 96 /* Sequence starting with "1 0 1" to enable reg access */ 97 #define AD4030_REG_ACCESS 0xA0 98 99 #define AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED BITS_TO_BYTES(64) 100 #define AD4030_MAX_HARDWARE_CHANNEL_NB 2 101 #define AD4030_MAX_IIO_CHANNEL_NB 5 102 #define AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK 0b10 103 #define AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK 0b1100 104 #define AD4030_GAIN_MIDLE_POINT 0x8000 105 /* 106 * This accounts for 1 sample per channel plus one s64 for the timestamp, 107 * aligned on a s64 boundary 108 */ 109 #define AD4030_MAXIMUM_RX_BUFFER_SIZE \ 110 (ALIGN(AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED * \ 111 AD4030_MAX_HARDWARE_CHANNEL_NB, \ 112 sizeof(s64)) + sizeof(s64)) 113 114 #define AD4030_VREF_MIN_UV (4096 * MILLI) 115 #define AD4030_VREF_MAX_UV (5000 * MILLI) 116 #define AD4030_VIO_THRESHOLD_UV (1400 * MILLI) 117 #define AD4030_SPI_MAX_XFER_LEN 8 118 #define AD4030_SPI_MAX_REG_XFER_SPEED (80 * MEGA) 119 #define AD4030_TCNVH_NS 10 120 #define AD4030_TCNVL_NS 20 121 #define AD4030_TCYC_NS 500 122 #define AD4030_TCYC_ADJUSTED_NS (AD4030_TCYC_NS - AD4030_TCNVL_NS) 123 #define AD4030_TRESET_PW_NS 50 124 #define AD4632_TCYC_NS 2000 125 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) 126 #define AD4030_TRESET_COM_DELAY_MS 750 127 /* Datasheet says 9.8ns, so use the closest integer value */ 128 #define AD4030_TQUIET_CNV_DELAY_NS 10 129 130 /* HARDWARE_GAIN */ 131 #define ADAQ4616_PGA_PINS 2 132 #define ADAQ4616_PGA_GAIN_MAX_NANO (NANO * 2 / 3) 133 134 enum ad4030_out_mode { 135 AD4030_OUT_DATA_MD_DIFF, 136 AD4030_OUT_DATA_MD_16_DIFF_8_COM, 137 AD4030_OUT_DATA_MD_24_DIFF_8_COM, 138 AD4030_OUT_DATA_MD_30_AVERAGED_DIFF, 139 AD4030_OUT_DATA_MD_32_PATTERN, 140 }; 141 142 enum { 143 AD4030_LANE_MD_1_PER_CH, 144 AD4030_LANE_MD_2_PER_CH, 145 AD4030_LANE_MD_4_PER_CH, 146 AD4030_LANE_MD_INTERLEAVED, 147 }; 148 149 enum { 150 AD4030_SCAN_TYPE_NORMAL, 151 AD4030_SCAN_TYPE_AVG, 152 }; 153 154 /* 155 * Gains computed as fractions of 1000 so they can be expressed by integers. 156 */ 157 static const int adaq4216_hw_gains_vpv[] = { 158 1 * MILLI / 3, /* 0.333 */ 159 5 * MILLI / 9, /* 0.555 */ 160 20 * MILLI / 9, /* 0.2222 */ 161 20 * MILLI / 3, /* 0.6666 */ 162 }; 163 164 static const int adaq4216_hw_gains_frac[][2] = { 165 { 1, 3 }, /* 1/3 V/V gain */ 166 { 5, 9 }, /* 5/9 V/V gain */ 167 { 20, 9 }, /* 20/9 V/V gain */ 168 { 20, 3 }, /* 20/3 V/V gain */ 169 }; 170 171 struct ad4030_chip_info { 172 const char *name; 173 const unsigned long *available_masks; 174 const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; 175 const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; 176 u8 grade; 177 u8 precision_bits; 178 bool has_pga; 179 /* Number of hardware channels */ 180 int num_voltage_inputs; 181 unsigned int tcyc_ns; 182 unsigned int max_sample_rate_hz; 183 }; 184 185 struct ad4030_state { 186 struct spi_device *spi; 187 struct regmap *regmap; 188 const struct ad4030_chip_info *chip; 189 struct gpio_desc *cnv_gpio; 190 int vref_uv; 191 int vio_uv; 192 int offset_avail[3]; 193 unsigned int avg_log2; 194 enum ad4030_out_mode mode; 195 /* Offload sampling */ 196 struct spi_transfer offload_xfer; 197 struct spi_message offload_msg; 198 struct spi_offload *offload; 199 struct spi_offload_trigger *offload_trigger; 200 struct spi_offload_trigger_config offload_trigger_config; 201 struct pwm_device *cnv_trigger; 202 size_t scale_avail_size; 203 struct pwm_waveform cnv_wf; 204 unsigned int scale_avail[ARRAY_SIZE(adaq4216_hw_gains_vpv)][2]; 205 struct gpio_descs *pga_gpios; 206 unsigned int pga_index; 207 208 /* 209 * DMA (thus cache coherency maintenance) requires the transfer buffers 210 * to live in their own cache lines. 211 */ 212 u8 tx_data[AD4030_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN); 213 union { 214 u8 raw[AD4030_MAXIMUM_RX_BUFFER_SIZE]; 215 struct { 216 s32 diff; 217 u8 common; 218 } single; 219 struct { 220 s32 diff[2]; 221 u8 common[2]; 222 } dual; 223 } rx_data; 224 }; 225 226 /* 227 * For a chip with 2 hardware channel this will be used to create 2 common-mode 228 * channels: 229 * - voltage4 230 * - voltage5 231 * As the common-mode channels are after the differential ones, we compute the 232 * channel number like this: 233 * - _idx is the scan_index (the order in the output buffer) 234 * - _ch is the hardware channel number this common-mode channel is related 235 * - _idx - _ch gives us the number of channel in the chip 236 * - _idx - _ch * 2 is the starting number of the common-mode channels, since 237 * for each differential channel there is a common-mode channel 238 * - _idx - _ch * 2 + _ch gives the channel number for this specific common-mode 239 * channel 240 */ 241 #define AD4030_CHAN_CMO(_idx, _ch) { \ 242 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 243 BIT(IIO_CHAN_INFO_SCALE), \ 244 .type = IIO_VOLTAGE, \ 245 .indexed = 1, \ 246 .address = (_ch), \ 247 .channel = ((_idx) - (_ch)) * 2 + (_ch), \ 248 .scan_index = (_idx), \ 249 .scan_type = { \ 250 .sign = 'u', \ 251 .storagebits = 8, \ 252 .realbits = 8, \ 253 .endianness = IIO_BE, \ 254 }, \ 255 } 256 257 /* 258 * For a chip with 2 hardware channel this will be used to create 2 differential 259 * channels: 260 * - voltage0-voltage1 261 * - voltage2-voltage3 262 */ 263 #define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload, _pga) { \ 264 .info_mask_shared_by_all = \ 265 (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ 266 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 267 .info_mask_shared_by_all_available = \ 268 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 269 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \ 270 BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 271 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 272 BIT(IIO_CHAN_INFO_RAW), \ 273 .info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 274 (_pga ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 275 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 276 .type = IIO_VOLTAGE, \ 277 .indexed = 1, \ 278 .address = (_idx), \ 279 .channel = (_idx) * 2, \ 280 .channel2 = (_idx) * 2 + 1, \ 281 .scan_index = (_idx), \ 282 .differential = true, \ 283 .has_ext_scan_type = 1, \ 284 .ext_scan_type = _scan_type, \ 285 .num_ext_scan_type = ARRAY_SIZE(_scan_type), \ 286 } 287 288 #define AD4030_CHAN_DIFF(_idx, _scan_type) \ 289 __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 0) 290 291 #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ 292 __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 0) 293 294 #define ADAQ4216_CHAN_DIFF(_idx, _scan_type) \ 295 __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 1) 296 297 #define ADAQ4216_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ 298 __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 1) 299 300 /* 301 * AD4030 can average over 2^N samples, where N = 1, 2, 3, ..., 16. 302 * We use N = 0 to mean no sample averaging. 303 */ 304 static const int ad4030_average_modes[] = { 305 BIT(0), /* No sampling average */ 306 BIT(1), BIT(2), BIT(3), BIT(4), 307 BIT(5), BIT(6), BIT(7), BIT(8), 308 BIT(9), BIT(10), BIT(11), BIT(12), 309 BIT(13), BIT(14), BIT(15), BIT(16), 310 }; 311 312 static const struct spi_offload_config ad4030_offload_config = { 313 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 314 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 315 }; 316 317 static int ad4030_enter_config_mode(struct ad4030_state *st) 318 { 319 st->tx_data[0] = AD4030_REG_ACCESS; 320 321 struct spi_transfer xfer = { 322 .tx_buf = st->tx_data, 323 .len = 1, 324 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED, 325 }; 326 327 return spi_sync_transfer(st->spi, &xfer, 1); 328 } 329 330 static int ad4030_exit_config_mode(struct ad4030_state *st) 331 { 332 st->tx_data[0] = 0; 333 st->tx_data[1] = AD4030_REG_EXIT_CFG_MODE; 334 st->tx_data[2] = AD4030_REG_EXIT_CFG_MODE_EXIT_MSK; 335 336 struct spi_transfer xfer = { 337 .tx_buf = st->tx_data, 338 .len = 3, 339 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED, 340 }; 341 342 return spi_sync_transfer(st->spi, &xfer, 1); 343 } 344 345 static int ad4030_spi_read(void *context, const void *reg, size_t reg_size, 346 void *val, size_t val_size) 347 { 348 int ret; 349 struct ad4030_state *st = context; 350 struct spi_transfer xfer = { 351 .tx_buf = st->tx_data, 352 .rx_buf = st->rx_data.raw, 353 .len = reg_size + val_size, 354 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED, 355 }; 356 357 if (xfer.len > sizeof(st->tx_data) || 358 xfer.len > sizeof(st->rx_data.raw)) 359 return -EINVAL; 360 361 ret = ad4030_enter_config_mode(st); 362 if (ret) 363 return ret; 364 365 memset(st->tx_data, 0, sizeof(st->tx_data)); 366 memcpy(st->tx_data, reg, reg_size); 367 368 ret = spi_sync_transfer(st->spi, &xfer, 1); 369 if (ret) 370 return ret; 371 372 memcpy(val, &st->rx_data.raw[reg_size], val_size); 373 374 return ad4030_exit_config_mode(st); 375 } 376 377 static int ad4030_spi_write(void *context, const void *data, size_t count) 378 { 379 int ret; 380 struct ad4030_state *st = context; 381 bool is_reset = count >= 3 && 382 ((u8 *)data)[0] == 0 && 383 ((u8 *)data)[1] == 0 && 384 ((u8 *)data)[2] == 0x81; 385 struct spi_transfer xfer = { 386 .tx_buf = st->tx_data, 387 .len = count, 388 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED, 389 }; 390 391 if (count > sizeof(st->tx_data)) 392 return -EINVAL; 393 394 ret = ad4030_enter_config_mode(st); 395 if (ret) 396 return ret; 397 398 memcpy(st->tx_data, data, count); 399 400 ret = spi_sync_transfer(st->spi, &xfer, 1); 401 if (ret) 402 return ret; 403 404 /* 405 * From datasheet: "After a [...] reset, no SPI commands or conversions 406 * can be started for 750us" 407 * After a reset we are in conversion mode, no need to exit config mode 408 */ 409 if (is_reset) { 410 fsleep(750); 411 return 0; 412 } 413 414 return ad4030_exit_config_mode(st); 415 } 416 417 static const struct regmap_bus ad4030_regmap_bus = { 418 .read = ad4030_spi_read, 419 .write = ad4030_spi_write, 420 .reg_format_endian_default = REGMAP_ENDIAN_BIG, 421 }; 422 423 static const struct regmap_range ad4030_regmap_rd_range[] = { 424 regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_A, AD4030_REG_CHIP_GRADE), 425 regmap_reg_range(AD4030_REG_SCRATCH_PAD, AD4030_REG_STREAM_MODE), 426 regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_C, 427 AD4030_REG_INTERFACE_STATUS_A), 428 regmap_reg_range(AD4030_REG_EXIT_CFG_MODE, AD4030_REG_PAT3), 429 regmap_reg_range(AD4030_REG_DIG_DIAG, AD4030_REG_DIG_ERR), 430 }; 431 432 static const struct regmap_range ad4030_regmap_wr_range[] = { 433 regmap_reg_range(AD4030_REG_CHIP_TYPE, AD4030_REG_CHIP_GRADE), 434 regmap_reg_range(AD4030_REG_SPI_REVISION, AD4030_REG_VENDOR_H), 435 }; 436 437 static const struct regmap_access_table ad4030_regmap_rd_table = { 438 .yes_ranges = ad4030_regmap_rd_range, 439 .n_yes_ranges = ARRAY_SIZE(ad4030_regmap_rd_range), 440 }; 441 442 static const struct regmap_access_table ad4030_regmap_wr_table = { 443 .no_ranges = ad4030_regmap_wr_range, 444 .n_no_ranges = ARRAY_SIZE(ad4030_regmap_wr_range), 445 }; 446 447 static const struct regmap_config ad4030_regmap_config = { 448 .reg_bits = 16, 449 .val_bits = 8, 450 .read_flag_mask = 0x80, 451 .rd_table = &ad4030_regmap_rd_table, 452 .wr_table = &ad4030_regmap_wr_table, 453 .max_register = AD4030_REG_DIG_ERR, 454 }; 455 456 static void ad4030_fill_scale_avail(struct ad4030_state *st) 457 { 458 unsigned int mag_bits, int_part, fract_part; 459 u64 range; 460 461 /* 462 * The maximum precision of differential channels is retrieved from the 463 * chip properties. The output code of differential channels is in two's 464 * complement format (i.e. signed), so the MSB is the sign bit and only 465 * (precision_bits - 1) bits express voltage magnitude. 466 */ 467 mag_bits = st->chip->precision_bits - 1; 468 469 for (unsigned int i = 0; i < ARRAY_SIZE(adaq4216_hw_gains_frac); i++) { 470 range = mult_frac(st->vref_uv, adaq4216_hw_gains_frac[i][1], 471 adaq4216_hw_gains_frac[i][0]); 472 /* 473 * If range were in mV, we would multiply it by NANO below. 474 * Though, range is in µV so multiply it by MICRO only so the 475 * result after right shift and division scales output codes to 476 * millivolts. 477 */ 478 int_part = div_u64_rem((range * MICRO) >> mag_bits, NANO, &fract_part); 479 st->scale_avail[i][0] = int_part; 480 st->scale_avail[i][1] = fract_part; 481 } 482 } 483 484 static int ad4030_set_pga_gain(struct ad4030_state *st) 485 { 486 DECLARE_BITMAP(bitmap, ADAQ4616_PGA_PINS) = { }; 487 488 bitmap_write(bitmap, st->pga_index, 0, ADAQ4616_PGA_PINS); 489 490 return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); 491 } 492 493 static int ad4030_set_pga(struct iio_dev *indio_dev, int gain_int, int gain_fract) 494 { 495 struct ad4030_state *st = iio_priv(indio_dev); 496 unsigned int mag_bits = st->chip->precision_bits - 1; 497 unsigned int tmp; 498 u64 gain_nano; 499 500 if (!st->pga_gpios) 501 return -EINVAL; 502 503 gain_nano = gain_int * NANO + gain_fract; 504 if (!in_range(gain_nano, 1, ADAQ4616_PGA_GAIN_MAX_NANO)) 505 return -EINVAL; 506 507 tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << mag_bits, NANO); 508 gain_nano = DIV_ROUND_CLOSEST(st->vref_uv, tmp); 509 st->pga_index = find_closest(gain_nano, adaq4216_hw_gains_vpv, 510 ARRAY_SIZE(adaq4216_hw_gains_vpv)); 511 512 return ad4030_set_pga_gain(st); 513 } 514 515 static int ad4030_get_chan_scale(struct iio_dev *indio_dev, 516 struct iio_chan_spec const *chan, 517 int *val, 518 int *val2) 519 { 520 struct ad4030_state *st = iio_priv(indio_dev); 521 const struct iio_scan_type *scan_type; 522 523 scan_type = iio_get_current_scan_type(indio_dev, chan); 524 if (IS_ERR(scan_type)) 525 return PTR_ERR(scan_type); 526 527 /* The LSB of the 8-bit common-mode data is always vref/256. */ 528 if (st->chip->has_pga && scan_type->realbits != 8) { 529 *val = st->scale_avail[st->pga_index][0]; 530 *val2 = st->scale_avail[st->pga_index][1]; 531 return IIO_VAL_INT_PLUS_NANO; 532 } 533 534 if (chan->differential) 535 *val = (st->vref_uv * 2) / MILLI; 536 else 537 *val = st->vref_uv / MILLI; 538 539 *val2 = scan_type->realbits; 540 541 return IIO_VAL_FRACTIONAL_LOG2; 542 } 543 544 static int ad4030_get_chan_calibscale(struct iio_dev *indio_dev, 545 struct iio_chan_spec const *chan, 546 int *val, 547 int *val2) 548 { 549 struct ad4030_state *st = iio_priv(indio_dev); 550 u16 gain; 551 int ret; 552 553 ret = regmap_bulk_read(st->regmap, AD4030_REG_GAIN_CHAN(chan->address), 554 st->rx_data.raw, AD4030_REG_GAIN_BYTES_NB); 555 if (ret) 556 return ret; 557 558 gain = get_unaligned_be16(st->rx_data.raw); 559 560 /* From datasheet: multiplied output = input × gain word/0x8000 */ 561 *val = gain / AD4030_GAIN_MIDLE_POINT; 562 *val2 = mul_u64_u32_div(gain % AD4030_GAIN_MIDLE_POINT, NANO, 563 AD4030_GAIN_MIDLE_POINT); 564 565 return IIO_VAL_INT_PLUS_NANO; 566 } 567 568 /* Returns the offset where 1 LSB = (VREF/2^precision_bits - 1)/gain */ 569 static int ad4030_get_chan_calibbias(struct iio_dev *indio_dev, 570 struct iio_chan_spec const *chan, 571 int *val) 572 { 573 struct ad4030_state *st = iio_priv(indio_dev); 574 int ret; 575 576 ret = regmap_bulk_read(st->regmap, 577 AD4030_REG_OFFSET_CHAN(chan->address), 578 st->rx_data.raw, AD4030_REG_OFFSET_BYTES_NB); 579 if (ret) 580 return ret; 581 582 switch (st->chip->precision_bits) { 583 case 16: 584 *val = sign_extend32(get_unaligned_be16(st->rx_data.raw), 15); 585 return IIO_VAL_INT; 586 587 case 24: 588 *val = sign_extend32(get_unaligned_be24(st->rx_data.raw), 23); 589 return IIO_VAL_INT; 590 591 default: 592 return -EINVAL; 593 } 594 } 595 596 static void ad4030_get_sampling_freq(struct ad4030_state *st, int *freq) 597 { 598 struct spi_offload_trigger_config *config = &st->offload_trigger_config; 599 600 /* 601 * Conversion data is fetched from the device when the offload transfer 602 * is triggered. Thus, provide the SPI offload trigger frequency as the 603 * sampling frequency. 604 */ 605 *freq = config->periodic.frequency_hz; 606 } 607 608 static int ad4030_update_conversion_rate(struct ad4030_state *st, 609 unsigned int freq_hz, unsigned int avg_log2) 610 { 611 struct spi_offload_trigger_config *config = &st->offload_trigger_config; 612 unsigned int offload_period_ns, cnv_rate_hz; 613 struct pwm_waveform cnv_wf = { }; 614 u64 target = AD4030_TCNVH_NS; 615 u64 offload_offset_ns; 616 int ret; 617 618 /* 619 * When averaging/oversampling over N samples, we fire the offload 620 * trigger once at every N pulses of the CNV signal. Conversely, the CNV 621 * signal needs to be N times faster than the offload trigger. Take that 622 * into account to correctly re-evaluate both the PWM waveform connected 623 * to CNV and the SPI offload trigger. 624 */ 625 cnv_rate_hz = freq_hz << avg_log2; 626 627 cnv_wf.period_length_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, cnv_rate_hz); 628 /* 629 * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the 630 * rounded PWM's value is less than 10, increase the target value by 10 631 * and attempt to round the waveform again, until the value is at least 632 * 10 ns. Use a separate variable to represent the target in case the 633 * rounding is severe enough to keep putting the first few results under 634 * the minimum 10ns condition checked by the while loop. 635 */ 636 do { 637 cnv_wf.duty_length_ns = target; 638 ret = pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf); 639 if (ret) 640 return ret; 641 target += AD4030_TCNVH_NS; 642 } while (cnv_wf.duty_length_ns < AD4030_TCNVH_NS); 643 644 /* 645 * The CNV waveform period (period_length_ns) might get rounded down by 646 * pwm_round_waveform_might_sleep(). Check the resultant PWM period 647 * is not smaller than the minimum data conversion cycle time. 648 */ 649 if (!in_range(cnv_wf.period_length_ns, AD4030_TCYC_NS, INT_MAX)) 650 return -EINVAL; 651 652 offload_period_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq_hz); 653 654 config->periodic.frequency_hz = DIV_ROUND_UP(HZ_PER_GHZ, offload_period_ns); 655 656 /* 657 * The hardware does the capture on zone 2 (when SPI trigger PWM 658 * is used). This means that the SPI trigger signal should happen at 659 * tsync + tquiet_con_delay being tsync the conversion signal period 660 * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly. 661 * 662 * The PWM waveform API only supports nanosecond resolution right now, 663 * so round this setting to the closest available value. 664 */ 665 offload_offset_ns = AD4030_TQUIET_CNV_DELAY_NS; 666 do { 667 config->periodic.offset_ns = offload_offset_ns; 668 ret = spi_offload_trigger_validate(st->offload_trigger, config); 669 if (ret) 670 return ret; 671 offload_offset_ns += AD4030_TQUIET_CNV_DELAY_NS; 672 } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS); 673 674 st->cnv_wf = cnv_wf; 675 676 return 0; 677 } 678 679 static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, int freq_hz) 680 { 681 struct ad4030_state *st = iio_priv(indio_dev); 682 683 if (freq_hz == 0) 684 return -EINVAL; 685 686 if (!in_range(freq_hz, 0, st->chip->max_sample_rate_hz)) 687 return -ERANGE; 688 689 return ad4030_update_conversion_rate(st, freq_hz, st->avg_log2); 690 } 691 692 static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, 693 struct iio_chan_spec const *chan, 694 int gain_int, 695 int gain_frac) 696 { 697 struct ad4030_state *st = iio_priv(indio_dev); 698 u64 gain; 699 700 if (gain_int < 0 || gain_frac < 0) 701 return -EINVAL; 702 703 gain = mul_u32_u32(gain_int, MICRO) + gain_frac; 704 705 if (gain > AD4030_REG_GAIN_MAX_GAIN) 706 return -EINVAL; 707 708 put_unaligned_be16(DIV_ROUND_CLOSEST_ULL(gain * AD4030_GAIN_MIDLE_POINT, 709 MICRO), 710 st->tx_data); 711 712 return regmap_bulk_write(st->regmap, 713 AD4030_REG_GAIN_CHAN(chan->address), 714 st->tx_data, AD4030_REG_GAIN_BYTES_NB); 715 } 716 717 static int ad4030_set_chan_calibbias(struct iio_dev *indio_dev, 718 struct iio_chan_spec const *chan, 719 int offset) 720 { 721 struct ad4030_state *st = iio_priv(indio_dev); 722 723 if (offset < st->offset_avail[0] || offset > st->offset_avail[2]) 724 return -EINVAL; 725 726 st->tx_data[2] = 0; 727 728 switch (st->chip->precision_bits) { 729 case 16: 730 put_unaligned_be16(offset, st->tx_data); 731 break; 732 733 case 24: 734 put_unaligned_be24(offset, st->tx_data); 735 break; 736 737 default: 738 return -EINVAL; 739 } 740 741 return regmap_bulk_write(st->regmap, 742 AD4030_REG_OFFSET_CHAN(chan->address), 743 st->tx_data, AD4030_REG_OFFSET_BYTES_NB); 744 } 745 746 static int ad4030_set_avg_frame_len(struct iio_dev *dev, int avg_val) 747 { 748 struct ad4030_state *st = iio_priv(dev); 749 unsigned int avg_log2 = ilog2(avg_val); 750 unsigned int last_avg_idx = ARRAY_SIZE(ad4030_average_modes) - 1; 751 int freq_hz; 752 int ret; 753 754 if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) 755 return -EINVAL; 756 757 if (st->offload_trigger) { 758 /* 759 * The sample averaging and sampling frequency configurations 760 * are mutually dependent on each other. That's because the 761 * effective data sample rate is fCNV / 2^N, where N is the 762 * number of samples being averaged. 763 * 764 * When SPI offload is supported and we have control over the 765 * sample rate, the conversion start signal (CNV) and the SPI 766 * offload trigger frequencies must be re-evaluated so data is 767 * fetched only after 'avg_val' conversions. 768 */ 769 ad4030_get_sampling_freq(st, &freq_hz); 770 ret = ad4030_update_conversion_rate(st, freq_hz, avg_log2); 771 if (ret) 772 return ret; 773 } 774 775 ret = regmap_write(st->regmap, AD4030_REG_AVG, 776 AD4030_REG_AVG_MASK_AVG_SYNC | 777 FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2)); 778 if (ret) 779 return ret; 780 781 st->avg_log2 = avg_log2; 782 783 return 0; 784 } 785 786 static bool ad4030_is_common_byte_asked(struct ad4030_state *st, 787 unsigned int mask) 788 { 789 return mask & (st->chip->num_voltage_inputs == 1 ? 790 AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK : 791 AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK); 792 } 793 794 static int ad4030_set_mode(struct iio_dev *indio_dev, unsigned long mask) 795 { 796 struct ad4030_state *st = iio_priv(indio_dev); 797 798 if (st->avg_log2 > 0) { 799 st->mode = AD4030_OUT_DATA_MD_30_AVERAGED_DIFF; 800 } else if (ad4030_is_common_byte_asked(st, mask)) { 801 switch (st->chip->precision_bits) { 802 case 16: 803 st->mode = AD4030_OUT_DATA_MD_16_DIFF_8_COM; 804 break; 805 806 case 24: 807 st->mode = AD4030_OUT_DATA_MD_24_DIFF_8_COM; 808 break; 809 810 default: 811 return -EINVAL; 812 } 813 } else { 814 st->mode = AD4030_OUT_DATA_MD_DIFF; 815 } 816 817 return regmap_update_bits(st->regmap, AD4030_REG_MODES, 818 AD4030_REG_MODES_MASK_OUT_DATA_MODE, 819 st->mode); 820 } 821 822 /* 823 * Descramble 2 32bits numbers out of a 64bits. The bits are interleaved: 824 * 1 bit for first number, 1 bit for the second, and so on... 825 */ 826 static void ad4030_extract_interleaved(u8 *src, u32 *ch0, u32 *ch1) 827 { 828 u8 h0, h1, l0, l1; 829 u32 out0, out1; 830 u8 *out0_raw = (u8 *)&out0; 831 u8 *out1_raw = (u8 *)&out1; 832 833 for (int i = 0; i < 4; i++) { 834 h0 = src[i * 2]; 835 l1 = src[i * 2 + 1]; 836 h1 = h0 << 1; 837 l0 = l1 >> 1; 838 839 h0 &= 0xAA; 840 l0 &= 0x55; 841 h1 &= 0xAA; 842 l1 &= 0x55; 843 844 h0 = (h0 | h0 << 001) & 0xCC; 845 h1 = (h1 | h1 << 001) & 0xCC; 846 l0 = (l0 | l0 >> 001) & 0x33; 847 l1 = (l1 | l1 >> 001) & 0x33; 848 h0 = (h0 | h0 << 002) & 0xF0; 849 h1 = (h1 | h1 << 002) & 0xF0; 850 l0 = (l0 | l0 >> 002) & 0x0F; 851 l1 = (l1 | l1 >> 002) & 0x0F; 852 853 out0_raw[i] = h0 | l0; 854 out1_raw[i] = h1 | l1; 855 } 856 857 *ch0 = out0; 858 *ch1 = out1; 859 } 860 861 static int ad4030_conversion(struct iio_dev *indio_dev) 862 { 863 struct ad4030_state *st = iio_priv(indio_dev); 864 const struct iio_scan_type *scan_type; 865 unsigned char diff_realbytes, diff_storagebytes; 866 unsigned int bytes_to_read; 867 unsigned long cnv_nb = BIT(st->avg_log2); 868 unsigned int i; 869 int ret; 870 871 scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels); 872 if (IS_ERR(scan_type)) 873 return PTR_ERR(scan_type); 874 875 diff_realbytes = BITS_TO_BYTES(scan_type->realbits); 876 diff_storagebytes = BITS_TO_BYTES(scan_type->storagebits); 877 878 /* Number of bytes for one differential channel */ 879 bytes_to_read = diff_realbytes; 880 /* Add one byte if we are using a differential + common byte mode */ 881 bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM || 882 st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0; 883 /* Multiply by the number of hardware channels */ 884 bytes_to_read *= st->chip->num_voltage_inputs; 885 886 for (i = 0; i < cnv_nb; i++) { 887 gpiod_set_value_cansleep(st->cnv_gpio, 1); 888 ndelay(AD4030_TCNVH_NS); 889 gpiod_set_value_cansleep(st->cnv_gpio, 0); 890 ndelay(st->chip->tcyc_ns); 891 } 892 893 ret = spi_read(st->spi, st->rx_data.raw, bytes_to_read); 894 if (ret) 895 return ret; 896 897 if (st->chip->num_voltage_inputs == 2) 898 ad4030_extract_interleaved(st->rx_data.raw, 899 &st->rx_data.dual.diff[0], 900 &st->rx_data.dual.diff[1]); 901 902 /* 903 * If no common mode voltage channel is enabled, we can use the raw 904 * data as is. Otherwise, we need to rearrange the data a bit to match 905 * the natural alignment of the IIO buffer. 906 */ 907 908 if (st->mode != AD4030_OUT_DATA_MD_16_DIFF_8_COM && 909 st->mode != AD4030_OUT_DATA_MD_24_DIFF_8_COM) 910 return 0; 911 912 if (st->chip->num_voltage_inputs == 1) { 913 st->rx_data.single.common = st->rx_data.raw[diff_realbytes]; 914 return 0; 915 } 916 917 for (i = 0; i < st->chip->num_voltage_inputs; i++) 918 st->rx_data.dual.common[i] = 919 st->rx_data.raw[diff_storagebytes * i + diff_realbytes]; 920 921 return 0; 922 } 923 924 static int ad4030_single_conversion(struct iio_dev *indio_dev, 925 const struct iio_chan_spec *chan, int *val) 926 { 927 struct ad4030_state *st = iio_priv(indio_dev); 928 int ret; 929 930 ret = ad4030_set_mode(indio_dev, BIT(chan->scan_index)); 931 if (ret) 932 return ret; 933 934 ret = ad4030_conversion(indio_dev); 935 if (ret) 936 return ret; 937 938 if (chan->differential) 939 if (st->chip->num_voltage_inputs == 1) 940 *val = st->rx_data.single.diff; 941 else 942 *val = st->rx_data.dual.diff[chan->address]; 943 else 944 if (st->chip->num_voltage_inputs == 1) 945 *val = st->rx_data.single.common; 946 else 947 *val = st->rx_data.dual.common[chan->address]; 948 949 return IIO_VAL_INT; 950 } 951 952 static irqreturn_t ad4030_trigger_handler(int irq, void *p) 953 { 954 struct iio_poll_func *pf = p; 955 struct iio_dev *indio_dev = pf->indio_dev; 956 struct ad4030_state *st = iio_priv(indio_dev); 957 int ret; 958 959 ret = ad4030_conversion(indio_dev); 960 if (ret) 961 goto out; 962 963 iio_push_to_buffers_with_ts(indio_dev, &st->rx_data, sizeof(st->rx_data), 964 pf->timestamp); 965 966 out: 967 iio_trigger_notify_done(indio_dev->trig); 968 969 return IRQ_HANDLED; 970 } 971 972 static const int ad4030_gain_avail[3][2] = { 973 { 0, 0 }, 974 { 0, 30518 }, 975 { 1, 999969482 }, 976 }; 977 978 static int ad4030_read_avail(struct iio_dev *indio_dev, 979 struct iio_chan_spec const *channel, 980 const int **vals, int *type, 981 int *length, long mask) 982 { 983 struct ad4030_state *st = iio_priv(indio_dev); 984 985 switch (mask) { 986 case IIO_CHAN_INFO_CALIBBIAS: 987 *vals = st->offset_avail; 988 *type = IIO_VAL_INT; 989 return IIO_AVAIL_RANGE; 990 991 case IIO_CHAN_INFO_CALIBSCALE: 992 *vals = (void *)ad4030_gain_avail; 993 *type = IIO_VAL_INT_PLUS_NANO; 994 return IIO_AVAIL_RANGE; 995 996 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 997 *vals = ad4030_average_modes; 998 *type = IIO_VAL_INT; 999 *length = ARRAY_SIZE(ad4030_average_modes); 1000 return IIO_AVAIL_LIST; 1001 1002 case IIO_CHAN_INFO_SCALE: 1003 if (st->scale_avail_size == 1) 1004 *vals = (int *)st->scale_avail[st->pga_index]; 1005 else 1006 *vals = (int *)st->scale_avail; 1007 *length = st->scale_avail_size * 2; /* print int and nano part */ 1008 *type = IIO_VAL_INT_PLUS_NANO; 1009 return IIO_AVAIL_LIST; 1010 1011 default: 1012 return -EINVAL; 1013 } 1014 } 1015 1016 static int ad4030_read_raw_dispatch(struct iio_dev *indio_dev, 1017 struct iio_chan_spec const *chan, int *val, 1018 int *val2, long info) 1019 { 1020 struct ad4030_state *st = iio_priv(indio_dev); 1021 1022 switch (info) { 1023 case IIO_CHAN_INFO_RAW: 1024 return ad4030_single_conversion(indio_dev, chan, val); 1025 1026 case IIO_CHAN_INFO_CALIBSCALE: 1027 return ad4030_get_chan_calibscale(indio_dev, chan, val, val2); 1028 1029 case IIO_CHAN_INFO_CALIBBIAS: 1030 return ad4030_get_chan_calibbias(indio_dev, chan, val); 1031 1032 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1033 *val = BIT(st->avg_log2); 1034 return IIO_VAL_INT; 1035 1036 case IIO_CHAN_INFO_SAMP_FREQ: 1037 ad4030_get_sampling_freq(st, val); 1038 return IIO_VAL_INT; 1039 1040 default: 1041 return -EINVAL; 1042 } 1043 } 1044 1045 static int ad4030_read_raw(struct iio_dev *indio_dev, 1046 struct iio_chan_spec const *chan, int *val, 1047 int *val2, long info) 1048 { 1049 int ret; 1050 1051 if (info == IIO_CHAN_INFO_SCALE) 1052 return ad4030_get_chan_scale(indio_dev, chan, val, val2); 1053 1054 if (!iio_device_claim_direct(indio_dev)) 1055 return -EBUSY; 1056 1057 ret = ad4030_read_raw_dispatch(indio_dev, chan, val, val2, info); 1058 1059 iio_device_release_direct(indio_dev); 1060 1061 return ret; 1062 } 1063 1064 static int ad4030_write_raw_dispatch(struct iio_dev *indio_dev, 1065 struct iio_chan_spec const *chan, int val, 1066 int val2, long info) 1067 { 1068 switch (info) { 1069 case IIO_CHAN_INFO_CALIBSCALE: 1070 return ad4030_set_chan_calibscale(indio_dev, chan, val, val2); 1071 1072 case IIO_CHAN_INFO_CALIBBIAS: 1073 if (val2 != 0) 1074 return -EINVAL; 1075 return ad4030_set_chan_calibbias(indio_dev, chan, val); 1076 1077 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1078 return ad4030_set_avg_frame_len(indio_dev, val); 1079 1080 case IIO_CHAN_INFO_SAMP_FREQ: 1081 return ad4030_set_sampling_freq(indio_dev, val); 1082 1083 case IIO_CHAN_INFO_SCALE: 1084 return ad4030_set_pga(indio_dev, val, val2); 1085 1086 default: 1087 return -EINVAL; 1088 } 1089 } 1090 1091 static int ad4030_write_raw(struct iio_dev *indio_dev, 1092 struct iio_chan_spec const *chan, int val, 1093 int val2, long info) 1094 { 1095 int ret; 1096 1097 if (!iio_device_claim_direct(indio_dev)) 1098 return -EBUSY; 1099 1100 ret = ad4030_write_raw_dispatch(indio_dev, chan, val, val2, info); 1101 1102 iio_device_release_direct(indio_dev); 1103 1104 return ret; 1105 } 1106 1107 static int ad4030_write_raw_get_fmt(struct iio_dev *indio_dev, 1108 struct iio_chan_spec const *chan, long mask) 1109 { 1110 switch (mask) { 1111 case IIO_CHAN_INFO_SCALE: 1112 return IIO_VAL_INT_PLUS_NANO; 1113 default: 1114 return IIO_VAL_INT_PLUS_MICRO; 1115 } 1116 } 1117 1118 static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1119 unsigned int writeval, unsigned int *readval) 1120 { 1121 const struct ad4030_state *st = iio_priv(indio_dev); 1122 int ret; 1123 1124 if (!iio_device_claim_direct(indio_dev)) 1125 return -EBUSY; 1126 1127 if (readval) 1128 ret = regmap_read(st->regmap, reg, readval); 1129 else 1130 ret = regmap_write(st->regmap, reg, writeval); 1131 1132 iio_device_release_direct(indio_dev); 1133 1134 return ret; 1135 } 1136 1137 static int ad4030_read_label(struct iio_dev *indio_dev, 1138 struct iio_chan_spec const *chan, 1139 char *label) 1140 { 1141 if (chan->differential) 1142 return sysfs_emit(label, "differential%lu\n", chan->address); 1143 return sysfs_emit(label, "common-mode%lu\n", chan->address); 1144 } 1145 1146 static int ad4030_get_current_scan_type(const struct iio_dev *indio_dev, 1147 const struct iio_chan_spec *chan) 1148 { 1149 struct ad4030_state *st = iio_priv(indio_dev); 1150 1151 return st->avg_log2 ? AD4030_SCAN_TYPE_AVG : AD4030_SCAN_TYPE_NORMAL; 1152 } 1153 1154 static int ad4030_update_scan_mode(struct iio_dev *indio_dev, 1155 const unsigned long *scan_mask) 1156 { 1157 return ad4030_set_mode(indio_dev, *scan_mask); 1158 } 1159 1160 static const struct iio_info ad4030_iio_info = { 1161 .read_avail = ad4030_read_avail, 1162 .read_raw = ad4030_read_raw, 1163 .write_raw = ad4030_write_raw, 1164 .write_raw_get_fmt = &ad4030_write_raw_get_fmt, 1165 .debugfs_reg_access = ad4030_reg_access, 1166 .read_label = ad4030_read_label, 1167 .get_current_scan_type = ad4030_get_current_scan_type, 1168 .update_scan_mode = ad4030_update_scan_mode, 1169 }; 1170 1171 static bool ad4030_validate_scan_mask(struct iio_dev *indio_dev, 1172 const unsigned long *scan_mask) 1173 { 1174 struct ad4030_state *st = iio_priv(indio_dev); 1175 1176 /* Asking for both common channels and averaging */ 1177 if (st->avg_log2 && ad4030_is_common_byte_asked(st, *scan_mask)) 1178 return false; 1179 1180 return true; 1181 } 1182 1183 static const struct iio_buffer_setup_ops ad4030_buffer_setup_ops = { 1184 .validate_scan_mask = ad4030_validate_scan_mask, 1185 }; 1186 1187 static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) 1188 { 1189 struct ad4030_state *st = iio_priv(indio_dev); 1190 u8 offload_bpw; 1191 1192 if (st->mode == AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) 1193 offload_bpw = 32; 1194 else 1195 offload_bpw = st->chip->precision_bits; 1196 1197 st->offload_xfer.bits_per_word = offload_bpw; 1198 st->offload_xfer.len = spi_bpw_to_bytes(offload_bpw); 1199 st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1200 spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 1201 } 1202 1203 static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) 1204 { 1205 struct ad4030_state *st = iio_priv(indio_dev); 1206 unsigned int reg_modes; 1207 int ret; 1208 1209 /* 1210 * When data from 2 analog input channels is output through a single 1211 * bus line (interleaved mode (LANE_MD == 0b11)) and gets pushed through 1212 * DMA, extra hardware is required to do the de-interleaving. While we 1213 * don't support such hardware configurations, disallow interleaved mode 1214 * when using SPI offload. 1215 */ 1216 ret = regmap_read(st->regmap, AD4030_REG_MODES, ®_modes); 1217 if (ret) 1218 return ret; 1219 1220 if (st->chip->num_voltage_inputs > 1 && 1221 FIELD_GET(AD4030_REG_MODES_MASK_LANE_MODE, reg_modes) == AD4030_LANE_MD_INTERLEAVED) 1222 return -EINVAL; 1223 1224 ad4030_prepare_offload_msg(indio_dev); 1225 st->offload_msg.offload = st->offload; 1226 ret = spi_optimize_message(st->spi, &st->offload_msg); 1227 if (ret) 1228 return ret; 1229 1230 ret = pwm_set_waveform_might_sleep(st->cnv_trigger, &st->cnv_wf, false); 1231 if (ret) 1232 goto out_unoptimize; 1233 1234 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, 1235 &st->offload_trigger_config); 1236 if (ret) 1237 goto out_pwm_disable; 1238 1239 return 0; 1240 1241 out_pwm_disable: 1242 pwm_disable(st->cnv_trigger); 1243 out_unoptimize: 1244 spi_unoptimize_message(&st->offload_msg); 1245 1246 return ret; 1247 } 1248 1249 static int ad4030_offload_buffer_predisable(struct iio_dev *indio_dev) 1250 { 1251 struct ad4030_state *st = iio_priv(indio_dev); 1252 1253 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1254 1255 pwm_disable(st->cnv_trigger); 1256 1257 spi_unoptimize_message(&st->offload_msg); 1258 1259 return 0; 1260 } 1261 1262 static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = { 1263 .postenable = &ad4030_offload_buffer_postenable, 1264 .predisable = &ad4030_offload_buffer_predisable, 1265 }; 1266 1267 static int ad4030_regulators_get(struct ad4030_state *st) 1268 { 1269 struct device *dev = &st->spi->dev; 1270 static const char * const ids[] = { "vdd-5v", "vdd-1v8" }; 1271 int ret; 1272 1273 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ids), ids); 1274 if (ret) 1275 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1276 1277 st->vio_uv = devm_regulator_get_enable_read_voltage(dev, "vio"); 1278 if (st->vio_uv < 0) 1279 return dev_err_probe(dev, st->vio_uv, 1280 "Failed to enable and read vio voltage\n"); 1281 1282 st->vref_uv = devm_regulator_get_enable_read_voltage(dev, "ref"); 1283 if (st->vref_uv < 0) { 1284 if (st->vref_uv != -ENODEV) 1285 return dev_err_probe(dev, st->vref_uv, 1286 "Failed to read ref voltage\n"); 1287 1288 /* if not using optional REF, the REFIN must be used */ 1289 st->vref_uv = devm_regulator_get_enable_read_voltage(dev, 1290 "refin"); 1291 if (st->vref_uv < 0) 1292 return dev_err_probe(dev, st->vref_uv, 1293 "Failed to read refin voltage\n"); 1294 } 1295 1296 return 0; 1297 } 1298 1299 static int ad4030_reset(struct ad4030_state *st) 1300 { 1301 struct device *dev = &st->spi->dev; 1302 struct gpio_desc *reset; 1303 1304 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1305 if (IS_ERR(reset)) 1306 return dev_err_probe(dev, PTR_ERR(reset), 1307 "Failed to get reset GPIO\n"); 1308 1309 if (reset) { 1310 ndelay(50); 1311 gpiod_set_value_cansleep(reset, 0); 1312 return 0; 1313 } 1314 1315 return regmap_write(st->regmap, AD4030_REG_INTERFACE_CONFIG_A, 1316 AD4030_REG_INTERFACE_CONFIG_A_SW_RESET); 1317 } 1318 1319 static int ad4030_detect_chip_info(const struct ad4030_state *st) 1320 { 1321 unsigned int grade; 1322 int ret; 1323 1324 ret = regmap_read(st->regmap, AD4030_REG_CHIP_GRADE, &grade); 1325 if (ret) 1326 return ret; 1327 1328 grade = FIELD_GET(AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE, grade); 1329 if (grade != st->chip->grade) 1330 dev_warn(&st->spi->dev, "Unknown grade(0x%x) for %s\n", grade, 1331 st->chip->name); 1332 1333 return 0; 1334 } 1335 1336 static int ad4030_pwm_get(struct ad4030_state *st) 1337 { 1338 struct device *dev = &st->spi->dev; 1339 1340 st->cnv_trigger = devm_pwm_get(dev, NULL); 1341 if (IS_ERR(st->cnv_trigger)) 1342 return dev_err_probe(dev, PTR_ERR(st->cnv_trigger), 1343 "Failed to get CNV PWM\n"); 1344 1345 /* 1346 * Preemptively disable the PWM, since we only want to enable it with 1347 * the buffer. 1348 */ 1349 pwm_disable(st->cnv_trigger); 1350 1351 return 0; 1352 } 1353 1354 static int ad4030_config(struct ad4030_state *st) 1355 { 1356 int ret; 1357 u8 reg_modes; 1358 1359 st->offset_avail[0] = (int)BIT(st->chip->precision_bits - 1) * -1; 1360 st->offset_avail[1] = 1; 1361 st->offset_avail[2] = BIT(st->chip->precision_bits - 1) - 1; 1362 1363 if (st->chip->num_voltage_inputs > 1) 1364 reg_modes = FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, 1365 AD4030_LANE_MD_INTERLEAVED); 1366 else 1367 reg_modes = FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, 1368 AD4030_LANE_MD_1_PER_CH); 1369 1370 ret = regmap_write(st->regmap, AD4030_REG_MODES, reg_modes); 1371 if (ret) 1372 return ret; 1373 1374 if (st->vio_uv < AD4030_VIO_THRESHOLD_UV) 1375 return regmap_write(st->regmap, AD4030_REG_IO, 1376 AD4030_REG_IO_MASK_IO2X); 1377 1378 return 0; 1379 } 1380 1381 static int ad4030_spi_offload_setup(struct iio_dev *indio_dev, 1382 struct ad4030_state *st) 1383 { 1384 struct device *dev = &st->spi->dev; 1385 struct dma_chan *rx_dma; 1386 1387 indio_dev->setup_ops = &ad4030_offload_buffer_setup_ops; 1388 1389 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1390 SPI_OFFLOAD_TRIGGER_PERIODIC); 1391 if (IS_ERR(st->offload_trigger)) 1392 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1393 "failed to get offload trigger\n"); 1394 1395 st->offload_trigger_config.type = SPI_OFFLOAD_TRIGGER_PERIODIC; 1396 1397 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1398 if (IS_ERR(rx_dma)) 1399 return dev_err_probe(dev, PTR_ERR(rx_dma), 1400 "failed to get offload RX DMA\n"); 1401 1402 return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 1403 IIO_BUFFER_DIRECTION_IN); 1404 } 1405 1406 static int ad4030_setup_pga(struct device *dev, struct iio_dev *indio_dev, 1407 struct ad4030_state *st) 1408 { 1409 /* Setup GPIOs for PGA control */ 1410 st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); 1411 if (IS_ERR(st->pga_gpios)) 1412 return dev_err_probe(dev, PTR_ERR(st->pga_gpios), 1413 "Failed to get PGA gpios.\n"); 1414 1415 if (st->pga_gpios->ndescs != ADAQ4616_PGA_PINS) 1416 return dev_err_probe(dev, -EINVAL, 1417 "Expected %d GPIOs for PGA control.\n", 1418 ADAQ4616_PGA_PINS); 1419 1420 st->scale_avail_size = ARRAY_SIZE(adaq4216_hw_gains_vpv); 1421 st->pga_index = 0; 1422 1423 return 0; 1424 } 1425 1426 static int ad4030_probe(struct spi_device *spi) 1427 { 1428 struct device *dev = &spi->dev; 1429 struct iio_dev *indio_dev; 1430 struct ad4030_state *st; 1431 int ret; 1432 1433 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1434 if (!indio_dev) 1435 return -ENOMEM; 1436 1437 st = iio_priv(indio_dev); 1438 st->spi = spi; 1439 1440 st->regmap = devm_regmap_init(dev, &ad4030_regmap_bus, st, 1441 &ad4030_regmap_config); 1442 if (IS_ERR(st->regmap)) 1443 return dev_err_probe(dev, PTR_ERR(st->regmap), 1444 "Failed to initialize regmap\n"); 1445 1446 st->chip = spi_get_device_match_data(spi); 1447 if (!st->chip) 1448 return -EINVAL; 1449 1450 ret = ad4030_regulators_get(st); 1451 if (ret) 1452 return ret; 1453 1454 /* 1455 * From datasheet: "Perform a reset no sooner than 3ms after the power 1456 * supplies are valid and stable" 1457 */ 1458 fsleep(3000); 1459 1460 ret = ad4030_reset(st); 1461 if (ret) 1462 return ret; 1463 1464 ret = ad4030_detect_chip_info(st); 1465 if (ret) 1466 return ret; 1467 1468 if (st->chip->has_pga) { 1469 ret = ad4030_setup_pga(dev, indio_dev, st); 1470 if (ret) 1471 return ret; 1472 1473 ad4030_fill_scale_avail(st); 1474 } 1475 1476 ret = ad4030_config(st); 1477 if (ret) 1478 return ret; 1479 1480 st->cnv_gpio = devm_gpiod_get(dev, "cnv", GPIOD_OUT_LOW); 1481 if (IS_ERR(st->cnv_gpio)) 1482 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), 1483 "Failed to get cnv gpio\n"); 1484 1485 indio_dev->name = st->chip->name; 1486 indio_dev->modes = INDIO_DIRECT_MODE; 1487 indio_dev->info = &ad4030_iio_info; 1488 indio_dev->available_scan_masks = st->chip->available_masks; 1489 1490 st->offload = devm_spi_offload_get(dev, spi, &ad4030_offload_config); 1491 ret = PTR_ERR_OR_ZERO(st->offload); 1492 /* Fall back to low speed usage when no SPI offload is available. */ 1493 if (ret == -ENODEV) { 1494 /* 1495 * One hardware channel is split in two software channels when 1496 * using common byte mode. Add one more channel for the timestamp. 1497 */ 1498 indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1; 1499 indio_dev->channels = st->chip->channels; 1500 1501 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1502 iio_pollfunc_store_time, 1503 ad4030_trigger_handler, 1504 &ad4030_buffer_setup_ops); 1505 if (ret) 1506 return dev_err_probe(dev, ret, 1507 "Failed to setup triggered buffer\n"); 1508 } else if (ret) { 1509 return dev_err_probe(dev, ret, "failed to get offload\n"); 1510 } else { 1511 /* 1512 * Offloaded SPI transfers can't support software timestamp so 1513 * no additional timestamp channel is added. 1514 */ 1515 indio_dev->num_channels = st->chip->num_voltage_inputs; 1516 indio_dev->channels = st->chip->offload_channels; 1517 ret = ad4030_spi_offload_setup(indio_dev, st); 1518 if (ret) 1519 return dev_err_probe(dev, ret, 1520 "Failed to setup SPI offload\n"); 1521 1522 ret = ad4030_pwm_get(st); 1523 if (ret) 1524 return dev_err_probe(dev, ret, "Failed to get PWM\n"); 1525 1526 /* 1527 * Start with a slower sampling rate so there is some room for 1528 * adjusting the sample averaging and the sampling frequency 1529 * without hitting the maximum conversion rate. 1530 */ 1531 ret = ad4030_update_conversion_rate(st, st->chip->max_sample_rate_hz >> 4, 1532 st->avg_log2); 1533 if (ret) 1534 return dev_err_probe(dev, ret, 1535 "Failed to set offload samp freq\n"); 1536 } 1537 1538 return devm_iio_device_register(dev, indio_dev); 1539 } 1540 1541 static const unsigned long ad4030_channel_masks[] = { 1542 /* Differential only */ 1543 BIT(0), 1544 /* Differential and common-mode voltage */ 1545 GENMASK(1, 0), 1546 0, 1547 }; 1548 1549 static const unsigned long ad4630_channel_masks[] = { 1550 /* Differential only */ 1551 BIT(1) | BIT(0), 1552 /* Differential with common byte */ 1553 GENMASK(3, 0), 1554 0, 1555 }; 1556 1557 static const struct iio_scan_type ad4030_24_scan_types[] = { 1558 [AD4030_SCAN_TYPE_NORMAL] = { 1559 .sign = 's', 1560 .storagebits = 32, 1561 .realbits = 24, 1562 .shift = 8, 1563 .endianness = IIO_BE, 1564 }, 1565 [AD4030_SCAN_TYPE_AVG] = { 1566 .sign = 's', 1567 .storagebits = 32, 1568 .realbits = 30, 1569 .shift = 2, 1570 .endianness = IIO_BE, 1571 }, 1572 }; 1573 1574 static const struct iio_scan_type ad4030_24_offload_scan_types[] = { 1575 [AD4030_SCAN_TYPE_NORMAL] = { 1576 .sign = 's', 1577 .realbits = 24, 1578 .storagebits = 32, 1579 .shift = 0, 1580 .endianness = IIO_CPU, 1581 }, 1582 [AD4030_SCAN_TYPE_AVG] = { 1583 .sign = 's', 1584 .realbits = 30, 1585 .storagebits = 32, 1586 .shift = 2, 1587 .endianness = IIO_CPU, 1588 }, 1589 }; 1590 1591 static const struct iio_scan_type ad4030_16_scan_types[] = { 1592 [AD4030_SCAN_TYPE_NORMAL] = { 1593 .sign = 's', 1594 .realbits = 16, 1595 .storagebits = 32, 1596 .shift = 16, 1597 .endianness = IIO_BE, 1598 }, 1599 [AD4030_SCAN_TYPE_AVG] = { 1600 .sign = 's', 1601 .storagebits = 32, 1602 .realbits = 30, 1603 .shift = 2, 1604 .endianness = IIO_BE, 1605 } 1606 }; 1607 1608 static const struct iio_scan_type ad4030_16_offload_scan_types[] = { 1609 [AD4030_SCAN_TYPE_NORMAL] = { 1610 .sign = 's', 1611 .realbits = 16, 1612 .storagebits = 32, 1613 .shift = 0, 1614 .endianness = IIO_CPU, 1615 }, 1616 [AD4030_SCAN_TYPE_AVG] = { 1617 .sign = 's', 1618 .realbits = 30, 1619 .storagebits = 32, 1620 .shift = 2, 1621 .endianness = IIO_CPU, 1622 }, 1623 }; 1624 1625 static const struct ad4030_chip_info ad4030_24_chip_info = { 1626 .name = "ad4030-24", 1627 .available_masks = ad4030_channel_masks, 1628 .channels = { 1629 AD4030_CHAN_DIFF(0, ad4030_24_scan_types), 1630 AD4030_CHAN_CMO(1, 0), 1631 IIO_CHAN_SOFT_TIMESTAMP(2), 1632 }, 1633 .offload_channels = { 1634 AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1635 }, 1636 .grade = AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, 1637 .precision_bits = 24, 1638 .num_voltage_inputs = 1, 1639 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1640 .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1641 }; 1642 1643 static const struct ad4030_chip_info ad4630_16_chip_info = { 1644 .name = "ad4630-16", 1645 .available_masks = ad4630_channel_masks, 1646 .channels = { 1647 AD4030_CHAN_DIFF(0, ad4030_16_scan_types), 1648 AD4030_CHAN_DIFF(1, ad4030_16_scan_types), 1649 AD4030_CHAN_CMO(2, 0), 1650 AD4030_CHAN_CMO(3, 1), 1651 IIO_CHAN_SOFT_TIMESTAMP(4), 1652 }, 1653 .offload_channels = { 1654 AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1655 AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), 1656 }, 1657 .grade = AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, 1658 .precision_bits = 16, 1659 .num_voltage_inputs = 2, 1660 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1661 .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1662 }; 1663 1664 static const struct ad4030_chip_info ad4630_24_chip_info = { 1665 .name = "ad4630-24", 1666 .available_masks = ad4630_channel_masks, 1667 .channels = { 1668 AD4030_CHAN_DIFF(0, ad4030_24_scan_types), 1669 AD4030_CHAN_DIFF(1, ad4030_24_scan_types), 1670 AD4030_CHAN_CMO(2, 0), 1671 AD4030_CHAN_CMO(3, 1), 1672 IIO_CHAN_SOFT_TIMESTAMP(4), 1673 }, 1674 .offload_channels = { 1675 AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1676 AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), 1677 }, 1678 .grade = AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, 1679 .precision_bits = 24, 1680 .num_voltage_inputs = 2, 1681 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1682 .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1683 }; 1684 1685 static const struct ad4030_chip_info ad4632_16_chip_info = { 1686 .name = "ad4632-16", 1687 .available_masks = ad4630_channel_masks, 1688 .channels = { 1689 AD4030_CHAN_DIFF(0, ad4030_16_scan_types), 1690 AD4030_CHAN_DIFF(1, ad4030_16_scan_types), 1691 AD4030_CHAN_CMO(2, 0), 1692 AD4030_CHAN_CMO(3, 1), 1693 IIO_CHAN_SOFT_TIMESTAMP(4), 1694 }, 1695 .offload_channels = { 1696 AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1697 AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), 1698 }, 1699 .grade = AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, 1700 .precision_bits = 16, 1701 .num_voltage_inputs = 2, 1702 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS, 1703 .max_sample_rate_hz = 500 * HZ_PER_KHZ, 1704 }; 1705 1706 static const struct ad4030_chip_info ad4632_24_chip_info = { 1707 .name = "ad4632-24", 1708 .available_masks = ad4630_channel_masks, 1709 .channels = { 1710 AD4030_CHAN_DIFF(0, ad4030_24_scan_types), 1711 AD4030_CHAN_DIFF(1, ad4030_24_scan_types), 1712 AD4030_CHAN_CMO(2, 0), 1713 AD4030_CHAN_CMO(3, 1), 1714 IIO_CHAN_SOFT_TIMESTAMP(4), 1715 }, 1716 .offload_channels = { 1717 AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1718 AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), 1719 }, 1720 .grade = AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, 1721 .precision_bits = 24, 1722 .num_voltage_inputs = 2, 1723 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS, 1724 .max_sample_rate_hz = 500 * HZ_PER_KHZ, 1725 }; 1726 1727 static const struct ad4030_chip_info adaq4216_chip_info = { 1728 .name = "adaq4216", 1729 .available_masks = ad4030_channel_masks, 1730 .channels = { 1731 ADAQ4216_CHAN_DIFF(0, ad4030_16_scan_types), 1732 AD4030_CHAN_CMO(1, 0), 1733 IIO_CHAN_SOFT_TIMESTAMP(2), 1734 }, 1735 .offload_channels = { 1736 ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1737 }, 1738 .grade = AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, 1739 .precision_bits = 16, 1740 .has_pga = true, 1741 .num_voltage_inputs = 1, 1742 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1743 .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1744 }; 1745 1746 static const struct ad4030_chip_info adaq4224_chip_info = { 1747 .name = "adaq4224", 1748 .available_masks = ad4030_channel_masks, 1749 .channels = { 1750 ADAQ4216_CHAN_DIFF(0, ad4030_24_scan_types), 1751 AD4030_CHAN_CMO(1, 0), 1752 IIO_CHAN_SOFT_TIMESTAMP(2), 1753 }, 1754 .offload_channels = { 1755 ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1756 }, 1757 .grade = AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, 1758 .precision_bits = 24, 1759 .has_pga = true, 1760 .num_voltage_inputs = 1, 1761 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1762 .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1763 }; 1764 1765 static const struct spi_device_id ad4030_id_table[] = { 1766 { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info }, 1767 { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info }, 1768 { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, 1769 { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info }, 1770 { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info }, 1771 { "adaq4216", (kernel_ulong_t)&adaq4216_chip_info }, 1772 { "adaq4224", (kernel_ulong_t)&adaq4224_chip_info }, 1773 { } 1774 }; 1775 MODULE_DEVICE_TABLE(spi, ad4030_id_table); 1776 1777 static const struct of_device_id ad4030_of_match[] = { 1778 { .compatible = "adi,ad4030-24", .data = &ad4030_24_chip_info }, 1779 { .compatible = "adi,ad4630-16", .data = &ad4630_16_chip_info }, 1780 { .compatible = "adi,ad4630-24", .data = &ad4630_24_chip_info }, 1781 { .compatible = "adi,ad4632-16", .data = &ad4632_16_chip_info }, 1782 { .compatible = "adi,ad4632-24", .data = &ad4632_24_chip_info }, 1783 { .compatible = "adi,adaq4216", .data = &adaq4216_chip_info }, 1784 { .compatible = "adi,adaq4224", .data = &adaq4224_chip_info }, 1785 { } 1786 }; 1787 MODULE_DEVICE_TABLE(of, ad4030_of_match); 1788 1789 static struct spi_driver ad4030_driver = { 1790 .driver = { 1791 .name = "ad4030", 1792 .of_match_table = ad4030_of_match, 1793 }, 1794 .probe = ad4030_probe, 1795 .id_table = ad4030_id_table, 1796 }; 1797 module_spi_driver(ad4030_driver); 1798 1799 MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>"); 1800 MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver"); 1801 MODULE_LICENSE("GPL"); 1802 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 1803