1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD4000 SPI ADC driver 4 * 5 * Copyright 2024 Analog Devices Inc. 6 */ 7 #include <linux/bits.h> 8 #include <linux/bitfield.h> 9 #include <linux/byteorder/generic.h> 10 #include <linux/cleanup.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/math.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/spi/spi.h> 19 #include <linux/units.h> 20 #include <linux/util_macros.h> 21 #include <linux/iio/iio.h> 22 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/triggered_buffer.h> 25 #include <linux/iio/trigger_consumer.h> 26 27 #define AD4000_READ_COMMAND 0x54 28 #define AD4000_WRITE_COMMAND 0x14 29 30 #define AD4000_CONFIG_REG_DEFAULT 0xE1 31 32 /* AD4000 Configuration Register programmable bits */ 33 #define AD4000_CFG_SPAN_COMP BIT(3) /* Input span compression */ 34 #define AD4000_CFG_HIGHZ BIT(2) /* High impedance mode */ 35 36 #define AD4000_SCALE_OPTIONS 2 37 38 #define __AD4000_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_access) \ 39 { \ 40 .type = IIO_VOLTAGE, \ 41 .indexed = 1, \ 42 .differential = 1, \ 43 .channel = 0, \ 44 .channel2 = 1, \ 45 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 46 BIT(IIO_CHAN_INFO_SCALE), \ 47 .info_mask_separate_available = _reg_access ? BIT(IIO_CHAN_INFO_SCALE) : 0,\ 48 .scan_index = 0, \ 49 .scan_type = { \ 50 .sign = _sign, \ 51 .realbits = _real_bits, \ 52 .storagebits = _storage_bits, \ 53 .shift = _storage_bits - _real_bits, \ 54 .endianness = IIO_BE, \ 55 }, \ 56 } 57 58 #define AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access) \ 59 __AD4000_DIFF_CHANNEL((_sign), (_real_bits), \ 60 ((_real_bits) > 16 ? 32 : 16), (_reg_access)) 61 62 #define AD4000_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ 63 { \ 64 AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access), \ 65 IIO_CHAN_SOFT_TIMESTAMP(1), \ 66 } 67 68 #define __AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_access)\ 69 { \ 70 .type = IIO_VOLTAGE, \ 71 .indexed = 1, \ 72 .channel = 0, \ 73 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 74 BIT(IIO_CHAN_INFO_SCALE) | \ 75 BIT(IIO_CHAN_INFO_OFFSET), \ 76 .info_mask_separate_available = _reg_access ? BIT(IIO_CHAN_INFO_SCALE) : 0,\ 77 .scan_index = 0, \ 78 .scan_type = { \ 79 .sign = _sign, \ 80 .realbits = _real_bits, \ 81 .storagebits = _storage_bits, \ 82 .shift = _storage_bits - _real_bits, \ 83 .endianness = IIO_BE, \ 84 }, \ 85 } 86 87 #define AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access) \ 88 __AD4000_PSEUDO_DIFF_CHANNEL((_sign), (_real_bits), \ 89 ((_real_bits) > 16 ? 32 : 16), (_reg_access)) 90 91 #define AD4000_PSEUDO_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ 92 { \ 93 AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access), \ 94 IIO_CHAN_SOFT_TIMESTAMP(1), \ 95 } 96 97 static const char * const ad4000_power_supplies[] = { 98 "vdd", "vio" 99 }; 100 101 enum ad4000_sdi { 102 AD4000_SDI_MOSI, 103 AD4000_SDI_VIO, 104 AD4000_SDI_CS, 105 AD4000_SDI_GND, 106 }; 107 108 /* maps adi,sdi-pin property value to enum */ 109 static const char * const ad4000_sdi_pin[] = { 110 [AD4000_SDI_MOSI] = "sdi", 111 [AD4000_SDI_VIO] = "high", 112 [AD4000_SDI_CS] = "cs", 113 [AD4000_SDI_GND] = "low", 114 }; 115 116 /* Gains stored as fractions of 1000 so they can be expressed by integers. */ 117 static const int ad4000_gains[] = { 118 454, 909, 1000, 1900, 119 }; 120 121 struct ad4000_time_spec { 122 int t_conv_ns; 123 int t_quiet2_ns; 124 }; 125 126 /* 127 * Same timing specifications for all of AD4000, AD4001, ..., AD4008, AD4010, 128 * ADAQ4001, and ADAQ4003. 129 */ 130 static const struct ad4000_time_spec ad4000_t_spec = { 131 .t_conv_ns = 320, 132 .t_quiet2_ns = 60, 133 }; 134 135 /* AD4020, AD4021, AD4022 */ 136 static const struct ad4000_time_spec ad4020_t_spec = { 137 .t_conv_ns = 350, 138 .t_quiet2_ns = 60, 139 }; 140 141 /* AD7983, AD7984 */ 142 static const struct ad4000_time_spec ad7983_t_spec = { 143 .t_conv_ns = 500, 144 .t_quiet2_ns = 0, 145 }; 146 147 /* AD7980, AD7982 */ 148 static const struct ad4000_time_spec ad7980_t_spec = { 149 .t_conv_ns = 800, 150 .t_quiet2_ns = 0, 151 }; 152 153 /* AD7946, AD7686, AD7688, AD7988-5, AD7693 */ 154 static const struct ad4000_time_spec ad7686_t_spec = { 155 .t_conv_ns = 1600, 156 .t_quiet2_ns = 0, 157 }; 158 159 /* AD7690 */ 160 static const struct ad4000_time_spec ad7690_t_spec = { 161 .t_conv_ns = 2100, 162 .t_quiet2_ns = 0, 163 }; 164 165 /* AD7942, AD7685, AD7687 */ 166 static const struct ad4000_time_spec ad7687_t_spec = { 167 .t_conv_ns = 3200, 168 .t_quiet2_ns = 0, 169 }; 170 171 /* AD7691 */ 172 static const struct ad4000_time_spec ad7691_t_spec = { 173 .t_conv_ns = 3700, 174 .t_quiet2_ns = 0, 175 }; 176 177 /* AD7988-1 */ 178 static const struct ad4000_time_spec ad7988_1_t_spec = { 179 .t_conv_ns = 9500, 180 .t_quiet2_ns = 0, 181 }; 182 183 struct ad4000_chip_info { 184 const char *dev_name; 185 struct iio_chan_spec chan_spec[2]; 186 struct iio_chan_spec reg_access_chan_spec[2]; 187 const struct ad4000_time_spec *time_spec; 188 bool has_hardware_gain; 189 }; 190 191 static const struct ad4000_chip_info ad4000_chip_info = { 192 .dev_name = "ad4000", 193 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 194 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), 195 .time_spec = &ad4000_t_spec, 196 }; 197 198 static const struct ad4000_chip_info ad4001_chip_info = { 199 .dev_name = "ad4001", 200 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 201 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1), 202 .time_spec = &ad4000_t_spec, 203 }; 204 205 static const struct ad4000_chip_info ad4002_chip_info = { 206 .dev_name = "ad4002", 207 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), 208 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), 209 .time_spec = &ad4000_t_spec, 210 }; 211 212 static const struct ad4000_chip_info ad4003_chip_info = { 213 .dev_name = "ad4003", 214 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 215 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 216 .time_spec = &ad4000_t_spec, 217 }; 218 219 static const struct ad4000_chip_info ad4004_chip_info = { 220 .dev_name = "ad4004", 221 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 222 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), 223 .time_spec = &ad4000_t_spec, 224 }; 225 226 static const struct ad4000_chip_info ad4005_chip_info = { 227 .dev_name = "ad4005", 228 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 229 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1), 230 .time_spec = &ad4000_t_spec, 231 }; 232 233 static const struct ad4000_chip_info ad4006_chip_info = { 234 .dev_name = "ad4006", 235 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), 236 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), 237 .time_spec = &ad4000_t_spec, 238 }; 239 240 static const struct ad4000_chip_info ad4007_chip_info = { 241 .dev_name = "ad4007", 242 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 243 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 244 .time_spec = &ad4000_t_spec, 245 }; 246 247 static const struct ad4000_chip_info ad4008_chip_info = { 248 .dev_name = "ad4008", 249 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 250 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), 251 .time_spec = &ad4000_t_spec, 252 }; 253 254 static const struct ad4000_chip_info ad4010_chip_info = { 255 .dev_name = "ad4010", 256 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), 257 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), 258 .time_spec = &ad4000_t_spec, 259 }; 260 261 static const struct ad4000_chip_info ad4011_chip_info = { 262 .dev_name = "ad4011", 263 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 264 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 265 .time_spec = &ad4000_t_spec, 266 }; 267 268 static const struct ad4000_chip_info ad4020_chip_info = { 269 .dev_name = "ad4020", 270 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0), 271 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1), 272 .time_spec = &ad4020_t_spec, 273 }; 274 275 static const struct ad4000_chip_info ad4021_chip_info = { 276 .dev_name = "ad4021", 277 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0), 278 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1), 279 .time_spec = &ad4020_t_spec, 280 }; 281 282 static const struct ad4000_chip_info ad4022_chip_info = { 283 .dev_name = "ad4022", 284 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0), 285 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1), 286 .time_spec = &ad4020_t_spec, 287 }; 288 289 static const struct ad4000_chip_info adaq4001_chip_info = { 290 .dev_name = "adaq4001", 291 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 292 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1), 293 .time_spec = &ad4000_t_spec, 294 .has_hardware_gain = true, 295 }; 296 297 static const struct ad4000_chip_info adaq4003_chip_info = { 298 .dev_name = "adaq4003", 299 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 300 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 301 .time_spec = &ad4000_t_spec, 302 .has_hardware_gain = true, 303 }; 304 305 static const struct ad4000_chip_info ad7685_chip_info = { 306 .dev_name = "ad7685", 307 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 308 .time_spec = &ad7687_t_spec, 309 }; 310 311 static const struct ad4000_chip_info ad7686_chip_info = { 312 .dev_name = "ad7686", 313 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 314 .time_spec = &ad7686_t_spec, 315 }; 316 317 static const struct ad4000_chip_info ad7687_chip_info = { 318 .dev_name = "ad7687", 319 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 320 .time_spec = &ad7687_t_spec, 321 }; 322 323 static const struct ad4000_chip_info ad7688_chip_info = { 324 .dev_name = "ad7688", 325 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 326 .time_spec = &ad7686_t_spec, 327 }; 328 329 static const struct ad4000_chip_info ad7690_chip_info = { 330 .dev_name = "ad7690", 331 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 332 .time_spec = &ad7690_t_spec, 333 }; 334 335 static const struct ad4000_chip_info ad7691_chip_info = { 336 .dev_name = "ad7691", 337 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 338 .time_spec = &ad7691_t_spec, 339 }; 340 341 static const struct ad4000_chip_info ad7693_chip_info = { 342 .dev_name = "ad7693", 343 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 344 .time_spec = &ad7686_t_spec, 345 }; 346 347 static const struct ad4000_chip_info ad7942_chip_info = { 348 .dev_name = "ad7942", 349 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), 350 .time_spec = &ad7687_t_spec, 351 }; 352 353 static const struct ad4000_chip_info ad7946_chip_info = { 354 .dev_name = "ad7946", 355 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), 356 .time_spec = &ad7686_t_spec, 357 }; 358 359 static const struct ad4000_chip_info ad7980_chip_info = { 360 .dev_name = "ad7980", 361 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 362 .time_spec = &ad7980_t_spec, 363 }; 364 365 static const struct ad4000_chip_info ad7982_chip_info = { 366 .dev_name = "ad7982", 367 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 368 .time_spec = &ad7980_t_spec, 369 }; 370 371 static const struct ad4000_chip_info ad7983_chip_info = { 372 .dev_name = "ad7983", 373 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 374 .time_spec = &ad7983_t_spec, 375 }; 376 377 static const struct ad4000_chip_info ad7984_chip_info = { 378 .dev_name = "ad7984", 379 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 380 .time_spec = &ad7983_t_spec, 381 }; 382 383 static const struct ad4000_chip_info ad7988_1_chip_info = { 384 .dev_name = "ad7988-1", 385 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 386 .time_spec = &ad7988_1_t_spec, 387 }; 388 389 static const struct ad4000_chip_info ad7988_5_chip_info = { 390 .dev_name = "ad7988-5", 391 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 392 .time_spec = &ad7686_t_spec, 393 }; 394 395 struct ad4000_state { 396 struct spi_device *spi; 397 struct gpio_desc *cnv_gpio; 398 struct spi_transfer xfers[2]; 399 struct spi_message msg; 400 struct mutex lock; /* Protect read modify write cycle */ 401 int vref_mv; 402 enum ad4000_sdi sdi_pin; 403 bool span_comp; 404 u16 gain_milli; 405 int scale_tbl[AD4000_SCALE_OPTIONS][2]; 406 const struct ad4000_time_spec *time_spec; 407 408 /* 409 * DMA (thus cache coherency maintenance) requires the transfer buffers 410 * to live in their own cache lines. 411 */ 412 struct { 413 union { 414 __be16 sample_buf16; 415 __be32 sample_buf32; 416 } data; 417 aligned_s64 timestamp; 418 } scan __aligned(IIO_DMA_MINALIGN); 419 u8 tx_buf[2]; 420 u8 rx_buf[2]; 421 }; 422 423 static void ad4000_fill_scale_tbl(struct ad4000_state *st, 424 struct iio_chan_spec const *chan) 425 { 426 int val, tmp0, tmp1; 427 int scale_bits; 428 u64 tmp2; 429 430 /* 431 * ADCs that output two's complement code have one less bit to express 432 * voltage magnitude. 433 */ 434 if (chan->scan_type.sign == 's') 435 scale_bits = chan->scan_type.realbits - 1; 436 else 437 scale_bits = chan->scan_type.realbits; 438 439 /* 440 * The gain is stored as a fraction of 1000 and, as we need to 441 * divide vref_mv by the gain, we invert the gain/1000 fraction. 442 * Also multiply by an extra MILLI to preserve precision. 443 * Thus, we have MILLI * MILLI equals MICRO as fraction numerator. 444 */ 445 val = mult_frac(st->vref_mv, MICRO, st->gain_milli); 446 447 /* Would multiply by NANO here but we multiplied by extra MILLI */ 448 tmp2 = shift_right((u64)val * MICRO, scale_bits); 449 tmp0 = div_s64_rem(tmp2, NANO, &tmp1); 450 451 /* Store scale for when span compression is disabled */ 452 st->scale_tbl[0][0] = tmp0; /* Integer part */ 453 st->scale_tbl[0][1] = abs(tmp1); /* Fractional part */ 454 455 /* Store scale for when span compression is enabled */ 456 st->scale_tbl[1][0] = tmp0; 457 458 /* The integer part is always zero so don't bother to divide it. */ 459 if (chan->differential) 460 st->scale_tbl[1][1] = DIV_ROUND_CLOSEST(abs(tmp1) * 4, 5); 461 else 462 st->scale_tbl[1][1] = DIV_ROUND_CLOSEST(abs(tmp1) * 9, 10); 463 } 464 465 static int ad4000_write_reg(struct ad4000_state *st, uint8_t val) 466 { 467 st->tx_buf[0] = AD4000_WRITE_COMMAND; 468 st->tx_buf[1] = val; 469 return spi_write(st->spi, st->tx_buf, ARRAY_SIZE(st->tx_buf)); 470 } 471 472 static int ad4000_read_reg(struct ad4000_state *st, unsigned int *val) 473 { 474 struct spi_transfer t = { 475 .tx_buf = st->tx_buf, 476 .rx_buf = st->rx_buf, 477 .len = 2, 478 }; 479 int ret; 480 481 st->tx_buf[0] = AD4000_READ_COMMAND; 482 ret = spi_sync_transfer(st->spi, &t, 1); 483 if (ret < 0) 484 return ret; 485 486 *val = st->rx_buf[1]; 487 return ret; 488 } 489 490 static int ad4000_convert_and_acquire(struct ad4000_state *st) 491 { 492 int ret; 493 494 /* 495 * In 4-wire mode, the CNV line is held high for the entire conversion 496 * and acquisition process. In other modes, the CNV GPIO is optional 497 * and, if provided, replaces controller CS. If CNV GPIO is not defined 498 * gpiod_set_value_cansleep() has no effect. 499 */ 500 gpiod_set_value_cansleep(st->cnv_gpio, 1); 501 ret = spi_sync(st->spi, &st->msg); 502 gpiod_set_value_cansleep(st->cnv_gpio, 0); 503 504 return ret; 505 } 506 507 static int ad4000_single_conversion(struct iio_dev *indio_dev, 508 const struct iio_chan_spec *chan, int *val) 509 { 510 struct ad4000_state *st = iio_priv(indio_dev); 511 u32 sample; 512 int ret; 513 514 ret = ad4000_convert_and_acquire(st); 515 if (ret < 0) 516 return ret; 517 518 if (chan->scan_type.storagebits > 16) 519 sample = be32_to_cpu(st->scan.data.sample_buf32); 520 else 521 sample = be16_to_cpu(st->scan.data.sample_buf16); 522 523 sample >>= chan->scan_type.shift; 524 525 if (chan->scan_type.sign == 's') 526 *val = sign_extend32(sample, chan->scan_type.realbits - 1); 527 else 528 *val = sample; 529 530 return IIO_VAL_INT; 531 } 532 533 static int ad4000_read_raw(struct iio_dev *indio_dev, 534 struct iio_chan_spec const *chan, int *val, 535 int *val2, long info) 536 { 537 struct ad4000_state *st = iio_priv(indio_dev); 538 int ret; 539 540 switch (info) { 541 case IIO_CHAN_INFO_RAW: 542 if (!iio_device_claim_direct(indio_dev)) 543 return -EBUSY; 544 545 ret = ad4000_single_conversion(indio_dev, chan, val); 546 iio_device_release_direct(indio_dev); 547 return ret; 548 case IIO_CHAN_INFO_SCALE: 549 *val = st->scale_tbl[st->span_comp][0]; 550 *val2 = st->scale_tbl[st->span_comp][1]; 551 return IIO_VAL_INT_PLUS_NANO; 552 case IIO_CHAN_INFO_OFFSET: 553 *val = 0; 554 if (st->span_comp) 555 *val = mult_frac(st->vref_mv, 1, 10); 556 557 return IIO_VAL_INT; 558 default: 559 return -EINVAL; 560 } 561 } 562 563 static int ad4000_read_avail(struct iio_dev *indio_dev, 564 struct iio_chan_spec const *chan, 565 const int **vals, int *type, int *length, 566 long info) 567 { 568 struct ad4000_state *st = iio_priv(indio_dev); 569 570 switch (info) { 571 case IIO_CHAN_INFO_SCALE: 572 *vals = (int *)st->scale_tbl; 573 *length = AD4000_SCALE_OPTIONS * 2; 574 *type = IIO_VAL_INT_PLUS_NANO; 575 return IIO_AVAIL_LIST; 576 default: 577 return -EINVAL; 578 } 579 } 580 581 static int ad4000_write_raw_get_fmt(struct iio_dev *indio_dev, 582 struct iio_chan_spec const *chan, long mask) 583 { 584 switch (mask) { 585 case IIO_CHAN_INFO_SCALE: 586 return IIO_VAL_INT_PLUS_NANO; 587 default: 588 return IIO_VAL_INT_PLUS_MICRO; 589 } 590 } 591 592 static int __ad4000_write_raw(struct iio_dev *indio_dev, 593 struct iio_chan_spec const *chan, 594 int val2) 595 { 596 struct ad4000_state *st = iio_priv(indio_dev); 597 unsigned int reg_val; 598 bool span_comp_en; 599 int ret; 600 601 guard(mutex)(&st->lock); 602 603 ret = ad4000_read_reg(st, ®_val); 604 if (ret < 0) 605 return ret; 606 607 span_comp_en = val2 == st->scale_tbl[1][1]; 608 reg_val &= ~AD4000_CFG_SPAN_COMP; 609 reg_val |= FIELD_PREP(AD4000_CFG_SPAN_COMP, span_comp_en); 610 611 ret = ad4000_write_reg(st, reg_val); 612 if (ret < 0) 613 return ret; 614 615 st->span_comp = span_comp_en; 616 return 0; 617 } 618 619 static int ad4000_write_raw(struct iio_dev *indio_dev, 620 struct iio_chan_spec const *chan, 621 int val, int val2, long mask) 622 { 623 int ret; 624 625 switch (mask) { 626 case IIO_CHAN_INFO_SCALE: 627 if (!iio_device_claim_direct(indio_dev)) 628 return -EBUSY; 629 ret = __ad4000_write_raw(indio_dev, chan, val2); 630 iio_device_release_direct(indio_dev); 631 return ret; 632 default: 633 return -EINVAL; 634 } 635 } 636 637 static irqreturn_t ad4000_trigger_handler(int irq, void *p) 638 { 639 struct iio_poll_func *pf = p; 640 struct iio_dev *indio_dev = pf->indio_dev; 641 struct ad4000_state *st = iio_priv(indio_dev); 642 int ret; 643 644 ret = ad4000_convert_and_acquire(st); 645 if (ret < 0) 646 goto err_out; 647 648 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan, pf->timestamp); 649 650 err_out: 651 iio_trigger_notify_done(indio_dev->trig); 652 return IRQ_HANDLED; 653 } 654 655 static const struct iio_info ad4000_reg_access_info = { 656 .read_raw = &ad4000_read_raw, 657 .read_avail = &ad4000_read_avail, 658 .write_raw = &ad4000_write_raw, 659 .write_raw_get_fmt = &ad4000_write_raw_get_fmt, 660 }; 661 662 static const struct iio_info ad4000_info = { 663 .read_raw = &ad4000_read_raw, 664 }; 665 666 /* 667 * This executes a data sample transfer for when the device connections are 668 * in "3-wire" mode, selected when the adi,sdi-pin device tree property is 669 * absent or set to "high". In this connection mode, the ADC SDI pin is 670 * connected to MOSI or to VIO and ADC CNV pin is connected either to a SPI 671 * controller CS or to a GPIO. 672 * AD4000 series of devices initiate conversions on the rising edge of CNV pin. 673 * 674 * If the CNV pin is connected to an SPI controller CS line (which is by default 675 * active low), the ADC readings would have a latency (delay) of one read. 676 * Moreover, since we also do ADC sampling for filling the buffer on triggered 677 * buffer mode, the timestamps of buffer readings would be disarranged. 678 * To prevent the read latency and reduce the time discrepancy between the 679 * sample read request and the time of actual sampling by the ADC, do a 680 * preparatory transfer to pulse the CS/CNV line. 681 */ 682 static int ad4000_prepare_3wire_mode_message(struct ad4000_state *st, 683 const struct iio_chan_spec *chan) 684 { 685 struct spi_transfer *xfers = st->xfers; 686 687 xfers[0].cs_change = 1; 688 xfers[0].cs_change_delay.value = st->time_spec->t_conv_ns; 689 xfers[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 690 691 xfers[1].rx_buf = &st->scan.data; 692 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits); 693 xfers[1].delay.value = st->time_spec->t_quiet2_ns; 694 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS; 695 696 spi_message_init_with_transfers(&st->msg, st->xfers, 2); 697 698 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg); 699 } 700 701 /* 702 * This executes a data sample transfer for when the device connections are 703 * in "4-wire" mode, selected when the adi,sdi-pin device tree property is 704 * set to "cs". In this connection mode, the controller CS pin is connected to 705 * ADC SDI pin and a GPIO is connected to ADC CNV pin. 706 * The GPIO connected to ADC CNV pin is set outside of the SPI transfer. 707 */ 708 static int ad4000_prepare_4wire_mode_message(struct ad4000_state *st, 709 const struct iio_chan_spec *chan) 710 { 711 struct spi_transfer *xfers = st->xfers; 712 713 /* 714 * Dummy transfer to cause enough delay between CNV going high and SDI 715 * going low. 716 */ 717 xfers[0].cs_off = 1; 718 xfers[0].delay.value = st->time_spec->t_conv_ns; 719 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 720 721 xfers[1].rx_buf = &st->scan.data; 722 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits); 723 724 spi_message_init_with_transfers(&st->msg, st->xfers, 2); 725 726 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg); 727 } 728 729 static int ad4000_config(struct ad4000_state *st) 730 { 731 unsigned int reg_val = AD4000_CONFIG_REG_DEFAULT; 732 733 if (device_property_present(&st->spi->dev, "adi,high-z-input")) 734 reg_val |= FIELD_PREP(AD4000_CFG_HIGHZ, 1); 735 736 return ad4000_write_reg(st, reg_val); 737 } 738 739 static int ad4000_probe(struct spi_device *spi) 740 { 741 const struct ad4000_chip_info *chip; 742 struct device *dev = &spi->dev; 743 struct iio_dev *indio_dev; 744 struct ad4000_state *st; 745 int gain_idx, ret; 746 747 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 748 if (!indio_dev) 749 return -ENOMEM; 750 751 chip = spi_get_device_match_data(spi); 752 if (!chip) 753 return -EINVAL; 754 755 st = iio_priv(indio_dev); 756 st->spi = spi; 757 st->time_spec = chip->time_spec; 758 759 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4000_power_supplies), 760 ad4000_power_supplies); 761 if (ret) 762 return dev_err_probe(dev, ret, "Failed to enable power supplies\n"); 763 764 ret = devm_regulator_get_enable_read_voltage(dev, "ref"); 765 if (ret < 0) 766 return dev_err_probe(dev, ret, 767 "Failed to get ref regulator reference\n"); 768 st->vref_mv = ret / 1000; 769 770 st->cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_HIGH); 771 if (IS_ERR(st->cnv_gpio)) 772 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), 773 "Failed to get CNV GPIO"); 774 775 ret = device_property_match_property_string(dev, "adi,sdi-pin", 776 ad4000_sdi_pin, 777 ARRAY_SIZE(ad4000_sdi_pin)); 778 if (ret < 0 && ret != -EINVAL) 779 return dev_err_probe(dev, ret, 780 "getting adi,sdi-pin property failed\n"); 781 782 /* Default to usual SPI connections if pin properties are not present */ 783 st->sdi_pin = ret == -EINVAL ? AD4000_SDI_MOSI : ret; 784 switch (st->sdi_pin) { 785 case AD4000_SDI_MOSI: 786 indio_dev->info = &ad4000_reg_access_info; 787 indio_dev->channels = chip->reg_access_chan_spec; 788 789 /* 790 * In "3-wire mode", the ADC SDI line must be kept high when 791 * data is not being clocked out of the controller. 792 * Request the SPI controller to make MOSI idle high. 793 */ 794 spi->mode |= SPI_MOSI_IDLE_HIGH; 795 ret = spi_setup(spi); 796 if (ret < 0) 797 return ret; 798 799 ret = ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); 800 if (ret) 801 return ret; 802 803 ret = ad4000_config(st); 804 if (ret < 0) 805 return dev_err_probe(dev, ret, "Failed to config device\n"); 806 807 break; 808 case AD4000_SDI_VIO: 809 indio_dev->info = &ad4000_info; 810 indio_dev->channels = chip->chan_spec; 811 ret = ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); 812 if (ret) 813 return ret; 814 815 break; 816 case AD4000_SDI_CS: 817 indio_dev->info = &ad4000_info; 818 indio_dev->channels = chip->chan_spec; 819 ret = ad4000_prepare_4wire_mode_message(st, &indio_dev->channels[0]); 820 if (ret) 821 return ret; 822 823 break; 824 case AD4000_SDI_GND: 825 return dev_err_probe(dev, -EPROTONOSUPPORT, 826 "Unsupported connection mode\n"); 827 828 default: 829 return dev_err_probe(dev, -EINVAL, "Unrecognized connection mode\n"); 830 } 831 832 indio_dev->name = chip->dev_name; 833 indio_dev->num_channels = 2; 834 835 ret = devm_mutex_init(dev, &st->lock); 836 if (ret) 837 return ret; 838 839 st->gain_milli = 1000; 840 if (chip->has_hardware_gain) { 841 ret = device_property_read_u16(dev, "adi,gain-milli", 842 &st->gain_milli); 843 if (!ret) { 844 /* Match gain value from dt to one of supported gains */ 845 gain_idx = find_closest(st->gain_milli, ad4000_gains, 846 ARRAY_SIZE(ad4000_gains)); 847 st->gain_milli = ad4000_gains[gain_idx]; 848 } else { 849 return dev_err_probe(dev, ret, 850 "Failed to read gain property\n"); 851 } 852 } 853 854 ad4000_fill_scale_tbl(st, &indio_dev->channels[0]); 855 856 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 857 &iio_pollfunc_store_time, 858 &ad4000_trigger_handler, NULL); 859 if (ret) 860 return ret; 861 862 return devm_iio_device_register(dev, indio_dev); 863 } 864 865 static const struct spi_device_id ad4000_id[] = { 866 { "ad4000", (kernel_ulong_t)&ad4000_chip_info }, 867 { "ad4001", (kernel_ulong_t)&ad4001_chip_info }, 868 { "ad4002", (kernel_ulong_t)&ad4002_chip_info }, 869 { "ad4003", (kernel_ulong_t)&ad4003_chip_info }, 870 { "ad4004", (kernel_ulong_t)&ad4004_chip_info }, 871 { "ad4005", (kernel_ulong_t)&ad4005_chip_info }, 872 { "ad4006", (kernel_ulong_t)&ad4006_chip_info }, 873 { "ad4007", (kernel_ulong_t)&ad4007_chip_info }, 874 { "ad4008", (kernel_ulong_t)&ad4008_chip_info }, 875 { "ad4010", (kernel_ulong_t)&ad4010_chip_info }, 876 { "ad4011", (kernel_ulong_t)&ad4011_chip_info }, 877 { "ad4020", (kernel_ulong_t)&ad4020_chip_info }, 878 { "ad4021", (kernel_ulong_t)&ad4021_chip_info }, 879 { "ad4022", (kernel_ulong_t)&ad4022_chip_info }, 880 { "adaq4001", (kernel_ulong_t)&adaq4001_chip_info }, 881 { "adaq4003", (kernel_ulong_t)&adaq4003_chip_info }, 882 { "ad7685", (kernel_ulong_t)&ad7685_chip_info }, 883 { "ad7686", (kernel_ulong_t)&ad7686_chip_info }, 884 { "ad7687", (kernel_ulong_t)&ad7687_chip_info }, 885 { "ad7688", (kernel_ulong_t)&ad7688_chip_info }, 886 { "ad7690", (kernel_ulong_t)&ad7690_chip_info }, 887 { "ad7691", (kernel_ulong_t)&ad7691_chip_info }, 888 { "ad7693", (kernel_ulong_t)&ad7693_chip_info }, 889 { "ad7942", (kernel_ulong_t)&ad7942_chip_info }, 890 { "ad7946", (kernel_ulong_t)&ad7946_chip_info }, 891 { "ad7980", (kernel_ulong_t)&ad7980_chip_info }, 892 { "ad7982", (kernel_ulong_t)&ad7982_chip_info }, 893 { "ad7983", (kernel_ulong_t)&ad7983_chip_info }, 894 { "ad7984", (kernel_ulong_t)&ad7984_chip_info }, 895 { "ad7988-1", (kernel_ulong_t)&ad7988_1_chip_info }, 896 { "ad7988-5", (kernel_ulong_t)&ad7988_5_chip_info }, 897 { } 898 }; 899 MODULE_DEVICE_TABLE(spi, ad4000_id); 900 901 static const struct of_device_id ad4000_of_match[] = { 902 { .compatible = "adi,ad4000", .data = &ad4000_chip_info }, 903 { .compatible = "adi,ad4001", .data = &ad4001_chip_info }, 904 { .compatible = "adi,ad4002", .data = &ad4002_chip_info }, 905 { .compatible = "adi,ad4003", .data = &ad4003_chip_info }, 906 { .compatible = "adi,ad4004", .data = &ad4004_chip_info }, 907 { .compatible = "adi,ad4005", .data = &ad4005_chip_info }, 908 { .compatible = "adi,ad4006", .data = &ad4006_chip_info }, 909 { .compatible = "adi,ad4007", .data = &ad4007_chip_info }, 910 { .compatible = "adi,ad4008", .data = &ad4008_chip_info }, 911 { .compatible = "adi,ad4010", .data = &ad4010_chip_info }, 912 { .compatible = "adi,ad4011", .data = &ad4011_chip_info }, 913 { .compatible = "adi,ad4020", .data = &ad4020_chip_info }, 914 { .compatible = "adi,ad4021", .data = &ad4021_chip_info }, 915 { .compatible = "adi,ad4022", .data = &ad4022_chip_info }, 916 { .compatible = "adi,adaq4001", .data = &adaq4001_chip_info }, 917 { .compatible = "adi,adaq4003", .data = &adaq4003_chip_info }, 918 { .compatible = "adi,ad7685", .data = &ad7685_chip_info }, 919 { .compatible = "adi,ad7686", .data = &ad7686_chip_info }, 920 { .compatible = "adi,ad7687", .data = &ad7687_chip_info }, 921 { .compatible = "adi,ad7688", .data = &ad7688_chip_info }, 922 { .compatible = "adi,ad7690", .data = &ad7690_chip_info }, 923 { .compatible = "adi,ad7691", .data = &ad7691_chip_info }, 924 { .compatible = "adi,ad7693", .data = &ad7693_chip_info }, 925 { .compatible = "adi,ad7942", .data = &ad7942_chip_info }, 926 { .compatible = "adi,ad7946", .data = &ad7946_chip_info }, 927 { .compatible = "adi,ad7980", .data = &ad7980_chip_info }, 928 { .compatible = "adi,ad7982", .data = &ad7982_chip_info }, 929 { .compatible = "adi,ad7983", .data = &ad7983_chip_info }, 930 { .compatible = "adi,ad7984", .data = &ad7984_chip_info }, 931 { .compatible = "adi,ad7988-1", .data = &ad7988_1_chip_info }, 932 { .compatible = "adi,ad7988-5", .data = &ad7988_5_chip_info }, 933 { } 934 }; 935 MODULE_DEVICE_TABLE(of, ad4000_of_match); 936 937 static struct spi_driver ad4000_driver = { 938 .driver = { 939 .name = "ad4000", 940 .of_match_table = ad4000_of_match, 941 }, 942 .probe = ad4000_probe, 943 .id_table = ad4000_id, 944 }; 945 module_spi_driver(ad4000_driver); 946 947 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>"); 948 MODULE_DESCRIPTION("Analog Devices AD4000 ADC driver"); 949 MODULE_LICENSE("GPL"); 950