1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD4000 SPI ADC driver 4 * 5 * Copyright 2024 Analog Devices Inc. 6 */ 7 #include <linux/bits.h> 8 #include <linux/bitfield.h> 9 #include <linux/byteorder/generic.h> 10 #include <linux/cleanup.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/math.h> 14 #include <linux/module.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/spi/offload/consumer.h> 18 #include <linux/spi/spi.h> 19 #include <linux/units.h> 20 #include <linux/util_macros.h> 21 22 #include <linux/iio/iio.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/buffer-dmaengine.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/iio/trigger_consumer.h> 27 28 #define AD4000_READ_COMMAND 0x54 29 #define AD4000_WRITE_COMMAND 0x14 30 31 #define AD4000_CONFIG_REG_DEFAULT 0xE1 32 33 /* AD4000 Configuration Register programmable bits */ 34 #define AD4000_CFG_SPAN_COMP BIT(3) /* Input span compression */ 35 #define AD4000_CFG_HIGHZ BIT(2) /* High impedance mode */ 36 #define AD4000_CFG_TURBO BIT(1) /* Turbo mode */ 37 38 #define AD4000_SCALE_OPTIONS 2 39 40 #define __AD4000_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_access, _offl)\ 41 { \ 42 .type = IIO_VOLTAGE, \ 43 .indexed = 1, \ 44 .differential = 1, \ 45 .channel = 0, \ 46 .channel2 = 1, \ 47 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 48 BIT(IIO_CHAN_INFO_SCALE) | \ 49 (_offl ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0), \ 50 .info_mask_separate_available = _reg_access ? BIT(IIO_CHAN_INFO_SCALE) : 0,\ 51 .scan_index = 0, \ 52 .scan_type = { \ 53 .sign = _sign, \ 54 .realbits = _real_bits, \ 55 .storagebits = _storage_bits, \ 56 .shift = (_offl ? 0 : _storage_bits - _real_bits), \ 57 .endianness = _offl ? IIO_CPU : IIO_BE \ 58 }, \ 59 } 60 61 #define AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access, _offl) \ 62 __AD4000_DIFF_CHANNEL((_sign), (_real_bits), \ 63 (((_offl) || ((_real_bits) > 16)) ? 32 : 16), \ 64 (_reg_access), (_offl)) 65 66 /* 67 * When SPI offload is configured, transfers are executed without CPU 68 * intervention so no soft timestamp can be recorded when transfers run. 69 * Because of that, the macros that set timestamp channel are only used when 70 * transfers are not offloaded. 71 */ 72 #define AD4000_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ 73 { \ 74 AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access, 0), \ 75 IIO_CHAN_SOFT_TIMESTAMP(1), \ 76 } 77 78 #define __AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, \ 79 _reg_access, _offl) \ 80 { \ 81 .type = IIO_VOLTAGE, \ 82 .indexed = 1, \ 83 .channel = 0, \ 84 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 85 BIT(IIO_CHAN_INFO_SCALE) | \ 86 BIT(IIO_CHAN_INFO_OFFSET) | \ 87 (_offl ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0), \ 88 .info_mask_separate_available = _reg_access ? BIT(IIO_CHAN_INFO_SCALE) : 0,\ 89 .scan_index = 0, \ 90 .scan_type = { \ 91 .sign = _sign, \ 92 .realbits = _real_bits, \ 93 .storagebits = _storage_bits, \ 94 .shift = (_offl ? 0 : _storage_bits - _real_bits), \ 95 .endianness = _offl ? IIO_CPU : IIO_BE \ 96 }, \ 97 } 98 99 #define AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access, _offl) \ 100 __AD4000_PSEUDO_DIFF_CHANNEL((_sign), (_real_bits), \ 101 (((_offl) || ((_real_bits) > 16)) ? 32 : 16),\ 102 (_reg_access), (_offl)) 103 104 #define AD4000_PSEUDO_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ 105 { \ 106 AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access, 0), \ 107 IIO_CHAN_SOFT_TIMESTAMP(1), \ 108 } 109 110 static const char * const ad4000_power_supplies[] = { 111 "vdd", "vio" 112 }; 113 114 enum ad4000_sdi { 115 AD4000_SDI_MOSI, 116 AD4000_SDI_VIO, 117 AD4000_SDI_CS, 118 AD4000_SDI_GND, 119 }; 120 121 /* maps adi,sdi-pin property value to enum */ 122 static const char * const ad4000_sdi_pin[] = { 123 [AD4000_SDI_MOSI] = "sdi", 124 [AD4000_SDI_VIO] = "high", 125 [AD4000_SDI_CS] = "cs", 126 [AD4000_SDI_GND] = "low", 127 }; 128 129 /* Gains stored as fractions of 1000 so they can be expressed by integers. */ 130 static const int ad4000_gains[] = { 131 454, 909, 1000, 1900, 132 }; 133 134 struct ad4000_time_spec { 135 int t_conv_ns; 136 int t_quiet2_ns; 137 }; 138 139 /* 140 * Same timing specifications for all of AD4000, AD4001, ..., AD4008, AD4010, 141 * ADAQ4001, and ADAQ4003. 142 */ 143 static const struct ad4000_time_spec ad4000_t_spec = { 144 .t_conv_ns = 320, 145 .t_quiet2_ns = 60, 146 }; 147 148 /* AD4020, AD4021, AD4022 */ 149 static const struct ad4000_time_spec ad4020_t_spec = { 150 .t_conv_ns = 350, 151 .t_quiet2_ns = 60, 152 }; 153 154 /* AD7983, AD7984 */ 155 static const struct ad4000_time_spec ad7983_t_spec = { 156 .t_conv_ns = 500, 157 .t_quiet2_ns = 0, 158 }; 159 160 /* AD7980, AD7982 */ 161 static const struct ad4000_time_spec ad7980_t_spec = { 162 .t_conv_ns = 800, 163 .t_quiet2_ns = 0, 164 }; 165 166 /* AD7946, AD7686, AD7688, AD7988-5, AD7693 */ 167 static const struct ad4000_time_spec ad7686_t_spec = { 168 .t_conv_ns = 1600, 169 .t_quiet2_ns = 0, 170 }; 171 172 /* AD7690 */ 173 static const struct ad4000_time_spec ad7690_t_spec = { 174 .t_conv_ns = 2100, 175 .t_quiet2_ns = 0, 176 }; 177 178 /* AD7942, AD7685, AD7687 */ 179 static const struct ad4000_time_spec ad7687_t_spec = { 180 .t_conv_ns = 3200, 181 .t_quiet2_ns = 0, 182 }; 183 184 /* AD7691 */ 185 static const struct ad4000_time_spec ad7691_t_spec = { 186 .t_conv_ns = 3700, 187 .t_quiet2_ns = 0, 188 }; 189 190 /* AD7988-1 */ 191 static const struct ad4000_time_spec ad7988_1_t_spec = { 192 .t_conv_ns = 9500, 193 .t_quiet2_ns = 0, 194 }; 195 196 struct ad4000_chip_info { 197 const char *dev_name; 198 struct iio_chan_spec chan_spec[2]; 199 struct iio_chan_spec reg_access_chan_spec[2]; 200 struct iio_chan_spec offload_chan_spec; 201 struct iio_chan_spec reg_access_offload_chan_spec; 202 const struct ad4000_time_spec *time_spec; 203 bool has_hardware_gain; 204 int max_rate_hz; 205 }; 206 207 static const struct ad4000_chip_info ad4000_chip_info = { 208 .dev_name = "ad4000", 209 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 210 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), 211 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 212 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, 1), 213 .time_spec = &ad4000_t_spec, 214 .max_rate_hz = 2 * MEGA, 215 }; 216 217 static const struct ad4000_chip_info ad4001_chip_info = { 218 .dev_name = "ad4001", 219 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 220 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1), 221 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1), 222 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 1, 1), 223 .time_spec = &ad4000_t_spec, 224 .max_rate_hz = 2 * MEGA, 225 }; 226 227 static const struct ad4000_chip_info ad4002_chip_info = { 228 .dev_name = "ad4002", 229 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), 230 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), 231 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1), 232 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, 1), 233 .time_spec = &ad4000_t_spec, 234 .max_rate_hz = 2 * MEGA, 235 }; 236 237 static const struct ad4000_chip_info ad4003_chip_info = { 238 .dev_name = "ad4003", 239 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 240 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 241 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 242 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1), 243 .time_spec = &ad4000_t_spec, 244 .max_rate_hz = 2 * MEGA, 245 }; 246 247 static const struct ad4000_chip_info ad4004_chip_info = { 248 .dev_name = "ad4004", 249 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 250 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), 251 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 252 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, 1), 253 .time_spec = &ad4000_t_spec, 254 .max_rate_hz = 1 * MEGA, 255 }; 256 257 static const struct ad4000_chip_info ad4005_chip_info = { 258 .dev_name = "ad4005", 259 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 260 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1), 261 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1), 262 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 1, 1), 263 .time_spec = &ad4000_t_spec, 264 .max_rate_hz = 1 * MEGA, 265 }; 266 267 static const struct ad4000_chip_info ad4006_chip_info = { 268 .dev_name = "ad4006", 269 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), 270 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), 271 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1), 272 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, 1), 273 .time_spec = &ad4000_t_spec, 274 .max_rate_hz = 1 * MEGA, 275 }; 276 277 static const struct ad4000_chip_info ad4007_chip_info = { 278 .dev_name = "ad4007", 279 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 280 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 281 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 282 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1), 283 .time_spec = &ad4000_t_spec, 284 .max_rate_hz = 1 * MEGA, 285 }; 286 287 static const struct ad4000_chip_info ad4008_chip_info = { 288 .dev_name = "ad4008", 289 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 290 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), 291 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 292 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, 1), 293 .time_spec = &ad4000_t_spec, 294 .max_rate_hz = 500 * KILO, 295 }; 296 297 static const struct ad4000_chip_info ad4010_chip_info = { 298 .dev_name = "ad4010", 299 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), 300 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), 301 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1), 302 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, 1), 303 .time_spec = &ad4000_t_spec, 304 .max_rate_hz = 500 * KILO, 305 }; 306 307 static const struct ad4000_chip_info ad4011_chip_info = { 308 .dev_name = "ad4011", 309 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 310 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 311 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 312 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1), 313 .time_spec = &ad4000_t_spec, 314 .max_rate_hz = 500 * KILO, 315 }; 316 317 static const struct ad4000_chip_info ad4020_chip_info = { 318 .dev_name = "ad4020", 319 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0), 320 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1), 321 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 0, 1), 322 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 1, 1), 323 .time_spec = &ad4020_t_spec, 324 .max_rate_hz = 1800 * KILO, 325 }; 326 327 static const struct ad4000_chip_info ad4021_chip_info = { 328 .dev_name = "ad4021", 329 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0), 330 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1), 331 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 0, 1), 332 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 1, 1), 333 .time_spec = &ad4020_t_spec, 334 .max_rate_hz = 1 * MEGA, 335 }; 336 337 static const struct ad4000_chip_info ad4022_chip_info = { 338 .dev_name = "ad4022", 339 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0), 340 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1), 341 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 0, 1), 342 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 1, 1), 343 .time_spec = &ad4020_t_spec, 344 .max_rate_hz = 500 * KILO, 345 }; 346 347 static const struct ad4000_chip_info adaq4001_chip_info = { 348 .dev_name = "adaq4001", 349 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 350 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1), 351 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1), 352 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 1, 1), 353 .time_spec = &ad4000_t_spec, 354 .has_hardware_gain = true, 355 .max_rate_hz = 2 * MEGA, 356 }; 357 358 static const struct ad4000_chip_info adaq4003_chip_info = { 359 .dev_name = "adaq4003", 360 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 361 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1), 362 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 363 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1), 364 .time_spec = &ad4000_t_spec, 365 .has_hardware_gain = true, 366 .max_rate_hz = 2 * MEGA, 367 }; 368 369 static const struct ad4000_chip_info ad7685_chip_info = { 370 .dev_name = "ad7685", 371 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 372 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 373 .time_spec = &ad7687_t_spec, 374 .max_rate_hz = 250 * KILO, 375 }; 376 377 static const struct ad4000_chip_info ad7686_chip_info = { 378 .dev_name = "ad7686", 379 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 380 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 381 .time_spec = &ad7686_t_spec, 382 .max_rate_hz = 500 * KILO, 383 }; 384 385 static const struct ad4000_chip_info ad7687_chip_info = { 386 .dev_name = "ad7687", 387 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 388 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1), 389 .time_spec = &ad7687_t_spec, 390 .max_rate_hz = 250 * KILO, 391 }; 392 393 static const struct ad4000_chip_info ad7688_chip_info = { 394 .dev_name = "ad7688", 395 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 396 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1), 397 .time_spec = &ad7686_t_spec, 398 .max_rate_hz = 500 * KILO, 399 }; 400 401 static const struct ad4000_chip_info ad7690_chip_info = { 402 .dev_name = "ad7690", 403 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 404 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 405 .time_spec = &ad7690_t_spec, 406 .max_rate_hz = 400 * KILO, 407 }; 408 409 static const struct ad4000_chip_info ad7691_chip_info = { 410 .dev_name = "ad7691", 411 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 412 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 413 .time_spec = &ad7691_t_spec, 414 .max_rate_hz = 250 * KILO, 415 }; 416 417 static const struct ad4000_chip_info ad7693_chip_info = { 418 .dev_name = "ad7693", 419 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0), 420 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1), 421 .time_spec = &ad7686_t_spec, 422 .max_rate_hz = 500 * KILO, 423 }; 424 425 static const struct ad4000_chip_info ad7942_chip_info = { 426 .dev_name = "ad7942", 427 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), 428 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 14, 0, 1), 429 .time_spec = &ad7687_t_spec, 430 .max_rate_hz = 250 * KILO, 431 }; 432 433 static const struct ad4000_chip_info ad7946_chip_info = { 434 .dev_name = "ad7946", 435 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), 436 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 14, 0, 1), 437 .time_spec = &ad7686_t_spec, 438 .max_rate_hz = 500 * KILO, 439 }; 440 441 static const struct ad4000_chip_info ad7980_chip_info = { 442 .dev_name = "ad7980", 443 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 444 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 445 .time_spec = &ad7980_t_spec, 446 .max_rate_hz = 1 * MEGA, 447 }; 448 449 static const struct ad4000_chip_info ad7982_chip_info = { 450 .dev_name = "ad7982", 451 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 452 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 453 .time_spec = &ad7980_t_spec, 454 .max_rate_hz = 1 * MEGA, 455 }; 456 457 static const struct ad4000_chip_info ad7983_chip_info = { 458 .dev_name = "ad7983", 459 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 460 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 461 .time_spec = &ad7983_t_spec, 462 .max_rate_hz = 1 * MEGA + 333 * KILO + 333, 463 }; 464 465 static const struct ad4000_chip_info ad7984_chip_info = { 466 .dev_name = "ad7984", 467 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0), 468 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1), 469 .time_spec = &ad7983_t_spec, 470 .max_rate_hz = 1 * MEGA + 333 * KILO + 333, 471 }; 472 473 static const struct ad4000_chip_info ad7988_1_chip_info = { 474 .dev_name = "ad7988-1", 475 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 476 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 477 .time_spec = &ad7988_1_t_spec, 478 .max_rate_hz = 100 * KILO, 479 }; 480 481 static const struct ad4000_chip_info ad7988_5_chip_info = { 482 .dev_name = "ad7988-5", 483 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), 484 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), 485 .time_spec = &ad7686_t_spec, 486 .max_rate_hz = 500 * KILO, 487 }; 488 489 static const struct spi_offload_config ad4000_offload_config = { 490 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 491 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 492 }; 493 494 struct ad4000_state { 495 struct spi_device *spi; 496 struct gpio_desc *cnv_gpio; 497 struct spi_transfer xfers[2]; 498 struct spi_message msg; 499 struct spi_transfer offload_xfer; 500 struct spi_message offload_msg; 501 struct spi_offload *offload; 502 struct spi_offload_trigger *offload_trigger; 503 bool using_offload; 504 unsigned long offload_trigger_hz; 505 int max_rate_hz; 506 struct mutex lock; /* Protect read modify write cycle */ 507 int vref_mv; 508 enum ad4000_sdi sdi_pin; 509 bool span_comp; 510 u16 gain_milli; 511 int scale_tbl[AD4000_SCALE_OPTIONS][2]; 512 const struct ad4000_time_spec *time_spec; 513 514 /* 515 * DMA (thus cache coherency maintenance) requires the transfer buffers 516 * to live in their own cache lines. 517 */ 518 struct { 519 union { 520 __be16 sample_buf16_be; 521 __be32 sample_buf32_be; 522 u16 sample_buf16; 523 u32 sample_buf32; 524 } data; 525 aligned_s64 timestamp; 526 } scan __aligned(IIO_DMA_MINALIGN); 527 u8 tx_buf[2]; 528 u8 rx_buf[2]; 529 }; 530 531 static void ad4000_fill_scale_tbl(struct ad4000_state *st, 532 struct iio_chan_spec const *chan) 533 { 534 int val, tmp0, tmp1; 535 int scale_bits; 536 u64 tmp2; 537 538 /* 539 * ADCs that output two's complement code have one less bit to express 540 * voltage magnitude. 541 */ 542 if (chan->scan_type.sign == 's') 543 scale_bits = chan->scan_type.realbits - 1; 544 else 545 scale_bits = chan->scan_type.realbits; 546 547 /* 548 * The gain is stored as a fraction of 1000 and, as we need to 549 * divide vref_mv by the gain, we invert the gain/1000 fraction. 550 * Also multiply by an extra MILLI to preserve precision. 551 * Thus, we have MILLI * MILLI equals MICRO as fraction numerator. 552 */ 553 val = mult_frac(st->vref_mv, MICRO, st->gain_milli); 554 555 /* Would multiply by NANO here but we multiplied by extra MILLI */ 556 tmp2 = (u64)val * MICRO >> scale_bits; 557 tmp0 = div_s64_rem(tmp2, NANO, &tmp1); 558 559 /* Store scale for when span compression is disabled */ 560 st->scale_tbl[0][0] = tmp0; /* Integer part */ 561 st->scale_tbl[0][1] = abs(tmp1); /* Fractional part */ 562 563 /* Store scale for when span compression is enabled */ 564 st->scale_tbl[1][0] = tmp0; 565 566 /* The integer part is always zero so don't bother to divide it. */ 567 if (chan->differential) 568 st->scale_tbl[1][1] = DIV_ROUND_CLOSEST(abs(tmp1) * 4, 5); 569 else 570 st->scale_tbl[1][1] = DIV_ROUND_CLOSEST(abs(tmp1) * 9, 10); 571 } 572 573 static int ad4000_write_reg(struct ad4000_state *st, uint8_t val) 574 { 575 st->tx_buf[0] = AD4000_WRITE_COMMAND; 576 st->tx_buf[1] = val; 577 return spi_write(st->spi, st->tx_buf, ARRAY_SIZE(st->tx_buf)); 578 } 579 580 static int ad4000_read_reg(struct ad4000_state *st, unsigned int *val) 581 { 582 struct spi_transfer t = { 583 .tx_buf = st->tx_buf, 584 .rx_buf = st->rx_buf, 585 .len = 2, 586 }; 587 int ret; 588 589 st->tx_buf[0] = AD4000_READ_COMMAND; 590 ret = spi_sync_transfer(st->spi, &t, 1); 591 if (ret < 0) 592 return ret; 593 594 *val = st->rx_buf[1]; 595 return ret; 596 } 597 598 static int ad4000_set_sampling_freq(struct ad4000_state *st, int freq) 599 { 600 struct spi_offload_trigger_config config = { 601 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 602 .periodic = { 603 .frequency_hz = freq, 604 }, 605 }; 606 int ret; 607 608 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 609 if (ret) 610 return ret; 611 612 st->offload_trigger_hz = config.periodic.frequency_hz; 613 614 return 0; 615 } 616 617 static int ad4000_convert_and_acquire(struct ad4000_state *st) 618 { 619 int ret; 620 621 /* 622 * In 4-wire mode, the CNV line is held high for the entire conversion 623 * and acquisition process. In other modes, the CNV GPIO is optional 624 * and, if provided, replaces controller CS. If CNV GPIO is not defined 625 * gpiod_set_value_cansleep() has no effect. 626 */ 627 gpiod_set_value_cansleep(st->cnv_gpio, 1); 628 ret = spi_sync(st->spi, &st->msg); 629 gpiod_set_value_cansleep(st->cnv_gpio, 0); 630 631 return ret; 632 } 633 634 static int ad4000_single_conversion(struct iio_dev *indio_dev, 635 const struct iio_chan_spec *chan, int *val) 636 { 637 struct ad4000_state *st = iio_priv(indio_dev); 638 u32 sample; 639 int ret; 640 641 ret = ad4000_convert_and_acquire(st); 642 if (ret < 0) 643 return ret; 644 645 if (chan->scan_type.endianness == IIO_BE) { 646 if (chan->scan_type.realbits > 16) 647 sample = be32_to_cpu(st->scan.data.sample_buf32_be); 648 else 649 sample = be16_to_cpu(st->scan.data.sample_buf16_be); 650 } else { 651 if (chan->scan_type.realbits > 16) 652 sample = st->scan.data.sample_buf32; 653 else 654 sample = st->scan.data.sample_buf16; 655 } 656 657 sample >>= chan->scan_type.shift; 658 659 if (chan->scan_type.sign == 's') 660 *val = sign_extend32(sample, chan->scan_type.realbits - 1); 661 else 662 *val = sample; 663 664 return IIO_VAL_INT; 665 } 666 667 static int ad4000_read_raw(struct iio_dev *indio_dev, 668 struct iio_chan_spec const *chan, int *val, 669 int *val2, long info) 670 { 671 struct ad4000_state *st = iio_priv(indio_dev); 672 int ret; 673 674 switch (info) { 675 case IIO_CHAN_INFO_RAW: 676 if (!iio_device_claim_direct(indio_dev)) 677 return -EBUSY; 678 679 ret = ad4000_single_conversion(indio_dev, chan, val); 680 iio_device_release_direct(indio_dev); 681 return ret; 682 case IIO_CHAN_INFO_SCALE: 683 *val = st->scale_tbl[st->span_comp][0]; 684 *val2 = st->scale_tbl[st->span_comp][1]; 685 return IIO_VAL_INT_PLUS_NANO; 686 case IIO_CHAN_INFO_OFFSET: 687 *val = 0; 688 if (st->span_comp) 689 *val = mult_frac(st->vref_mv, 1, 10); 690 691 return IIO_VAL_INT; 692 case IIO_CHAN_INFO_SAMP_FREQ: 693 *val = st->offload_trigger_hz; 694 return IIO_VAL_INT; 695 default: 696 return -EINVAL; 697 } 698 } 699 700 static int ad4000_read_avail(struct iio_dev *indio_dev, 701 struct iio_chan_spec const *chan, 702 const int **vals, int *type, int *length, 703 long info) 704 { 705 struct ad4000_state *st = iio_priv(indio_dev); 706 707 switch (info) { 708 case IIO_CHAN_INFO_SCALE: 709 *vals = (int *)st->scale_tbl; 710 *length = AD4000_SCALE_OPTIONS * 2; 711 *type = IIO_VAL_INT_PLUS_NANO; 712 return IIO_AVAIL_LIST; 713 default: 714 return -EINVAL; 715 } 716 } 717 718 static int ad4000_write_raw_get_fmt(struct iio_dev *indio_dev, 719 struct iio_chan_spec const *chan, long mask) 720 { 721 switch (mask) { 722 case IIO_CHAN_INFO_SCALE: 723 return IIO_VAL_INT_PLUS_NANO; 724 default: 725 return IIO_VAL_INT_PLUS_MICRO; 726 } 727 } 728 729 static int __ad4000_write_raw(struct iio_dev *indio_dev, 730 struct iio_chan_spec const *chan, 731 int val2) 732 { 733 struct ad4000_state *st = iio_priv(indio_dev); 734 unsigned int reg_val; 735 bool span_comp_en; 736 int ret; 737 738 guard(mutex)(&st->lock); 739 740 ret = ad4000_read_reg(st, ®_val); 741 if (ret < 0) 742 return ret; 743 744 span_comp_en = val2 == st->scale_tbl[1][1]; 745 reg_val &= ~AD4000_CFG_SPAN_COMP; 746 reg_val |= FIELD_PREP(AD4000_CFG_SPAN_COMP, span_comp_en); 747 748 ret = ad4000_write_reg(st, reg_val); 749 if (ret < 0) 750 return ret; 751 752 st->span_comp = span_comp_en; 753 return 0; 754 } 755 756 static int ad4000_write_raw(struct iio_dev *indio_dev, 757 struct iio_chan_spec const *chan, 758 int val, int val2, long mask) 759 { 760 struct ad4000_state *st = iio_priv(indio_dev); 761 int ret; 762 763 switch (mask) { 764 case IIO_CHAN_INFO_SCALE: 765 if (!iio_device_claim_direct(indio_dev)) 766 return -EBUSY; 767 ret = __ad4000_write_raw(indio_dev, chan, val2); 768 iio_device_release_direct(indio_dev); 769 return ret; 770 case IIO_CHAN_INFO_SAMP_FREQ: 771 if (val < 1 || val > st->max_rate_hz) 772 return -EINVAL; 773 774 if (!iio_device_claim_direct(indio_dev)) 775 return -EBUSY; 776 ret = ad4000_set_sampling_freq(st, val); 777 iio_device_release_direct(indio_dev); 778 return ret; 779 default: 780 return -EINVAL; 781 } 782 } 783 784 static irqreturn_t ad4000_trigger_handler(int irq, void *p) 785 { 786 struct iio_poll_func *pf = p; 787 struct iio_dev *indio_dev = pf->indio_dev; 788 struct ad4000_state *st = iio_priv(indio_dev); 789 int ret; 790 791 ret = ad4000_convert_and_acquire(st); 792 if (ret < 0) 793 goto err_out; 794 795 iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan), 796 pf->timestamp); 797 798 err_out: 799 iio_trigger_notify_done(indio_dev->trig); 800 return IRQ_HANDLED; 801 } 802 803 static const struct iio_info ad4000_reg_access_info = { 804 .read_raw = &ad4000_read_raw, 805 .read_avail = &ad4000_read_avail, 806 .write_raw = &ad4000_write_raw, 807 .write_raw_get_fmt = &ad4000_write_raw_get_fmt, 808 }; 809 810 static const struct iio_info ad4000_offload_info = { 811 .read_raw = &ad4000_read_raw, 812 .write_raw = &ad4000_write_raw, 813 .write_raw_get_fmt = &ad4000_write_raw_get_fmt, 814 }; 815 816 static const struct iio_info ad4000_info = { 817 .read_raw = &ad4000_read_raw, 818 }; 819 820 static int ad4000_offload_buffer_postenable(struct iio_dev *indio_dev) 821 { 822 struct ad4000_state *st = iio_priv(indio_dev); 823 struct spi_offload_trigger_config config = { 824 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 825 .periodic = { 826 .frequency_hz = st->offload_trigger_hz, 827 }, 828 }; 829 830 return spi_offload_trigger_enable(st->offload, st->offload_trigger, 831 &config); 832 } 833 834 static int ad4000_offload_buffer_predisable(struct iio_dev *indio_dev) 835 { 836 struct ad4000_state *st = iio_priv(indio_dev); 837 838 spi_offload_trigger_disable(st->offload, st->offload_trigger); 839 840 return 0; 841 } 842 843 static const struct iio_buffer_setup_ops ad4000_offload_buffer_setup_ops = { 844 .postenable = &ad4000_offload_buffer_postenable, 845 .predisable = &ad4000_offload_buffer_predisable, 846 }; 847 848 static int ad4000_spi_offload_setup(struct iio_dev *indio_dev, 849 struct ad4000_state *st) 850 { 851 struct spi_device *spi = st->spi; 852 struct device *dev = &spi->dev; 853 struct dma_chan *rx_dma; 854 int ret; 855 856 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 857 SPI_OFFLOAD_TRIGGER_PERIODIC); 858 if (IS_ERR(st->offload_trigger)) 859 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 860 "Failed to get offload trigger\n"); 861 862 ret = ad4000_set_sampling_freq(st, st->max_rate_hz); 863 if (ret) 864 return dev_err_probe(dev, ret, 865 "Failed to set sampling frequency\n"); 866 867 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 868 if (IS_ERR(rx_dma)) 869 return dev_err_probe(dev, PTR_ERR(rx_dma), 870 "Failed to get offload RX DMA\n"); 871 872 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 873 IIO_BUFFER_DIRECTION_IN); 874 if (ret) 875 return dev_err_probe(dev, ret, "Failed to setup DMA buffer\n"); 876 877 return 0; 878 } 879 880 /* 881 * This executes a data sample transfer when using SPI offloading. The device 882 * connections should be in "3-wire" mode, selected either when the adi,sdi-pin 883 * device tree property is absent or set to "high". Also, the ADC CNV pin must 884 * be connected to a SPI controller CS (it can't be connected to a GPIO). 885 * 886 * In order to achieve the maximum sample rate, we only do one transfer per 887 * SPI offload trigger. Because the ADC output has a one sample latency (delay) 888 * when the device is wired in "3-wire" mode and only one transfer per sample is 889 * being made in turbo mode, the first data sample is not valid because it 890 * contains the output of an earlier conversion result. We also set transfer 891 * `bits_per_word` to achieve higher throughput by using the minimum number of 892 * SCLK cycles. Also, a delay is added to make sure we meet the minimum quiet 893 * time before releasing the CS line. 894 * 895 * Note that, with `bits_per_word` set to the number of ADC precision bits, 896 * transfers use larger word sizes that get stored in 'in-memory wordsizes' that 897 * are always in native CPU byte order. Because of that, IIO buffer elements 898 * ought to be read in CPU endianness which requires setting IIO scan_type 899 * endianness accordingly (i.e. IIO_CPU). 900 */ 901 static int ad4000_prepare_offload_message(struct ad4000_state *st, 902 const struct iio_chan_spec *chan) 903 { 904 struct spi_transfer *xfer = &st->offload_xfer; 905 906 xfer->bits_per_word = chan->scan_type.realbits; 907 xfer->len = chan->scan_type.realbits > 16 ? 4 : 2; 908 xfer->delay.value = st->time_spec->t_quiet2_ns; 909 xfer->delay.unit = SPI_DELAY_UNIT_NSECS; 910 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 911 912 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); 913 st->offload_msg.offload = st->offload; 914 915 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->offload_msg); 916 } 917 918 /* 919 * This executes a data sample transfer for when the device connections are 920 * in "3-wire" mode, selected when the adi,sdi-pin device tree property is 921 * absent or set to "high". In this connection mode, the ADC SDI pin is 922 * connected to MOSI or to VIO and ADC CNV pin is connected either to a SPI 923 * controller CS or to a GPIO. 924 * AD4000 series of devices initiate conversions on the rising edge of CNV pin. 925 * 926 * If the CNV pin is connected to an SPI controller CS line (which is by default 927 * active low), the ADC readings would have a latency (delay) of one read. 928 * Moreover, since we also do ADC sampling for filling the buffer on triggered 929 * buffer mode, the timestamps of buffer readings would be disarranged. 930 * To prevent the read latency and reduce the time discrepancy between the 931 * sample read request and the time of actual sampling by the ADC, do a 932 * preparatory transfer to pulse the CS/CNV line. 933 */ 934 static int ad4000_prepare_3wire_mode_message(struct ad4000_state *st, 935 const struct iio_chan_spec *chan) 936 { 937 struct spi_transfer *xfers = st->xfers; 938 939 xfers[0].cs_change = 1; 940 xfers[0].cs_change_delay.value = st->time_spec->t_conv_ns; 941 xfers[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 942 943 xfers[1].rx_buf = &st->scan.data; 944 xfers[1].len = chan->scan_type.realbits > 16 ? 4 : 2; 945 946 /* 947 * If the device is set up for SPI offloading, IIO channel scan_type is 948 * set to IIO_CPU. When that is the case, use larger SPI word sizes for 949 * single-shot reads too. Thus, sample data can be correctly handled in 950 * ad4000_single_conversion() according to scan_type endianness. 951 */ 952 if (chan->scan_type.endianness != IIO_BE) 953 xfers[1].bits_per_word = chan->scan_type.realbits; 954 xfers[1].delay.value = st->time_spec->t_quiet2_ns; 955 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS; 956 957 spi_message_init_with_transfers(&st->msg, st->xfers, 2); 958 959 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg); 960 } 961 962 /* 963 * This executes a data sample transfer for when the device connections are 964 * in "4-wire" mode, selected when the adi,sdi-pin device tree property is 965 * set to "cs". In this connection mode, the controller CS pin is connected to 966 * ADC SDI pin and a GPIO is connected to ADC CNV pin. 967 * The GPIO connected to ADC CNV pin is set outside of the SPI transfer. 968 */ 969 static int ad4000_prepare_4wire_mode_message(struct ad4000_state *st, 970 const struct iio_chan_spec *chan) 971 { 972 struct spi_transfer *xfers = st->xfers; 973 974 /* 975 * Dummy transfer to cause enough delay between CNV going high and SDI 976 * going low. 977 */ 978 xfers[0].cs_off = 1; 979 xfers[0].delay.value = st->time_spec->t_conv_ns; 980 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS; 981 982 xfers[1].rx_buf = &st->scan.data; 983 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits); 984 985 spi_message_init_with_transfers(&st->msg, st->xfers, 2); 986 987 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg); 988 } 989 990 static int ad4000_config(struct ad4000_state *st) 991 { 992 unsigned int reg_val = AD4000_CONFIG_REG_DEFAULT; 993 994 if (device_property_present(&st->spi->dev, "adi,high-z-input")) 995 reg_val |= FIELD_PREP(AD4000_CFG_HIGHZ, 1); 996 997 if (st->using_offload) 998 reg_val |= FIELD_PREP(AD4000_CFG_TURBO, 1); 999 1000 return ad4000_write_reg(st, reg_val); 1001 } 1002 1003 static int ad4000_probe(struct spi_device *spi) 1004 { 1005 const struct ad4000_chip_info *chip; 1006 struct device *dev = &spi->dev; 1007 struct iio_dev *indio_dev; 1008 struct ad4000_state *st; 1009 int gain_idx, ret; 1010 1011 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1012 if (!indio_dev) 1013 return -ENOMEM; 1014 1015 chip = spi_get_device_match_data(spi); 1016 if (!chip) 1017 return -EINVAL; 1018 1019 st = iio_priv(indio_dev); 1020 st->spi = spi; 1021 st->time_spec = chip->time_spec; 1022 st->max_rate_hz = chip->max_rate_hz; 1023 1024 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4000_power_supplies), 1025 ad4000_power_supplies); 1026 if (ret) 1027 return dev_err_probe(dev, ret, "Failed to enable power supplies\n"); 1028 1029 ret = devm_regulator_get_enable_read_voltage(dev, "ref"); 1030 if (ret < 0) 1031 return dev_err_probe(dev, ret, 1032 "Failed to get ref regulator reference\n"); 1033 st->vref_mv = ret / 1000; 1034 1035 st->cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_HIGH); 1036 if (IS_ERR(st->cnv_gpio)) 1037 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), 1038 "Failed to get CNV GPIO"); 1039 1040 st->offload = devm_spi_offload_get(dev, spi, &ad4000_offload_config); 1041 ret = PTR_ERR_OR_ZERO(st->offload); 1042 if (ret && ret != -ENODEV) 1043 return dev_err_probe(dev, ret, "Failed to get offload\n"); 1044 1045 st->using_offload = !IS_ERR(st->offload); 1046 if (st->using_offload) { 1047 indio_dev->setup_ops = &ad4000_offload_buffer_setup_ops; 1048 ret = ad4000_spi_offload_setup(indio_dev, st); 1049 if (ret) 1050 return ret; 1051 } else { 1052 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1053 &iio_pollfunc_store_time, 1054 &ad4000_trigger_handler, 1055 NULL); 1056 if (ret) 1057 return ret; 1058 } 1059 1060 ret = device_property_match_property_string(dev, "adi,sdi-pin", 1061 ad4000_sdi_pin, 1062 ARRAY_SIZE(ad4000_sdi_pin)); 1063 if (ret < 0 && ret != -EINVAL) 1064 return dev_err_probe(dev, ret, 1065 "getting adi,sdi-pin property failed\n"); 1066 1067 /* Default to usual SPI connections if pin properties are not present */ 1068 st->sdi_pin = ret == -EINVAL ? AD4000_SDI_MOSI : ret; 1069 switch (st->sdi_pin) { 1070 case AD4000_SDI_MOSI: 1071 indio_dev->info = &ad4000_reg_access_info; 1072 1073 /* 1074 * In "3-wire mode", the ADC SDI line must be kept high when 1075 * data is not being clocked out of the controller. 1076 * Request the SPI controller to make MOSI idle high. 1077 */ 1078 spi->mode |= SPI_MOSI_IDLE_HIGH; 1079 ret = spi_setup(spi); 1080 if (ret < 0) 1081 return ret; 1082 1083 if (st->using_offload) { 1084 indio_dev->channels = &chip->reg_access_offload_chan_spec; 1085 indio_dev->num_channels = 1; 1086 ret = ad4000_prepare_offload_message(st, indio_dev->channels); 1087 if (ret) 1088 return dev_err_probe(dev, ret, 1089 "Failed to optimize SPI msg\n"); 1090 } else { 1091 indio_dev->channels = chip->reg_access_chan_spec; 1092 indio_dev->num_channels = ARRAY_SIZE(chip->reg_access_chan_spec); 1093 } 1094 1095 /* 1096 * Call ad4000_prepare_3wire_mode_message() so single-shot read 1097 * SPI messages are always initialized. 1098 */ 1099 ret = ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); 1100 if (ret) 1101 return dev_err_probe(dev, ret, 1102 "Failed to optimize SPI msg\n"); 1103 1104 ret = ad4000_config(st); 1105 if (ret < 0) 1106 return dev_err_probe(dev, ret, "Failed to config device\n"); 1107 1108 break; 1109 case AD4000_SDI_VIO: 1110 if (st->using_offload) { 1111 indio_dev->info = &ad4000_offload_info; 1112 indio_dev->channels = &chip->offload_chan_spec; 1113 indio_dev->num_channels = 1; 1114 1115 ret = ad4000_prepare_offload_message(st, indio_dev->channels); 1116 if (ret) 1117 return dev_err_probe(dev, ret, 1118 "Failed to optimize SPI msg\n"); 1119 } else { 1120 indio_dev->info = &ad4000_info; 1121 indio_dev->channels = chip->chan_spec; 1122 indio_dev->num_channels = ARRAY_SIZE(chip->chan_spec); 1123 } 1124 1125 ret = ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); 1126 if (ret) 1127 return dev_err_probe(dev, ret, 1128 "Failed to optimize SPI msg\n"); 1129 1130 break; 1131 case AD4000_SDI_CS: 1132 if (st->using_offload) 1133 return dev_err_probe(dev, -EPROTONOSUPPORT, 1134 "Unsupported sdi-pin + offload config\n"); 1135 indio_dev->info = &ad4000_info; 1136 indio_dev->channels = chip->chan_spec; 1137 indio_dev->num_channels = ARRAY_SIZE(chip->chan_spec); 1138 ret = ad4000_prepare_4wire_mode_message(st, &indio_dev->channels[0]); 1139 if (ret) 1140 return dev_err_probe(dev, ret, 1141 "Failed to optimize SPI msg\n"); 1142 1143 break; 1144 case AD4000_SDI_GND: 1145 return dev_err_probe(dev, -EPROTONOSUPPORT, 1146 "Unsupported connection mode\n"); 1147 1148 default: 1149 return dev_err_probe(dev, -EINVAL, "Unrecognized connection mode\n"); 1150 } 1151 1152 indio_dev->name = chip->dev_name; 1153 1154 ret = devm_mutex_init(dev, &st->lock); 1155 if (ret) 1156 return ret; 1157 1158 st->gain_milli = 1000; 1159 if (chip->has_hardware_gain) { 1160 ret = device_property_read_u16(dev, "adi,gain-milli", 1161 &st->gain_milli); 1162 if (!ret) { 1163 /* Match gain value from dt to one of supported gains */ 1164 gain_idx = find_closest(st->gain_milli, ad4000_gains, 1165 ARRAY_SIZE(ad4000_gains)); 1166 st->gain_milli = ad4000_gains[gain_idx]; 1167 } else { 1168 return dev_err_probe(dev, ret, 1169 "Failed to read gain property\n"); 1170 } 1171 } 1172 1173 ad4000_fill_scale_tbl(st, &indio_dev->channels[0]); 1174 1175 return devm_iio_device_register(dev, indio_dev); 1176 } 1177 1178 static const struct spi_device_id ad4000_id[] = { 1179 { .name = "ad4000", .driver_data = (kernel_ulong_t)&ad4000_chip_info }, 1180 { .name = "ad4001", .driver_data = (kernel_ulong_t)&ad4001_chip_info }, 1181 { .name = "ad4002", .driver_data = (kernel_ulong_t)&ad4002_chip_info }, 1182 { .name = "ad4003", .driver_data = (kernel_ulong_t)&ad4003_chip_info }, 1183 { .name = "ad4004", .driver_data = (kernel_ulong_t)&ad4004_chip_info }, 1184 { .name = "ad4005", .driver_data = (kernel_ulong_t)&ad4005_chip_info }, 1185 { .name = "ad4006", .driver_data = (kernel_ulong_t)&ad4006_chip_info }, 1186 { .name = "ad4007", .driver_data = (kernel_ulong_t)&ad4007_chip_info }, 1187 { .name = "ad4008", .driver_data = (kernel_ulong_t)&ad4008_chip_info }, 1188 { .name = "ad4010", .driver_data = (kernel_ulong_t)&ad4010_chip_info }, 1189 { .name = "ad4011", .driver_data = (kernel_ulong_t)&ad4011_chip_info }, 1190 { .name = "ad4020", .driver_data = (kernel_ulong_t)&ad4020_chip_info }, 1191 { .name = "ad4021", .driver_data = (kernel_ulong_t)&ad4021_chip_info }, 1192 { .name = "ad4022", .driver_data = (kernel_ulong_t)&ad4022_chip_info }, 1193 { .name = "adaq4001", .driver_data = (kernel_ulong_t)&adaq4001_chip_info }, 1194 { .name = "adaq4003", .driver_data = (kernel_ulong_t)&adaq4003_chip_info }, 1195 { .name = "ad7685", .driver_data = (kernel_ulong_t)&ad7685_chip_info }, 1196 { .name = "ad7686", .driver_data = (kernel_ulong_t)&ad7686_chip_info }, 1197 { .name = "ad7687", .driver_data = (kernel_ulong_t)&ad7687_chip_info }, 1198 { .name = "ad7688", .driver_data = (kernel_ulong_t)&ad7688_chip_info }, 1199 { .name = "ad7690", .driver_data = (kernel_ulong_t)&ad7690_chip_info }, 1200 { .name = "ad7691", .driver_data = (kernel_ulong_t)&ad7691_chip_info }, 1201 { .name = "ad7693", .driver_data = (kernel_ulong_t)&ad7693_chip_info }, 1202 { .name = "ad7942", .driver_data = (kernel_ulong_t)&ad7942_chip_info }, 1203 { .name = "ad7946", .driver_data = (kernel_ulong_t)&ad7946_chip_info }, 1204 { .name = "ad7980", .driver_data = (kernel_ulong_t)&ad7980_chip_info }, 1205 { .name = "ad7982", .driver_data = (kernel_ulong_t)&ad7982_chip_info }, 1206 { .name = "ad7983", .driver_data = (kernel_ulong_t)&ad7983_chip_info }, 1207 { .name = "ad7984", .driver_data = (kernel_ulong_t)&ad7984_chip_info }, 1208 { .name = "ad7988-1", .driver_data = (kernel_ulong_t)&ad7988_1_chip_info }, 1209 { .name = "ad7988-5", .driver_data = (kernel_ulong_t)&ad7988_5_chip_info }, 1210 { } 1211 }; 1212 MODULE_DEVICE_TABLE(spi, ad4000_id); 1213 1214 static const struct of_device_id ad4000_of_match[] = { 1215 { .compatible = "adi,ad4000", .data = &ad4000_chip_info }, 1216 { .compatible = "adi,ad4001", .data = &ad4001_chip_info }, 1217 { .compatible = "adi,ad4002", .data = &ad4002_chip_info }, 1218 { .compatible = "adi,ad4003", .data = &ad4003_chip_info }, 1219 { .compatible = "adi,ad4004", .data = &ad4004_chip_info }, 1220 { .compatible = "adi,ad4005", .data = &ad4005_chip_info }, 1221 { .compatible = "adi,ad4006", .data = &ad4006_chip_info }, 1222 { .compatible = "adi,ad4007", .data = &ad4007_chip_info }, 1223 { .compatible = "adi,ad4008", .data = &ad4008_chip_info }, 1224 { .compatible = "adi,ad4010", .data = &ad4010_chip_info }, 1225 { .compatible = "adi,ad4011", .data = &ad4011_chip_info }, 1226 { .compatible = "adi,ad4020", .data = &ad4020_chip_info }, 1227 { .compatible = "adi,ad4021", .data = &ad4021_chip_info }, 1228 { .compatible = "adi,ad4022", .data = &ad4022_chip_info }, 1229 { .compatible = "adi,adaq4001", .data = &adaq4001_chip_info }, 1230 { .compatible = "adi,adaq4003", .data = &adaq4003_chip_info }, 1231 { .compatible = "adi,ad7685", .data = &ad7685_chip_info }, 1232 { .compatible = "adi,ad7686", .data = &ad7686_chip_info }, 1233 { .compatible = "adi,ad7687", .data = &ad7687_chip_info }, 1234 { .compatible = "adi,ad7688", .data = &ad7688_chip_info }, 1235 { .compatible = "adi,ad7690", .data = &ad7690_chip_info }, 1236 { .compatible = "adi,ad7691", .data = &ad7691_chip_info }, 1237 { .compatible = "adi,ad7693", .data = &ad7693_chip_info }, 1238 { .compatible = "adi,ad7942", .data = &ad7942_chip_info }, 1239 { .compatible = "adi,ad7946", .data = &ad7946_chip_info }, 1240 { .compatible = "adi,ad7980", .data = &ad7980_chip_info }, 1241 { .compatible = "adi,ad7982", .data = &ad7982_chip_info }, 1242 { .compatible = "adi,ad7983", .data = &ad7983_chip_info }, 1243 { .compatible = "adi,ad7984", .data = &ad7984_chip_info }, 1244 { .compatible = "adi,ad7988-1", .data = &ad7988_1_chip_info }, 1245 { .compatible = "adi,ad7988-5", .data = &ad7988_5_chip_info }, 1246 { } 1247 }; 1248 MODULE_DEVICE_TABLE(of, ad4000_of_match); 1249 1250 static struct spi_driver ad4000_driver = { 1251 .driver = { 1252 .name = "ad4000", 1253 .of_match_table = ad4000_of_match, 1254 }, 1255 .probe = ad4000_probe, 1256 .id_table = ad4000_id, 1257 }; 1258 module_spi_driver(ad4000_driver); 1259 1260 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>"); 1261 MODULE_DESCRIPTION("Analog Devices AD4000 ADC driver"); 1262 MODULE_LICENSE("GPL"); 1263 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 1264