1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Murata SCA3300 3-axis industrial accelerometer 4 * 5 * Copyright (c) 2021 Vaisala Oyj. All rights reserved. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/crc8.h> 10 #include <linux/delay.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/spi/spi.h> 14 15 #include <linux/unaligned.h> 16 17 #include <linux/iio/buffer.h> 18 #include <linux/iio/iio.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/trigger_consumer.h> 21 #include <linux/iio/triggered_buffer.h> 22 23 #define SCA3300_CRC8_POLYNOMIAL 0x1d 24 25 /* Device mode register */ 26 #define SCA3300_REG_MODE 0xd 27 #define SCA3300_MODE_SW_RESET 0x20 28 29 /* Last register in map */ 30 #define SCA3300_REG_SELBANK 0x1f 31 32 /* Device status and mask */ 33 #define SCA3300_REG_STATUS 0x6 34 #define SCA3300_STATUS_MASK GENMASK(8, 0) 35 36 /* Device ID */ 37 #define SCA3300_REG_WHOAMI 0x10 38 #define SCA3300_WHOAMI_ID 0x51 39 #define SCL3300_WHOAMI_ID 0xC1 40 41 /* Device return status and mask */ 42 #define SCA3300_VALUE_RS_ERROR 0x3 43 #define SCA3300_MASK_RS_STATUS GENMASK(1, 0) 44 45 #define SCL3300_REG_ANG_CTRL 0x0C 46 #define SCL3300_ANG_ENABLE 0x1F 47 48 enum sca3300_scan_indexes { 49 SCA3300_ACC_X = 0, 50 SCA3300_ACC_Y, 51 SCA3300_ACC_Z, 52 SCA3300_TEMP, 53 SCA3300_INCLI_X, 54 SCA3300_INCLI_Y, 55 SCA3300_INCLI_Z, 56 SCA3300_SCAN_MAX 57 }; 58 59 #define SCA3300_ACCEL_CHANNEL(index, reg, axis) { \ 60 .type = IIO_ACCEL, \ 61 .address = reg, \ 62 .modified = 1, \ 63 .channel2 = IIO_MOD_##axis, \ 64 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 65 .info_mask_shared_by_type = \ 66 BIT(IIO_CHAN_INFO_SCALE) | \ 67 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 68 .info_mask_shared_by_type_available = \ 69 BIT(IIO_CHAN_INFO_SCALE) | \ 70 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 71 .scan_index = index, \ 72 .scan_type = { \ 73 .sign = 's', \ 74 .realbits = 16, \ 75 .storagebits = 16, \ 76 .endianness = IIO_CPU, \ 77 }, \ 78 } 79 80 #define SCA3300_INCLI_CHANNEL(index, reg, axis) { \ 81 .type = IIO_INCLI, \ 82 .address = reg, \ 83 .modified = 1, \ 84 .channel2 = IIO_MOD_##axis, \ 85 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 86 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 87 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 88 .scan_index = index, \ 89 .scan_type = { \ 90 .sign = 's', \ 91 .realbits = 16, \ 92 .storagebits = 16, \ 93 .endianness = IIO_CPU, \ 94 }, \ 95 } 96 97 #define SCA3300_TEMP_CHANNEL(index, reg) { \ 98 .type = IIO_TEMP, \ 99 .address = reg, \ 100 .scan_index = index, \ 101 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 102 .scan_type = { \ 103 .sign = 's', \ 104 .realbits = 16, \ 105 .storagebits = 16, \ 106 .endianness = IIO_CPU, \ 107 }, \ 108 } 109 110 static const struct iio_chan_spec sca3300_channels[] = { 111 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), 112 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), 113 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), 114 SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), 115 IIO_CHAN_SOFT_TIMESTAMP(4), 116 }; 117 118 static const int sca3300_lp_freq[] = {70, 10}; 119 static const int sca3300_lp_freq_map[] = {0, 0, 0, 1}; 120 121 static const int scl3300_lp_freq[] = {40, 70, 10}; 122 static const int scl3300_lp_freq_map[] = {0, 1, 2}; 123 124 static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}}; 125 static const int sca3300_accel_scale_map[] = {0, 1, 2, 2}; 126 127 static const int scl3300_accel_scale[][2] = {{0, 167}, {0, 333}, {0, 83}}; 128 static const int scl3300_accel_scale_map[] = {0, 1, 2}; 129 130 static const int scl3300_incli_scale[][2] = {{0, 5495}}; 131 static const int scl3300_incli_scale_map[] = {0, 0, 0}; 132 133 static const int sca3300_avail_modes_map[] = {0, 1, 2, 3}; 134 static const int scl3300_avail_modes_map[] = {0, 1, 3}; 135 136 static const struct iio_chan_spec scl3300_channels[] = { 137 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), 138 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), 139 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), 140 SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), 141 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_X, 0x09, X), 142 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Y, 0x0A, Y), 143 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Z, 0x0B, Z), 144 IIO_CHAN_SOFT_TIMESTAMP(7), 145 }; 146 147 static const unsigned long sca3300_scan_masks[] = { 148 BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | 149 BIT(SCA3300_TEMP), 150 0 151 }; 152 153 static const unsigned long scl3300_scan_masks[] = { 154 BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | 155 BIT(SCA3300_TEMP) | 156 BIT(SCA3300_INCLI_X) | BIT(SCA3300_INCLI_Y) | BIT(SCA3300_INCLI_Z), 157 0 158 }; 159 160 struct sca3300_chip_info { 161 const char *name; 162 const unsigned long *scan_masks; 163 const struct iio_chan_spec *channels; 164 u8 num_channels; 165 u8 num_accel_scales; 166 const int (*accel_scale)[2]; 167 const int *accel_scale_map; 168 const int (*incli_scale)[2]; 169 const int *incli_scale_map; 170 u8 num_incli_scales; 171 u8 num_freqs; 172 const int *freq_table; 173 const int *freq_map; 174 const int *avail_modes_table; 175 u8 num_avail_modes; 176 u8 chip_id; 177 bool angle_supported; 178 }; 179 180 /** 181 * struct sca3300_data - device data 182 * @spi: SPI device structure 183 * @lock: Data buffer lock 184 * @chip: Sensor chip specific information 185 * @txbuf: Transmit buffer 186 * @rxbuf: Receive buffer 187 */ 188 struct sca3300_data { 189 struct spi_device *spi; 190 struct mutex lock; 191 const struct sca3300_chip_info *chip; 192 u8 txbuf[4] __aligned(IIO_DMA_MINALIGN); 193 u8 rxbuf[4]; 194 }; 195 196 static const struct sca3300_chip_info sca3300_chip_tbl[] = { 197 { 198 .name = "sca3300", 199 .scan_masks = sca3300_scan_masks, 200 .channels = sca3300_channels, 201 .num_channels = ARRAY_SIZE(sca3300_channels), 202 .num_accel_scales = ARRAY_SIZE(sca3300_accel_scale)*2, 203 .accel_scale = sca3300_accel_scale, 204 .accel_scale_map = sca3300_accel_scale_map, 205 .num_freqs = ARRAY_SIZE(sca3300_lp_freq), 206 .freq_table = sca3300_lp_freq, 207 .freq_map = sca3300_lp_freq_map, 208 .avail_modes_table = sca3300_avail_modes_map, 209 .num_avail_modes = 4, 210 .chip_id = SCA3300_WHOAMI_ID, 211 .angle_supported = false, 212 }, 213 { 214 .name = "scl3300", 215 .scan_masks = scl3300_scan_masks, 216 .channels = scl3300_channels, 217 .num_channels = ARRAY_SIZE(scl3300_channels), 218 .num_accel_scales = ARRAY_SIZE(scl3300_accel_scale)*2, 219 .accel_scale = scl3300_accel_scale, 220 .accel_scale_map = scl3300_accel_scale_map, 221 .incli_scale = scl3300_incli_scale, 222 .incli_scale_map = scl3300_incli_scale_map, 223 .num_incli_scales = ARRAY_SIZE(scl3300_incli_scale)*2, 224 .num_freqs = ARRAY_SIZE(scl3300_lp_freq), 225 .freq_table = scl3300_lp_freq, 226 .freq_map = scl3300_lp_freq_map, 227 .avail_modes_table = scl3300_avail_modes_map, 228 .num_avail_modes = 3, 229 .chip_id = SCL3300_WHOAMI_ID, 230 .angle_supported = true, 231 }, 232 }; 233 234 DECLARE_CRC8_TABLE(sca3300_crc_table); 235 236 static int sca3300_transfer(struct sca3300_data *sca_data, int *val) 237 { 238 /* Consecutive requests min. 10 us delay (Datasheet section 5.1.2) */ 239 struct spi_delay delay = { .value = 10, .unit = SPI_DELAY_UNIT_USECS }; 240 int32_t ret; 241 int rs; 242 u8 crc; 243 struct spi_transfer xfers[2] = { 244 { 245 .tx_buf = sca_data->txbuf, 246 .len = ARRAY_SIZE(sca_data->txbuf), 247 .delay = delay, 248 .cs_change = 1, 249 }, 250 { 251 .rx_buf = sca_data->rxbuf, 252 .len = ARRAY_SIZE(sca_data->rxbuf), 253 .delay = delay, 254 } 255 }; 256 257 /* inverted crc value as described in device data sheet */ 258 crc = ~crc8(sca3300_crc_table, &sca_data->txbuf[0], 3, CRC8_INIT_VALUE); 259 sca_data->txbuf[3] = crc; 260 261 ret = spi_sync_transfer(sca_data->spi, xfers, ARRAY_SIZE(xfers)); 262 if (ret) { 263 dev_err(&sca_data->spi->dev, 264 "transfer error, error: %d\n", ret); 265 return -EIO; 266 } 267 268 crc = ~crc8(sca3300_crc_table, &sca_data->rxbuf[0], 3, CRC8_INIT_VALUE); 269 if (sca_data->rxbuf[3] != crc) { 270 dev_err(&sca_data->spi->dev, "CRC checksum mismatch"); 271 return -EIO; 272 } 273 274 /* get return status */ 275 rs = sca_data->rxbuf[0] & SCA3300_MASK_RS_STATUS; 276 if (rs == SCA3300_VALUE_RS_ERROR) 277 ret = -EINVAL; 278 279 *val = sign_extend32(get_unaligned_be16(&sca_data->rxbuf[1]), 15); 280 281 return ret; 282 } 283 284 static int sca3300_error_handler(struct sca3300_data *sca_data) 285 { 286 int ret; 287 int val; 288 289 mutex_lock(&sca_data->lock); 290 sca_data->txbuf[0] = SCA3300_REG_STATUS << 2; 291 ret = sca3300_transfer(sca_data, &val); 292 mutex_unlock(&sca_data->lock); 293 /* 294 * Return status error is cleared after reading status register once, 295 * expect EINVAL here. 296 */ 297 if (ret != -EINVAL) { 298 dev_err(&sca_data->spi->dev, 299 "error reading device status: %d\n", ret); 300 return ret; 301 } 302 303 dev_err(&sca_data->spi->dev, "device status: 0x%lx\n", 304 val & SCA3300_STATUS_MASK); 305 306 return 0; 307 } 308 309 static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val) 310 { 311 int ret; 312 313 mutex_lock(&sca_data->lock); 314 sca_data->txbuf[0] = reg << 2; 315 ret = sca3300_transfer(sca_data, val); 316 mutex_unlock(&sca_data->lock); 317 if (ret != -EINVAL) 318 return ret; 319 320 return sca3300_error_handler(sca_data); 321 } 322 323 static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val) 324 { 325 int reg_val = 0; 326 int ret; 327 328 mutex_lock(&sca_data->lock); 329 /* BIT(7) for write operation */ 330 sca_data->txbuf[0] = BIT(7) | (reg << 2); 331 put_unaligned_be16(val, &sca_data->txbuf[1]); 332 ret = sca3300_transfer(sca_data, ®_val); 333 mutex_unlock(&sca_data->lock); 334 if (ret != -EINVAL) 335 return ret; 336 337 return sca3300_error_handler(sca_data); 338 } 339 340 static int sca3300_set_op_mode(struct sca3300_data *sca_data, int index) 341 { 342 if ((index < 0) || (index >= sca_data->chip->num_avail_modes)) 343 return -EINVAL; 344 345 return sca3300_write_reg(sca_data, SCA3300_REG_MODE, 346 sca_data->chip->avail_modes_table[index]); 347 } 348 349 static int sca3300_get_op_mode(struct sca3300_data *sca_data, int *index) 350 { 351 int reg_val; 352 int ret; 353 int i; 354 355 ret = sca3300_read_reg(sca_data, SCA3300_REG_MODE, ®_val); 356 if (ret) 357 return ret; 358 359 for (i = 0; i < sca_data->chip->num_avail_modes; i++) { 360 if (sca_data->chip->avail_modes_table[i] == reg_val) 361 break; 362 } 363 if (i == sca_data->chip->num_avail_modes) 364 return -EINVAL; 365 366 *index = i; 367 return 0; 368 } 369 370 static int sca3300_set_frequency(struct sca3300_data *data, int val) 371 { 372 const struct sca3300_chip_info *chip = data->chip; 373 unsigned int index; 374 int *opmode_scale; 375 int *new_scale; 376 unsigned int i; 377 378 if (sca3300_get_op_mode(data, &index)) 379 return -EINVAL; 380 381 /* 382 * Find a mode in which the requested sampling frequency is available 383 * and the scaling currently set is retained. 384 */ 385 opmode_scale = (int *)chip->accel_scale[chip->accel_scale_map[index]]; 386 for (i = 0; i < chip->num_avail_modes; i++) { 387 new_scale = (int *)chip->accel_scale[chip->accel_scale_map[i]]; 388 if ((val == chip->freq_table[chip->freq_map[i]]) && 389 (opmode_scale[1] == new_scale[1]) && 390 (opmode_scale[0] == new_scale[0])) 391 break; 392 } 393 if (i == chip->num_avail_modes) 394 return -EINVAL; 395 396 return sca3300_set_op_mode(data, i); 397 } 398 399 static int sca3300_write_raw(struct iio_dev *indio_dev, 400 struct iio_chan_spec const *chan, 401 int val, int val2, long mask) 402 { 403 struct sca3300_data *data = iio_priv(indio_dev); 404 int index; 405 int i; 406 407 switch (mask) { 408 case IIO_CHAN_INFO_SCALE: 409 if (chan->type != IIO_ACCEL) 410 return -EINVAL; 411 /* 412 * Letting scale take priority over sampling frequency. 413 * That makes sense given we can only ever end up increasing 414 * the sampling frequency which is unlikely to be a problem. 415 */ 416 for (i = 0; i < data->chip->num_avail_modes; i++) { 417 index = data->chip->accel_scale_map[i]; 418 if ((val == data->chip->accel_scale[index][0]) && 419 (val2 == data->chip->accel_scale[index][1])) 420 return sca3300_set_op_mode(data, i); 421 } 422 return -EINVAL; 423 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 424 return sca3300_set_frequency(data, val); 425 default: 426 return -EINVAL; 427 } 428 } 429 430 static int sca3300_read_raw(struct iio_dev *indio_dev, 431 struct iio_chan_spec const *chan, 432 int *val, int *val2, long mask) 433 { 434 struct sca3300_data *data = iio_priv(indio_dev); 435 int index; 436 int ret; 437 438 switch (mask) { 439 case IIO_CHAN_INFO_RAW: 440 ret = sca3300_read_reg(data, chan->address, val); 441 if (ret) 442 return ret; 443 return IIO_VAL_INT; 444 case IIO_CHAN_INFO_SCALE: 445 ret = sca3300_get_op_mode(data, &index); 446 if (ret) 447 return ret; 448 switch (chan->type) { 449 case IIO_INCLI: 450 index = data->chip->incli_scale_map[index]; 451 *val = data->chip->incli_scale[index][0]; 452 *val2 = data->chip->incli_scale[index][1]; 453 return IIO_VAL_INT_PLUS_MICRO; 454 case IIO_ACCEL: 455 index = data->chip->accel_scale_map[index]; 456 *val = data->chip->accel_scale[index][0]; 457 *val2 = data->chip->accel_scale[index][1]; 458 return IIO_VAL_INT_PLUS_MICRO; 459 default: 460 return -EINVAL; 461 } 462 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 463 ret = sca3300_get_op_mode(data, &index); 464 if (ret) 465 return ret; 466 index = data->chip->freq_map[index]; 467 *val = data->chip->freq_table[index]; 468 return IIO_VAL_INT; 469 default: 470 return -EINVAL; 471 } 472 } 473 474 static irqreturn_t sca3300_trigger_handler(int irq, void *p) 475 { 476 struct iio_poll_func *pf = p; 477 struct iio_dev *indio_dev = pf->indio_dev; 478 struct sca3300_data *data = iio_priv(indio_dev); 479 int bit, ret, val, i = 0; 480 IIO_DECLARE_BUFFER_WITH_TS(s16, channels, SCA3300_SCAN_MAX); 481 482 iio_for_each_active_channel(indio_dev, bit) { 483 ret = sca3300_read_reg(data, indio_dev->channels[bit].address, &val); 484 if (ret) { 485 dev_err_ratelimited(&data->spi->dev, 486 "failed to read register, error: %d\n", ret); 487 /* handled, but bailing out due to errors */ 488 goto out; 489 } 490 channels[i++] = val; 491 } 492 493 iio_push_to_buffers_with_ts(indio_dev, channels, sizeof(channels), 494 iio_get_time_ns(indio_dev)); 495 out: 496 iio_trigger_notify_done(indio_dev->trig); 497 498 return IRQ_HANDLED; 499 } 500 501 /* 502 * sca3300_init - Device init sequence. See datasheet rev 2 section 503 * 4.2 Start-Up Sequence for details. 504 */ 505 static int sca3300_init(struct sca3300_data *sca_data, 506 struct iio_dev *indio_dev) 507 { 508 int value = 0; 509 int ret; 510 int i; 511 512 ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE, 513 SCA3300_MODE_SW_RESET); 514 if (ret) 515 return ret; 516 517 /* 518 * Wait 1ms after SW-reset command. 519 * Wait for the settling of signal paths, 520 * 15ms for SCA3300 and 25ms for SCL3300, 521 */ 522 usleep_range(26e3, 50e3); 523 524 ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value); 525 if (ret) 526 return ret; 527 528 for (i = 0; i < ARRAY_SIZE(sca3300_chip_tbl); i++) { 529 if (sca3300_chip_tbl[i].chip_id == value) 530 break; 531 } 532 if (i == ARRAY_SIZE(sca3300_chip_tbl)) { 533 dev_err(&sca_data->spi->dev, "unknown chip id %x\n", value); 534 return -ENODEV; 535 } 536 537 sca_data->chip = &sca3300_chip_tbl[i]; 538 539 if (sca_data->chip->angle_supported) { 540 ret = sca3300_write_reg(sca_data, SCL3300_REG_ANG_CTRL, 541 SCL3300_ANG_ENABLE); 542 if (ret) 543 return ret; 544 } 545 546 return 0; 547 } 548 549 static int sca3300_debugfs_reg_access(struct iio_dev *indio_dev, 550 unsigned int reg, unsigned int writeval, 551 unsigned int *readval) 552 { 553 struct sca3300_data *data = iio_priv(indio_dev); 554 int value; 555 int ret; 556 557 if (reg > SCA3300_REG_SELBANK) 558 return -EINVAL; 559 560 if (!readval) 561 return sca3300_write_reg(data, reg, writeval); 562 563 ret = sca3300_read_reg(data, reg, &value); 564 if (ret) 565 return ret; 566 567 *readval = value; 568 569 return 0; 570 } 571 572 static int sca3300_read_avail(struct iio_dev *indio_dev, 573 struct iio_chan_spec const *chan, 574 const int **vals, int *type, int *length, 575 long mask) 576 { 577 struct sca3300_data *data = iio_priv(indio_dev); 578 switch (mask) { 579 case IIO_CHAN_INFO_SCALE: 580 switch (chan->type) { 581 case IIO_INCLI: 582 *vals = (const int *)data->chip->incli_scale; 583 *length = data->chip->num_incli_scales; 584 *type = IIO_VAL_INT_PLUS_MICRO; 585 return IIO_AVAIL_LIST; 586 case IIO_ACCEL: 587 *vals = (const int *)data->chip->accel_scale; 588 *length = data->chip->num_accel_scales; 589 *type = IIO_VAL_INT_PLUS_MICRO; 590 return IIO_AVAIL_LIST; 591 default: 592 return -EINVAL; 593 } 594 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 595 *vals = (const int *)data->chip->freq_table; 596 *length = data->chip->num_freqs; 597 *type = IIO_VAL_INT; 598 return IIO_AVAIL_LIST; 599 default: 600 return -EINVAL; 601 } 602 } 603 604 static const struct iio_info sca3300_info = { 605 .read_raw = sca3300_read_raw, 606 .write_raw = sca3300_write_raw, 607 .debugfs_reg_access = &sca3300_debugfs_reg_access, 608 .read_avail = sca3300_read_avail, 609 }; 610 611 static int sca3300_probe(struct spi_device *spi) 612 { 613 struct sca3300_data *sca_data; 614 struct iio_dev *indio_dev; 615 int ret; 616 617 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data)); 618 if (!indio_dev) 619 return -ENOMEM; 620 621 sca_data = iio_priv(indio_dev); 622 mutex_init(&sca_data->lock); 623 sca_data->spi = spi; 624 625 crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL); 626 627 indio_dev->info = &sca3300_info; 628 629 ret = sca3300_init(sca_data, indio_dev); 630 if (ret) { 631 dev_err(&spi->dev, "failed to init device, error: %d\n", ret); 632 return ret; 633 } 634 635 indio_dev->name = sca_data->chip->name; 636 indio_dev->modes = INDIO_DIRECT_MODE; 637 indio_dev->channels = sca_data->chip->channels; 638 indio_dev->num_channels = sca_data->chip->num_channels; 639 indio_dev->available_scan_masks = sca_data->chip->scan_masks; 640 641 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 642 iio_pollfunc_store_time, 643 sca3300_trigger_handler, NULL); 644 if (ret) { 645 dev_err(&spi->dev, 646 "iio triggered buffer setup failed, error: %d\n", ret); 647 return ret; 648 } 649 650 ret = devm_iio_device_register(&spi->dev, indio_dev); 651 if (ret) { 652 dev_err(&spi->dev, "iio device register failed, error: %d\n", 653 ret); 654 } 655 656 return ret; 657 } 658 659 static const struct of_device_id sca3300_dt_ids[] = { 660 { .compatible = "murata,sca3300"}, 661 { .compatible = "murata,scl3300"}, 662 { } 663 }; 664 MODULE_DEVICE_TABLE(of, sca3300_dt_ids); 665 666 static const struct spi_device_id sca3300_ids[] = { 667 { "sca3300" }, 668 { "scl3300" }, 669 { } 670 }; 671 MODULE_DEVICE_TABLE(spi, sca3300_ids); 672 673 static struct spi_driver sca3300_driver = { 674 .driver = { 675 .name = "sca3300", 676 .of_match_table = sca3300_dt_ids, 677 }, 678 .probe = sca3300_probe, 679 .id_table = sca3300_ids, 680 }; 681 module_spi_driver(sca3300_driver); 682 683 MODULE_AUTHOR("Tomas Melin <tomas.melin@vaisala.com>"); 684 MODULE_DESCRIPTION("Murata SCA3300 SPI Accelerometer"); 685 MODULE_LICENSE("GPL v2"); 686