1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI 4 * 5 * Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org> 6 * 7 * See industrialio/accels/sca3000.h for comments. 8 */ 9 10 #include <linux/cleanup.h> 11 #include <linux/interrupt.h> 12 #include <linux/fs.h> 13 #include <linux/device.h> 14 #include <linux/slab.h> 15 #include <linux/kernel.h> 16 #include <linux/spi/spi.h> 17 #include <linux/sysfs.h> 18 #include <linux/module.h> 19 #include <linux/uaccess.h> 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/events.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/kfifo_buf.h> 25 26 #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02) 27 #define SCA3000_READ_REG(a) ((a) << 2) 28 29 #define SCA3000_REG_REVID_ADDR 0x00 30 #define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4) 31 #define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0) 32 33 #define SCA3000_REG_STATUS_ADDR 0x02 34 #define SCA3000_LOCKED BIT(5) 35 #define SCA3000_EEPROM_CS_ERROR BIT(1) 36 #define SCA3000_SPI_FRAME_ERROR BIT(0) 37 38 /* All reads done using register decrement so no need to directly access LSBs */ 39 #define SCA3000_REG_X_MSB_ADDR 0x05 40 #define SCA3000_REG_Y_MSB_ADDR 0x07 41 #define SCA3000_REG_Z_MSB_ADDR 0x09 42 43 #define SCA3000_REG_RING_OUT_ADDR 0x0f 44 45 /* Temp read untested - the e05 doesn't have the sensor */ 46 #define SCA3000_REG_TEMP_MSB_ADDR 0x13 47 48 #define SCA3000_REG_MODE_ADDR 0x14 49 #define SCA3000_MODE_PROT_MASK 0x28 50 #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7) 51 #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6) 52 53 /* 54 * Free fall detection triggers an interrupt if the acceleration 55 * is below a threshold for equivalent of 25cm drop 56 */ 57 #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4) 58 #define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00 59 #define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01 60 #define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02 61 62 /* 63 * In motion detection mode the accelerations are band pass filtered 64 * (approx 1 - 25Hz) and then a programmable threshold used to trigger 65 * and interrupt. 66 */ 67 #define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03 68 #define SCA3000_REG_MODE_MODE_MASK 0x03 69 70 #define SCA3000_REG_BUF_COUNT_ADDR 0x15 71 72 #define SCA3000_REG_INT_STATUS_ADDR 0x16 73 #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7) 74 #define SCA3000_REG_INT_STATUS_HALF BIT(6) 75 76 #define SCA3000_INT_STATUS_FREE_FALL BIT(3) 77 #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2) 78 #define SCA3000_INT_STATUS_X_TRIGGER BIT(1) 79 #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0) 80 81 /* Used to allow access to multiplexed registers */ 82 #define SCA3000_REG_CTRL_SEL_ADDR 0x18 83 /* Only available for SCA3000-D03 and SCA3000-D01 */ 84 #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01 85 #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02 86 #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03 87 #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04 88 #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05 89 /* 90 * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device 91 * will not function 92 */ 93 #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B 94 95 #define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0 96 #define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10 97 #define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08 98 #define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04 99 #define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03 100 #define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02 101 #define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01 102 103 104 /* 105 * Control which motion detector interrupts are on. 106 * For now only OR combinations are supported. 107 */ 108 #define SCA3000_MD_CTRL_PROT_MASK 0xC0 109 #define SCA3000_MD_CTRL_OR_Y BIT(0) 110 #define SCA3000_MD_CTRL_OR_X BIT(1) 111 #define SCA3000_MD_CTRL_OR_Z BIT(2) 112 /* Currently unsupported */ 113 #define SCA3000_MD_CTRL_AND_Y BIT(3) 114 #define SCA3000_MD_CTRL_AND_X BIT(4) 115 #define SCA3000_MD_CTRL_AND_Z BIT(5) 116 117 /* 118 * Some control registers of complex access methods requiring this register to 119 * be used to remove a lock. 120 */ 121 #define SCA3000_REG_UNLOCK_ADDR 0x1e 122 123 #define SCA3000_REG_INT_MASK_ADDR 0x21 124 #define SCA3000_REG_INT_MASK_PROT_MASK 0x1C 125 126 #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7) 127 #define SCA3000_REG_INT_MASK_RING_HALF BIT(6) 128 129 #define SCA3000_REG_INT_MASK_ALL_INTS 0x02 130 #define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01 131 #define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00 132 /* Values of multiplexed registers (write to ctrl_data after select) */ 133 #define SCA3000_REG_CTRL_DATA_ADDR 0x22 134 135 /* 136 * Measurement modes available on some sca3000 series chips. Code assumes others 137 * may become available in the future. 138 * 139 * Bypass - Bypass the low-pass filter in the signal channel so as to increase 140 * signal bandwidth. 141 * 142 * Narrow - Narrow low-pass filtering of the signal channel and half output 143 * data rate by decimation. 144 * 145 * Wide - Widen low-pass filtering of signal channel to increase bandwidth 146 */ 147 #define SCA3000_OP_MODE_BYPASS 0x01 148 #define SCA3000_OP_MODE_NARROW 0x02 149 #define SCA3000_OP_MODE_WIDE 0x04 150 #define SCA3000_MAX_TX 6 151 #define SCA3000_MAX_RX 2 152 153 /** 154 * struct sca3000_state - device instance state information 155 * @us: the associated spi device 156 * @info: chip variant information 157 * @mo_det_use_count: reference counter for the motion detection unit 158 * @lock: lock used to protect elements of sca3000_state 159 * and the underlying device state. 160 * @tx: dma-able transmit buffer 161 * @rx: dma-able receive buffer 162 **/ 163 struct sca3000_state { 164 struct spi_device *us; 165 const struct sca3000_chip_info *info; 166 int mo_det_use_count; 167 struct mutex lock; 168 /* Can these share a cacheline ? */ 169 u8 rx[384] __aligned(IIO_DMA_MINALIGN); 170 u8 tx[6] __aligned(IIO_DMA_MINALIGN); 171 }; 172 173 /** 174 * struct sca3000_chip_info - model dependent parameters 175 * @name: name of the chip 176 * @scale: scale * 10^-6 177 * @temp_output: some devices have temperature sensors. 178 * @measurement_mode_freq: normal mode sampling frequency 179 * @measurement_mode_3db_freq: 3db cutoff frequency of the low pass filter for 180 * the normal measurement mode. 181 * @option_mode_1: first optional mode. Not all models have one 182 * @option_mode_1_freq: option mode 1 sampling frequency 183 * @option_mode_1_3db_freq: 3db cutoff frequency of the low pass filter for 184 * the first option mode. 185 * @option_mode_2: second optional mode. Not all chips have one 186 * @option_mode_2_freq: option mode 2 sampling frequency 187 * @option_mode_2_3db_freq: 3db cutoff frequency of the low pass filter for 188 * the second option mode. 189 * @mot_det_mult_xz: Bit wise multipliers to calculate the threshold 190 * for motion detection in the x and z axis. 191 * @mot_det_mult_y: Bit wise multipliers to calculate the threshold 192 * for motion detection in the y axis. 193 * 194 * This structure is used to hold information about the functionality of a given 195 * sca3000 variant. 196 **/ 197 struct sca3000_chip_info { 198 const char *name; 199 unsigned int scale; 200 bool temp_output; 201 int measurement_mode_freq; 202 int measurement_mode_3db_freq; 203 int option_mode_1; 204 int option_mode_1_freq; 205 int option_mode_1_3db_freq; 206 int option_mode_2; 207 int option_mode_2_freq; 208 int option_mode_2_3db_freq; 209 int mot_det_mult_xz[6]; 210 int mot_det_mult_y[7]; 211 }; 212 213 static const struct sca3000_chip_info sca3000_chip_info_d01 = { 214 .name = "sca3000_d01", 215 .scale = 7357, 216 .temp_output = true, 217 .measurement_mode_freq = 250, 218 .measurement_mode_3db_freq = 45, 219 .option_mode_1 = SCA3000_OP_MODE_BYPASS, 220 .option_mode_1_freq = 250, 221 .option_mode_1_3db_freq = 70, 222 .mot_det_mult_xz = { 50, 100, 200, 350, 650, 1300 }, 223 .mot_det_mult_y = { 50, 100, 150, 250, 450, 850, 1750 }, 224 }; 225 226 static const struct sca3000_chip_info sca3000_chip_info_e02 = { 227 .name = "sca3000_e02", 228 .scale = 9810, 229 .measurement_mode_freq = 125, 230 .measurement_mode_3db_freq = 40, 231 .option_mode_1 = SCA3000_OP_MODE_NARROW, 232 .option_mode_1_freq = 63, 233 .option_mode_1_3db_freq = 11, 234 .mot_det_mult_xz = { 100, 150, 300, 550, 1050, 2050 }, 235 .mot_det_mult_y = { 50, 100, 200, 350, 700, 1350, 2700 }, 236 }; 237 238 static const struct sca3000_chip_info sca3000_chip_info_e04 = { 239 .name = "sca3000_e04", 240 .scale = 19620, 241 .measurement_mode_freq = 100, 242 .measurement_mode_3db_freq = 38, 243 .option_mode_1 = SCA3000_OP_MODE_NARROW, 244 .option_mode_1_freq = 50, 245 .option_mode_1_3db_freq = 9, 246 .option_mode_2 = SCA3000_OP_MODE_WIDE, 247 .option_mode_2_freq = 400, 248 .option_mode_2_3db_freq = 70, 249 .mot_det_mult_xz = { 200, 300, 600, 1100, 2100, 4100 }, 250 .mot_det_mult_y = { 100, 200, 400, 7000, 1400, 2700, 54000 }, 251 }; 252 253 static const struct sca3000_chip_info sca3000_chip_info_e05 = { 254 .name = "sca3000_e05", 255 .scale = 61313, 256 .measurement_mode_freq = 200, 257 .measurement_mode_3db_freq = 60, 258 .option_mode_1 = SCA3000_OP_MODE_NARROW, 259 .option_mode_1_freq = 50, 260 .option_mode_1_3db_freq = 9, 261 .option_mode_2 = SCA3000_OP_MODE_WIDE, 262 .option_mode_2_freq = 400, 263 .option_mode_2_3db_freq = 75, 264 .mot_det_mult_xz = { 600, 900, 1700, 3200, 6100, 11900 }, 265 .mot_det_mult_y = { 300, 600, 1200, 2000, 4100, 7800, 15600 }, 266 }; 267 268 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) 269 { 270 st->tx[0] = SCA3000_WRITE_REG(address); 271 st->tx[1] = val; 272 return spi_write(st->us, st->tx, 2); 273 } 274 275 static int sca3000_read_data_short(struct sca3000_state *st, 276 u8 reg_address_high, 277 int len) 278 { 279 struct spi_transfer xfer[2] = { 280 { 281 .len = 1, 282 .tx_buf = st->tx, 283 }, { 284 .len = len, 285 .rx_buf = st->rx, 286 } 287 }; 288 st->tx[0] = SCA3000_READ_REG(reg_address_high); 289 290 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer)); 291 } 292 293 /** 294 * sca3000_reg_lock_on() - test if the ctrl register lock is on 295 * @st: Driver specific device instance data. 296 * 297 * Lock must be held. 298 **/ 299 static int sca3000_reg_lock_on(struct sca3000_state *st) 300 { 301 int ret; 302 303 ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1); 304 if (ret < 0) 305 return ret; 306 307 return !(st->rx[0] & SCA3000_LOCKED); 308 } 309 310 /** 311 * __sca3000_unlock_reg_lock() - unlock the control registers 312 * @st: Driver specific device instance data. 313 * 314 * Note the device does not appear to support doing this in a single transfer. 315 * This should only ever be used as part of ctrl reg read. 316 * Lock must be held before calling this 317 */ 318 static int __sca3000_unlock_reg_lock(struct sca3000_state *st) 319 { 320 struct spi_transfer xfer[3] = { 321 { 322 .len = 2, 323 .cs_change = 1, 324 .tx_buf = st->tx, 325 }, { 326 .len = 2, 327 .cs_change = 1, 328 .tx_buf = st->tx + 2, 329 }, { 330 .len = 2, 331 .tx_buf = st->tx + 4, 332 }, 333 }; 334 st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR); 335 st->tx[1] = 0x00; 336 st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR); 337 st->tx[3] = 0x50; 338 st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR); 339 st->tx[5] = 0xA0; 340 341 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer)); 342 } 343 344 /** 345 * sca3000_write_ctrl_reg() - write to a lock protect ctrl register 346 * @st: Driver specific device instance data. 347 * @sel: selects which registers we wish to write to 348 * @val: the value to be written 349 * 350 * Certain control registers are protected against overwriting by the lock 351 * register and use a shared write address. This function allows writing of 352 * these registers. 353 * Lock must be held. 354 */ 355 static int sca3000_write_ctrl_reg(struct sca3000_state *st, 356 u8 sel, 357 uint8_t val) 358 { 359 int ret; 360 361 ret = sca3000_reg_lock_on(st); 362 if (ret < 0) 363 return ret; 364 if (ret) { 365 ret = __sca3000_unlock_reg_lock(st); 366 if (ret) 367 return ret; 368 } 369 370 /* Set the control select register */ 371 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel); 372 if (ret) 373 return ret; 374 375 /* Write the actual value into the register */ 376 return sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val); 377 } 378 379 /** 380 * sca3000_read_ctrl_reg() - read from lock protected control register. 381 * @st: Driver specific device instance data. 382 * @ctrl_reg: Which ctrl register do we want to read. 383 * 384 * Lock must be held. 385 */ 386 static int sca3000_read_ctrl_reg(struct sca3000_state *st, 387 u8 ctrl_reg) 388 { 389 int ret; 390 391 ret = sca3000_reg_lock_on(st); 392 if (ret < 0) 393 return ret; 394 if (ret) { 395 ret = __sca3000_unlock_reg_lock(st); 396 if (ret) 397 return ret; 398 } 399 /* Set the control select register */ 400 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg); 401 if (ret) 402 return ret; 403 ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1); 404 if (ret) 405 return ret; 406 return st->rx[0]; 407 } 408 409 /** 410 * sca3000_print_rev() - sysfs interface to read the chip revision number 411 * @indio_dev: Device instance specific generic IIO data. 412 * Driver specific device instance data can be obtained via 413 * iio_priv(indio_dev) 414 */ 415 static int sca3000_print_rev(struct iio_dev *indio_dev) 416 { 417 int ret; 418 struct sca3000_state *st = iio_priv(indio_dev); 419 420 mutex_lock(&st->lock); 421 ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1); 422 if (ret < 0) 423 goto error_ret; 424 dev_info(&indio_dev->dev, 425 "sca3000 revision major=%lu, minor=%lu\n", 426 st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK, 427 st->rx[0] & SCA3000_REG_REVID_MINOR_MASK); 428 error_ret: 429 mutex_unlock(&st->lock); 430 431 return ret; 432 } 433 434 static ssize_t 435 sca3000_show_available_3db_freqs(struct device *dev, 436 struct device_attribute *attr, 437 char *buf) 438 { 439 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 440 struct sca3000_state *st = iio_priv(indio_dev); 441 int len; 442 443 len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq); 444 if (st->info->option_mode_1) 445 len += sprintf(buf + len, " %d", 446 st->info->option_mode_1_3db_freq); 447 if (st->info->option_mode_2) 448 len += sprintf(buf + len, " %d", 449 st->info->option_mode_2_3db_freq); 450 len += sprintf(buf + len, "\n"); 451 452 return len; 453 } 454 455 static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available, 456 S_IRUGO, sca3000_show_available_3db_freqs, 457 NULL, 0); 458 459 static const struct iio_event_spec sca3000_event = { 460 .type = IIO_EV_TYPE_MAG, 461 .dir = IIO_EV_DIR_RISING, 462 .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), 463 }; 464 465 /* 466 * Note the hack in the number of bits to pretend we have 2 more than 467 * we do in the fifo. 468 */ 469 #define SCA3000_CHAN(index, mod) \ 470 { \ 471 .type = IIO_ACCEL, \ 472 .modified = 1, \ 473 .channel2 = mod, \ 474 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 475 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\ 476 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\ 477 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 478 .address = index, \ 479 .scan_index = index, \ 480 .scan_type = { \ 481 .sign = 's', \ 482 .realbits = 13, \ 483 .storagebits = 16, \ 484 .shift = 3, \ 485 .endianness = IIO_BE, \ 486 }, \ 487 .event_spec = &sca3000_event, \ 488 .num_event_specs = 1, \ 489 } 490 491 static const struct iio_event_spec sca3000_freefall_event_spec = { 492 .type = IIO_EV_TYPE_MAG, 493 .dir = IIO_EV_DIR_FALLING, 494 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 495 BIT(IIO_EV_INFO_PERIOD), 496 }; 497 498 static const struct iio_chan_spec sca3000_channels[] = { 499 SCA3000_CHAN(0, IIO_MOD_X), 500 SCA3000_CHAN(1, IIO_MOD_Y), 501 SCA3000_CHAN(2, IIO_MOD_Z), 502 { 503 .type = IIO_ACCEL, 504 .modified = 1, 505 .channel2 = IIO_MOD_X_AND_Y_AND_Z, 506 .scan_index = -1, /* Fake channel */ 507 .event_spec = &sca3000_freefall_event_spec, 508 .num_event_specs = 1, 509 }, 510 }; 511 512 static const struct iio_chan_spec sca3000_channels_with_temp[] = { 513 SCA3000_CHAN(0, IIO_MOD_X), 514 SCA3000_CHAN(1, IIO_MOD_Y), 515 SCA3000_CHAN(2, IIO_MOD_Z), 516 { 517 .type = IIO_TEMP, 518 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 519 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 520 BIT(IIO_CHAN_INFO_OFFSET), 521 /* No buffer support */ 522 .scan_index = -1, 523 .scan_type = { 524 .sign = 'u', 525 .realbits = 9, 526 .storagebits = 16, 527 .shift = 5, 528 .endianness = IIO_BE, 529 }, 530 }, 531 { 532 .type = IIO_ACCEL, 533 .modified = 1, 534 .channel2 = IIO_MOD_X_AND_Y_AND_Z, 535 .scan_index = -1, /* Fake channel */ 536 .event_spec = &sca3000_freefall_event_spec, 537 .num_event_specs = 1, 538 }, 539 }; 540 541 static u8 sca3000_addresses[3][3] = { 542 [0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH, 543 SCA3000_MD_CTRL_OR_X}, 544 [1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH, 545 SCA3000_MD_CTRL_OR_Y}, 546 [2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH, 547 SCA3000_MD_CTRL_OR_Z}, 548 }; 549 550 /** 551 * __sca3000_get_base_freq() - obtain mode specific base frequency 552 * @st: Private driver specific device instance specific state. 553 * @info: chip type specific information. 554 * @base_freq: Base frequency for the current measurement mode. 555 * 556 * lock must be held 557 */ 558 static inline int __sca3000_get_base_freq(struct sca3000_state *st, 559 const struct sca3000_chip_info *info, 560 int *base_freq) 561 { 562 int ret; 563 564 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 565 if (ret) 566 return ret; 567 568 switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) { 569 case SCA3000_REG_MODE_MEAS_MODE_NORMAL: 570 *base_freq = info->measurement_mode_freq; 571 break; 572 case SCA3000_REG_MODE_MEAS_MODE_OP_1: 573 *base_freq = info->option_mode_1_freq; 574 break; 575 case SCA3000_REG_MODE_MEAS_MODE_OP_2: 576 *base_freq = info->option_mode_2_freq; 577 break; 578 default: 579 ret = -EINVAL; 580 } 581 return ret; 582 } 583 584 /** 585 * sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ 586 * @st: Private driver specific device instance specific state. 587 * @val: The frequency read back. 588 * 589 * lock must be held 590 **/ 591 static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val) 592 { 593 int ret; 594 595 ret = __sca3000_get_base_freq(st, st->info, val); 596 if (ret) 597 return ret; 598 599 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL); 600 if (ret < 0) 601 return ret; 602 603 if (*val > 0) { 604 ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK; 605 switch (ret) { 606 case SCA3000_REG_OUT_CTRL_BUF_DIV_2: 607 *val /= 2; 608 break; 609 case SCA3000_REG_OUT_CTRL_BUF_DIV_4: 610 *val /= 4; 611 break; 612 } 613 } 614 615 return 0; 616 } 617 618 /** 619 * sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ 620 * @st: Private driver specific device instance specific state. 621 * @val: The frequency desired. 622 * 623 * lock must be held 624 */ 625 static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val) 626 { 627 int ret, base_freq, ctrlval; 628 629 ret = __sca3000_get_base_freq(st, st->info, &base_freq); 630 if (ret) 631 return ret; 632 633 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL); 634 if (ret < 0) 635 return ret; 636 637 ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK; 638 639 if (val == base_freq / 2) 640 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2; 641 if (val == base_freq / 4) 642 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4; 643 else if (val != base_freq) 644 return -EINVAL; 645 646 return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, 647 ctrlval); 648 } 649 650 static int sca3000_read_3db_freq(struct sca3000_state *st, int *val) 651 { 652 int ret; 653 654 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 655 if (ret) 656 return ret; 657 658 /* mask bottom 2 bits - only ones that are relevant */ 659 st->rx[0] &= SCA3000_REG_MODE_MODE_MASK; 660 switch (st->rx[0]) { 661 case SCA3000_REG_MODE_MEAS_MODE_NORMAL: 662 *val = st->info->measurement_mode_3db_freq; 663 return IIO_VAL_INT; 664 case SCA3000_REG_MODE_MEAS_MODE_MOT_DET: 665 return -EBUSY; 666 case SCA3000_REG_MODE_MEAS_MODE_OP_1: 667 *val = st->info->option_mode_1_3db_freq; 668 return IIO_VAL_INT; 669 case SCA3000_REG_MODE_MEAS_MODE_OP_2: 670 *val = st->info->option_mode_2_3db_freq; 671 return IIO_VAL_INT; 672 default: 673 return -EINVAL; 674 } 675 } 676 677 static int sca3000_write_3db_freq(struct sca3000_state *st, int val) 678 { 679 int ret; 680 int mode; 681 682 if (val == st->info->measurement_mode_3db_freq) 683 mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL; 684 else if (st->info->option_mode_1 && 685 (val == st->info->option_mode_1_3db_freq)) 686 mode = SCA3000_REG_MODE_MEAS_MODE_OP_1; 687 else if (st->info->option_mode_2 && 688 (val == st->info->option_mode_2_3db_freq)) 689 mode = SCA3000_REG_MODE_MEAS_MODE_OP_2; 690 else 691 return -EINVAL; 692 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 693 if (ret) 694 return ret; 695 696 st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK; 697 st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK); 698 699 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]); 700 } 701 702 static int sca3000_read_raw(struct iio_dev *indio_dev, 703 struct iio_chan_spec const *chan, 704 int *val, 705 int *val2, 706 long mask) 707 { 708 struct sca3000_state *st = iio_priv(indio_dev); 709 int ret; 710 u8 address; 711 712 switch (mask) { 713 case IIO_CHAN_INFO_RAW: 714 mutex_lock(&st->lock); 715 if (chan->type == IIO_ACCEL) { 716 if (st->mo_det_use_count) { 717 mutex_unlock(&st->lock); 718 return -EBUSY; 719 } 720 address = sca3000_addresses[chan->address][0]; 721 ret = sca3000_read_data_short(st, address, 2); 722 if (ret < 0) { 723 mutex_unlock(&st->lock); 724 return ret; 725 } 726 *val = sign_extend32(be16_to_cpup((__be16 *)st->rx) >> 727 chan->scan_type.shift, 728 chan->scan_type.realbits - 1); 729 } else { 730 /* get the temperature when available */ 731 ret = sca3000_read_data_short(st, 732 SCA3000_REG_TEMP_MSB_ADDR, 733 2); 734 if (ret < 0) { 735 mutex_unlock(&st->lock); 736 return ret; 737 } 738 *val = (be16_to_cpup((__be16 *)st->rx) >> 739 chan->scan_type.shift) & 740 GENMASK(chan->scan_type.realbits - 1, 0); 741 } 742 mutex_unlock(&st->lock); 743 return IIO_VAL_INT; 744 case IIO_CHAN_INFO_SCALE: 745 *val = 0; 746 if (chan->type == IIO_ACCEL) 747 *val2 = st->info->scale; 748 else /* temperature */ 749 *val2 = 555556; 750 return IIO_VAL_INT_PLUS_MICRO; 751 case IIO_CHAN_INFO_OFFSET: 752 *val = -214; 753 *val2 = 600000; 754 return IIO_VAL_INT_PLUS_MICRO; 755 case IIO_CHAN_INFO_SAMP_FREQ: 756 mutex_lock(&st->lock); 757 ret = sca3000_read_raw_samp_freq(st, val); 758 mutex_unlock(&st->lock); 759 return ret ? ret : IIO_VAL_INT; 760 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 761 mutex_lock(&st->lock); 762 ret = sca3000_read_3db_freq(st, val); 763 mutex_unlock(&st->lock); 764 return ret; 765 default: 766 return -EINVAL; 767 } 768 } 769 770 static int sca3000_write_raw(struct iio_dev *indio_dev, 771 struct iio_chan_spec const *chan, 772 int val, int val2, long mask) 773 { 774 struct sca3000_state *st = iio_priv(indio_dev); 775 int ret; 776 777 switch (mask) { 778 case IIO_CHAN_INFO_SAMP_FREQ: 779 if (val2) 780 return -EINVAL; 781 mutex_lock(&st->lock); 782 ret = sca3000_write_raw_samp_freq(st, val); 783 mutex_unlock(&st->lock); 784 return ret; 785 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 786 if (val2) 787 return -EINVAL; 788 mutex_lock(&st->lock); 789 ret = sca3000_write_3db_freq(st, val); 790 mutex_unlock(&st->lock); 791 return ret; 792 default: 793 return -EINVAL; 794 } 795 796 return ret; 797 } 798 799 /** 800 * sca3000_read_av_freq() - sysfs function to get available frequencies 801 * @dev: Device structure for this device. 802 * @attr: Description of the attribute. 803 * @buf: Incoming string 804 * 805 * The later modes are only relevant to the ring buffer - and depend on current 806 * mode. Note that data sheet gives rather wide tolerances for these so integer 807 * division will give good enough answer and not all chips have them specified 808 * at all. 809 **/ 810 static ssize_t sca3000_read_av_freq(struct device *dev, 811 struct device_attribute *attr, 812 char *buf) 813 { 814 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 815 struct sca3000_state *st = iio_priv(indio_dev); 816 int len = 0, ret, val; 817 818 mutex_lock(&st->lock); 819 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 820 val = st->rx[0]; 821 mutex_unlock(&st->lock); 822 if (ret) 823 return ret; 824 825 switch (val & SCA3000_REG_MODE_MODE_MASK) { 826 case SCA3000_REG_MODE_MEAS_MODE_NORMAL: 827 len += sprintf(buf + len, "%d %d %d\n", 828 st->info->measurement_mode_freq, 829 st->info->measurement_mode_freq / 2, 830 st->info->measurement_mode_freq / 4); 831 break; 832 case SCA3000_REG_MODE_MEAS_MODE_OP_1: 833 len += sprintf(buf + len, "%d %d %d\n", 834 st->info->option_mode_1_freq, 835 st->info->option_mode_1_freq / 2, 836 st->info->option_mode_1_freq / 4); 837 break; 838 case SCA3000_REG_MODE_MEAS_MODE_OP_2: 839 len += sprintf(buf + len, "%d %d %d\n", 840 st->info->option_mode_2_freq, 841 st->info->option_mode_2_freq / 2, 842 st->info->option_mode_2_freq / 4); 843 break; 844 } 845 return len; 846 } 847 848 /* 849 * Should only really be registered if ring buffer support is compiled in. 850 * Does no harm however and doing it right would add a fair bit of complexity 851 */ 852 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq); 853 854 /* 855 * sca3000_read_event_value() - query of a threshold or period 856 */ 857 static int sca3000_read_event_value(struct iio_dev *indio_dev, 858 const struct iio_chan_spec *chan, 859 enum iio_event_type type, 860 enum iio_event_direction dir, 861 enum iio_event_info info, 862 int *val, int *val2) 863 { 864 struct sca3000_state *st = iio_priv(indio_dev); 865 long ret; 866 int i; 867 868 switch (info) { 869 case IIO_EV_INFO_VALUE: 870 mutex_lock(&st->lock); 871 ret = sca3000_read_ctrl_reg(st, 872 sca3000_addresses[chan->address][1]); 873 mutex_unlock(&st->lock); 874 if (ret < 0) 875 return ret; 876 *val = 0; 877 if (chan->channel2 == IIO_MOD_Y) 878 for_each_set_bit(i, &ret, 879 ARRAY_SIZE(st->info->mot_det_mult_y)) 880 *val += st->info->mot_det_mult_y[i]; 881 else 882 for_each_set_bit(i, &ret, 883 ARRAY_SIZE(st->info->mot_det_mult_xz)) 884 *val += st->info->mot_det_mult_xz[i]; 885 886 return IIO_VAL_INT; 887 case IIO_EV_INFO_PERIOD: 888 *val = 0; 889 *val2 = 226000; 890 return IIO_VAL_INT_PLUS_MICRO; 891 default: 892 return -EINVAL; 893 } 894 } 895 896 /** 897 * sca3000_write_event_value() - control of threshold and period 898 * @indio_dev: Device instance specific IIO information. 899 * @chan: Description of the channel for which the event is being 900 * configured. 901 * @type: The type of event being configured, here magnitude rising 902 * as everything else is read only. 903 * @dir: Direction of the event (here rising) 904 * @info: What information about the event are we configuring. 905 * Here the threshold only. 906 * @val: Integer part of the value being written.. 907 * @val2: Non integer part of the value being written. Here always 0. 908 */ 909 static int sca3000_write_event_value(struct iio_dev *indio_dev, 910 const struct iio_chan_spec *chan, 911 enum iio_event_type type, 912 enum iio_event_direction dir, 913 enum iio_event_info info, 914 int val, int val2) 915 { 916 struct sca3000_state *st = iio_priv(indio_dev); 917 int ret; 918 int i; 919 u8 nonlinear = 0; 920 921 if (chan->channel2 == IIO_MOD_Y) { 922 i = ARRAY_SIZE(st->info->mot_det_mult_y); 923 while (i > 0) 924 if (val >= st->info->mot_det_mult_y[--i]) { 925 nonlinear |= (1 << i); 926 val -= st->info->mot_det_mult_y[i]; 927 } 928 } else { 929 i = ARRAY_SIZE(st->info->mot_det_mult_xz); 930 while (i > 0) 931 if (val >= st->info->mot_det_mult_xz[--i]) { 932 nonlinear |= (1 << i); 933 val -= st->info->mot_det_mult_xz[i]; 934 } 935 } 936 937 mutex_lock(&st->lock); 938 ret = sca3000_write_ctrl_reg(st, 939 sca3000_addresses[chan->address][1], 940 nonlinear); 941 mutex_unlock(&st->lock); 942 943 return ret; 944 } 945 946 static struct attribute *sca3000_attributes[] = { 947 &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr, 948 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 949 NULL, 950 }; 951 952 static const struct attribute_group sca3000_attribute_group = { 953 .attrs = sca3000_attributes, 954 }; 955 956 static int sca3000_read_data(struct sca3000_state *st, 957 u8 reg_address_high, 958 u8 *rx, 959 int len) 960 { 961 int ret; 962 struct spi_transfer xfer[2] = { 963 { 964 .len = 1, 965 .tx_buf = st->tx, 966 }, { 967 .len = len, 968 .rx_buf = rx, 969 } 970 }; 971 972 st->tx[0] = SCA3000_READ_REG(reg_address_high); 973 ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer)); 974 if (ret) { 975 dev_err(&st->us->dev, "problem reading register\n"); 976 return ret; 977 } 978 979 return 0; 980 } 981 982 /** 983 * sca3000_ring_int_process() - ring specific interrupt handling. 984 * @val: Value of the interrupt status register. 985 * @indio_dev: Device instance specific IIO device structure. 986 */ 987 static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev) 988 { 989 struct sca3000_state *st = iio_priv(indio_dev); 990 int ret, i, num_available; 991 992 mutex_lock(&st->lock); 993 994 if (val & SCA3000_REG_INT_STATUS_HALF) { 995 ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR, 996 1); 997 if (ret) 998 goto error_ret; 999 num_available = st->rx[0]; 1000 /* 1001 * num_available is the total number of samples available 1002 * i.e. number of time points * number of channels. 1003 */ 1004 ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx, 1005 num_available * 2); 1006 if (ret) 1007 goto error_ret; 1008 for (i = 0; i < num_available / 3; i++) { 1009 /* 1010 * Dirty hack to cover for 11 bit in fifo, 13 bit 1011 * direct reading. 1012 * 1013 * In theory the bottom two bits are undefined. 1014 * In reality they appear to always be 0. 1015 */ 1016 iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2); 1017 } 1018 } 1019 error_ret: 1020 mutex_unlock(&st->lock); 1021 } 1022 1023 /** 1024 * sca3000_event_handler() - handling ring and non ring events 1025 * @irq: The irq being handled. 1026 * @private: struct iio_device pointer for the device. 1027 * 1028 * Ring related interrupt handler. Depending on event, push to 1029 * the ring buffer event chrdev or the event one. 1030 * 1031 * This function is complicated by the fact that the devices can signify ring 1032 * and non ring events via the same interrupt line and they can only 1033 * be distinguished via a read of the relevant status register. 1034 */ 1035 static irqreturn_t sca3000_event_handler(int irq, void *private) 1036 { 1037 struct iio_dev *indio_dev = private; 1038 struct sca3000_state *st = iio_priv(indio_dev); 1039 int ret, val; 1040 s64 last_timestamp = iio_get_time_ns(indio_dev); 1041 1042 /* 1043 * Could lead if badly timed to an extra read of status reg, 1044 * but ensures no interrupt is missed. 1045 */ 1046 mutex_lock(&st->lock); 1047 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1); 1048 val = st->rx[0]; 1049 mutex_unlock(&st->lock); 1050 if (ret) 1051 goto done; 1052 1053 sca3000_ring_int_process(val, indio_dev); 1054 1055 if (val & SCA3000_INT_STATUS_FREE_FALL) 1056 iio_push_event(indio_dev, 1057 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1058 0, 1059 IIO_MOD_X_AND_Y_AND_Z, 1060 IIO_EV_TYPE_MAG, 1061 IIO_EV_DIR_FALLING), 1062 last_timestamp); 1063 1064 if (val & SCA3000_INT_STATUS_Y_TRIGGER) 1065 iio_push_event(indio_dev, 1066 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1067 0, 1068 IIO_MOD_Y, 1069 IIO_EV_TYPE_MAG, 1070 IIO_EV_DIR_RISING), 1071 last_timestamp); 1072 1073 if (val & SCA3000_INT_STATUS_X_TRIGGER) 1074 iio_push_event(indio_dev, 1075 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1076 0, 1077 IIO_MOD_X, 1078 IIO_EV_TYPE_MAG, 1079 IIO_EV_DIR_RISING), 1080 last_timestamp); 1081 1082 if (val & SCA3000_INT_STATUS_Z_TRIGGER) 1083 iio_push_event(indio_dev, 1084 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1085 0, 1086 IIO_MOD_Z, 1087 IIO_EV_TYPE_MAG, 1088 IIO_EV_DIR_RISING), 1089 last_timestamp); 1090 1091 done: 1092 return IRQ_HANDLED; 1093 } 1094 1095 /* 1096 * sca3000_read_event_config() what events are enabled 1097 */ 1098 static int sca3000_read_event_config(struct iio_dev *indio_dev, 1099 const struct iio_chan_spec *chan, 1100 enum iio_event_type type, 1101 enum iio_event_direction dir) 1102 { 1103 struct sca3000_state *st = iio_priv(indio_dev); 1104 int ret; 1105 /* read current value of mode register */ 1106 mutex_lock(&st->lock); 1107 1108 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 1109 if (ret) 1110 goto error_ret; 1111 1112 switch (chan->channel2) { 1113 case IIO_MOD_X_AND_Y_AND_Z: 1114 ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT); 1115 break; 1116 case IIO_MOD_X: 1117 case IIO_MOD_Y: 1118 case IIO_MOD_Z: 1119 /* 1120 * Motion detection mode cannot run at the same time as 1121 * acceleration data being read. 1122 */ 1123 if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK) 1124 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) { 1125 ret = 0; 1126 } else { 1127 ret = sca3000_read_ctrl_reg(st, 1128 SCA3000_REG_CTRL_SEL_MD_CTRL); 1129 if (ret < 0) 1130 goto error_ret; 1131 /* only supporting logical or's for now */ 1132 ret = !!(ret & sca3000_addresses[chan->address][2]); 1133 } 1134 break; 1135 default: 1136 ret = -EINVAL; 1137 } 1138 1139 error_ret: 1140 mutex_unlock(&st->lock); 1141 1142 return ret; 1143 } 1144 1145 static int sca3000_freefall_set_state(struct iio_dev *indio_dev, bool state) 1146 { 1147 struct sca3000_state *st = iio_priv(indio_dev); 1148 int ret; 1149 1150 /* read current value of mode register */ 1151 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 1152 if (ret) 1153 return ret; 1154 1155 /* if off and should be on */ 1156 if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT)) 1157 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, 1158 st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT); 1159 /* if on and should be off */ 1160 else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT)) 1161 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, 1162 st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT); 1163 else 1164 return 0; 1165 } 1166 1167 static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis, 1168 bool state) 1169 { 1170 struct sca3000_state *st = iio_priv(indio_dev); 1171 int ret, ctrlval; 1172 1173 /* 1174 * First read the motion detector config to find out if 1175 * this axis is on 1176 */ 1177 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL); 1178 if (ret < 0) 1179 return ret; 1180 ctrlval = ret; 1181 /* if off and should be on */ 1182 if (state && !(ctrlval & sca3000_addresses[axis][2])) { 1183 ret = sca3000_write_ctrl_reg(st, 1184 SCA3000_REG_CTRL_SEL_MD_CTRL, 1185 ctrlval | 1186 sca3000_addresses[axis][2]); 1187 if (ret) 1188 return ret; 1189 st->mo_det_use_count++; 1190 } else if (!state && (ctrlval & sca3000_addresses[axis][2])) { 1191 ret = sca3000_write_ctrl_reg(st, 1192 SCA3000_REG_CTRL_SEL_MD_CTRL, 1193 ctrlval & 1194 ~(sca3000_addresses[axis][2])); 1195 if (ret) 1196 return ret; 1197 st->mo_det_use_count--; 1198 } 1199 1200 /* read current value of mode register */ 1201 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 1202 if (ret) 1203 return ret; 1204 /* if off and should be on */ 1205 if ((st->mo_det_use_count) && 1206 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK) 1207 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET)) 1208 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, 1209 (st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK) 1210 | SCA3000_REG_MODE_MEAS_MODE_MOT_DET); 1211 /* if on and should be off */ 1212 else if (!(st->mo_det_use_count) && 1213 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK) 1214 == SCA3000_REG_MODE_MEAS_MODE_MOT_DET)) 1215 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, 1216 st->rx[0] & SCA3000_REG_MODE_MODE_MASK); 1217 else 1218 return 0; 1219 } 1220 1221 /** 1222 * sca3000_write_event_config() - simple on off control for motion detector 1223 * @indio_dev: IIO device instance specific structure. Data specific to this 1224 * particular driver may be accessed via iio_priv(indio_dev). 1225 * @chan: Description of the channel whose event we are configuring. 1226 * @type: The type of event. 1227 * @dir: The direction of the event. 1228 * @state: Desired state of event being configured. 1229 * 1230 * This is a per axis control, but enabling any will result in the 1231 * motion detector unit being enabled. 1232 * N.B. enabling motion detector stops normal data acquisition. 1233 * There is a complexity in knowing which mode to return to when 1234 * this mode is disabled. Currently normal mode is assumed. 1235 **/ 1236 static int sca3000_write_event_config(struct iio_dev *indio_dev, 1237 const struct iio_chan_spec *chan, 1238 enum iio_event_type type, 1239 enum iio_event_direction dir, 1240 bool state) 1241 { 1242 struct sca3000_state *st = iio_priv(indio_dev); 1243 int ret; 1244 1245 mutex_lock(&st->lock); 1246 switch (chan->channel2) { 1247 case IIO_MOD_X_AND_Y_AND_Z: 1248 ret = sca3000_freefall_set_state(indio_dev, state); 1249 break; 1250 1251 case IIO_MOD_X: 1252 case IIO_MOD_Y: 1253 case IIO_MOD_Z: 1254 ret = sca3000_motion_detect_set_state(indio_dev, 1255 chan->address, 1256 state); 1257 break; 1258 default: 1259 ret = -EINVAL; 1260 break; 1261 } 1262 mutex_unlock(&st->lock); 1263 1264 return ret; 1265 } 1266 1267 static inline 1268 int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state) 1269 { 1270 struct sca3000_state *st = iio_priv(indio_dev); 1271 int ret; 1272 1273 mutex_lock(&st->lock); 1274 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 1275 if (ret) 1276 goto error_ret; 1277 if (state) { 1278 dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n"); 1279 ret = sca3000_write_reg(st, 1280 SCA3000_REG_MODE_ADDR, 1281 (st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE)); 1282 } else 1283 ret = sca3000_write_reg(st, 1284 SCA3000_REG_MODE_ADDR, 1285 (st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE)); 1286 error_ret: 1287 mutex_unlock(&st->lock); 1288 1289 return ret; 1290 } 1291 1292 /** 1293 * sca3000_hw_ring_preenable() - hw ring buffer preenable function 1294 * @indio_dev: structure representing the IIO device. Device instance 1295 * specific state can be accessed via iio_priv(indio_dev). 1296 * 1297 * Very simple enable function as the chip will allows normal reads 1298 * during ring buffer operation so as long as it is indeed running 1299 * before we notify the core, the precise ordering does not matter. 1300 */ 1301 static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev) 1302 { 1303 int ret; 1304 struct sca3000_state *st = iio_priv(indio_dev); 1305 1306 mutex_lock(&st->lock); 1307 1308 /* Enable the 50% full interrupt */ 1309 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1); 1310 if (ret) 1311 goto error_unlock; 1312 ret = sca3000_write_reg(st, 1313 SCA3000_REG_INT_MASK_ADDR, 1314 st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF); 1315 if (ret) 1316 goto error_unlock; 1317 1318 mutex_unlock(&st->lock); 1319 1320 return __sca3000_hw_ring_state_set(indio_dev, 1); 1321 1322 error_unlock: 1323 mutex_unlock(&st->lock); 1324 1325 return ret; 1326 } 1327 1328 static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev) 1329 { 1330 int ret; 1331 struct sca3000_state *st = iio_priv(indio_dev); 1332 1333 ret = __sca3000_hw_ring_state_set(indio_dev, 0); 1334 if (ret) 1335 return ret; 1336 1337 /* Disable the 50% full interrupt */ 1338 mutex_lock(&st->lock); 1339 1340 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1); 1341 if (ret) 1342 goto unlock; 1343 ret = sca3000_write_reg(st, 1344 SCA3000_REG_INT_MASK_ADDR, 1345 st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF); 1346 unlock: 1347 mutex_unlock(&st->lock); 1348 return ret; 1349 } 1350 1351 static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = { 1352 .preenable = &sca3000_hw_ring_preenable, 1353 .postdisable = &sca3000_hw_ring_postdisable, 1354 }; 1355 1356 /** 1357 * sca3000_clean_setup() - get the device into a predictable state 1358 * @st: Device instance specific private data structure 1359 * 1360 * Devices use flash memory to store many of the register values 1361 * and hence can come up in somewhat unpredictable states. 1362 * Hence reset everything on driver load. 1363 */ 1364 static int sca3000_clean_setup(struct sca3000_state *st) 1365 { 1366 int ret; 1367 1368 mutex_lock(&st->lock); 1369 /* Ensure all interrupts have been acknowledged */ 1370 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1); 1371 if (ret) 1372 goto error_ret; 1373 1374 /* Turn off all motion detection channels */ 1375 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL); 1376 if (ret < 0) 1377 goto error_ret; 1378 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL, 1379 ret & SCA3000_MD_CTRL_PROT_MASK); 1380 if (ret) 1381 goto error_ret; 1382 1383 /* Disable ring buffer */ 1384 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL); 1385 if (ret < 0) 1386 goto error_ret; 1387 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, 1388 (ret & SCA3000_REG_OUT_CTRL_PROT_MASK) 1389 | SCA3000_REG_OUT_CTRL_BUF_X_EN 1390 | SCA3000_REG_OUT_CTRL_BUF_Y_EN 1391 | SCA3000_REG_OUT_CTRL_BUF_Z_EN 1392 | SCA3000_REG_OUT_CTRL_BUF_DIV_4); 1393 if (ret) 1394 goto error_ret; 1395 /* Enable interrupts, relevant to mode and set up as active low */ 1396 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1); 1397 if (ret) 1398 goto error_ret; 1399 ret = sca3000_write_reg(st, 1400 SCA3000_REG_INT_MASK_ADDR, 1401 (ret & SCA3000_REG_INT_MASK_PROT_MASK) 1402 | SCA3000_REG_INT_MASK_ACTIVE_LOW); 1403 if (ret) 1404 goto error_ret; 1405 /* 1406 * Select normal measurement mode, free fall off, ring off 1407 * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5 1408 * as that occurs in one of the example on the datasheet 1409 */ 1410 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1); 1411 if (ret) 1412 goto error_ret; 1413 ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, 1414 (st->rx[0] & SCA3000_MODE_PROT_MASK)); 1415 1416 error_ret: 1417 mutex_unlock(&st->lock); 1418 return ret; 1419 } 1420 1421 static const struct iio_info sca3000_info = { 1422 .attrs = &sca3000_attribute_group, 1423 .read_raw = &sca3000_read_raw, 1424 .write_raw = &sca3000_write_raw, 1425 .read_event_value = &sca3000_read_event_value, 1426 .write_event_value = &sca3000_write_event_value, 1427 .read_event_config = &sca3000_read_event_config, 1428 .write_event_config = &sca3000_write_event_config, 1429 }; 1430 1431 static void sca3000_stop_all_interrupts(void *data) 1432 { 1433 struct iio_dev *indio_dev = data; 1434 struct sca3000_state *st = iio_priv(indio_dev); 1435 int ret; 1436 1437 guard(mutex)(&st->lock); 1438 1439 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1); 1440 if (ret) 1441 return; 1442 1443 sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR, 1444 (st->rx[0] & 1445 ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER | 1446 SCA3000_REG_INT_MASK_RING_HALF | 1447 SCA3000_REG_INT_MASK_ALL_INTS))); 1448 } 1449 1450 static int sca3000_probe(struct spi_device *spi) 1451 { 1452 struct device *dev = &spi->dev; 1453 struct sca3000_state *st; 1454 struct iio_dev *indio_dev; 1455 int ret; 1456 1457 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1458 if (!indio_dev) 1459 return -ENOMEM; 1460 1461 st = iio_priv(indio_dev); 1462 st->us = spi; 1463 mutex_init(&st->lock); 1464 st->info = spi_get_device_match_data(spi); 1465 1466 indio_dev->name = st->info->name; 1467 indio_dev->info = &sca3000_info; 1468 if (st->info->temp_output) { 1469 indio_dev->channels = sca3000_channels_with_temp; 1470 indio_dev->num_channels = 1471 ARRAY_SIZE(sca3000_channels_with_temp); 1472 } else { 1473 indio_dev->channels = sca3000_channels; 1474 indio_dev->num_channels = ARRAY_SIZE(sca3000_channels); 1475 } 1476 indio_dev->modes = INDIO_DIRECT_MODE; 1477 1478 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &sca3000_ring_setup_ops); 1479 if (ret) 1480 return ret; 1481 1482 if (spi->irq) { 1483 ret = devm_request_threaded_irq(dev, spi->irq, NULL, 1484 &sca3000_event_handler, 1485 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1486 "sca3000", 1487 indio_dev); 1488 if (ret) 1489 return ret; 1490 } 1491 ret = sca3000_clean_setup(st); 1492 if (ret) 1493 return ret; 1494 1495 ret = sca3000_print_rev(indio_dev); 1496 if (ret) 1497 return ret; 1498 1499 ret = devm_add_action_or_reset(dev, sca3000_stop_all_interrupts, indio_dev); 1500 if (ret) 1501 return ret; 1502 1503 return devm_iio_device_register(dev, indio_dev); 1504 } 1505 1506 static const struct spi_device_id sca3000_id[] = { 1507 { "sca3000_d01", (kernel_ulong_t)&sca3000_chip_info_d01 }, 1508 { "sca3000_e02", (kernel_ulong_t)&sca3000_chip_info_e02 }, 1509 { "sca3000_e04", (kernel_ulong_t)&sca3000_chip_info_e04 }, 1510 { "sca3000_e05", (kernel_ulong_t)&sca3000_chip_info_e05 }, 1511 { } 1512 }; 1513 MODULE_DEVICE_TABLE(spi, sca3000_id); 1514 1515 static struct spi_driver sca3000_driver = { 1516 .driver = { 1517 .name = "sca3000", 1518 }, 1519 .probe = sca3000_probe, 1520 .id_table = sca3000_id, 1521 }; 1522 module_spi_driver(sca3000_driver); 1523 1524 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>"); 1525 MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver"); 1526 MODULE_LICENSE("GPL v2"); 1527