1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver for MXC4005XC Memsic sensor 4 * 5 * Copyright (c) 2014, Intel Corporation. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/module.h> 10 #include <linux/i2c.h> 11 #include <linux/iio/iio.h> 12 #include <linux/regmap.h> 13 #include <linux/types.h> 14 #include <linux/iio/sysfs.h> 15 #include <linux/iio/trigger.h> 16 #include <linux/iio/buffer.h> 17 #include <linux/iio/triggered_buffer.h> 18 #include <linux/iio/trigger_consumer.h> 19 20 #define MXC4005_DRV_NAME "mxc4005" 21 22 #define MXC4005_REG_XOUT_UPPER 0x03 23 #define MXC4005_REG_XOUT_LOWER 0x04 24 #define MXC4005_REG_YOUT_UPPER 0x05 25 #define MXC4005_REG_YOUT_LOWER 0x06 26 #define MXC4005_REG_ZOUT_UPPER 0x07 27 #define MXC4005_REG_ZOUT_LOWER 0x08 28 29 #define MXC4005_REG_INT_MASK0 0x0A 30 31 #define MXC4005_REG_INT_MASK1 0x0B 32 #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01 33 34 #define MXC4005_REG_INT_CLR0 0x00 35 36 #define MXC4005_REG_INT_CLR1 0x01 37 #define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01 38 #define MXC4005_REG_INT_CLR1_SW_RST 0x10 39 40 #define MXC4005_REG_CONTROL 0x0D 41 #define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5) 42 #define MXC4005_CONTROL_FSR_SHIFT 5 43 44 #define MXC4005_REG_DEVICE_ID 0x0E 45 46 /* Datasheet does not specify a reset time, this is a conservative guess */ 47 #define MXC4005_RESET_TIME_US 2000 48 49 enum mxc4005_axis { 50 AXIS_X, 51 AXIS_Y, 52 AXIS_Z, 53 }; 54 55 enum mxc4005_range { 56 MXC4005_RANGE_2G, 57 MXC4005_RANGE_4G, 58 MXC4005_RANGE_8G, 59 }; 60 61 struct mxc4005_data { 62 struct device *dev; 63 struct mutex mutex; 64 struct regmap *regmap; 65 struct iio_trigger *dready_trig; 66 struct iio_mount_matrix orientation; 67 /* Ensure timestamp is naturally aligned */ 68 struct { 69 __be16 chans[3]; 70 aligned_s64 timestamp; 71 } scan; 72 bool trigger_enabled; 73 unsigned int control; 74 unsigned int int_mask1; 75 }; 76 77 /* 78 * MXC4005 can operate in the following ranges: 79 * +/- 2G, 4G, 8G (the default +/-2G) 80 * 81 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582 82 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164 83 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329 84 */ 85 static const struct { 86 u8 range; 87 int scale; 88 } mxc4005_scale_table[] = { 89 {MXC4005_RANGE_2G, 9582}, 90 {MXC4005_RANGE_4G, 19164}, 91 {MXC4005_RANGE_8G, 38329}, 92 }; 93 94 95 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329"); 96 97 static struct attribute *mxc4005_attributes[] = { 98 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 99 NULL, 100 }; 101 102 static const struct attribute_group mxc4005_attrs_group = { 103 .attrs = mxc4005_attributes, 104 }; 105 106 static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg) 107 { 108 switch (reg) { 109 case MXC4005_REG_XOUT_UPPER: 110 case MXC4005_REG_XOUT_LOWER: 111 case MXC4005_REG_YOUT_UPPER: 112 case MXC4005_REG_YOUT_LOWER: 113 case MXC4005_REG_ZOUT_UPPER: 114 case MXC4005_REG_ZOUT_LOWER: 115 case MXC4005_REG_DEVICE_ID: 116 case MXC4005_REG_CONTROL: 117 return true; 118 default: 119 return false; 120 } 121 } 122 123 static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg) 124 { 125 switch (reg) { 126 case MXC4005_REG_INT_CLR0: 127 case MXC4005_REG_INT_CLR1: 128 case MXC4005_REG_INT_MASK0: 129 case MXC4005_REG_INT_MASK1: 130 case MXC4005_REG_CONTROL: 131 return true; 132 default: 133 return false; 134 } 135 } 136 137 static const struct regmap_config mxc4005_regmap_config = { 138 .name = "mxc4005_regmap", 139 140 .reg_bits = 8, 141 .val_bits = 8, 142 143 .max_register = MXC4005_REG_DEVICE_ID, 144 145 .readable_reg = mxc4005_is_readable_reg, 146 .writeable_reg = mxc4005_is_writeable_reg, 147 }; 148 149 static int mxc4005_read_xyz(struct mxc4005_data *data) 150 { 151 int ret; 152 153 ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER, 154 data->scan.chans, sizeof(data->scan.chans)); 155 if (ret < 0) { 156 dev_err(data->dev, "failed to read axes\n"); 157 return ret; 158 } 159 160 return 0; 161 } 162 163 static int mxc4005_read_axis(struct mxc4005_data *data, 164 unsigned int addr) 165 { 166 __be16 reg; 167 int ret; 168 169 ret = regmap_bulk_read(data->regmap, addr, ®, sizeof(reg)); 170 if (ret < 0) { 171 dev_err(data->dev, "failed to read reg %02x\n", addr); 172 return ret; 173 } 174 175 return be16_to_cpu(reg); 176 } 177 178 static int mxc4005_read_scale(struct mxc4005_data *data) 179 { 180 unsigned int reg; 181 int ret; 182 int i; 183 184 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®); 185 if (ret < 0) { 186 dev_err(data->dev, "failed to read reg_control\n"); 187 return ret; 188 } 189 190 i = reg >> MXC4005_CONTROL_FSR_SHIFT; 191 192 if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table)) 193 return -EINVAL; 194 195 return mxc4005_scale_table[i].scale; 196 } 197 198 static int mxc4005_set_scale(struct mxc4005_data *data, int val) 199 { 200 unsigned int reg; 201 int i; 202 int ret; 203 204 for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) { 205 if (mxc4005_scale_table[i].scale == val) { 206 reg = i << MXC4005_CONTROL_FSR_SHIFT; 207 ret = regmap_update_bits(data->regmap, 208 MXC4005_REG_CONTROL, 209 MXC4005_REG_CONTROL_MASK_FSR, 210 reg); 211 if (ret < 0) 212 dev_err(data->dev, 213 "failed to write reg_control\n"); 214 return ret; 215 } 216 } 217 218 return -EINVAL; 219 } 220 221 static int mxc4005_read_raw(struct iio_dev *indio_dev, 222 struct iio_chan_spec const *chan, 223 int *val, int *val2, long mask) 224 { 225 struct mxc4005_data *data = iio_priv(indio_dev); 226 int ret; 227 228 switch (mask) { 229 case IIO_CHAN_INFO_RAW: 230 switch (chan->type) { 231 case IIO_ACCEL: 232 if (iio_buffer_enabled(indio_dev)) 233 return -EBUSY; 234 235 ret = mxc4005_read_axis(data, chan->address); 236 if (ret < 0) 237 return ret; 238 *val = sign_extend32(ret >> chan->scan_type.shift, 239 chan->scan_type.realbits - 1); 240 return IIO_VAL_INT; 241 default: 242 return -EINVAL; 243 } 244 case IIO_CHAN_INFO_SCALE: 245 ret = mxc4005_read_scale(data); 246 if (ret < 0) 247 return ret; 248 249 *val = 0; 250 *val2 = ret; 251 return IIO_VAL_INT_PLUS_MICRO; 252 default: 253 return -EINVAL; 254 } 255 } 256 257 static int mxc4005_write_raw(struct iio_dev *indio_dev, 258 struct iio_chan_spec const *chan, 259 int val, int val2, long mask) 260 { 261 struct mxc4005_data *data = iio_priv(indio_dev); 262 263 switch (mask) { 264 case IIO_CHAN_INFO_SCALE: 265 if (val != 0) 266 return -EINVAL; 267 268 return mxc4005_set_scale(data, val2); 269 default: 270 return -EINVAL; 271 } 272 } 273 274 static const struct iio_mount_matrix * 275 mxc4005_get_mount_matrix(const struct iio_dev *indio_dev, 276 const struct iio_chan_spec *chan) 277 { 278 struct mxc4005_data *data = iio_priv(indio_dev); 279 280 return &data->orientation; 281 } 282 283 static const struct iio_chan_spec_ext_info mxc4005_ext_info[] = { 284 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mxc4005_get_mount_matrix), 285 { } 286 }; 287 288 static const struct iio_info mxc4005_info = { 289 .read_raw = mxc4005_read_raw, 290 .write_raw = mxc4005_write_raw, 291 .attrs = &mxc4005_attrs_group, 292 }; 293 294 static const unsigned long mxc4005_scan_masks[] = { 295 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 296 0 297 }; 298 299 #define MXC4005_CHANNEL(_axis, _addr) { \ 300 .type = IIO_ACCEL, \ 301 .modified = 1, \ 302 .channel2 = IIO_MOD_##_axis, \ 303 .address = _addr, \ 304 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 305 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 306 .scan_index = AXIS_##_axis, \ 307 .scan_type = { \ 308 .sign = 's', \ 309 .realbits = 12, \ 310 .storagebits = 16, \ 311 .shift = 4, \ 312 .endianness = IIO_BE, \ 313 }, \ 314 .ext_info = mxc4005_ext_info, \ 315 } 316 317 static const struct iio_chan_spec mxc4005_channels[] = { 318 MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER), 319 MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER), 320 MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER), 321 IIO_CHAN_SOFT_TIMESTAMP(3), 322 }; 323 324 static irqreturn_t mxc4005_trigger_handler(int irq, void *private) 325 { 326 struct iio_poll_func *pf = private; 327 struct iio_dev *indio_dev = pf->indio_dev; 328 struct mxc4005_data *data = iio_priv(indio_dev); 329 int ret; 330 331 ret = mxc4005_read_xyz(data); 332 if (ret < 0) 333 goto err; 334 335 iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan), 336 pf->timestamp); 337 338 err: 339 iio_trigger_notify_done(indio_dev->trig); 340 341 return IRQ_HANDLED; 342 } 343 344 static void mxc4005_clr_intr(struct mxc4005_data *data) 345 { 346 int ret; 347 348 /* clear interrupt */ 349 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 350 MXC4005_REG_INT_CLR1_BIT_DRDYC); 351 if (ret < 0) 352 dev_err(data->dev, "failed to write to reg_int_clr1\n"); 353 } 354 355 static int mxc4005_set_trigger_state(struct iio_trigger *trig, 356 bool state) 357 { 358 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 359 struct mxc4005_data *data = iio_priv(indio_dev); 360 unsigned int val; 361 int ret; 362 363 mutex_lock(&data->mutex); 364 365 val = state ? MXC4005_REG_INT_MASK1_BIT_DRDYE : 0; 366 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, val); 367 if (ret < 0) { 368 mutex_unlock(&data->mutex); 369 dev_err(data->dev, "failed to update reg_int_mask1"); 370 return ret; 371 } 372 373 data->int_mask1 = val; 374 data->trigger_enabled = state; 375 mutex_unlock(&data->mutex); 376 377 return 0; 378 } 379 380 static void mxc4005_trigger_reen(struct iio_trigger *trig) 381 { 382 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 383 struct mxc4005_data *data = iio_priv(indio_dev); 384 385 if (!data->dready_trig) 386 return; 387 388 mxc4005_clr_intr(data); 389 } 390 391 static const struct iio_trigger_ops mxc4005_trigger_ops = { 392 .set_trigger_state = mxc4005_set_trigger_state, 393 .reenable = mxc4005_trigger_reen, 394 }; 395 396 static int mxc4005_chip_init(struct mxc4005_data *data) 397 { 398 int ret; 399 unsigned int reg; 400 401 ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®); 402 if (ret < 0) { 403 dev_err(data->dev, "failed to read chip id\n"); 404 return ret; 405 } 406 407 dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg); 408 409 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 410 MXC4005_REG_INT_CLR1_SW_RST); 411 if (ret < 0) 412 return dev_err_probe(data->dev, ret, "resetting chip\n"); 413 414 fsleep(MXC4005_RESET_TIME_US); 415 416 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0); 417 if (ret < 0) 418 return dev_err_probe(data->dev, ret, "writing INT_MASK0\n"); 419 420 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, 0); 421 if (ret < 0) 422 return dev_err_probe(data->dev, ret, "writing INT_MASK1\n"); 423 424 return 0; 425 } 426 427 static int mxc4005_probe(struct i2c_client *client) 428 { 429 struct mxc4005_data *data; 430 struct iio_dev *indio_dev; 431 struct regmap *regmap; 432 int ret; 433 434 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 435 if (!indio_dev) 436 return -ENOMEM; 437 438 regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config); 439 if (IS_ERR(regmap)) { 440 dev_err(&client->dev, "failed to initialize regmap\n"); 441 return PTR_ERR(regmap); 442 } 443 444 data = iio_priv(indio_dev); 445 i2c_set_clientdata(client, indio_dev); 446 data->dev = &client->dev; 447 data->regmap = regmap; 448 449 ret = mxc4005_chip_init(data); 450 if (ret < 0) { 451 dev_err(&client->dev, "failed to initialize chip\n"); 452 return ret; 453 } 454 455 mutex_init(&data->mutex); 456 457 if (!iio_read_acpi_mount_matrix(&client->dev, &data->orientation, "ROTM")) { 458 ret = iio_read_mount_matrix(&client->dev, &data->orientation); 459 if (ret) 460 return ret; 461 } 462 463 indio_dev->channels = mxc4005_channels; 464 indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels); 465 indio_dev->available_scan_masks = mxc4005_scan_masks; 466 indio_dev->name = MXC4005_DRV_NAME; 467 indio_dev->modes = INDIO_DIRECT_MODE; 468 indio_dev->info = &mxc4005_info; 469 470 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, 471 iio_pollfunc_store_time, 472 mxc4005_trigger_handler, 473 NULL); 474 if (ret < 0) { 475 dev_err(&client->dev, 476 "failed to setup iio triggered buffer\n"); 477 return ret; 478 } 479 480 if (client->irq > 0) { 481 data->dready_trig = devm_iio_trigger_alloc(&client->dev, 482 "%s-dev%d", 483 indio_dev->name, 484 iio_device_id(indio_dev)); 485 if (!data->dready_trig) 486 return -ENOMEM; 487 488 ret = devm_request_irq(&client->dev, client->irq, 489 iio_trigger_generic_data_rdy_poll, 490 IRQF_TRIGGER_FALLING | IRQF_NO_THREAD, 491 "mxc4005_event", data->dready_trig); 492 if (ret) 493 return ret; 494 495 data->dready_trig->ops = &mxc4005_trigger_ops; 496 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 497 ret = devm_iio_trigger_register(&client->dev, 498 data->dready_trig); 499 if (ret) { 500 dev_err(&client->dev, 501 "failed to register trigger\n"); 502 return ret; 503 } 504 505 indio_dev->trig = iio_trigger_get(data->dready_trig); 506 } 507 508 return devm_iio_device_register(&client->dev, indio_dev); 509 } 510 511 static int mxc4005_suspend(struct device *dev) 512 { 513 struct iio_dev *indio_dev = dev_get_drvdata(dev); 514 struct mxc4005_data *data = iio_priv(indio_dev); 515 int ret; 516 517 /* Save control to restore it on resume */ 518 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &data->control); 519 if (ret < 0) 520 dev_err(data->dev, "failed to read reg_control\n"); 521 522 return ret; 523 } 524 525 static int mxc4005_resume(struct device *dev) 526 { 527 struct iio_dev *indio_dev = dev_get_drvdata(dev); 528 struct mxc4005_data *data = iio_priv(indio_dev); 529 int ret; 530 531 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 532 MXC4005_REG_INT_CLR1_SW_RST); 533 if (ret) { 534 dev_err(data->dev, "failed to reset chip: %d\n", ret); 535 return ret; 536 } 537 538 fsleep(MXC4005_RESET_TIME_US); 539 540 ret = regmap_write(data->regmap, MXC4005_REG_CONTROL, data->control); 541 if (ret) { 542 dev_err(data->dev, "failed to restore control register\n"); 543 return ret; 544 } 545 546 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0); 547 if (ret) { 548 dev_err(data->dev, "failed to restore interrupt 0 mask\n"); 549 return ret; 550 } 551 552 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, data->int_mask1); 553 if (ret) { 554 dev_err(data->dev, "failed to restore interrupt 1 mask\n"); 555 return ret; 556 } 557 558 return 0; 559 } 560 561 static DEFINE_SIMPLE_DEV_PM_OPS(mxc4005_pm_ops, mxc4005_suspend, mxc4005_resume); 562 563 static const struct acpi_device_id mxc4005_acpi_match[] = { 564 {"MXC4005", 0}, 565 {"MXC6655", 0}, 566 {"MDA6655", 0}, 567 { } 568 }; 569 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match); 570 571 static const struct of_device_id mxc4005_of_match[] = { 572 { .compatible = "memsic,mxc4005", }, 573 { .compatible = "memsic,mxc6655", }, 574 { } 575 }; 576 MODULE_DEVICE_TABLE(of, mxc4005_of_match); 577 578 static const struct i2c_device_id mxc4005_id[] = { 579 { .name = "mxc4005" }, 580 { .name = "mxc6655" }, 581 { } 582 }; 583 MODULE_DEVICE_TABLE(i2c, mxc4005_id); 584 585 static struct i2c_driver mxc4005_driver = { 586 .driver = { 587 .name = MXC4005_DRV_NAME, 588 .acpi_match_table = mxc4005_acpi_match, 589 .of_match_table = mxc4005_of_match, 590 .pm = pm_sleep_ptr(&mxc4005_pm_ops), 591 }, 592 .probe = mxc4005_probe, 593 .id_table = mxc4005_id, 594 }; 595 596 module_i2c_driver(mxc4005_driver); 597 598 MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>"); 599 MODULE_LICENSE("GPL v2"); 600 MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver"); 601