1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver for MXC4005XC Memsic sensor 4 * 5 * Copyright (c) 2014, Intel Corporation. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/module.h> 10 #include <linux/i2c.h> 11 #include <linux/iio/iio.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/regmap.h> 14 #include <linux/types.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/trigger.h> 17 #include <linux/iio/buffer.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/trigger_consumer.h> 20 21 #define MXC4005_DRV_NAME "mxc4005" 22 #define MXC4005_IRQ_NAME "mxc4005_event" 23 #define MXC4005_REGMAP_NAME "mxc4005_regmap" 24 25 #define MXC4005_REG_XOUT_UPPER 0x03 26 #define MXC4005_REG_XOUT_LOWER 0x04 27 #define MXC4005_REG_YOUT_UPPER 0x05 28 #define MXC4005_REG_YOUT_LOWER 0x06 29 #define MXC4005_REG_ZOUT_UPPER 0x07 30 #define MXC4005_REG_ZOUT_LOWER 0x08 31 32 #define MXC4005_REG_INT_MASK0 0x0A 33 34 #define MXC4005_REG_INT_MASK1 0x0B 35 #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01 36 37 #define MXC4005_REG_INT_CLR0 0x00 38 39 #define MXC4005_REG_INT_CLR1 0x01 40 #define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01 41 #define MXC4005_REG_INT_CLR1_SW_RST 0x10 42 43 #define MXC4005_REG_CONTROL 0x0D 44 #define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5) 45 #define MXC4005_CONTROL_FSR_SHIFT 5 46 47 #define MXC4005_REG_DEVICE_ID 0x0E 48 49 /* Datasheet does not specify a reset time, this is a conservative guess */ 50 #define MXC4005_RESET_TIME_US 2000 51 52 enum mxc4005_axis { 53 AXIS_X, 54 AXIS_Y, 55 AXIS_Z, 56 }; 57 58 enum mxc4005_range { 59 MXC4005_RANGE_2G, 60 MXC4005_RANGE_4G, 61 MXC4005_RANGE_8G, 62 }; 63 64 struct mxc4005_data { 65 struct device *dev; 66 struct mutex mutex; 67 struct regmap *regmap; 68 struct iio_trigger *dready_trig; 69 struct iio_mount_matrix orientation; 70 /* Ensure timestamp is naturally aligned */ 71 struct { 72 __be16 chans[3]; 73 aligned_s64 timestamp; 74 } scan; 75 bool trigger_enabled; 76 unsigned int control; 77 unsigned int int_mask1; 78 }; 79 80 /* 81 * MXC4005 can operate in the following ranges: 82 * +/- 2G, 4G, 8G (the default +/-2G) 83 * 84 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582 85 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164 86 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329 87 */ 88 static const struct { 89 u8 range; 90 int scale; 91 } mxc4005_scale_table[] = { 92 {MXC4005_RANGE_2G, 9582}, 93 {MXC4005_RANGE_4G, 19164}, 94 {MXC4005_RANGE_8G, 38329}, 95 }; 96 97 98 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329"); 99 100 static struct attribute *mxc4005_attributes[] = { 101 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 102 NULL, 103 }; 104 105 static const struct attribute_group mxc4005_attrs_group = { 106 .attrs = mxc4005_attributes, 107 }; 108 109 static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg) 110 { 111 switch (reg) { 112 case MXC4005_REG_XOUT_UPPER: 113 case MXC4005_REG_XOUT_LOWER: 114 case MXC4005_REG_YOUT_UPPER: 115 case MXC4005_REG_YOUT_LOWER: 116 case MXC4005_REG_ZOUT_UPPER: 117 case MXC4005_REG_ZOUT_LOWER: 118 case MXC4005_REG_DEVICE_ID: 119 case MXC4005_REG_CONTROL: 120 return true; 121 default: 122 return false; 123 } 124 } 125 126 static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg) 127 { 128 switch (reg) { 129 case MXC4005_REG_INT_CLR0: 130 case MXC4005_REG_INT_CLR1: 131 case MXC4005_REG_INT_MASK0: 132 case MXC4005_REG_INT_MASK1: 133 case MXC4005_REG_CONTROL: 134 return true; 135 default: 136 return false; 137 } 138 } 139 140 static const struct regmap_config mxc4005_regmap_config = { 141 .name = MXC4005_REGMAP_NAME, 142 143 .reg_bits = 8, 144 .val_bits = 8, 145 146 .max_register = MXC4005_REG_DEVICE_ID, 147 148 .readable_reg = mxc4005_is_readable_reg, 149 .writeable_reg = mxc4005_is_writeable_reg, 150 }; 151 152 static int mxc4005_read_xyz(struct mxc4005_data *data) 153 { 154 int ret; 155 156 ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER, 157 data->scan.chans, sizeof(data->scan.chans)); 158 if (ret < 0) { 159 dev_err(data->dev, "failed to read axes\n"); 160 return ret; 161 } 162 163 return 0; 164 } 165 166 static int mxc4005_read_axis(struct mxc4005_data *data, 167 unsigned int addr) 168 { 169 __be16 reg; 170 int ret; 171 172 ret = regmap_bulk_read(data->regmap, addr, ®, sizeof(reg)); 173 if (ret < 0) { 174 dev_err(data->dev, "failed to read reg %02x\n", addr); 175 return ret; 176 } 177 178 return be16_to_cpu(reg); 179 } 180 181 static int mxc4005_read_scale(struct mxc4005_data *data) 182 { 183 unsigned int reg; 184 int ret; 185 int i; 186 187 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®); 188 if (ret < 0) { 189 dev_err(data->dev, "failed to read reg_control\n"); 190 return ret; 191 } 192 193 i = reg >> MXC4005_CONTROL_FSR_SHIFT; 194 195 if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table)) 196 return -EINVAL; 197 198 return mxc4005_scale_table[i].scale; 199 } 200 201 static int mxc4005_set_scale(struct mxc4005_data *data, int val) 202 { 203 unsigned int reg; 204 int i; 205 int ret; 206 207 for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) { 208 if (mxc4005_scale_table[i].scale == val) { 209 reg = i << MXC4005_CONTROL_FSR_SHIFT; 210 ret = regmap_update_bits(data->regmap, 211 MXC4005_REG_CONTROL, 212 MXC4005_REG_CONTROL_MASK_FSR, 213 reg); 214 if (ret < 0) 215 dev_err(data->dev, 216 "failed to write reg_control\n"); 217 return ret; 218 } 219 } 220 221 return -EINVAL; 222 } 223 224 static int mxc4005_read_raw(struct iio_dev *indio_dev, 225 struct iio_chan_spec const *chan, 226 int *val, int *val2, long mask) 227 { 228 struct mxc4005_data *data = iio_priv(indio_dev); 229 int ret; 230 231 switch (mask) { 232 case IIO_CHAN_INFO_RAW: 233 switch (chan->type) { 234 case IIO_ACCEL: 235 if (iio_buffer_enabled(indio_dev)) 236 return -EBUSY; 237 238 ret = mxc4005_read_axis(data, chan->address); 239 if (ret < 0) 240 return ret; 241 *val = sign_extend32(ret >> chan->scan_type.shift, 242 chan->scan_type.realbits - 1); 243 return IIO_VAL_INT; 244 default: 245 return -EINVAL; 246 } 247 case IIO_CHAN_INFO_SCALE: 248 ret = mxc4005_read_scale(data); 249 if (ret < 0) 250 return ret; 251 252 *val = 0; 253 *val2 = ret; 254 return IIO_VAL_INT_PLUS_MICRO; 255 default: 256 return -EINVAL; 257 } 258 } 259 260 static int mxc4005_write_raw(struct iio_dev *indio_dev, 261 struct iio_chan_spec const *chan, 262 int val, int val2, long mask) 263 { 264 struct mxc4005_data *data = iio_priv(indio_dev); 265 266 switch (mask) { 267 case IIO_CHAN_INFO_SCALE: 268 if (val != 0) 269 return -EINVAL; 270 271 return mxc4005_set_scale(data, val2); 272 default: 273 return -EINVAL; 274 } 275 } 276 277 static const struct iio_mount_matrix * 278 mxc4005_get_mount_matrix(const struct iio_dev *indio_dev, 279 const struct iio_chan_spec *chan) 280 { 281 struct mxc4005_data *data = iio_priv(indio_dev); 282 283 return &data->orientation; 284 } 285 286 static const struct iio_chan_spec_ext_info mxc4005_ext_info[] = { 287 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mxc4005_get_mount_matrix), 288 { } 289 }; 290 291 static const struct iio_info mxc4005_info = { 292 .read_raw = mxc4005_read_raw, 293 .write_raw = mxc4005_write_raw, 294 .attrs = &mxc4005_attrs_group, 295 }; 296 297 static const unsigned long mxc4005_scan_masks[] = { 298 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 299 0 300 }; 301 302 #define MXC4005_CHANNEL(_axis, _addr) { \ 303 .type = IIO_ACCEL, \ 304 .modified = 1, \ 305 .channel2 = IIO_MOD_##_axis, \ 306 .address = _addr, \ 307 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 308 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 309 .scan_index = AXIS_##_axis, \ 310 .scan_type = { \ 311 .sign = 's', \ 312 .realbits = 12, \ 313 .storagebits = 16, \ 314 .shift = 4, \ 315 .endianness = IIO_BE, \ 316 }, \ 317 .ext_info = mxc4005_ext_info, \ 318 } 319 320 static const struct iio_chan_spec mxc4005_channels[] = { 321 MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER), 322 MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER), 323 MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER), 324 IIO_CHAN_SOFT_TIMESTAMP(3), 325 }; 326 327 static irqreturn_t mxc4005_trigger_handler(int irq, void *private) 328 { 329 struct iio_poll_func *pf = private; 330 struct iio_dev *indio_dev = pf->indio_dev; 331 struct mxc4005_data *data = iio_priv(indio_dev); 332 int ret; 333 334 ret = mxc4005_read_xyz(data); 335 if (ret < 0) 336 goto err; 337 338 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 339 pf->timestamp); 340 341 err: 342 iio_trigger_notify_done(indio_dev->trig); 343 344 return IRQ_HANDLED; 345 } 346 347 static void mxc4005_clr_intr(struct mxc4005_data *data) 348 { 349 int ret; 350 351 /* clear interrupt */ 352 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 353 MXC4005_REG_INT_CLR1_BIT_DRDYC); 354 if (ret < 0) 355 dev_err(data->dev, "failed to write to reg_int_clr1\n"); 356 } 357 358 static int mxc4005_set_trigger_state(struct iio_trigger *trig, 359 bool state) 360 { 361 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 362 struct mxc4005_data *data = iio_priv(indio_dev); 363 unsigned int val; 364 int ret; 365 366 mutex_lock(&data->mutex); 367 368 val = state ? MXC4005_REG_INT_MASK1_BIT_DRDYE : 0; 369 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, val); 370 if (ret < 0) { 371 mutex_unlock(&data->mutex); 372 dev_err(data->dev, "failed to update reg_int_mask1"); 373 return ret; 374 } 375 376 data->int_mask1 = val; 377 data->trigger_enabled = state; 378 mutex_unlock(&data->mutex); 379 380 return 0; 381 } 382 383 static void mxc4005_trigger_reen(struct iio_trigger *trig) 384 { 385 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 386 struct mxc4005_data *data = iio_priv(indio_dev); 387 388 if (!data->dready_trig) 389 return; 390 391 mxc4005_clr_intr(data); 392 } 393 394 static const struct iio_trigger_ops mxc4005_trigger_ops = { 395 .set_trigger_state = mxc4005_set_trigger_state, 396 .reenable = mxc4005_trigger_reen, 397 }; 398 399 static int mxc4005_chip_init(struct mxc4005_data *data) 400 { 401 int ret; 402 unsigned int reg; 403 404 ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®); 405 if (ret < 0) { 406 dev_err(data->dev, "failed to read chip id\n"); 407 return ret; 408 } 409 410 dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg); 411 412 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 413 MXC4005_REG_INT_CLR1_SW_RST); 414 if (ret < 0) 415 return dev_err_probe(data->dev, ret, "resetting chip\n"); 416 417 fsleep(MXC4005_RESET_TIME_US); 418 419 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0); 420 if (ret < 0) 421 return dev_err_probe(data->dev, ret, "writing INT_MASK0\n"); 422 423 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, 0); 424 if (ret < 0) 425 return dev_err_probe(data->dev, ret, "writing INT_MASK1\n"); 426 427 return 0; 428 } 429 430 static int mxc4005_probe(struct i2c_client *client) 431 { 432 struct mxc4005_data *data; 433 struct iio_dev *indio_dev; 434 struct regmap *regmap; 435 int ret; 436 437 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 438 if (!indio_dev) 439 return -ENOMEM; 440 441 regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config); 442 if (IS_ERR(regmap)) { 443 dev_err(&client->dev, "failed to initialize regmap\n"); 444 return PTR_ERR(regmap); 445 } 446 447 data = iio_priv(indio_dev); 448 i2c_set_clientdata(client, indio_dev); 449 data->dev = &client->dev; 450 data->regmap = regmap; 451 452 ret = mxc4005_chip_init(data); 453 if (ret < 0) { 454 dev_err(&client->dev, "failed to initialize chip\n"); 455 return ret; 456 } 457 458 mutex_init(&data->mutex); 459 460 if (!iio_read_acpi_mount_matrix(&client->dev, &data->orientation, "ROTM")) { 461 ret = iio_read_mount_matrix(&client->dev, &data->orientation); 462 if (ret) 463 return ret; 464 } 465 466 indio_dev->channels = mxc4005_channels; 467 indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels); 468 indio_dev->available_scan_masks = mxc4005_scan_masks; 469 indio_dev->name = MXC4005_DRV_NAME; 470 indio_dev->modes = INDIO_DIRECT_MODE; 471 indio_dev->info = &mxc4005_info; 472 473 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, 474 iio_pollfunc_store_time, 475 mxc4005_trigger_handler, 476 NULL); 477 if (ret < 0) { 478 dev_err(&client->dev, 479 "failed to setup iio triggered buffer\n"); 480 return ret; 481 } 482 483 if (client->irq > 0) { 484 data->dready_trig = devm_iio_trigger_alloc(&client->dev, 485 "%s-dev%d", 486 indio_dev->name, 487 iio_device_id(indio_dev)); 488 if (!data->dready_trig) 489 return -ENOMEM; 490 491 ret = devm_request_threaded_irq(&client->dev, client->irq, 492 iio_trigger_generic_data_rdy_poll, 493 NULL, 494 IRQF_TRIGGER_FALLING | 495 IRQF_ONESHOT, 496 MXC4005_IRQ_NAME, 497 data->dready_trig); 498 if (ret) { 499 dev_err(&client->dev, 500 "failed to init threaded irq\n"); 501 return ret; 502 } 503 504 data->dready_trig->ops = &mxc4005_trigger_ops; 505 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 506 ret = devm_iio_trigger_register(&client->dev, 507 data->dready_trig); 508 if (ret) { 509 dev_err(&client->dev, 510 "failed to register trigger\n"); 511 return ret; 512 } 513 514 indio_dev->trig = iio_trigger_get(data->dready_trig); 515 } 516 517 return devm_iio_device_register(&client->dev, indio_dev); 518 } 519 520 static int mxc4005_suspend(struct device *dev) 521 { 522 struct iio_dev *indio_dev = dev_get_drvdata(dev); 523 struct mxc4005_data *data = iio_priv(indio_dev); 524 int ret; 525 526 /* Save control to restore it on resume */ 527 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &data->control); 528 if (ret < 0) 529 dev_err(data->dev, "failed to read reg_control\n"); 530 531 return ret; 532 } 533 534 static int mxc4005_resume(struct device *dev) 535 { 536 struct iio_dev *indio_dev = dev_get_drvdata(dev); 537 struct mxc4005_data *data = iio_priv(indio_dev); 538 int ret; 539 540 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 541 MXC4005_REG_INT_CLR1_SW_RST); 542 if (ret) { 543 dev_err(data->dev, "failed to reset chip: %d\n", ret); 544 return ret; 545 } 546 547 fsleep(MXC4005_RESET_TIME_US); 548 549 ret = regmap_write(data->regmap, MXC4005_REG_CONTROL, data->control); 550 if (ret) { 551 dev_err(data->dev, "failed to restore control register\n"); 552 return ret; 553 } 554 555 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0); 556 if (ret) { 557 dev_err(data->dev, "failed to restore interrupt 0 mask\n"); 558 return ret; 559 } 560 561 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, data->int_mask1); 562 if (ret) { 563 dev_err(data->dev, "failed to restore interrupt 1 mask\n"); 564 return ret; 565 } 566 567 return 0; 568 } 569 570 static DEFINE_SIMPLE_DEV_PM_OPS(mxc4005_pm_ops, mxc4005_suspend, mxc4005_resume); 571 572 static const struct acpi_device_id mxc4005_acpi_match[] = { 573 {"MXC4005", 0}, 574 {"MXC6655", 0}, 575 {"MDA6655", 0}, 576 { }, 577 }; 578 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match); 579 580 static const struct of_device_id mxc4005_of_match[] = { 581 { .compatible = "memsic,mxc4005", }, 582 { .compatible = "memsic,mxc6655", }, 583 { }, 584 }; 585 MODULE_DEVICE_TABLE(of, mxc4005_of_match); 586 587 static const struct i2c_device_id mxc4005_id[] = { 588 { "mxc4005" }, 589 { "mxc6655" }, 590 { } 591 }; 592 MODULE_DEVICE_TABLE(i2c, mxc4005_id); 593 594 static struct i2c_driver mxc4005_driver = { 595 .driver = { 596 .name = MXC4005_DRV_NAME, 597 .acpi_match_table = mxc4005_acpi_match, 598 .of_match_table = mxc4005_of_match, 599 .pm = pm_sleep_ptr(&mxc4005_pm_ops), 600 }, 601 .probe = mxc4005_probe, 602 .id_table = mxc4005_id, 603 }; 604 605 module_i2c_driver(mxc4005_driver); 606 607 MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>"); 608 MODULE_LICENSE("GPL v2"); 609 MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver"); 610