1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21 #include <linux/module.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/property.h> 24 #include <linux/i2c.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/trigger.h> 29 #include <linux/iio/trigger_consumer.h> 30 #include <linux/iio/triggered_buffer.h> 31 #include <linux/iio/events.h> 32 #include <linux/delay.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/types.h> 36 37 #define MMA8452_STATUS 0x00 38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 39 #define MMA8452_OUT_X 0x01 /* MSB first */ 40 #define MMA8452_OUT_Y 0x03 41 #define MMA8452_OUT_Z 0x05 42 #define MMA8452_INT_SRC 0x0c 43 #define MMA8452_WHO_AM_I 0x0d 44 #define MMA8452_DATA_CFG 0x0e 45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 46 #define MMA8452_DATA_CFG_FS_2G 0 47 #define MMA8452_DATA_CFG_FS_4G 1 48 #define MMA8452_DATA_CFG_FS_8G 2 49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 50 #define MMA8452_HP_FILTER_CUTOFF 0x0f 51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 52 #define MMA8452_FF_MT_CFG 0x15 53 #define MMA8452_FF_MT_CFG_OAE BIT(6) 54 #define MMA8452_FF_MT_CFG_ELE BIT(7) 55 #define MMA8452_FF_MT_SRC 0x16 56 #define MMA8452_FF_MT_SRC_XHE BIT(1) 57 #define MMA8452_FF_MT_SRC_YHE BIT(3) 58 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 59 #define MMA8452_FF_MT_THS 0x17 60 #define MMA8452_FF_MT_THS_MASK 0x7f 61 #define MMA8452_FF_MT_COUNT 0x18 62 #define MMA8452_FF_MT_CHAN_SHIFT 3 63 #define MMA8452_TRANSIENT_CFG 0x1d 64 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 65 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 66 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 67 #define MMA8452_TRANSIENT_SRC 0x1e 68 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 69 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 70 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 71 #define MMA8452_TRANSIENT_THS 0x1f 72 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 73 #define MMA8452_TRANSIENT_COUNT 0x20 74 #define MMA8452_TRANSIENT_CHAN_SHIFT 1 75 #define MMA8452_CTRL_REG1 0x2a 76 #define MMA8452_CTRL_ACTIVE BIT(0) 77 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 78 #define MMA8452_CTRL_DR_SHIFT 3 79 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 80 #define MMA8452_CTRL_REG2 0x2b 81 #define MMA8452_CTRL_REG2_RST BIT(6) 82 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 83 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 84 #define MMA8452_CTRL_REG4 0x2d 85 #define MMA8452_CTRL_REG5 0x2e 86 #define MMA8452_OFF_X 0x2f 87 #define MMA8452_OFF_Y 0x30 88 #define MMA8452_OFF_Z 0x31 89 90 #define MMA8452_MAX_REG 0x31 91 92 #define MMA8452_INT_DRDY BIT(0) 93 #define MMA8452_INT_FF_MT BIT(2) 94 #define MMA8452_INT_TRANS BIT(5) 95 96 #define MMA8451_DEVICE_ID 0x1a 97 #define MMA8452_DEVICE_ID 0x2a 98 #define MMA8453_DEVICE_ID 0x3a 99 #define MMA8652_DEVICE_ID 0x4a 100 #define MMA8653_DEVICE_ID 0x5a 101 #define FXLS8471_DEVICE_ID 0x6a 102 103 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 104 105 struct mma8452_data { 106 struct i2c_client *client; 107 struct mutex lock; 108 struct iio_mount_matrix orientation; 109 u8 ctrl_reg1; 110 u8 data_cfg; 111 const struct mma_chip_info *chip_info; 112 int sleep_val; 113 struct regulator *vdd_reg; 114 struct regulator *vddio_reg; 115 116 /* Ensure correct alignment of time stamp when present */ 117 struct { 118 __be16 channels[3]; 119 aligned_s64 ts; 120 } buffer; 121 }; 122 123 /** 124 * struct mma8452_event_regs - chip specific data related to events 125 * @ev_cfg: event config register address 126 * @ev_cfg_ele: latch bit in event config register 127 * @ev_cfg_chan_shift: number of the bit to enable events in X 128 * direction; in event config register 129 * @ev_src: event source register address 130 * @ev_ths: event threshold register address 131 * @ev_ths_mask: mask for the threshold value 132 * @ev_count: event count (period) register address 133 * 134 * Since not all chips supported by the driver support comparing high pass 135 * filtered data for events (interrupts), different interrupt sources are 136 * used for different chips and the relevant registers are included here. 137 */ 138 struct mma8452_event_regs { 139 u8 ev_cfg; 140 u8 ev_cfg_ele; 141 u8 ev_cfg_chan_shift; 142 u8 ev_src; 143 u8 ev_ths; 144 u8 ev_ths_mask; 145 u8 ev_count; 146 }; 147 148 static const struct mma8452_event_regs ff_mt_ev_regs = { 149 .ev_cfg = MMA8452_FF_MT_CFG, 150 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 151 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 152 .ev_src = MMA8452_FF_MT_SRC, 153 .ev_ths = MMA8452_FF_MT_THS, 154 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 155 .ev_count = MMA8452_FF_MT_COUNT 156 }; 157 158 static const struct mma8452_event_regs trans_ev_regs = { 159 .ev_cfg = MMA8452_TRANSIENT_CFG, 160 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 161 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 162 .ev_src = MMA8452_TRANSIENT_SRC, 163 .ev_ths = MMA8452_TRANSIENT_THS, 164 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 165 .ev_count = MMA8452_TRANSIENT_COUNT, 166 }; 167 168 /** 169 * struct mma_chip_info - chip specific data 170 * @name: part number of device reported via 'name' attr 171 * @chip_id: WHO_AM_I register's value 172 * @channels: struct iio_chan_spec matching the device's 173 * capabilities 174 * @num_channels: number of channels 175 * @mma_scales: scale factors for converting register values 176 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 177 * per mode: m/s^2 and micro m/s^2 178 * @all_events: all events supported by this chip 179 * @enabled_events: event flags enabled and handled by this driver 180 */ 181 struct mma_chip_info { 182 const char *name; 183 u8 chip_id; 184 const struct iio_chan_spec *channels; 185 int num_channels; 186 const int mma_scales[3][2]; 187 int all_events; 188 int enabled_events; 189 }; 190 191 enum { 192 idx_x, 193 idx_y, 194 idx_z, 195 idx_ts, 196 }; 197 198 static int mma8452_drdy(struct mma8452_data *data) 199 { 200 int tries = 150; 201 202 while (tries-- > 0) { 203 int ret = i2c_smbus_read_byte_data(data->client, 204 MMA8452_STATUS); 205 if (ret < 0) 206 return ret; 207 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 208 return 0; 209 210 if (data->sleep_val <= 20) 211 usleep_range(data->sleep_val * 250, 212 data->sleep_val * 500); 213 else 214 msleep(20); 215 } 216 217 dev_err(&data->client->dev, "data not ready\n"); 218 219 return -EIO; 220 } 221 222 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 223 { 224 #ifdef CONFIG_PM 225 int ret; 226 227 if (on) { 228 ret = pm_runtime_resume_and_get(&client->dev); 229 } else { 230 pm_runtime_mark_last_busy(&client->dev); 231 ret = pm_runtime_put_autosuspend(&client->dev); 232 } 233 234 if (ret < 0) { 235 dev_err(&client->dev, 236 "failed to change power state to %d\n", on); 237 238 return ret; 239 } 240 #endif 241 242 return 0; 243 } 244 245 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 246 { 247 int ret = mma8452_drdy(data); 248 249 if (ret < 0) 250 return ret; 251 252 ret = mma8452_set_runtime_pm_state(data->client, true); 253 if (ret) 254 return ret; 255 256 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 257 3 * sizeof(__be16), (u8 *)buf); 258 259 ret = mma8452_set_runtime_pm_state(data->client, false); 260 261 return ret; 262 } 263 264 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 265 int n) 266 { 267 size_t len = 0; 268 269 while (n-- > 0) 270 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 271 vals[n][0], vals[n][1]); 272 273 /* replace trailing space by newline */ 274 buf[len - 1] = '\n'; 275 276 return len; 277 } 278 279 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 280 int val, int val2) 281 { 282 while (n-- > 0) 283 if (val == vals[n][0] && val2 == vals[n][1]) 284 return n; 285 286 return -EINVAL; 287 } 288 289 static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 290 { 291 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 292 MMA8452_CTRL_DR_SHIFT; 293 } 294 295 static const int mma8452_samp_freq[8][2] = { 296 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 297 {6, 250000}, {1, 560000} 298 }; 299 300 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 301 static const unsigned int mma8452_time_step_us[4][8] = { 302 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 303 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 304 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 305 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 306 }; 307 308 /* Datasheet table "High-Pass Filter Cutoff Options" */ 309 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 310 { /* normal */ 311 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 312 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 313 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 314 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 318 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 319 }, 320 { /* low noise low power */ 321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 322 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 323 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 324 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 325 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 327 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 328 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 329 }, 330 { /* high resolution */ 331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 338 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 339 }, 340 { /* low power */ 341 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 342 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 343 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 344 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 345 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 347 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 348 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 349 } 350 }; 351 352 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 353 static const u16 mma8452_os_ratio[4][8] = { 354 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 355 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 356 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 357 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 358 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 359 }; 360 361 static int mma8452_get_power_mode(struct mma8452_data *data) 362 { 363 int reg; 364 365 reg = i2c_smbus_read_byte_data(data->client, 366 MMA8452_CTRL_REG2); 367 if (reg < 0) 368 return reg; 369 370 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 371 MMA8452_CTRL_REG2_MODS_SHIFT); 372 } 373 374 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 375 struct device_attribute *attr, 376 char *buf) 377 { 378 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 379 ARRAY_SIZE(mma8452_samp_freq)); 380 } 381 382 static ssize_t mma8452_show_scale_avail(struct device *dev, 383 struct device_attribute *attr, 384 char *buf) 385 { 386 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 387 struct mma8452_data *data = iio_priv(indio_dev); 388 389 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 390 ARRAY_SIZE(data->chip_info->mma_scales)); 391 } 392 393 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 394 struct device_attribute *attr, 395 char *buf) 396 { 397 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 398 struct mma8452_data *data = iio_priv(indio_dev); 399 int i, j; 400 401 i = mma8452_get_odr_index(data); 402 j = mma8452_get_power_mode(data); 403 if (j < 0) 404 return j; 405 406 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 407 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 408 } 409 410 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 411 struct device_attribute *attr, 412 char *buf) 413 { 414 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 415 struct mma8452_data *data = iio_priv(indio_dev); 416 int i = mma8452_get_odr_index(data); 417 int j; 418 u16 val = 0; 419 size_t len = 0; 420 421 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 422 if (val == mma8452_os_ratio[j][i]) 423 continue; 424 425 val = mma8452_os_ratio[j][i]; 426 427 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 428 } 429 buf[len - 1] = '\n'; 430 431 return len; 432 } 433 434 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 435 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 436 mma8452_show_scale_avail, NULL, 0); 437 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 438 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 439 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 440 mma8452_show_os_ratio_avail, NULL, 0); 441 442 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 443 int val, int val2) 444 { 445 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 446 ARRAY_SIZE(mma8452_samp_freq), 447 val, val2); 448 } 449 450 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 451 { 452 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 453 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 454 } 455 456 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 457 int val, int val2) 458 { 459 int i, j; 460 461 i = mma8452_get_odr_index(data); 462 j = mma8452_get_power_mode(data); 463 if (j < 0) 464 return j; 465 466 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 467 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 468 } 469 470 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 471 { 472 int j, i, ret; 473 474 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 475 if (ret < 0) 476 return ret; 477 478 i = mma8452_get_odr_index(data); 479 j = mma8452_get_power_mode(data); 480 if (j < 0) 481 return j; 482 483 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 484 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 485 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 486 487 return 0; 488 } 489 490 static int mma8452_read_raw(struct iio_dev *indio_dev, 491 struct iio_chan_spec const *chan, 492 int *val, int *val2, long mask) 493 { 494 struct mma8452_data *data = iio_priv(indio_dev); 495 __be16 buffer[3]; 496 int i, ret; 497 498 switch (mask) { 499 case IIO_CHAN_INFO_RAW: 500 if (!iio_device_claim_direct(indio_dev)) 501 return -EBUSY; 502 503 mutex_lock(&data->lock); 504 ret = mma8452_read(data, buffer); 505 mutex_unlock(&data->lock); 506 iio_device_release_direct(indio_dev); 507 if (ret < 0) 508 return ret; 509 510 *val = sign_extend32(be16_to_cpu( 511 buffer[chan->scan_index]) >> chan->scan_type.shift, 512 chan->scan_type.realbits - 1); 513 514 return IIO_VAL_INT; 515 case IIO_CHAN_INFO_SCALE: 516 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 517 *val = data->chip_info->mma_scales[i][0]; 518 *val2 = data->chip_info->mma_scales[i][1]; 519 520 return IIO_VAL_INT_PLUS_MICRO; 521 case IIO_CHAN_INFO_SAMP_FREQ: 522 i = mma8452_get_odr_index(data); 523 *val = mma8452_samp_freq[i][0]; 524 *val2 = mma8452_samp_freq[i][1]; 525 526 return IIO_VAL_INT_PLUS_MICRO; 527 case IIO_CHAN_INFO_CALIBBIAS: 528 ret = i2c_smbus_read_byte_data(data->client, 529 MMA8452_OFF_X + 530 chan->scan_index); 531 if (ret < 0) 532 return ret; 533 534 *val = sign_extend32(ret, 7); 535 536 return IIO_VAL_INT; 537 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 538 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 539 ret = mma8452_read_hp_filter(data, val, val2); 540 if (ret < 0) 541 return ret; 542 } else { 543 *val = 0; 544 *val2 = 0; 545 } 546 547 return IIO_VAL_INT_PLUS_MICRO; 548 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 549 ret = mma8452_get_power_mode(data); 550 if (ret < 0) 551 return ret; 552 553 i = mma8452_get_odr_index(data); 554 555 *val = mma8452_os_ratio[ret][i]; 556 return IIO_VAL_INT; 557 } 558 559 return -EINVAL; 560 } 561 562 static int mma8452_calculate_sleep(struct mma8452_data *data) 563 { 564 int ret, i = mma8452_get_odr_index(data); 565 566 if (mma8452_samp_freq[i][0] > 0) 567 ret = 1000 / mma8452_samp_freq[i][0]; 568 else 569 ret = 1000; 570 571 return ret == 0 ? 1 : ret; 572 } 573 574 static int mma8452_standby(struct mma8452_data *data) 575 { 576 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 577 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 578 } 579 580 static int mma8452_active(struct mma8452_data *data) 581 { 582 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 583 data->ctrl_reg1); 584 } 585 586 /* returns >0 if active, 0 if in standby and <0 on error */ 587 static int mma8452_is_active(struct mma8452_data *data) 588 { 589 int reg; 590 591 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 592 if (reg < 0) 593 return reg; 594 595 return reg & MMA8452_CTRL_ACTIVE; 596 } 597 598 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 599 { 600 int ret; 601 int is_active; 602 603 mutex_lock(&data->lock); 604 605 is_active = mma8452_is_active(data); 606 if (is_active < 0) { 607 ret = is_active; 608 goto fail; 609 } 610 611 /* config can only be changed when in standby */ 612 if (is_active > 0) { 613 ret = mma8452_standby(data); 614 if (ret < 0) 615 goto fail; 616 } 617 618 ret = i2c_smbus_write_byte_data(data->client, reg, val); 619 if (ret < 0) 620 goto fail; 621 622 if (is_active > 0) { 623 ret = mma8452_active(data); 624 if (ret < 0) 625 goto fail; 626 } 627 628 ret = 0; 629 fail: 630 mutex_unlock(&data->lock); 631 632 return ret; 633 } 634 635 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 636 { 637 int reg; 638 639 reg = i2c_smbus_read_byte_data(data->client, 640 MMA8452_CTRL_REG2); 641 if (reg < 0) 642 return reg; 643 644 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 645 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 646 647 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 648 } 649 650 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 651 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 652 { 653 int val; 654 655 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 656 if (val < 0) 657 return val; 658 659 return !(val & MMA8452_FF_MT_CFG_OAE); 660 } 661 662 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 663 { 664 int val; 665 666 if ((state && mma8452_freefall_mode_enabled(data)) || 667 (!state && !(mma8452_freefall_mode_enabled(data)))) 668 return 0; 669 670 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 671 if (val < 0) 672 return val; 673 674 if (state) { 675 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 676 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 677 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 678 val &= ~MMA8452_FF_MT_CFG_OAE; 679 } else { 680 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 681 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 682 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 683 val |= MMA8452_FF_MT_CFG_OAE; 684 } 685 686 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 687 } 688 689 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 690 int val, int val2) 691 { 692 int i, reg; 693 694 i = mma8452_get_hp_filter_index(data, val, val2); 695 if (i < 0) 696 return i; 697 698 reg = i2c_smbus_read_byte_data(data->client, 699 MMA8452_HP_FILTER_CUTOFF); 700 if (reg < 0) 701 return reg; 702 703 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 704 reg |= i; 705 706 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 707 } 708 709 static int __mma8452_write_raw(struct iio_dev *indio_dev, 710 struct iio_chan_spec const *chan, 711 int val, int val2, long mask) 712 { 713 struct mma8452_data *data = iio_priv(indio_dev); 714 int i, j, ret; 715 716 switch (mask) { 717 case IIO_CHAN_INFO_SAMP_FREQ: 718 i = mma8452_get_samp_freq_index(data, val, val2); 719 if (i < 0) 720 return i; 721 722 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 723 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 724 725 data->sleep_val = mma8452_calculate_sleep(data); 726 727 return mma8452_change_config(data, MMA8452_CTRL_REG1, 728 data->ctrl_reg1); 729 730 case IIO_CHAN_INFO_SCALE: 731 i = mma8452_get_scale_index(data, val, val2); 732 if (i < 0) 733 return i; 734 735 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 736 data->data_cfg |= i; 737 738 return mma8452_change_config(data, MMA8452_DATA_CFG, 739 data->data_cfg); 740 741 case IIO_CHAN_INFO_CALIBBIAS: 742 if (val < -128 || val > 127) 743 return -EINVAL; 744 745 return mma8452_change_config(data, 746 MMA8452_OFF_X + chan->scan_index, 747 val); 748 749 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 750 if (val == 0 && val2 == 0) { 751 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 752 } else { 753 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 754 ret = mma8452_set_hp_filter_frequency(data, val, val2); 755 if (ret < 0) 756 return ret; 757 } 758 759 return mma8452_change_config(data, MMA8452_DATA_CFG, 760 data->data_cfg); 761 762 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 763 j = mma8452_get_odr_index(data); 764 765 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 766 if (mma8452_os_ratio[i][j] == val) 767 return mma8452_set_power_mode(data, i); 768 } 769 770 return -EINVAL; 771 772 default: 773 return -EINVAL; 774 } 775 } 776 777 static int mma8452_write_raw(struct iio_dev *indio_dev, 778 struct iio_chan_spec const *chan, 779 int val, int val2, long mask) 780 { 781 int ret; 782 783 if (!iio_device_claim_direct(indio_dev)) 784 return -EBUSY; 785 786 ret = __mma8452_write_raw(indio_dev, chan, val, val2, mask); 787 iio_device_release_direct(indio_dev); 788 return ret; 789 } 790 791 static int mma8452_get_event_regs(struct mma8452_data *data, 792 const struct iio_chan_spec *chan, enum iio_event_direction dir, 793 const struct mma8452_event_regs **ev_reg) 794 { 795 if (!chan) 796 return -EINVAL; 797 798 switch (chan->type) { 799 case IIO_ACCEL: 800 switch (dir) { 801 case IIO_EV_DIR_RISING: 802 if ((data->chip_info->all_events 803 & MMA8452_INT_TRANS) && 804 (data->chip_info->enabled_events 805 & MMA8452_INT_TRANS)) 806 *ev_reg = &trans_ev_regs; 807 else 808 *ev_reg = &ff_mt_ev_regs; 809 return 0; 810 case IIO_EV_DIR_FALLING: 811 *ev_reg = &ff_mt_ev_regs; 812 return 0; 813 default: 814 return -EINVAL; 815 } 816 default: 817 return -EINVAL; 818 } 819 } 820 821 static int mma8452_read_event_value(struct iio_dev *indio_dev, 822 const struct iio_chan_spec *chan, 823 enum iio_event_type type, 824 enum iio_event_direction dir, 825 enum iio_event_info info, 826 int *val, int *val2) 827 { 828 struct mma8452_data *data = iio_priv(indio_dev); 829 int ret, us, power_mode; 830 const struct mma8452_event_regs *ev_regs; 831 832 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 833 if (ret) 834 return ret; 835 836 switch (info) { 837 case IIO_EV_INFO_VALUE: 838 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 839 if (ret < 0) 840 return ret; 841 842 *val = ret & ev_regs->ev_ths_mask; 843 844 return IIO_VAL_INT; 845 846 case IIO_EV_INFO_PERIOD: 847 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 848 if (ret < 0) 849 return ret; 850 851 power_mode = mma8452_get_power_mode(data); 852 if (power_mode < 0) 853 return power_mode; 854 855 us = ret * mma8452_time_step_us[power_mode][ 856 mma8452_get_odr_index(data)]; 857 *val = us / USEC_PER_SEC; 858 *val2 = us % USEC_PER_SEC; 859 860 return IIO_VAL_INT_PLUS_MICRO; 861 862 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 863 ret = i2c_smbus_read_byte_data(data->client, 864 MMA8452_TRANSIENT_CFG); 865 if (ret < 0) 866 return ret; 867 868 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 869 *val = 0; 870 *val2 = 0; 871 } else { 872 ret = mma8452_read_hp_filter(data, val, val2); 873 if (ret < 0) 874 return ret; 875 } 876 877 return IIO_VAL_INT_PLUS_MICRO; 878 879 default: 880 return -EINVAL; 881 } 882 } 883 884 static int mma8452_write_event_value(struct iio_dev *indio_dev, 885 const struct iio_chan_spec *chan, 886 enum iio_event_type type, 887 enum iio_event_direction dir, 888 enum iio_event_info info, 889 int val, int val2) 890 { 891 struct mma8452_data *data = iio_priv(indio_dev); 892 int ret, reg, steps; 893 const struct mma8452_event_regs *ev_regs; 894 895 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 896 if (ret) 897 return ret; 898 899 switch (info) { 900 case IIO_EV_INFO_VALUE: 901 if (val < 0 || val > ev_regs->ev_ths_mask) 902 return -EINVAL; 903 904 return mma8452_change_config(data, ev_regs->ev_ths, val); 905 906 case IIO_EV_INFO_PERIOD: 907 ret = mma8452_get_power_mode(data); 908 if (ret < 0) 909 return ret; 910 911 steps = (val * USEC_PER_SEC + val2) / 912 mma8452_time_step_us[ret][ 913 mma8452_get_odr_index(data)]; 914 915 if (steps < 0 || steps > 0xff) 916 return -EINVAL; 917 918 return mma8452_change_config(data, ev_regs->ev_count, steps); 919 920 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 921 reg = i2c_smbus_read_byte_data(data->client, 922 MMA8452_TRANSIENT_CFG); 923 if (reg < 0) 924 return reg; 925 926 if (val == 0 && val2 == 0) { 927 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 928 } else { 929 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 930 ret = mma8452_set_hp_filter_frequency(data, val, val2); 931 if (ret < 0) 932 return ret; 933 } 934 935 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 936 937 default: 938 return -EINVAL; 939 } 940 } 941 942 static int mma8452_read_event_config(struct iio_dev *indio_dev, 943 const struct iio_chan_spec *chan, 944 enum iio_event_type type, 945 enum iio_event_direction dir) 946 { 947 struct mma8452_data *data = iio_priv(indio_dev); 948 int ret; 949 const struct mma8452_event_regs *ev_regs; 950 951 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 952 if (ret) 953 return ret; 954 955 switch (dir) { 956 case IIO_EV_DIR_FALLING: 957 return mma8452_freefall_mode_enabled(data); 958 case IIO_EV_DIR_RISING: 959 ret = i2c_smbus_read_byte_data(data->client, 960 ev_regs->ev_cfg); 961 if (ret < 0) 962 return ret; 963 964 return !!(ret & BIT(chan->scan_index + 965 ev_regs->ev_cfg_chan_shift)); 966 default: 967 return -EINVAL; 968 } 969 } 970 971 static int mma8452_write_event_config(struct iio_dev *indio_dev, 972 const struct iio_chan_spec *chan, 973 enum iio_event_type type, 974 enum iio_event_direction dir, 975 bool state) 976 { 977 struct mma8452_data *data = iio_priv(indio_dev); 978 int val, ret; 979 const struct mma8452_event_regs *ev_regs; 980 981 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 982 if (ret) 983 return ret; 984 985 ret = mma8452_set_runtime_pm_state(data->client, state); 986 if (ret) 987 return ret; 988 989 switch (dir) { 990 case IIO_EV_DIR_FALLING: 991 return mma8452_set_freefall_mode(data, state); 992 case IIO_EV_DIR_RISING: 993 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 994 if (val < 0) 995 return val; 996 997 if (state) { 998 if (mma8452_freefall_mode_enabled(data)) { 999 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 1000 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 1001 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 1002 val |= MMA8452_FF_MT_CFG_OAE; 1003 } 1004 val |= BIT(chan->scan_index + 1005 ev_regs->ev_cfg_chan_shift); 1006 } else { 1007 if (mma8452_freefall_mode_enabled(data)) 1008 return 0; 1009 1010 val &= ~BIT(chan->scan_index + 1011 ev_regs->ev_cfg_chan_shift); 1012 } 1013 1014 val |= ev_regs->ev_cfg_ele; 1015 1016 return mma8452_change_config(data, ev_regs->ev_cfg, val); 1017 default: 1018 return -EINVAL; 1019 } 1020 } 1021 1022 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 1023 { 1024 struct mma8452_data *data = iio_priv(indio_dev); 1025 s64 ts = iio_get_time_ns(indio_dev); 1026 int src; 1027 1028 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1029 if (src < 0) 1030 return; 1031 1032 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1033 iio_push_event(indio_dev, 1034 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1035 IIO_EV_TYPE_MAG, 1036 IIO_EV_DIR_RISING), 1037 ts); 1038 1039 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1040 iio_push_event(indio_dev, 1041 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1042 IIO_EV_TYPE_MAG, 1043 IIO_EV_DIR_RISING), 1044 ts); 1045 1046 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1047 iio_push_event(indio_dev, 1048 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1049 IIO_EV_TYPE_MAG, 1050 IIO_EV_DIR_RISING), 1051 ts); 1052 } 1053 1054 static irqreturn_t mma8452_interrupt(int irq, void *p) 1055 { 1056 struct iio_dev *indio_dev = p; 1057 struct mma8452_data *data = iio_priv(indio_dev); 1058 irqreturn_t ret = IRQ_NONE; 1059 int src; 1060 1061 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1062 if (src < 0) 1063 return IRQ_NONE; 1064 1065 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY))) 1066 return IRQ_NONE; 1067 1068 if (src & MMA8452_INT_DRDY) { 1069 iio_trigger_poll_nested(indio_dev->trig); 1070 ret = IRQ_HANDLED; 1071 } 1072 1073 if (src & MMA8452_INT_FF_MT) { 1074 if (mma8452_freefall_mode_enabled(data)) { 1075 s64 ts = iio_get_time_ns(indio_dev); 1076 1077 iio_push_event(indio_dev, 1078 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1079 IIO_MOD_X_AND_Y_AND_Z, 1080 IIO_EV_TYPE_MAG, 1081 IIO_EV_DIR_FALLING), 1082 ts); 1083 } 1084 ret = IRQ_HANDLED; 1085 } 1086 1087 if (src & MMA8452_INT_TRANS) { 1088 mma8452_transient_interrupt(indio_dev); 1089 ret = IRQ_HANDLED; 1090 } 1091 1092 return ret; 1093 } 1094 1095 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1096 { 1097 struct iio_poll_func *pf = p; 1098 struct iio_dev *indio_dev = pf->indio_dev; 1099 struct mma8452_data *data = iio_priv(indio_dev); 1100 int ret; 1101 1102 ret = mma8452_read(data, data->buffer.channels); 1103 if (ret < 0) 1104 goto done; 1105 1106 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer, 1107 iio_get_time_ns(indio_dev)); 1108 1109 done: 1110 iio_trigger_notify_done(indio_dev->trig); 1111 1112 return IRQ_HANDLED; 1113 } 1114 1115 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1116 unsigned int reg, unsigned int writeval, 1117 unsigned int *readval) 1118 { 1119 int ret; 1120 struct mma8452_data *data = iio_priv(indio_dev); 1121 1122 if (reg > MMA8452_MAX_REG) 1123 return -EINVAL; 1124 1125 if (!readval) 1126 return mma8452_change_config(data, reg, writeval); 1127 1128 ret = i2c_smbus_read_byte_data(data->client, reg); 1129 if (ret < 0) 1130 return ret; 1131 1132 *readval = ret; 1133 1134 return 0; 1135 } 1136 1137 static const struct iio_event_spec mma8452_freefall_event[] = { 1138 { 1139 .type = IIO_EV_TYPE_MAG, 1140 .dir = IIO_EV_DIR_FALLING, 1141 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1142 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1143 BIT(IIO_EV_INFO_PERIOD) | 1144 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1145 }, 1146 }; 1147 1148 static const struct iio_event_spec mma8652_freefall_event[] = { 1149 { 1150 .type = IIO_EV_TYPE_MAG, 1151 .dir = IIO_EV_DIR_FALLING, 1152 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1153 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1154 BIT(IIO_EV_INFO_PERIOD) 1155 }, 1156 }; 1157 1158 static const struct iio_event_spec mma8452_transient_event[] = { 1159 { 1160 .type = IIO_EV_TYPE_MAG, 1161 .dir = IIO_EV_DIR_RISING, 1162 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1163 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1164 BIT(IIO_EV_INFO_PERIOD) | 1165 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1166 }, 1167 }; 1168 1169 static const struct iio_event_spec mma8452_motion_event[] = { 1170 { 1171 .type = IIO_EV_TYPE_MAG, 1172 .dir = IIO_EV_DIR_RISING, 1173 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1174 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1175 BIT(IIO_EV_INFO_PERIOD) 1176 }, 1177 }; 1178 1179 /* 1180 * Threshold is configured in fixed 8G/127 steps regardless of 1181 * currently selected scale for measurement. 1182 */ 1183 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1184 1185 static struct attribute *mma8452_event_attributes[] = { 1186 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1187 NULL, 1188 }; 1189 1190 static const struct attribute_group mma8452_event_attribute_group = { 1191 .attrs = mma8452_event_attributes, 1192 }; 1193 1194 static const struct iio_mount_matrix * 1195 mma8452_get_mount_matrix(const struct iio_dev *indio_dev, 1196 const struct iio_chan_spec *chan) 1197 { 1198 struct mma8452_data *data = iio_priv(indio_dev); 1199 1200 return &data->orientation; 1201 } 1202 1203 static const struct iio_chan_spec_ext_info mma8452_ext_info[] = { 1204 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mma8452_get_mount_matrix), 1205 { } 1206 }; 1207 1208 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1209 .type = IIO_ACCEL, \ 1210 .modified = 1, \ 1211 .channel2 = modifier, \ 1212 .scan_index = -1, \ 1213 .event_spec = mma8452_freefall_event, \ 1214 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1215 } 1216 1217 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1218 .type = IIO_ACCEL, \ 1219 .modified = 1, \ 1220 .channel2 = modifier, \ 1221 .scan_index = -1, \ 1222 .event_spec = mma8652_freefall_event, \ 1223 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1224 } 1225 1226 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1227 .type = IIO_ACCEL, \ 1228 .modified = 1, \ 1229 .channel2 = IIO_MOD_##axis, \ 1230 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1231 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1232 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1233 BIT(IIO_CHAN_INFO_SCALE) | \ 1234 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1235 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1236 .scan_index = idx, \ 1237 .scan_type = { \ 1238 .sign = 's', \ 1239 .realbits = (bits), \ 1240 .storagebits = 16, \ 1241 .shift = 16 - (bits), \ 1242 .endianness = IIO_BE, \ 1243 }, \ 1244 .event_spec = mma8452_transient_event, \ 1245 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1246 .ext_info = mma8452_ext_info, \ 1247 } 1248 1249 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1250 .type = IIO_ACCEL, \ 1251 .modified = 1, \ 1252 .channel2 = IIO_MOD_##axis, \ 1253 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1254 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1255 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1256 BIT(IIO_CHAN_INFO_SCALE) | \ 1257 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1258 .scan_index = idx, \ 1259 .scan_type = { \ 1260 .sign = 's', \ 1261 .realbits = (bits), \ 1262 .storagebits = 16, \ 1263 .shift = 16 - (bits), \ 1264 .endianness = IIO_BE, \ 1265 }, \ 1266 .event_spec = mma8452_motion_event, \ 1267 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1268 .ext_info = mma8452_ext_info, \ 1269 } 1270 1271 static const struct iio_chan_spec mma8451_channels[] = { 1272 MMA8452_CHANNEL(X, idx_x, 14), 1273 MMA8452_CHANNEL(Y, idx_y, 14), 1274 MMA8452_CHANNEL(Z, idx_z, 14), 1275 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1276 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1277 }; 1278 1279 static const struct iio_chan_spec mma8452_channels[] = { 1280 MMA8452_CHANNEL(X, idx_x, 12), 1281 MMA8452_CHANNEL(Y, idx_y, 12), 1282 MMA8452_CHANNEL(Z, idx_z, 12), 1283 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1284 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1285 }; 1286 1287 static const struct iio_chan_spec mma8453_channels[] = { 1288 MMA8452_CHANNEL(X, idx_x, 10), 1289 MMA8452_CHANNEL(Y, idx_y, 10), 1290 MMA8452_CHANNEL(Z, idx_z, 10), 1291 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1292 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1293 }; 1294 1295 static const struct iio_chan_spec mma8652_channels[] = { 1296 MMA8652_CHANNEL(X, idx_x, 12), 1297 MMA8652_CHANNEL(Y, idx_y, 12), 1298 MMA8652_CHANNEL(Z, idx_z, 12), 1299 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1300 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1301 }; 1302 1303 static const struct iio_chan_spec mma8653_channels[] = { 1304 MMA8652_CHANNEL(X, idx_x, 10), 1305 MMA8652_CHANNEL(Y, idx_y, 10), 1306 MMA8652_CHANNEL(Z, idx_z, 10), 1307 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1308 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1309 }; 1310 1311 enum { 1312 mma8451, 1313 mma8452, 1314 mma8453, 1315 mma8652, 1316 mma8653, 1317 fxls8471, 1318 }; 1319 1320 static const struct mma_chip_info mma_chip_info_table[] = { 1321 [mma8451] = { 1322 .name = "mma8451", 1323 .chip_id = MMA8451_DEVICE_ID, 1324 .channels = mma8451_channels, 1325 .num_channels = ARRAY_SIZE(mma8451_channels), 1326 /* 1327 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1328 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1329 * bit. 1330 * The userspace interface uses m/s^2 and we declare micro units 1331 * So scale factor for 12 bit here is given by: 1332 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1333 */ 1334 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1335 /* 1336 * Although we enable the interrupt sources once and for 1337 * all here the event detection itself is not enabled until 1338 * userspace asks for it by mma8452_write_event_config() 1339 */ 1340 .all_events = MMA8452_INT_DRDY | 1341 MMA8452_INT_TRANS | 1342 MMA8452_INT_FF_MT, 1343 .enabled_events = MMA8452_INT_TRANS | 1344 MMA8452_INT_FF_MT, 1345 }, 1346 [mma8452] = { 1347 .name = "mma8452", 1348 .chip_id = MMA8452_DEVICE_ID, 1349 .channels = mma8452_channels, 1350 .num_channels = ARRAY_SIZE(mma8452_channels), 1351 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1352 /* 1353 * Although we enable the interrupt sources once and for 1354 * all here the event detection itself is not enabled until 1355 * userspace asks for it by mma8452_write_event_config() 1356 */ 1357 .all_events = MMA8452_INT_DRDY | 1358 MMA8452_INT_TRANS | 1359 MMA8452_INT_FF_MT, 1360 .enabled_events = MMA8452_INT_TRANS | 1361 MMA8452_INT_FF_MT, 1362 }, 1363 [mma8453] = { 1364 .name = "mma8453", 1365 .chip_id = MMA8453_DEVICE_ID, 1366 .channels = mma8453_channels, 1367 .num_channels = ARRAY_SIZE(mma8453_channels), 1368 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1369 /* 1370 * Although we enable the interrupt sources once and for 1371 * all here the event detection itself is not enabled until 1372 * userspace asks for it by mma8452_write_event_config() 1373 */ 1374 .all_events = MMA8452_INT_DRDY | 1375 MMA8452_INT_TRANS | 1376 MMA8452_INT_FF_MT, 1377 .enabled_events = MMA8452_INT_TRANS | 1378 MMA8452_INT_FF_MT, 1379 }, 1380 [mma8652] = { 1381 .name = "mma8652", 1382 .chip_id = MMA8652_DEVICE_ID, 1383 .channels = mma8652_channels, 1384 .num_channels = ARRAY_SIZE(mma8652_channels), 1385 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1386 .all_events = MMA8452_INT_DRDY | 1387 MMA8452_INT_FF_MT, 1388 .enabled_events = MMA8452_INT_FF_MT, 1389 }, 1390 [mma8653] = { 1391 .name = "mma8653", 1392 .chip_id = MMA8653_DEVICE_ID, 1393 .channels = mma8653_channels, 1394 .num_channels = ARRAY_SIZE(mma8653_channels), 1395 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1396 /* 1397 * Although we enable the interrupt sources once and for 1398 * all here the event detection itself is not enabled until 1399 * userspace asks for it by mma8452_write_event_config() 1400 */ 1401 .all_events = MMA8452_INT_DRDY | 1402 MMA8452_INT_FF_MT, 1403 .enabled_events = MMA8452_INT_FF_MT, 1404 }, 1405 [fxls8471] = { 1406 .name = "fxls8471", 1407 .chip_id = FXLS8471_DEVICE_ID, 1408 .channels = mma8451_channels, 1409 .num_channels = ARRAY_SIZE(mma8451_channels), 1410 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1411 /* 1412 * Although we enable the interrupt sources once and for 1413 * all here the event detection itself is not enabled until 1414 * userspace asks for it by mma8452_write_event_config() 1415 */ 1416 .all_events = MMA8452_INT_DRDY | 1417 MMA8452_INT_TRANS | 1418 MMA8452_INT_FF_MT, 1419 .enabled_events = MMA8452_INT_TRANS | 1420 MMA8452_INT_FF_MT, 1421 }, 1422 }; 1423 1424 static struct attribute *mma8452_attributes[] = { 1425 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1426 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1427 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1428 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1429 NULL 1430 }; 1431 1432 static const struct attribute_group mma8452_group = { 1433 .attrs = mma8452_attributes, 1434 }; 1435 1436 static const struct iio_info mma8452_info = { 1437 .attrs = &mma8452_group, 1438 .read_raw = &mma8452_read_raw, 1439 .write_raw = &mma8452_write_raw, 1440 .event_attrs = &mma8452_event_attribute_group, 1441 .read_event_value = &mma8452_read_event_value, 1442 .write_event_value = &mma8452_write_event_value, 1443 .read_event_config = &mma8452_read_event_config, 1444 .write_event_config = &mma8452_write_event_config, 1445 .debugfs_reg_access = &mma8452_reg_access_dbg, 1446 }; 1447 1448 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1449 1450 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1451 bool state) 1452 { 1453 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1454 struct mma8452_data *data = iio_priv(indio_dev); 1455 int reg, ret; 1456 1457 ret = mma8452_set_runtime_pm_state(data->client, state); 1458 if (ret) 1459 return ret; 1460 1461 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1462 if (reg < 0) 1463 return reg; 1464 1465 if (state) 1466 reg |= MMA8452_INT_DRDY; 1467 else 1468 reg &= ~MMA8452_INT_DRDY; 1469 1470 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1471 } 1472 1473 static const struct iio_trigger_ops mma8452_trigger_ops = { 1474 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1475 .validate_device = iio_trigger_validate_own_device, 1476 }; 1477 1478 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1479 { 1480 struct mma8452_data *data = iio_priv(indio_dev); 1481 struct iio_trigger *trig; 1482 int ret; 1483 1484 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1485 indio_dev->name, 1486 iio_device_id(indio_dev)); 1487 if (!trig) 1488 return -ENOMEM; 1489 1490 trig->ops = &mma8452_trigger_ops; 1491 iio_trigger_set_drvdata(trig, indio_dev); 1492 1493 ret = iio_trigger_register(trig); 1494 if (ret) 1495 return ret; 1496 1497 indio_dev->trig = iio_trigger_get(trig); 1498 1499 return 0; 1500 } 1501 1502 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1503 { 1504 if (indio_dev->trig) 1505 iio_trigger_unregister(indio_dev->trig); 1506 } 1507 1508 static int mma8452_reset(struct i2c_client *client) 1509 { 1510 int i; 1511 int ret; 1512 1513 /* 1514 * Find on fxls8471, after config reset bit, it reset immediately, 1515 * and will not give ACK, so here do not check the return value. 1516 * The following code will read the reset register, and check whether 1517 * this reset works. 1518 */ 1519 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1520 MMA8452_CTRL_REG2_RST); 1521 1522 for (i = 0; i < 10; i++) { 1523 usleep_range(100, 200); 1524 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1525 if (ret == -EIO) 1526 continue; /* I2C comm reset */ 1527 if (ret < 0) 1528 return ret; 1529 if (!(ret & MMA8452_CTRL_REG2_RST)) 1530 return 0; 1531 } 1532 1533 return -ETIMEDOUT; 1534 } 1535 1536 static const struct of_device_id mma8452_dt_ids[] = { 1537 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1538 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1539 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1540 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1541 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1542 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1543 { } 1544 }; 1545 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1546 1547 static int mma8452_probe(struct i2c_client *client) 1548 { 1549 struct mma8452_data *data; 1550 struct iio_dev *indio_dev; 1551 int ret; 1552 1553 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1554 if (!indio_dev) 1555 return -ENOMEM; 1556 1557 data = iio_priv(indio_dev); 1558 data->client = client; 1559 mutex_init(&data->lock); 1560 1561 data->chip_info = i2c_get_match_data(client); 1562 if (!data->chip_info) 1563 return dev_err_probe(&client->dev, -ENODEV, 1564 "unknown device model\n"); 1565 1566 ret = iio_read_mount_matrix(&client->dev, &data->orientation); 1567 if (ret) 1568 return ret; 1569 1570 data->vdd_reg = devm_regulator_get(&client->dev, "vdd"); 1571 if (IS_ERR(data->vdd_reg)) 1572 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg), 1573 "failed to get VDD regulator!\n"); 1574 1575 data->vddio_reg = devm_regulator_get(&client->dev, "vddio"); 1576 if (IS_ERR(data->vddio_reg)) 1577 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg), 1578 "failed to get VDDIO regulator!\n"); 1579 1580 ret = regulator_enable(data->vdd_reg); 1581 if (ret) { 1582 dev_err(&client->dev, "failed to enable VDD regulator!\n"); 1583 return ret; 1584 } 1585 1586 ret = regulator_enable(data->vddio_reg); 1587 if (ret) { 1588 dev_err(&client->dev, "failed to enable VDDIO regulator!\n"); 1589 goto disable_regulator_vdd; 1590 } 1591 1592 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1593 if (ret < 0) 1594 goto disable_regulators; 1595 1596 switch (ret) { 1597 case MMA8451_DEVICE_ID: 1598 case MMA8452_DEVICE_ID: 1599 case MMA8453_DEVICE_ID: 1600 case MMA8652_DEVICE_ID: 1601 case MMA8653_DEVICE_ID: 1602 case FXLS8471_DEVICE_ID: 1603 if (ret == data->chip_info->chip_id) 1604 break; 1605 fallthrough; 1606 default: 1607 ret = -ENODEV; 1608 goto disable_regulators; 1609 } 1610 1611 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1612 data->chip_info->name, data->chip_info->chip_id); 1613 1614 i2c_set_clientdata(client, indio_dev); 1615 indio_dev->info = &mma8452_info; 1616 indio_dev->name = data->chip_info->name; 1617 indio_dev->modes = INDIO_DIRECT_MODE; 1618 indio_dev->channels = data->chip_info->channels; 1619 indio_dev->num_channels = data->chip_info->num_channels; 1620 indio_dev->available_scan_masks = mma8452_scan_masks; 1621 1622 ret = mma8452_reset(client); 1623 if (ret < 0) 1624 goto disable_regulators; 1625 1626 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1627 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1628 data->data_cfg); 1629 if (ret < 0) 1630 goto disable_regulators; 1631 1632 /* 1633 * By default set transient threshold to max to avoid events if 1634 * enabling without configuring threshold. 1635 */ 1636 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1637 MMA8452_TRANSIENT_THS_MASK); 1638 if (ret < 0) 1639 goto disable_regulators; 1640 1641 if (client->irq) { 1642 int irq2; 1643 1644 irq2 = fwnode_irq_get_byname(dev_fwnode(&client->dev), "INT2"); 1645 1646 if (irq2 == client->irq) { 1647 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1648 } else { 1649 ret = i2c_smbus_write_byte_data(client, 1650 MMA8452_CTRL_REG5, 1651 data->chip_info->all_events); 1652 if (ret < 0) 1653 goto disable_regulators; 1654 1655 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1656 } 1657 1658 ret = i2c_smbus_write_byte_data(client, 1659 MMA8452_CTRL_REG4, 1660 data->chip_info->enabled_events); 1661 if (ret < 0) 1662 goto disable_regulators; 1663 1664 ret = mma8452_trigger_setup(indio_dev); 1665 if (ret < 0) 1666 goto disable_regulators; 1667 } 1668 1669 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1670 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1671 1672 data->sleep_val = mma8452_calculate_sleep(data); 1673 1674 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1675 data->ctrl_reg1); 1676 if (ret < 0) 1677 goto trigger_cleanup; 1678 1679 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1680 mma8452_trigger_handler, NULL); 1681 if (ret < 0) 1682 goto trigger_cleanup; 1683 1684 if (client->irq) { 1685 ret = devm_request_threaded_irq(&client->dev, 1686 client->irq, 1687 NULL, mma8452_interrupt, 1688 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1689 client->name, indio_dev); 1690 if (ret) 1691 goto buffer_cleanup; 1692 } 1693 1694 ret = pm_runtime_set_active(&client->dev); 1695 if (ret < 0) 1696 goto buffer_cleanup; 1697 1698 pm_runtime_enable(&client->dev); 1699 pm_runtime_set_autosuspend_delay(&client->dev, 1700 MMA8452_AUTO_SUSPEND_DELAY_MS); 1701 pm_runtime_use_autosuspend(&client->dev); 1702 1703 ret = iio_device_register(indio_dev); 1704 if (ret < 0) 1705 goto buffer_cleanup; 1706 1707 ret = mma8452_set_freefall_mode(data, false); 1708 if (ret < 0) 1709 goto unregister_device; 1710 1711 return 0; 1712 1713 unregister_device: 1714 iio_device_unregister(indio_dev); 1715 1716 buffer_cleanup: 1717 iio_triggered_buffer_cleanup(indio_dev); 1718 1719 trigger_cleanup: 1720 mma8452_trigger_cleanup(indio_dev); 1721 1722 disable_regulators: 1723 regulator_disable(data->vddio_reg); 1724 1725 disable_regulator_vdd: 1726 regulator_disable(data->vdd_reg); 1727 1728 return ret; 1729 } 1730 1731 static void mma8452_remove(struct i2c_client *client) 1732 { 1733 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1734 struct mma8452_data *data = iio_priv(indio_dev); 1735 1736 iio_device_unregister(indio_dev); 1737 1738 pm_runtime_disable(&client->dev); 1739 pm_runtime_set_suspended(&client->dev); 1740 1741 iio_triggered_buffer_cleanup(indio_dev); 1742 mma8452_trigger_cleanup(indio_dev); 1743 mma8452_standby(iio_priv(indio_dev)); 1744 1745 regulator_disable(data->vddio_reg); 1746 regulator_disable(data->vdd_reg); 1747 } 1748 1749 #ifdef CONFIG_PM 1750 static int mma8452_runtime_suspend(struct device *dev) 1751 { 1752 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1753 struct mma8452_data *data = iio_priv(indio_dev); 1754 int ret; 1755 1756 mutex_lock(&data->lock); 1757 ret = mma8452_standby(data); 1758 mutex_unlock(&data->lock); 1759 if (ret < 0) { 1760 dev_err(&data->client->dev, "powering off device failed\n"); 1761 return -EAGAIN; 1762 } 1763 1764 ret = regulator_disable(data->vddio_reg); 1765 if (ret) { 1766 dev_err(dev, "failed to disable VDDIO regulator\n"); 1767 return ret; 1768 } 1769 1770 ret = regulator_disable(data->vdd_reg); 1771 if (ret) { 1772 dev_err(dev, "failed to disable VDD regulator\n"); 1773 return ret; 1774 } 1775 1776 return 0; 1777 } 1778 1779 static int mma8452_runtime_resume(struct device *dev) 1780 { 1781 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1782 struct mma8452_data *data = iio_priv(indio_dev); 1783 int ret, sleep_val; 1784 1785 ret = regulator_enable(data->vdd_reg); 1786 if (ret) { 1787 dev_err(dev, "failed to enable VDD regulator\n"); 1788 return ret; 1789 } 1790 1791 ret = regulator_enable(data->vddio_reg); 1792 if (ret) { 1793 dev_err(dev, "failed to enable VDDIO regulator\n"); 1794 regulator_disable(data->vdd_reg); 1795 return ret; 1796 } 1797 1798 ret = mma8452_active(data); 1799 if (ret < 0) 1800 goto runtime_resume_failed; 1801 1802 ret = mma8452_get_odr_index(data); 1803 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1804 if (sleep_val < 20) 1805 usleep_range(sleep_val * 1000, 20000); 1806 else 1807 msleep_interruptible(sleep_val); 1808 1809 return 0; 1810 1811 runtime_resume_failed: 1812 regulator_disable(data->vddio_reg); 1813 regulator_disable(data->vdd_reg); 1814 1815 return ret; 1816 } 1817 #endif 1818 1819 static const struct dev_pm_ops mma8452_pm_ops = { 1820 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1821 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1822 mma8452_runtime_resume, NULL) 1823 }; 1824 1825 static const struct i2c_device_id mma8452_id[] = { 1826 { "fxls8471", (kernel_ulong_t)&mma_chip_info_table[fxls8471] }, 1827 { "mma8451", (kernel_ulong_t)&mma_chip_info_table[mma8451] }, 1828 { "mma8452", (kernel_ulong_t)&mma_chip_info_table[mma8452] }, 1829 { "mma8453", (kernel_ulong_t)&mma_chip_info_table[mma8453] }, 1830 { "mma8652", (kernel_ulong_t)&mma_chip_info_table[mma8652] }, 1831 { "mma8653", (kernel_ulong_t)&mma_chip_info_table[mma8653] }, 1832 { } 1833 }; 1834 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1835 1836 static struct i2c_driver mma8452_driver = { 1837 .driver = { 1838 .name = "mma8452", 1839 .of_match_table = mma8452_dt_ids, 1840 .pm = &mma8452_pm_ops, 1841 }, 1842 .probe = mma8452_probe, 1843 .remove = mma8452_remove, 1844 .id_table = mma8452_id, 1845 }; 1846 module_i2c_driver(mma8452_driver); 1847 1848 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1849 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1850 MODULE_LICENSE("GPL"); 1851