1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21 #include <linux/module.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/property.h> 24 #include <linux/i2c.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/trigger.h> 29 #include <linux/iio/trigger_consumer.h> 30 #include <linux/iio/triggered_buffer.h> 31 #include <linux/iio/events.h> 32 #include <linux/delay.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/types.h> 36 37 #define MMA8452_STATUS 0x00 38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 39 #define MMA8452_OUT_X 0x01 /* MSB first */ 40 #define MMA8452_OUT_Y 0x03 41 #define MMA8452_OUT_Z 0x05 42 #define MMA8452_INT_SRC 0x0c 43 #define MMA8452_WHO_AM_I 0x0d 44 #define MMA8452_DATA_CFG 0x0e 45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 46 #define MMA8452_DATA_CFG_FS_2G 0 47 #define MMA8452_DATA_CFG_FS_4G 1 48 #define MMA8452_DATA_CFG_FS_8G 2 49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 50 #define MMA8452_HP_FILTER_CUTOFF 0x0f 51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 52 #define MMA8452_FF_MT_CFG 0x15 53 #define MMA8452_FF_MT_CFG_OAE BIT(6) 54 #define MMA8452_FF_MT_CFG_ELE BIT(7) 55 #define MMA8452_FF_MT_SRC 0x16 56 #define MMA8452_FF_MT_SRC_XHE BIT(1) 57 #define MMA8452_FF_MT_SRC_YHE BIT(3) 58 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 59 #define MMA8452_FF_MT_THS 0x17 60 #define MMA8452_FF_MT_THS_MASK 0x7f 61 #define MMA8452_FF_MT_COUNT 0x18 62 #define MMA8452_FF_MT_CHAN_SHIFT 3 63 #define MMA8452_TRANSIENT_CFG 0x1d 64 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 65 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 66 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 67 #define MMA8452_TRANSIENT_SRC 0x1e 68 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 69 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 70 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 71 #define MMA8452_TRANSIENT_THS 0x1f 72 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 73 #define MMA8452_TRANSIENT_COUNT 0x20 74 #define MMA8452_TRANSIENT_CHAN_SHIFT 1 75 #define MMA8452_CTRL_REG1 0x2a 76 #define MMA8452_CTRL_ACTIVE BIT(0) 77 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 78 #define MMA8452_CTRL_DR_SHIFT 3 79 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 80 #define MMA8452_CTRL_REG2 0x2b 81 #define MMA8452_CTRL_REG2_RST BIT(6) 82 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 83 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 84 #define MMA8452_CTRL_REG4 0x2d 85 #define MMA8452_CTRL_REG5 0x2e 86 #define MMA8452_OFF_X 0x2f 87 #define MMA8452_OFF_Y 0x30 88 #define MMA8452_OFF_Z 0x31 89 90 #define MMA8452_MAX_REG 0x31 91 92 #define MMA8452_INT_DRDY BIT(0) 93 #define MMA8452_INT_FF_MT BIT(2) 94 #define MMA8452_INT_TRANS BIT(5) 95 96 #define MMA8451_DEVICE_ID 0x1a 97 #define MMA8452_DEVICE_ID 0x2a 98 #define MMA8453_DEVICE_ID 0x3a 99 #define MMA8652_DEVICE_ID 0x4a 100 #define MMA8653_DEVICE_ID 0x5a 101 #define FXLS8471_DEVICE_ID 0x6a 102 103 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 104 105 struct mma8452_data { 106 struct i2c_client *client; 107 struct mutex lock; 108 struct iio_mount_matrix orientation; 109 u8 ctrl_reg1; 110 u8 data_cfg; 111 const struct mma_chip_info *chip_info; 112 int sleep_val; 113 struct regulator *vdd_reg; 114 struct regulator *vddio_reg; 115 116 /* Ensure correct alignment of time stamp when present */ 117 struct { 118 __be16 channels[3]; 119 aligned_s64 ts; 120 } buffer; 121 }; 122 123 /** 124 * struct mma8452_event_regs - chip specific data related to events 125 * @ev_cfg: event config register address 126 * @ev_cfg_ele: latch bit in event config register 127 * @ev_cfg_chan_shift: number of the bit to enable events in X 128 * direction; in event config register 129 * @ev_src: event source register address 130 * @ev_ths: event threshold register address 131 * @ev_ths_mask: mask for the threshold value 132 * @ev_count: event count (period) register address 133 * 134 * Since not all chips supported by the driver support comparing high pass 135 * filtered data for events (interrupts), different interrupt sources are 136 * used for different chips and the relevant registers are included here. 137 */ 138 struct mma8452_event_regs { 139 u8 ev_cfg; 140 u8 ev_cfg_ele; 141 u8 ev_cfg_chan_shift; 142 u8 ev_src; 143 u8 ev_ths; 144 u8 ev_ths_mask; 145 u8 ev_count; 146 }; 147 148 static const struct mma8452_event_regs ff_mt_ev_regs = { 149 .ev_cfg = MMA8452_FF_MT_CFG, 150 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 151 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 152 .ev_src = MMA8452_FF_MT_SRC, 153 .ev_ths = MMA8452_FF_MT_THS, 154 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 155 .ev_count = MMA8452_FF_MT_COUNT 156 }; 157 158 static const struct mma8452_event_regs trans_ev_regs = { 159 .ev_cfg = MMA8452_TRANSIENT_CFG, 160 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 161 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 162 .ev_src = MMA8452_TRANSIENT_SRC, 163 .ev_ths = MMA8452_TRANSIENT_THS, 164 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 165 .ev_count = MMA8452_TRANSIENT_COUNT, 166 }; 167 168 /** 169 * struct mma_chip_info - chip specific data 170 * @name: part number of device reported via 'name' attr 171 * @chip_id: WHO_AM_I register's value 172 * @channels: struct iio_chan_spec matching the device's 173 * capabilities 174 * @num_channels: number of channels 175 * @mma_scales: scale factors for converting register values 176 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 177 * per mode: m/s^2 and micro m/s^2 178 * @all_events: all events supported by this chip 179 * @enabled_events: event flags enabled and handled by this driver 180 */ 181 struct mma_chip_info { 182 const char *name; 183 u8 chip_id; 184 const struct iio_chan_spec *channels; 185 int num_channels; 186 const int mma_scales[3][2]; 187 int all_events; 188 int enabled_events; 189 }; 190 191 enum { 192 idx_x, 193 idx_y, 194 idx_z, 195 idx_ts, 196 }; 197 198 static int mma8452_drdy(struct mma8452_data *data) 199 { 200 int tries = 150; 201 202 while (tries-- > 0) { 203 int ret = i2c_smbus_read_byte_data(data->client, 204 MMA8452_STATUS); 205 if (ret < 0) 206 return ret; 207 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 208 return 0; 209 210 if (data->sleep_val <= 20) 211 usleep_range(data->sleep_val * 250, 212 data->sleep_val * 500); 213 else 214 msleep(20); 215 } 216 217 dev_err(&data->client->dev, "data not ready\n"); 218 219 return -EIO; 220 } 221 222 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 223 { 224 #ifdef CONFIG_PM 225 int ret; 226 227 if (on) { 228 ret = pm_runtime_resume_and_get(&client->dev); 229 } else { 230 pm_runtime_mark_last_busy(&client->dev); 231 ret = pm_runtime_put_autosuspend(&client->dev); 232 } 233 234 if (ret < 0) { 235 dev_err(&client->dev, 236 "failed to change power state to %d\n", on); 237 238 return ret; 239 } 240 #endif 241 242 return 0; 243 } 244 245 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 246 { 247 int ret = mma8452_drdy(data); 248 249 if (ret < 0) 250 return ret; 251 252 ret = mma8452_set_runtime_pm_state(data->client, true); 253 if (ret) 254 return ret; 255 256 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 257 3 * sizeof(__be16), (u8 *)buf); 258 259 ret = mma8452_set_runtime_pm_state(data->client, false); 260 261 return ret; 262 } 263 264 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 265 int n) 266 { 267 size_t len = 0; 268 269 while (n-- > 0) 270 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 271 vals[n][0], vals[n][1]); 272 273 /* replace trailing space by newline */ 274 buf[len - 1] = '\n'; 275 276 return len; 277 } 278 279 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 280 int val, int val2) 281 { 282 while (n-- > 0) 283 if (val == vals[n][0] && val2 == vals[n][1]) 284 return n; 285 286 return -EINVAL; 287 } 288 289 static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 290 { 291 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 292 MMA8452_CTRL_DR_SHIFT; 293 } 294 295 static const int mma8452_samp_freq[8][2] = { 296 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 297 {6, 250000}, {1, 560000} 298 }; 299 300 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 301 static const unsigned int mma8452_time_step_us[4][8] = { 302 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 303 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 304 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 305 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 306 }; 307 308 /* Datasheet table "High-Pass Filter Cutoff Options" */ 309 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 310 { /* normal */ 311 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 312 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 313 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 314 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 318 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 319 }, 320 { /* low noise low power */ 321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 322 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 323 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 324 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 325 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 327 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 328 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 329 }, 330 { /* high resolution */ 331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 338 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 339 }, 340 { /* low power */ 341 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 342 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 343 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 344 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 345 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 347 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 348 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 349 } 350 }; 351 352 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 353 static const u16 mma8452_os_ratio[4][8] = { 354 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 355 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 356 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 357 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 358 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 359 }; 360 361 static int mma8452_get_power_mode(struct mma8452_data *data) 362 { 363 int reg; 364 365 reg = i2c_smbus_read_byte_data(data->client, 366 MMA8452_CTRL_REG2); 367 if (reg < 0) 368 return reg; 369 370 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 371 MMA8452_CTRL_REG2_MODS_SHIFT); 372 } 373 374 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 375 struct device_attribute *attr, 376 char *buf) 377 { 378 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 379 ARRAY_SIZE(mma8452_samp_freq)); 380 } 381 382 static ssize_t mma8452_show_scale_avail(struct device *dev, 383 struct device_attribute *attr, 384 char *buf) 385 { 386 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 387 struct mma8452_data *data = iio_priv(indio_dev); 388 389 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 390 ARRAY_SIZE(data->chip_info->mma_scales)); 391 } 392 393 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 394 struct device_attribute *attr, 395 char *buf) 396 { 397 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 398 struct mma8452_data *data = iio_priv(indio_dev); 399 int i, j; 400 401 i = mma8452_get_odr_index(data); 402 j = mma8452_get_power_mode(data); 403 if (j < 0) 404 return j; 405 406 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 407 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 408 } 409 410 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 411 struct device_attribute *attr, 412 char *buf) 413 { 414 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 415 struct mma8452_data *data = iio_priv(indio_dev); 416 int i = mma8452_get_odr_index(data); 417 int j; 418 u16 val = 0; 419 size_t len = 0; 420 421 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 422 if (val == mma8452_os_ratio[j][i]) 423 continue; 424 425 val = mma8452_os_ratio[j][i]; 426 427 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 428 } 429 buf[len - 1] = '\n'; 430 431 return len; 432 } 433 434 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 435 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 436 mma8452_show_scale_avail, NULL, 0); 437 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 438 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 439 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 440 mma8452_show_os_ratio_avail, NULL, 0); 441 442 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 443 int val, int val2) 444 { 445 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 446 ARRAY_SIZE(mma8452_samp_freq), 447 val, val2); 448 } 449 450 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 451 { 452 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 453 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 454 } 455 456 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 457 int val, int val2) 458 { 459 int i, j; 460 461 i = mma8452_get_odr_index(data); 462 j = mma8452_get_power_mode(data); 463 if (j < 0) 464 return j; 465 466 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 467 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 468 } 469 470 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 471 { 472 int j, i, ret; 473 474 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 475 if (ret < 0) 476 return ret; 477 478 i = mma8452_get_odr_index(data); 479 j = mma8452_get_power_mode(data); 480 if (j < 0) 481 return j; 482 483 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 484 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 485 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 486 487 return 0; 488 } 489 490 static int mma8452_read_raw(struct iio_dev *indio_dev, 491 struct iio_chan_spec const *chan, 492 int *val, int *val2, long mask) 493 { 494 struct mma8452_data *data = iio_priv(indio_dev); 495 __be16 buffer[3]; 496 int i, ret; 497 498 switch (mask) { 499 case IIO_CHAN_INFO_RAW: 500 ret = iio_device_claim_direct_mode(indio_dev); 501 if (ret) 502 return ret; 503 504 mutex_lock(&data->lock); 505 ret = mma8452_read(data, buffer); 506 mutex_unlock(&data->lock); 507 iio_device_release_direct_mode(indio_dev); 508 if (ret < 0) 509 return ret; 510 511 *val = sign_extend32(be16_to_cpu( 512 buffer[chan->scan_index]) >> chan->scan_type.shift, 513 chan->scan_type.realbits - 1); 514 515 return IIO_VAL_INT; 516 case IIO_CHAN_INFO_SCALE: 517 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 518 *val = data->chip_info->mma_scales[i][0]; 519 *val2 = data->chip_info->mma_scales[i][1]; 520 521 return IIO_VAL_INT_PLUS_MICRO; 522 case IIO_CHAN_INFO_SAMP_FREQ: 523 i = mma8452_get_odr_index(data); 524 *val = mma8452_samp_freq[i][0]; 525 *val2 = mma8452_samp_freq[i][1]; 526 527 return IIO_VAL_INT_PLUS_MICRO; 528 case IIO_CHAN_INFO_CALIBBIAS: 529 ret = i2c_smbus_read_byte_data(data->client, 530 MMA8452_OFF_X + 531 chan->scan_index); 532 if (ret < 0) 533 return ret; 534 535 *val = sign_extend32(ret, 7); 536 537 return IIO_VAL_INT; 538 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 539 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 540 ret = mma8452_read_hp_filter(data, val, val2); 541 if (ret < 0) 542 return ret; 543 } else { 544 *val = 0; 545 *val2 = 0; 546 } 547 548 return IIO_VAL_INT_PLUS_MICRO; 549 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 550 ret = mma8452_get_power_mode(data); 551 if (ret < 0) 552 return ret; 553 554 i = mma8452_get_odr_index(data); 555 556 *val = mma8452_os_ratio[ret][i]; 557 return IIO_VAL_INT; 558 } 559 560 return -EINVAL; 561 } 562 563 static int mma8452_calculate_sleep(struct mma8452_data *data) 564 { 565 int ret, i = mma8452_get_odr_index(data); 566 567 if (mma8452_samp_freq[i][0] > 0) 568 ret = 1000 / mma8452_samp_freq[i][0]; 569 else 570 ret = 1000; 571 572 return ret == 0 ? 1 : ret; 573 } 574 575 static int mma8452_standby(struct mma8452_data *data) 576 { 577 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 578 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 579 } 580 581 static int mma8452_active(struct mma8452_data *data) 582 { 583 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 584 data->ctrl_reg1); 585 } 586 587 /* returns >0 if active, 0 if in standby and <0 on error */ 588 static int mma8452_is_active(struct mma8452_data *data) 589 { 590 int reg; 591 592 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 593 if (reg < 0) 594 return reg; 595 596 return reg & MMA8452_CTRL_ACTIVE; 597 } 598 599 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 600 { 601 int ret; 602 int is_active; 603 604 mutex_lock(&data->lock); 605 606 is_active = mma8452_is_active(data); 607 if (is_active < 0) { 608 ret = is_active; 609 goto fail; 610 } 611 612 /* config can only be changed when in standby */ 613 if (is_active > 0) { 614 ret = mma8452_standby(data); 615 if (ret < 0) 616 goto fail; 617 } 618 619 ret = i2c_smbus_write_byte_data(data->client, reg, val); 620 if (ret < 0) 621 goto fail; 622 623 if (is_active > 0) { 624 ret = mma8452_active(data); 625 if (ret < 0) 626 goto fail; 627 } 628 629 ret = 0; 630 fail: 631 mutex_unlock(&data->lock); 632 633 return ret; 634 } 635 636 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 637 { 638 int reg; 639 640 reg = i2c_smbus_read_byte_data(data->client, 641 MMA8452_CTRL_REG2); 642 if (reg < 0) 643 return reg; 644 645 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 646 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 647 648 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 649 } 650 651 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 652 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 653 { 654 int val; 655 656 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 657 if (val < 0) 658 return val; 659 660 return !(val & MMA8452_FF_MT_CFG_OAE); 661 } 662 663 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 664 { 665 int val; 666 667 if ((state && mma8452_freefall_mode_enabled(data)) || 668 (!state && !(mma8452_freefall_mode_enabled(data)))) 669 return 0; 670 671 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 672 if (val < 0) 673 return val; 674 675 if (state) { 676 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 677 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 678 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 679 val &= ~MMA8452_FF_MT_CFG_OAE; 680 } else { 681 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 682 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 683 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 684 val |= MMA8452_FF_MT_CFG_OAE; 685 } 686 687 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 688 } 689 690 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 691 int val, int val2) 692 { 693 int i, reg; 694 695 i = mma8452_get_hp_filter_index(data, val, val2); 696 if (i < 0) 697 return i; 698 699 reg = i2c_smbus_read_byte_data(data->client, 700 MMA8452_HP_FILTER_CUTOFF); 701 if (reg < 0) 702 return reg; 703 704 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 705 reg |= i; 706 707 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 708 } 709 710 static int mma8452_write_raw(struct iio_dev *indio_dev, 711 struct iio_chan_spec const *chan, 712 int val, int val2, long mask) 713 { 714 struct mma8452_data *data = iio_priv(indio_dev); 715 int i, ret; 716 717 ret = iio_device_claim_direct_mode(indio_dev); 718 if (ret) 719 return ret; 720 721 switch (mask) { 722 case IIO_CHAN_INFO_SAMP_FREQ: 723 i = mma8452_get_samp_freq_index(data, val, val2); 724 if (i < 0) { 725 ret = i; 726 break; 727 } 728 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 729 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 730 731 data->sleep_val = mma8452_calculate_sleep(data); 732 733 ret = mma8452_change_config(data, MMA8452_CTRL_REG1, 734 data->ctrl_reg1); 735 break; 736 case IIO_CHAN_INFO_SCALE: 737 i = mma8452_get_scale_index(data, val, val2); 738 if (i < 0) { 739 ret = i; 740 break; 741 } 742 743 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 744 data->data_cfg |= i; 745 746 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 747 data->data_cfg); 748 break; 749 case IIO_CHAN_INFO_CALIBBIAS: 750 if (val < -128 || val > 127) { 751 ret = -EINVAL; 752 break; 753 } 754 755 ret = mma8452_change_config(data, 756 MMA8452_OFF_X + chan->scan_index, 757 val); 758 break; 759 760 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 761 if (val == 0 && val2 == 0) { 762 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 763 } else { 764 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 765 ret = mma8452_set_hp_filter_frequency(data, val, val2); 766 if (ret < 0) 767 break; 768 } 769 770 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 771 data->data_cfg); 772 break; 773 774 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 775 ret = mma8452_get_odr_index(data); 776 777 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 778 if (mma8452_os_ratio[i][ret] == val) { 779 ret = mma8452_set_power_mode(data, i); 780 break; 781 } 782 } 783 break; 784 default: 785 ret = -EINVAL; 786 break; 787 } 788 789 iio_device_release_direct_mode(indio_dev); 790 return ret; 791 } 792 793 static int mma8452_get_event_regs(struct mma8452_data *data, 794 const struct iio_chan_spec *chan, enum iio_event_direction dir, 795 const struct mma8452_event_regs **ev_reg) 796 { 797 if (!chan) 798 return -EINVAL; 799 800 switch (chan->type) { 801 case IIO_ACCEL: 802 switch (dir) { 803 case IIO_EV_DIR_RISING: 804 if ((data->chip_info->all_events 805 & MMA8452_INT_TRANS) && 806 (data->chip_info->enabled_events 807 & MMA8452_INT_TRANS)) 808 *ev_reg = &trans_ev_regs; 809 else 810 *ev_reg = &ff_mt_ev_regs; 811 return 0; 812 case IIO_EV_DIR_FALLING: 813 *ev_reg = &ff_mt_ev_regs; 814 return 0; 815 default: 816 return -EINVAL; 817 } 818 default: 819 return -EINVAL; 820 } 821 } 822 823 static int mma8452_read_event_value(struct iio_dev *indio_dev, 824 const struct iio_chan_spec *chan, 825 enum iio_event_type type, 826 enum iio_event_direction dir, 827 enum iio_event_info info, 828 int *val, int *val2) 829 { 830 struct mma8452_data *data = iio_priv(indio_dev); 831 int ret, us, power_mode; 832 const struct mma8452_event_regs *ev_regs; 833 834 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 835 if (ret) 836 return ret; 837 838 switch (info) { 839 case IIO_EV_INFO_VALUE: 840 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 841 if (ret < 0) 842 return ret; 843 844 *val = ret & ev_regs->ev_ths_mask; 845 846 return IIO_VAL_INT; 847 848 case IIO_EV_INFO_PERIOD: 849 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 850 if (ret < 0) 851 return ret; 852 853 power_mode = mma8452_get_power_mode(data); 854 if (power_mode < 0) 855 return power_mode; 856 857 us = ret * mma8452_time_step_us[power_mode][ 858 mma8452_get_odr_index(data)]; 859 *val = us / USEC_PER_SEC; 860 *val2 = us % USEC_PER_SEC; 861 862 return IIO_VAL_INT_PLUS_MICRO; 863 864 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 865 ret = i2c_smbus_read_byte_data(data->client, 866 MMA8452_TRANSIENT_CFG); 867 if (ret < 0) 868 return ret; 869 870 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 871 *val = 0; 872 *val2 = 0; 873 } else { 874 ret = mma8452_read_hp_filter(data, val, val2); 875 if (ret < 0) 876 return ret; 877 } 878 879 return IIO_VAL_INT_PLUS_MICRO; 880 881 default: 882 return -EINVAL; 883 } 884 } 885 886 static int mma8452_write_event_value(struct iio_dev *indio_dev, 887 const struct iio_chan_spec *chan, 888 enum iio_event_type type, 889 enum iio_event_direction dir, 890 enum iio_event_info info, 891 int val, int val2) 892 { 893 struct mma8452_data *data = iio_priv(indio_dev); 894 int ret, reg, steps; 895 const struct mma8452_event_regs *ev_regs; 896 897 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 898 if (ret) 899 return ret; 900 901 switch (info) { 902 case IIO_EV_INFO_VALUE: 903 if (val < 0 || val > ev_regs->ev_ths_mask) 904 return -EINVAL; 905 906 return mma8452_change_config(data, ev_regs->ev_ths, val); 907 908 case IIO_EV_INFO_PERIOD: 909 ret = mma8452_get_power_mode(data); 910 if (ret < 0) 911 return ret; 912 913 steps = (val * USEC_PER_SEC + val2) / 914 mma8452_time_step_us[ret][ 915 mma8452_get_odr_index(data)]; 916 917 if (steps < 0 || steps > 0xff) 918 return -EINVAL; 919 920 return mma8452_change_config(data, ev_regs->ev_count, steps); 921 922 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 923 reg = i2c_smbus_read_byte_data(data->client, 924 MMA8452_TRANSIENT_CFG); 925 if (reg < 0) 926 return reg; 927 928 if (val == 0 && val2 == 0) { 929 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 930 } else { 931 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 932 ret = mma8452_set_hp_filter_frequency(data, val, val2); 933 if (ret < 0) 934 return ret; 935 } 936 937 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 938 939 default: 940 return -EINVAL; 941 } 942 } 943 944 static int mma8452_read_event_config(struct iio_dev *indio_dev, 945 const struct iio_chan_spec *chan, 946 enum iio_event_type type, 947 enum iio_event_direction dir) 948 { 949 struct mma8452_data *data = iio_priv(indio_dev); 950 int ret; 951 const struct mma8452_event_regs *ev_regs; 952 953 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 954 if (ret) 955 return ret; 956 957 switch (dir) { 958 case IIO_EV_DIR_FALLING: 959 return mma8452_freefall_mode_enabled(data); 960 case IIO_EV_DIR_RISING: 961 ret = i2c_smbus_read_byte_data(data->client, 962 ev_regs->ev_cfg); 963 if (ret < 0) 964 return ret; 965 966 return !!(ret & BIT(chan->scan_index + 967 ev_regs->ev_cfg_chan_shift)); 968 default: 969 return -EINVAL; 970 } 971 } 972 973 static int mma8452_write_event_config(struct iio_dev *indio_dev, 974 const struct iio_chan_spec *chan, 975 enum iio_event_type type, 976 enum iio_event_direction dir, 977 bool state) 978 { 979 struct mma8452_data *data = iio_priv(indio_dev); 980 int val, ret; 981 const struct mma8452_event_regs *ev_regs; 982 983 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 984 if (ret) 985 return ret; 986 987 ret = mma8452_set_runtime_pm_state(data->client, state); 988 if (ret) 989 return ret; 990 991 switch (dir) { 992 case IIO_EV_DIR_FALLING: 993 return mma8452_set_freefall_mode(data, state); 994 case IIO_EV_DIR_RISING: 995 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 996 if (val < 0) 997 return val; 998 999 if (state) { 1000 if (mma8452_freefall_mode_enabled(data)) { 1001 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 1002 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 1003 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 1004 val |= MMA8452_FF_MT_CFG_OAE; 1005 } 1006 val |= BIT(chan->scan_index + 1007 ev_regs->ev_cfg_chan_shift); 1008 } else { 1009 if (mma8452_freefall_mode_enabled(data)) 1010 return 0; 1011 1012 val &= ~BIT(chan->scan_index + 1013 ev_regs->ev_cfg_chan_shift); 1014 } 1015 1016 val |= ev_regs->ev_cfg_ele; 1017 1018 return mma8452_change_config(data, ev_regs->ev_cfg, val); 1019 default: 1020 return -EINVAL; 1021 } 1022 } 1023 1024 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 1025 { 1026 struct mma8452_data *data = iio_priv(indio_dev); 1027 s64 ts = iio_get_time_ns(indio_dev); 1028 int src; 1029 1030 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1031 if (src < 0) 1032 return; 1033 1034 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1035 iio_push_event(indio_dev, 1036 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1037 IIO_EV_TYPE_MAG, 1038 IIO_EV_DIR_RISING), 1039 ts); 1040 1041 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1042 iio_push_event(indio_dev, 1043 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1044 IIO_EV_TYPE_MAG, 1045 IIO_EV_DIR_RISING), 1046 ts); 1047 1048 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1049 iio_push_event(indio_dev, 1050 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1051 IIO_EV_TYPE_MAG, 1052 IIO_EV_DIR_RISING), 1053 ts); 1054 } 1055 1056 static irqreturn_t mma8452_interrupt(int irq, void *p) 1057 { 1058 struct iio_dev *indio_dev = p; 1059 struct mma8452_data *data = iio_priv(indio_dev); 1060 irqreturn_t ret = IRQ_NONE; 1061 int src; 1062 1063 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1064 if (src < 0) 1065 return IRQ_NONE; 1066 1067 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY))) 1068 return IRQ_NONE; 1069 1070 if (src & MMA8452_INT_DRDY) { 1071 iio_trigger_poll_nested(indio_dev->trig); 1072 ret = IRQ_HANDLED; 1073 } 1074 1075 if (src & MMA8452_INT_FF_MT) { 1076 if (mma8452_freefall_mode_enabled(data)) { 1077 s64 ts = iio_get_time_ns(indio_dev); 1078 1079 iio_push_event(indio_dev, 1080 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1081 IIO_MOD_X_AND_Y_AND_Z, 1082 IIO_EV_TYPE_MAG, 1083 IIO_EV_DIR_FALLING), 1084 ts); 1085 } 1086 ret = IRQ_HANDLED; 1087 } 1088 1089 if (src & MMA8452_INT_TRANS) { 1090 mma8452_transient_interrupt(indio_dev); 1091 ret = IRQ_HANDLED; 1092 } 1093 1094 return ret; 1095 } 1096 1097 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1098 { 1099 struct iio_poll_func *pf = p; 1100 struct iio_dev *indio_dev = pf->indio_dev; 1101 struct mma8452_data *data = iio_priv(indio_dev); 1102 int ret; 1103 1104 ret = mma8452_read(data, data->buffer.channels); 1105 if (ret < 0) 1106 goto done; 1107 1108 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer, 1109 iio_get_time_ns(indio_dev)); 1110 1111 done: 1112 iio_trigger_notify_done(indio_dev->trig); 1113 1114 return IRQ_HANDLED; 1115 } 1116 1117 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1118 unsigned int reg, unsigned int writeval, 1119 unsigned int *readval) 1120 { 1121 int ret; 1122 struct mma8452_data *data = iio_priv(indio_dev); 1123 1124 if (reg > MMA8452_MAX_REG) 1125 return -EINVAL; 1126 1127 if (!readval) 1128 return mma8452_change_config(data, reg, writeval); 1129 1130 ret = i2c_smbus_read_byte_data(data->client, reg); 1131 if (ret < 0) 1132 return ret; 1133 1134 *readval = ret; 1135 1136 return 0; 1137 } 1138 1139 static const struct iio_event_spec mma8452_freefall_event[] = { 1140 { 1141 .type = IIO_EV_TYPE_MAG, 1142 .dir = IIO_EV_DIR_FALLING, 1143 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1144 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1145 BIT(IIO_EV_INFO_PERIOD) | 1146 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1147 }, 1148 }; 1149 1150 static const struct iio_event_spec mma8652_freefall_event[] = { 1151 { 1152 .type = IIO_EV_TYPE_MAG, 1153 .dir = IIO_EV_DIR_FALLING, 1154 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1155 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1156 BIT(IIO_EV_INFO_PERIOD) 1157 }, 1158 }; 1159 1160 static const struct iio_event_spec mma8452_transient_event[] = { 1161 { 1162 .type = IIO_EV_TYPE_MAG, 1163 .dir = IIO_EV_DIR_RISING, 1164 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1165 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1166 BIT(IIO_EV_INFO_PERIOD) | 1167 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1168 }, 1169 }; 1170 1171 static const struct iio_event_spec mma8452_motion_event[] = { 1172 { 1173 .type = IIO_EV_TYPE_MAG, 1174 .dir = IIO_EV_DIR_RISING, 1175 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1176 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1177 BIT(IIO_EV_INFO_PERIOD) 1178 }, 1179 }; 1180 1181 /* 1182 * Threshold is configured in fixed 8G/127 steps regardless of 1183 * currently selected scale for measurement. 1184 */ 1185 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1186 1187 static struct attribute *mma8452_event_attributes[] = { 1188 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1189 NULL, 1190 }; 1191 1192 static const struct attribute_group mma8452_event_attribute_group = { 1193 .attrs = mma8452_event_attributes, 1194 }; 1195 1196 static const struct iio_mount_matrix * 1197 mma8452_get_mount_matrix(const struct iio_dev *indio_dev, 1198 const struct iio_chan_spec *chan) 1199 { 1200 struct mma8452_data *data = iio_priv(indio_dev); 1201 1202 return &data->orientation; 1203 } 1204 1205 static const struct iio_chan_spec_ext_info mma8452_ext_info[] = { 1206 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mma8452_get_mount_matrix), 1207 { } 1208 }; 1209 1210 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1211 .type = IIO_ACCEL, \ 1212 .modified = 1, \ 1213 .channel2 = modifier, \ 1214 .scan_index = -1, \ 1215 .event_spec = mma8452_freefall_event, \ 1216 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1217 } 1218 1219 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1220 .type = IIO_ACCEL, \ 1221 .modified = 1, \ 1222 .channel2 = modifier, \ 1223 .scan_index = -1, \ 1224 .event_spec = mma8652_freefall_event, \ 1225 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1226 } 1227 1228 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1229 .type = IIO_ACCEL, \ 1230 .modified = 1, \ 1231 .channel2 = IIO_MOD_##axis, \ 1232 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1233 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1234 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1235 BIT(IIO_CHAN_INFO_SCALE) | \ 1236 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1237 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1238 .scan_index = idx, \ 1239 .scan_type = { \ 1240 .sign = 's', \ 1241 .realbits = (bits), \ 1242 .storagebits = 16, \ 1243 .shift = 16 - (bits), \ 1244 .endianness = IIO_BE, \ 1245 }, \ 1246 .event_spec = mma8452_transient_event, \ 1247 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1248 .ext_info = mma8452_ext_info, \ 1249 } 1250 1251 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1252 .type = IIO_ACCEL, \ 1253 .modified = 1, \ 1254 .channel2 = IIO_MOD_##axis, \ 1255 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1256 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1257 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1258 BIT(IIO_CHAN_INFO_SCALE) | \ 1259 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1260 .scan_index = idx, \ 1261 .scan_type = { \ 1262 .sign = 's', \ 1263 .realbits = (bits), \ 1264 .storagebits = 16, \ 1265 .shift = 16 - (bits), \ 1266 .endianness = IIO_BE, \ 1267 }, \ 1268 .event_spec = mma8452_motion_event, \ 1269 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1270 .ext_info = mma8452_ext_info, \ 1271 } 1272 1273 static const struct iio_chan_spec mma8451_channels[] = { 1274 MMA8452_CHANNEL(X, idx_x, 14), 1275 MMA8452_CHANNEL(Y, idx_y, 14), 1276 MMA8452_CHANNEL(Z, idx_z, 14), 1277 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1278 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1279 }; 1280 1281 static const struct iio_chan_spec mma8452_channels[] = { 1282 MMA8452_CHANNEL(X, idx_x, 12), 1283 MMA8452_CHANNEL(Y, idx_y, 12), 1284 MMA8452_CHANNEL(Z, idx_z, 12), 1285 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1286 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1287 }; 1288 1289 static const struct iio_chan_spec mma8453_channels[] = { 1290 MMA8452_CHANNEL(X, idx_x, 10), 1291 MMA8452_CHANNEL(Y, idx_y, 10), 1292 MMA8452_CHANNEL(Z, idx_z, 10), 1293 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1294 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1295 }; 1296 1297 static const struct iio_chan_spec mma8652_channels[] = { 1298 MMA8652_CHANNEL(X, idx_x, 12), 1299 MMA8652_CHANNEL(Y, idx_y, 12), 1300 MMA8652_CHANNEL(Z, idx_z, 12), 1301 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1302 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1303 }; 1304 1305 static const struct iio_chan_spec mma8653_channels[] = { 1306 MMA8652_CHANNEL(X, idx_x, 10), 1307 MMA8652_CHANNEL(Y, idx_y, 10), 1308 MMA8652_CHANNEL(Z, idx_z, 10), 1309 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1310 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1311 }; 1312 1313 enum { 1314 mma8451, 1315 mma8452, 1316 mma8453, 1317 mma8652, 1318 mma8653, 1319 fxls8471, 1320 }; 1321 1322 static const struct mma_chip_info mma_chip_info_table[] = { 1323 [mma8451] = { 1324 .name = "mma8451", 1325 .chip_id = MMA8451_DEVICE_ID, 1326 .channels = mma8451_channels, 1327 .num_channels = ARRAY_SIZE(mma8451_channels), 1328 /* 1329 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1330 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1331 * bit. 1332 * The userspace interface uses m/s^2 and we declare micro units 1333 * So scale factor for 12 bit here is given by: 1334 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1335 */ 1336 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1337 /* 1338 * Although we enable the interrupt sources once and for 1339 * all here the event detection itself is not enabled until 1340 * userspace asks for it by mma8452_write_event_config() 1341 */ 1342 .all_events = MMA8452_INT_DRDY | 1343 MMA8452_INT_TRANS | 1344 MMA8452_INT_FF_MT, 1345 .enabled_events = MMA8452_INT_TRANS | 1346 MMA8452_INT_FF_MT, 1347 }, 1348 [mma8452] = { 1349 .name = "mma8452", 1350 .chip_id = MMA8452_DEVICE_ID, 1351 .channels = mma8452_channels, 1352 .num_channels = ARRAY_SIZE(mma8452_channels), 1353 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1354 /* 1355 * Although we enable the interrupt sources once and for 1356 * all here the event detection itself is not enabled until 1357 * userspace asks for it by mma8452_write_event_config() 1358 */ 1359 .all_events = MMA8452_INT_DRDY | 1360 MMA8452_INT_TRANS | 1361 MMA8452_INT_FF_MT, 1362 .enabled_events = MMA8452_INT_TRANS | 1363 MMA8452_INT_FF_MT, 1364 }, 1365 [mma8453] = { 1366 .name = "mma8453", 1367 .chip_id = MMA8453_DEVICE_ID, 1368 .channels = mma8453_channels, 1369 .num_channels = ARRAY_SIZE(mma8453_channels), 1370 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1371 /* 1372 * Although we enable the interrupt sources once and for 1373 * all here the event detection itself is not enabled until 1374 * userspace asks for it by mma8452_write_event_config() 1375 */ 1376 .all_events = MMA8452_INT_DRDY | 1377 MMA8452_INT_TRANS | 1378 MMA8452_INT_FF_MT, 1379 .enabled_events = MMA8452_INT_TRANS | 1380 MMA8452_INT_FF_MT, 1381 }, 1382 [mma8652] = { 1383 .name = "mma8652", 1384 .chip_id = MMA8652_DEVICE_ID, 1385 .channels = mma8652_channels, 1386 .num_channels = ARRAY_SIZE(mma8652_channels), 1387 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1388 .all_events = MMA8452_INT_DRDY | 1389 MMA8452_INT_FF_MT, 1390 .enabled_events = MMA8452_INT_FF_MT, 1391 }, 1392 [mma8653] = { 1393 .name = "mma8653", 1394 .chip_id = MMA8653_DEVICE_ID, 1395 .channels = mma8653_channels, 1396 .num_channels = ARRAY_SIZE(mma8653_channels), 1397 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1398 /* 1399 * Although we enable the interrupt sources once and for 1400 * all here the event detection itself is not enabled until 1401 * userspace asks for it by mma8452_write_event_config() 1402 */ 1403 .all_events = MMA8452_INT_DRDY | 1404 MMA8452_INT_FF_MT, 1405 .enabled_events = MMA8452_INT_FF_MT, 1406 }, 1407 [fxls8471] = { 1408 .name = "fxls8471", 1409 .chip_id = FXLS8471_DEVICE_ID, 1410 .channels = mma8451_channels, 1411 .num_channels = ARRAY_SIZE(mma8451_channels), 1412 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1413 /* 1414 * Although we enable the interrupt sources once and for 1415 * all here the event detection itself is not enabled until 1416 * userspace asks for it by mma8452_write_event_config() 1417 */ 1418 .all_events = MMA8452_INT_DRDY | 1419 MMA8452_INT_TRANS | 1420 MMA8452_INT_FF_MT, 1421 .enabled_events = MMA8452_INT_TRANS | 1422 MMA8452_INT_FF_MT, 1423 }, 1424 }; 1425 1426 static struct attribute *mma8452_attributes[] = { 1427 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1428 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1429 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1430 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1431 NULL 1432 }; 1433 1434 static const struct attribute_group mma8452_group = { 1435 .attrs = mma8452_attributes, 1436 }; 1437 1438 static const struct iio_info mma8452_info = { 1439 .attrs = &mma8452_group, 1440 .read_raw = &mma8452_read_raw, 1441 .write_raw = &mma8452_write_raw, 1442 .event_attrs = &mma8452_event_attribute_group, 1443 .read_event_value = &mma8452_read_event_value, 1444 .write_event_value = &mma8452_write_event_value, 1445 .read_event_config = &mma8452_read_event_config, 1446 .write_event_config = &mma8452_write_event_config, 1447 .debugfs_reg_access = &mma8452_reg_access_dbg, 1448 }; 1449 1450 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1451 1452 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1453 bool state) 1454 { 1455 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1456 struct mma8452_data *data = iio_priv(indio_dev); 1457 int reg, ret; 1458 1459 ret = mma8452_set_runtime_pm_state(data->client, state); 1460 if (ret) 1461 return ret; 1462 1463 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1464 if (reg < 0) 1465 return reg; 1466 1467 if (state) 1468 reg |= MMA8452_INT_DRDY; 1469 else 1470 reg &= ~MMA8452_INT_DRDY; 1471 1472 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1473 } 1474 1475 static const struct iio_trigger_ops mma8452_trigger_ops = { 1476 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1477 .validate_device = iio_trigger_validate_own_device, 1478 }; 1479 1480 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1481 { 1482 struct mma8452_data *data = iio_priv(indio_dev); 1483 struct iio_trigger *trig; 1484 int ret; 1485 1486 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1487 indio_dev->name, 1488 iio_device_id(indio_dev)); 1489 if (!trig) 1490 return -ENOMEM; 1491 1492 trig->ops = &mma8452_trigger_ops; 1493 iio_trigger_set_drvdata(trig, indio_dev); 1494 1495 ret = iio_trigger_register(trig); 1496 if (ret) 1497 return ret; 1498 1499 indio_dev->trig = iio_trigger_get(trig); 1500 1501 return 0; 1502 } 1503 1504 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1505 { 1506 if (indio_dev->trig) 1507 iio_trigger_unregister(indio_dev->trig); 1508 } 1509 1510 static int mma8452_reset(struct i2c_client *client) 1511 { 1512 int i; 1513 int ret; 1514 1515 /* 1516 * Find on fxls8471, after config reset bit, it reset immediately, 1517 * and will not give ACK, so here do not check the return value. 1518 * The following code will read the reset register, and check whether 1519 * this reset works. 1520 */ 1521 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1522 MMA8452_CTRL_REG2_RST); 1523 1524 for (i = 0; i < 10; i++) { 1525 usleep_range(100, 200); 1526 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1527 if (ret == -EIO) 1528 continue; /* I2C comm reset */ 1529 if (ret < 0) 1530 return ret; 1531 if (!(ret & MMA8452_CTRL_REG2_RST)) 1532 return 0; 1533 } 1534 1535 return -ETIMEDOUT; 1536 } 1537 1538 static const struct of_device_id mma8452_dt_ids[] = { 1539 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1540 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1541 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1542 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1543 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1544 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1545 { } 1546 }; 1547 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1548 1549 static int mma8452_probe(struct i2c_client *client) 1550 { 1551 struct mma8452_data *data; 1552 struct iio_dev *indio_dev; 1553 int ret; 1554 1555 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1556 if (!indio_dev) 1557 return -ENOMEM; 1558 1559 data = iio_priv(indio_dev); 1560 data->client = client; 1561 mutex_init(&data->lock); 1562 1563 data->chip_info = i2c_get_match_data(client); 1564 if (!data->chip_info) 1565 return dev_err_probe(&client->dev, -ENODEV, 1566 "unknown device model\n"); 1567 1568 ret = iio_read_mount_matrix(&client->dev, &data->orientation); 1569 if (ret) 1570 return ret; 1571 1572 data->vdd_reg = devm_regulator_get(&client->dev, "vdd"); 1573 if (IS_ERR(data->vdd_reg)) 1574 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg), 1575 "failed to get VDD regulator!\n"); 1576 1577 data->vddio_reg = devm_regulator_get(&client->dev, "vddio"); 1578 if (IS_ERR(data->vddio_reg)) 1579 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg), 1580 "failed to get VDDIO regulator!\n"); 1581 1582 ret = regulator_enable(data->vdd_reg); 1583 if (ret) { 1584 dev_err(&client->dev, "failed to enable VDD regulator!\n"); 1585 return ret; 1586 } 1587 1588 ret = regulator_enable(data->vddio_reg); 1589 if (ret) { 1590 dev_err(&client->dev, "failed to enable VDDIO regulator!\n"); 1591 goto disable_regulator_vdd; 1592 } 1593 1594 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1595 if (ret < 0) 1596 goto disable_regulators; 1597 1598 switch (ret) { 1599 case MMA8451_DEVICE_ID: 1600 case MMA8452_DEVICE_ID: 1601 case MMA8453_DEVICE_ID: 1602 case MMA8652_DEVICE_ID: 1603 case MMA8653_DEVICE_ID: 1604 case FXLS8471_DEVICE_ID: 1605 if (ret == data->chip_info->chip_id) 1606 break; 1607 fallthrough; 1608 default: 1609 ret = -ENODEV; 1610 goto disable_regulators; 1611 } 1612 1613 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1614 data->chip_info->name, data->chip_info->chip_id); 1615 1616 i2c_set_clientdata(client, indio_dev); 1617 indio_dev->info = &mma8452_info; 1618 indio_dev->name = data->chip_info->name; 1619 indio_dev->modes = INDIO_DIRECT_MODE; 1620 indio_dev->channels = data->chip_info->channels; 1621 indio_dev->num_channels = data->chip_info->num_channels; 1622 indio_dev->available_scan_masks = mma8452_scan_masks; 1623 1624 ret = mma8452_reset(client); 1625 if (ret < 0) 1626 goto disable_regulators; 1627 1628 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1629 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1630 data->data_cfg); 1631 if (ret < 0) 1632 goto disable_regulators; 1633 1634 /* 1635 * By default set transient threshold to max to avoid events if 1636 * enabling without configuring threshold. 1637 */ 1638 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1639 MMA8452_TRANSIENT_THS_MASK); 1640 if (ret < 0) 1641 goto disable_regulators; 1642 1643 if (client->irq) { 1644 int irq2; 1645 1646 irq2 = fwnode_irq_get_byname(dev_fwnode(&client->dev), "INT2"); 1647 1648 if (irq2 == client->irq) { 1649 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1650 } else { 1651 ret = i2c_smbus_write_byte_data(client, 1652 MMA8452_CTRL_REG5, 1653 data->chip_info->all_events); 1654 if (ret < 0) 1655 goto disable_regulators; 1656 1657 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1658 } 1659 1660 ret = i2c_smbus_write_byte_data(client, 1661 MMA8452_CTRL_REG4, 1662 data->chip_info->enabled_events); 1663 if (ret < 0) 1664 goto disable_regulators; 1665 1666 ret = mma8452_trigger_setup(indio_dev); 1667 if (ret < 0) 1668 goto disable_regulators; 1669 } 1670 1671 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1672 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1673 1674 data->sleep_val = mma8452_calculate_sleep(data); 1675 1676 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1677 data->ctrl_reg1); 1678 if (ret < 0) 1679 goto trigger_cleanup; 1680 1681 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1682 mma8452_trigger_handler, NULL); 1683 if (ret < 0) 1684 goto trigger_cleanup; 1685 1686 if (client->irq) { 1687 ret = devm_request_threaded_irq(&client->dev, 1688 client->irq, 1689 NULL, mma8452_interrupt, 1690 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1691 client->name, indio_dev); 1692 if (ret) 1693 goto buffer_cleanup; 1694 } 1695 1696 ret = pm_runtime_set_active(&client->dev); 1697 if (ret < 0) 1698 goto buffer_cleanup; 1699 1700 pm_runtime_enable(&client->dev); 1701 pm_runtime_set_autosuspend_delay(&client->dev, 1702 MMA8452_AUTO_SUSPEND_DELAY_MS); 1703 pm_runtime_use_autosuspend(&client->dev); 1704 1705 ret = iio_device_register(indio_dev); 1706 if (ret < 0) 1707 goto buffer_cleanup; 1708 1709 ret = mma8452_set_freefall_mode(data, false); 1710 if (ret < 0) 1711 goto unregister_device; 1712 1713 return 0; 1714 1715 unregister_device: 1716 iio_device_unregister(indio_dev); 1717 1718 buffer_cleanup: 1719 iio_triggered_buffer_cleanup(indio_dev); 1720 1721 trigger_cleanup: 1722 mma8452_trigger_cleanup(indio_dev); 1723 1724 disable_regulators: 1725 regulator_disable(data->vddio_reg); 1726 1727 disable_regulator_vdd: 1728 regulator_disable(data->vdd_reg); 1729 1730 return ret; 1731 } 1732 1733 static void mma8452_remove(struct i2c_client *client) 1734 { 1735 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1736 struct mma8452_data *data = iio_priv(indio_dev); 1737 1738 iio_device_unregister(indio_dev); 1739 1740 pm_runtime_disable(&client->dev); 1741 pm_runtime_set_suspended(&client->dev); 1742 1743 iio_triggered_buffer_cleanup(indio_dev); 1744 mma8452_trigger_cleanup(indio_dev); 1745 mma8452_standby(iio_priv(indio_dev)); 1746 1747 regulator_disable(data->vddio_reg); 1748 regulator_disable(data->vdd_reg); 1749 } 1750 1751 #ifdef CONFIG_PM 1752 static int mma8452_runtime_suspend(struct device *dev) 1753 { 1754 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1755 struct mma8452_data *data = iio_priv(indio_dev); 1756 int ret; 1757 1758 mutex_lock(&data->lock); 1759 ret = mma8452_standby(data); 1760 mutex_unlock(&data->lock); 1761 if (ret < 0) { 1762 dev_err(&data->client->dev, "powering off device failed\n"); 1763 return -EAGAIN; 1764 } 1765 1766 ret = regulator_disable(data->vddio_reg); 1767 if (ret) { 1768 dev_err(dev, "failed to disable VDDIO regulator\n"); 1769 return ret; 1770 } 1771 1772 ret = regulator_disable(data->vdd_reg); 1773 if (ret) { 1774 dev_err(dev, "failed to disable VDD regulator\n"); 1775 return ret; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static int mma8452_runtime_resume(struct device *dev) 1782 { 1783 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1784 struct mma8452_data *data = iio_priv(indio_dev); 1785 int ret, sleep_val; 1786 1787 ret = regulator_enable(data->vdd_reg); 1788 if (ret) { 1789 dev_err(dev, "failed to enable VDD regulator\n"); 1790 return ret; 1791 } 1792 1793 ret = regulator_enable(data->vddio_reg); 1794 if (ret) { 1795 dev_err(dev, "failed to enable VDDIO regulator\n"); 1796 regulator_disable(data->vdd_reg); 1797 return ret; 1798 } 1799 1800 ret = mma8452_active(data); 1801 if (ret < 0) 1802 goto runtime_resume_failed; 1803 1804 ret = mma8452_get_odr_index(data); 1805 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1806 if (sleep_val < 20) 1807 usleep_range(sleep_val * 1000, 20000); 1808 else 1809 msleep_interruptible(sleep_val); 1810 1811 return 0; 1812 1813 runtime_resume_failed: 1814 regulator_disable(data->vddio_reg); 1815 regulator_disable(data->vdd_reg); 1816 1817 return ret; 1818 } 1819 #endif 1820 1821 static const struct dev_pm_ops mma8452_pm_ops = { 1822 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1823 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1824 mma8452_runtime_resume, NULL) 1825 }; 1826 1827 static const struct i2c_device_id mma8452_id[] = { 1828 { "fxls8471", (kernel_ulong_t)&mma_chip_info_table[fxls8471] }, 1829 { "mma8451", (kernel_ulong_t)&mma_chip_info_table[mma8451] }, 1830 { "mma8452", (kernel_ulong_t)&mma_chip_info_table[mma8452] }, 1831 { "mma8453", (kernel_ulong_t)&mma_chip_info_table[mma8453] }, 1832 { "mma8652", (kernel_ulong_t)&mma_chip_info_table[mma8652] }, 1833 { "mma8653", (kernel_ulong_t)&mma_chip_info_table[mma8653] }, 1834 { } 1835 }; 1836 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1837 1838 static struct i2c_driver mma8452_driver = { 1839 .driver = { 1840 .name = "mma8452", 1841 .of_match_table = mma8452_dt_ids, 1842 .pm = &mma8452_pm_ops, 1843 }, 1844 .probe = mma8452_probe, 1845 .remove = mma8452_remove, 1846 .id_table = mma8452_id, 1847 }; 1848 module_i2c_driver(mma8452_driver); 1849 1850 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1851 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1852 MODULE_LICENSE("GPL"); 1853