1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * KXCJK-1013 3-axis accelerometer driver 4 * Copyright (c) 2014, Intel Corporation. 5 */ 6 7 #include <linux/i2c.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/bitops.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/string.h> 15 #include <linux/types.h> 16 #include <linux/acpi.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/events.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/iio/accel/kxcjk_1013.h> 28 29 #define KXCJK1013_DRV_NAME "kxcjk1013" 30 #define KXCJK1013_IRQ_NAME "kxcjk1013_event" 31 32 #define KXTF9_REG_HP_XOUT_L 0x00 33 #define KXTF9_REG_HP_XOUT_H 0x01 34 #define KXTF9_REG_HP_YOUT_L 0x02 35 #define KXTF9_REG_HP_YOUT_H 0x03 36 #define KXTF9_REG_HP_ZOUT_L 0x04 37 #define KXTF9_REG_HP_ZOUT_H 0x05 38 39 #define KXCJK1013_REG_XOUT_L 0x06 40 /* 41 * From low byte X axis register, all the other addresses of Y and Z can be 42 * obtained by just applying axis offset. The following axis defines are just 43 * provide clarity, but not used. 44 */ 45 #define KXCJK1013_REG_XOUT_H 0x07 46 #define KXCJK1013_REG_YOUT_L 0x08 47 #define KXCJK1013_REG_YOUT_H 0x09 48 #define KXCJK1013_REG_ZOUT_L 0x0A 49 #define KXCJK1013_REG_ZOUT_H 0x0B 50 51 #define KXCJK1013_REG_DCST_RESP 0x0C 52 #define KXCJK1013_REG_WHO_AM_I 0x0F 53 #define KXTF9_REG_TILT_POS_CUR 0x10 54 #define KXTF9_REG_TILT_POS_PREV 0x11 55 #define KXTF9_REG_INT_SRC1 0x15 56 #define KXTF9_REG_INT_SRC2 0x16 57 #define KXCJK1013_REG_INT_SRC1 0x16 58 #define KXCJK1013_REG_INT_SRC2 0x17 59 #define KXCJK1013_REG_STATUS_REG 0x18 60 #define KXCJK1013_REG_INT_REL 0x1A 61 #define KXCJK1013_REG_CTRL1 0x1B 62 #define KXTF9_REG_CTRL2 0x1C 63 #define KXTF9_REG_CTRL3 0x1D 64 #define KXCJK1013_REG_CTRL2 0x1D 65 #define KXCJK1013_REG_INT_CTRL1 0x1E 66 #define KXCJK1013_REG_INT_CTRL2 0x1F 67 #define KXTF9_REG_INT_CTRL3 0x20 68 #define KXCJK1013_REG_DATA_CTRL 0x21 69 #define KXTF9_REG_TILT_TIMER 0x28 70 #define KXCJK1013_REG_WAKE_TIMER 0x29 71 #define KXTF9_REG_TDT_TIMER 0x2B 72 #define KXTF9_REG_TDT_THRESH_H 0x2C 73 #define KXTF9_REG_TDT_THRESH_L 0x2D 74 #define KXTF9_REG_TDT_TAP_TIMER 0x2E 75 #define KXTF9_REG_TDT_TOTAL_TIMER 0x2F 76 #define KXTF9_REG_TDT_LATENCY_TIMER 0x30 77 #define KXTF9_REG_TDT_WINDOW_TIMER 0x31 78 #define KXCJK1013_REG_SELF_TEST 0x3A 79 #define KXTF9_REG_WAKE_THRESH 0x5A 80 #define KXTF9_REG_TILT_ANGLE 0x5C 81 #define KXTF9_REG_HYST_SET 0x5F 82 #define KXCJK1013_REG_WAKE_THRES 0x6A 83 84 /* Everything up to 0x11 is equal to KXCJK1013/KXTF9 above */ 85 #define KX023_REG_INS1 0x12 86 #define KX023_REG_INS2 0x13 87 #define KX023_REG_INS3 0x14 88 #define KX023_REG_STAT 0x15 89 #define KX023_REG_INT_REL 0x17 90 #define KX023_REG_CNTL1 0x18 91 #define KX023_REG_CNTL2 0x19 92 #define KX023_REG_CNTL3 0x1A 93 #define KX023_REG_ODCNTL 0x1B 94 #define KX023_REG_INC1 0x1C 95 #define KX023_REG_INC2 0x1D 96 #define KX023_REG_INC3 0x1E 97 #define KX023_REG_INC4 0x1F 98 #define KX023_REG_INC5 0x20 99 #define KX023_REG_INC6 0x21 100 #define KX023_REG_TILT_TIMER 0x22 101 #define KX023_REG_WUFC 0x23 102 #define KX023_REG_TDTRC 0x24 103 #define KX023_REG_TDTC 0x25 104 #define KX023_REG_TTH 0x26 105 #define KX023_REG_TTL 0x27 106 #define KX023_REG_FTD 0x28 107 #define KX023_REG_STD 0x29 108 #define KX023_REG_TLT 0x2A 109 #define KX023_REG_TWS 0x2B 110 #define KX023_REG_ATH 0x30 111 #define KX023_REG_TILT_ANGLE_LL 0x32 112 #define KX023_REG_TILT_ANGLE_HL 0x33 113 #define KX023_REG_HYST_SET 0x34 114 #define KX023_REG_LP_CNTL 0x35 115 #define KX023_REG_BUF_CNTL1 0x3A 116 #define KX023_REG_BUF_CNTL2 0x3B 117 #define KX023_REG_BUF_STATUS_1 0x3C 118 #define KX023_REG_BUF_STATUS_2 0x3D 119 #define KX023_REG_BUF_CLEAR 0x3E 120 #define KX023_REG_BUF_READ 0x3F 121 #define KX023_REG_SELF_TEST 0x60 122 123 #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7) 124 #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6) 125 #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5) 126 #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4) 127 #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3) 128 #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1) 129 130 #define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */ 131 #define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3) 132 #define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4) 133 #define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5) 134 135 #define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5) 136 #define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4) 137 #define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3) 138 #define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2) 139 #define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1) 140 #define KXTF9_REG_TILT_BIT_FACE_UP BIT(0) 141 142 #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF 143 #define KXCJK1013_MAX_STARTUP_TIME_US 100000 144 145 #define KXCJK1013_SLEEP_DELAY_MS 2000 146 147 #define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */ 148 #define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1) 149 #define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */ 150 #define KXCJK1013_REG_INT_SRC1_TAP_NONE 0 151 #define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2) 152 #define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3) 153 #define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4) 154 155 /* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */ 156 #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0) 157 #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1) 158 #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2) 159 #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3) 160 #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4) 161 #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5) 162 163 /* KX023 interrupt routing to INT1. INT2 can be configured with INC6 */ 164 #define KX023_REG_INC4_BFI1 BIT(6) 165 #define KX023_REG_INC4_WMI1 BIT(5) 166 #define KX023_REG_INC4_DRDY1 BIT(4) 167 #define KX023_REG_INC4_TDTI1 BIT(2) 168 #define KX023_REG_INC4_WUFI1 BIT(1) 169 #define KX023_REG_INC4_TPI1 BIT(0) 170 171 #define KXCJK1013_DEFAULT_WAKE_THRES 1 172 173 /* Refer to section 4 of the specification */ 174 struct kx_odr_start_up_time { 175 int odr_bits; 176 int usec; 177 }; 178 179 /* KXCJK-1013 */ 180 static const struct kx_odr_start_up_time kxcjk1013_odr_start_up_times[] = { 181 { 0x08, 100000 }, 182 { 0x09, 100000 }, 183 { 0x0A, 100000 }, 184 { 0x0B, 100000 }, 185 { 0x00, 80000 }, 186 { 0x01, 41000 }, 187 { 0x02, 21000 }, 188 { 0x03, 11000 }, 189 { 0x04, 6400 }, 190 { 0x05, 3900 }, 191 { 0x06, 2700 }, 192 { 0x07, 2100 }, 193 { } 194 }; 195 196 /* KXCTJ2-1009 */ 197 static const struct kx_odr_start_up_time kxtj21009_odr_start_up_times[] = { 198 { 0x08, 1240000 }, 199 { 0x09, 621000 }, 200 { 0x0A, 309000 }, 201 { 0x0B, 151000 }, 202 { 0x00, 80000 }, 203 { 0x01, 41000 }, 204 { 0x02, 21000 }, 205 { 0x03, 11000 }, 206 { 0x04, 6000 }, 207 { 0x05, 4000 }, 208 { 0x06, 3000 }, 209 { 0x07, 2000 }, 210 { } 211 }; 212 213 /* KXTF9 */ 214 static const struct kx_odr_start_up_time kxtf9_odr_start_up_times[] = { 215 { 0x01, 81000 }, 216 { 0x02, 41000 }, 217 { 0x03, 21000 }, 218 { 0x04, 11000 }, 219 { 0x05, 5100 }, 220 { 0x06, 2700 }, 221 { } 222 }; 223 224 /* KX023-1025 */ 225 static const struct kx_odr_start_up_time kx0231025_odr_start_up_times[] = { 226 /* First 4 are not in datasheet, taken from KXCTJ2-1009 */ 227 { 0x08, 1240000 }, 228 { 0x09, 621000 }, 229 { 0x0A, 309000 }, 230 { 0x0B, 151000 }, 231 { 0x00, 81000 }, 232 { 0x01, 40000 }, 233 { 0x02, 22000 }, 234 { 0x03, 12000 }, 235 { 0x04, 7000 }, 236 { 0x05, 4400 }, 237 { 0x06, 3000 }, 238 { 0x07, 3000 }, 239 { } 240 }; 241 242 enum kx_acpi_type { 243 ACPI_GENERIC, 244 ACPI_SMO8500, 245 ACPI_KIOX010A, 246 }; 247 248 struct kx_chipset_regs { 249 u8 int_src1; 250 u8 int_src2; 251 u8 int_rel; 252 u8 ctrl1; 253 u8 wuf_ctrl; 254 u8 int_ctrl1; 255 u8 data_ctrl; 256 u8 wake_timer; 257 u8 wake_thres; 258 }; 259 260 static const struct kx_chipset_regs kxcjk1013_regs = { 261 .int_src1 = KXCJK1013_REG_INT_SRC1, 262 .int_src2 = KXCJK1013_REG_INT_SRC2, 263 .int_rel = KXCJK1013_REG_INT_REL, 264 .ctrl1 = KXCJK1013_REG_CTRL1, 265 .wuf_ctrl = KXCJK1013_REG_CTRL2, 266 .int_ctrl1 = KXCJK1013_REG_INT_CTRL1, 267 .data_ctrl = KXCJK1013_REG_DATA_CTRL, 268 .wake_timer = KXCJK1013_REG_WAKE_TIMER, 269 .wake_thres = KXCJK1013_REG_WAKE_THRES, 270 }; 271 272 static const struct kx_chipset_regs kxtf9_regs = { 273 /* .int_src1 was moved to INT_SRC2 on KXTF9 */ 274 .int_src1 = KXTF9_REG_INT_SRC2, 275 /* .int_src2 is not available */ 276 .int_rel = KXCJK1013_REG_INT_REL, 277 .ctrl1 = KXCJK1013_REG_CTRL1, 278 .wuf_ctrl = KXTF9_REG_CTRL3, 279 .int_ctrl1 = KXCJK1013_REG_INT_CTRL1, 280 .data_ctrl = KXCJK1013_REG_DATA_CTRL, 281 .wake_timer = KXCJK1013_REG_WAKE_TIMER, 282 .wake_thres = KXTF9_REG_WAKE_THRESH, 283 }; 284 285 /* The registers have totally different names but the bits are compatible */ 286 static const struct kx_chipset_regs kx0231025_regs = { 287 .int_src1 = KX023_REG_INS2, 288 .int_src2 = KX023_REG_INS3, 289 .int_rel = KX023_REG_INT_REL, 290 .ctrl1 = KX023_REG_CNTL1, 291 .wuf_ctrl = KX023_REG_CNTL3, 292 .int_ctrl1 = KX023_REG_INC1, 293 .data_ctrl = KX023_REG_ODCNTL, 294 .wake_timer = KX023_REG_WUFC, 295 .wake_thres = KX023_REG_ATH, 296 }; 297 298 struct kx_chipset_info { 299 const struct kx_chipset_regs *regs; 300 const struct kx_odr_start_up_time *times; 301 enum kx_acpi_type acpi_type; 302 }; 303 304 static const struct kx_chipset_info kxcjk1013_info = { 305 .regs = &kxcjk1013_regs, 306 .times = pm_ptr(kxcjk1013_odr_start_up_times), 307 }; 308 309 static const struct kx_chipset_info kxcj91008_info = { 310 .regs = &kxcjk1013_regs, 311 .times = pm_ptr(kxcjk1013_odr_start_up_times), 312 }; 313 314 static const struct kx_chipset_info kxcj91008_kiox010a_info = { 315 .regs = &kxcjk1013_regs, 316 .times = pm_ptr(kxcjk1013_odr_start_up_times), 317 .acpi_type = ACPI_KIOX010A, 318 }; 319 320 static const struct kx_chipset_info kxcj91008_kiox020a_info = { 321 .regs = &kxcjk1013_regs, 322 .times = pm_ptr(kxcjk1013_odr_start_up_times), 323 .acpi_type = ACPI_GENERIC, 324 }; 325 326 static const struct kx_chipset_info kxcj91008_smo8500_info = { 327 .regs = &kxcjk1013_regs, 328 .times = pm_ptr(kxcjk1013_odr_start_up_times), 329 .acpi_type = ACPI_SMO8500, 330 }; 331 332 static const struct kx_chipset_info kxtj21009_info = { 333 .regs = &kxcjk1013_regs, 334 .times = pm_ptr(kxtj21009_odr_start_up_times), 335 }; 336 337 static const struct kx_chipset_info kxtf9_info = { 338 .regs = &kxtf9_regs, 339 .times = pm_ptr(kxtf9_odr_start_up_times), 340 }; 341 342 static const struct kx_chipset_info kx0231025_info = { 343 .regs = &kx0231025_regs, 344 .times = pm_ptr(kx0231025_odr_start_up_times), 345 }; 346 347 enum kxcjk1013_axis { 348 AXIS_X, 349 AXIS_Y, 350 AXIS_Z, 351 AXIS_MAX 352 }; 353 354 struct kxcjk1013_data { 355 struct i2c_client *client; 356 struct iio_trigger *dready_trig; 357 struct iio_trigger *motion_trig; 358 struct iio_mount_matrix orientation; 359 struct mutex mutex; 360 /* Ensure timestamp naturally aligned */ 361 struct { 362 s16 chans[AXIS_MAX]; 363 aligned_s64 timestamp; 364 } scan; 365 u8 odr_bits; 366 u8 range; 367 int wake_thres; 368 int wake_dur; 369 bool active_high_intr; 370 bool dready_trigger_on; 371 int ev_enable_state; 372 bool motion_trigger_on; 373 int64_t timestamp; 374 const struct kx_chipset_info *info; 375 }; 376 377 enum kxcjk1013_mode { 378 STANDBY, 379 OPERATION, 380 }; 381 382 enum kxcjk1013_range { 383 KXCJK1013_RANGE_2G, 384 KXCJK1013_RANGE_4G, 385 KXCJK1013_RANGE_8G, 386 }; 387 388 struct kx_odr_map { 389 int val; 390 int val2; 391 int odr_bits; 392 int wuf_bits; 393 }; 394 395 static const struct kx_odr_map samp_freq_table[] = { 396 { 0, 781000, 0x08, 0x00 }, 397 { 1, 563000, 0x09, 0x01 }, 398 { 3, 125000, 0x0A, 0x02 }, 399 { 6, 250000, 0x0B, 0x03 }, 400 { 12, 500000, 0x00, 0x04 }, 401 { 25, 0, 0x01, 0x05 }, 402 { 50, 0, 0x02, 0x06 }, 403 { 100, 0, 0x03, 0x06 }, 404 { 200, 0, 0x04, 0x06 }, 405 { 400, 0, 0x05, 0x06 }, 406 { 800, 0, 0x06, 0x06 }, 407 { 1600, 0, 0x07, 0x06 }, 408 }; 409 410 static const char *const kxcjk1013_samp_freq_avail = 411 "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600"; 412 413 static const struct kx_odr_map kxtf9_samp_freq_table[] = { 414 { 25, 0, 0x01, 0x00 }, 415 { 50, 0, 0x02, 0x01 }, 416 { 100, 0, 0x03, 0x01 }, 417 { 200, 0, 0x04, 0x01 }, 418 { 400, 0, 0x05, 0x01 }, 419 { 800, 0, 0x06, 0x01 }, 420 }; 421 422 static const char *const kxtf9_samp_freq_avail = 423 "25 50 100 200 400 800"; 424 425 static const struct { 426 u16 scale; 427 u8 gsel_0; 428 u8 gsel_1; 429 } KXCJK1013_scale_table[] = { {9582, 0, 0}, 430 {19163, 1, 0}, 431 {38326, 0, 1} }; 432 433 #ifdef CONFIG_ACPI 434 enum kiox010a_fn_index { 435 KIOX010A_SET_LAPTOP_MODE = 1, 436 KIOX010A_SET_TABLET_MODE = 2, 437 }; 438 439 static int kiox010a_dsm(struct device *dev, int fn_index) 440 { 441 acpi_handle handle = ACPI_HANDLE(dev); 442 guid_t kiox010a_dsm_guid; 443 union acpi_object *obj; 444 445 if (!handle) 446 return -ENODEV; 447 448 guid_parse("1f339696-d475-4e26-8cad-2e9f8e6d7a91", &kiox010a_dsm_guid); 449 450 obj = acpi_evaluate_dsm(handle, &kiox010a_dsm_guid, 1, fn_index, NULL); 451 if (!obj) 452 return -EIO; 453 454 ACPI_FREE(obj); 455 return 0; 456 } 457 458 #endif 459 460 static int kxcjk1013_set_mode(struct kxcjk1013_data *data, 461 enum kxcjk1013_mode mode) 462 { 463 const struct kx_chipset_regs *regs = data->info->regs; 464 int ret; 465 466 ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1); 467 if (ret < 0) { 468 dev_err(&data->client->dev, "Error reading reg_ctrl1\n"); 469 return ret; 470 } 471 472 if (mode == STANDBY) 473 ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1; 474 else 475 ret |= KXCJK1013_REG_CTRL1_BIT_PC1; 476 477 ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret); 478 if (ret < 0) { 479 dev_err(&data->client->dev, "Error writing reg_ctrl1\n"); 480 return ret; 481 } 482 483 return 0; 484 } 485 486 static int kxcjk1013_get_mode(struct kxcjk1013_data *data, 487 enum kxcjk1013_mode *mode) 488 { 489 const struct kx_chipset_regs *regs = data->info->regs; 490 int ret; 491 492 ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1); 493 if (ret < 0) { 494 dev_err(&data->client->dev, "Error reading reg_ctrl1\n"); 495 return ret; 496 } 497 498 if (ret & KXCJK1013_REG_CTRL1_BIT_PC1) 499 *mode = OPERATION; 500 else 501 *mode = STANDBY; 502 503 return 0; 504 } 505 506 static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index) 507 { 508 const struct kx_chipset_regs *regs = data->info->regs; 509 int ret; 510 511 ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1); 512 if (ret < 0) { 513 dev_err(&data->client->dev, "Error reading reg_ctrl1\n"); 514 return ret; 515 } 516 517 ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 | 518 KXCJK1013_REG_CTRL1_BIT_GSEL1); 519 ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3); 520 ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4); 521 522 ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret); 523 if (ret < 0) { 524 dev_err(&data->client->dev, "Error writing reg_ctrl1\n"); 525 return ret; 526 } 527 528 data->range = range_index; 529 530 return 0; 531 } 532 533 static int kxcjk1013_chip_init(struct kxcjk1013_data *data) 534 { 535 const struct kx_chipset_regs *regs = data->info->regs; 536 int ret; 537 538 #ifdef CONFIG_ACPI 539 if (data->info->acpi_type == ACPI_KIOX010A) { 540 /* Make sure the kbd and touchpad on 2-in-1s using 2 KXCJ91008-s work */ 541 kiox010a_dsm(&data->client->dev, KIOX010A_SET_LAPTOP_MODE); 542 } 543 #endif 544 545 ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I); 546 if (ret < 0) { 547 dev_err(&data->client->dev, "Error reading who_am_i\n"); 548 return ret; 549 } 550 551 dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret); 552 553 ret = kxcjk1013_set_mode(data, STANDBY); 554 if (ret < 0) 555 return ret; 556 557 ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1); 558 if (ret < 0) { 559 dev_err(&data->client->dev, "Error reading reg_ctrl1\n"); 560 return ret; 561 } 562 563 /* Set 12 bit mode */ 564 ret |= KXCJK1013_REG_CTRL1_BIT_RES; 565 566 ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret); 567 if (ret < 0) { 568 dev_err(&data->client->dev, "Error reading reg_ctrl\n"); 569 return ret; 570 } 571 572 /* Setting range to 4G */ 573 ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G); 574 if (ret < 0) 575 return ret; 576 577 ret = i2c_smbus_read_byte_data(data->client, regs->data_ctrl); 578 if (ret < 0) { 579 dev_err(&data->client->dev, "Error reading reg_data_ctrl\n"); 580 return ret; 581 } 582 583 data->odr_bits = ret; 584 585 /* Set up INT polarity */ 586 ret = i2c_smbus_read_byte_data(data->client, regs->int_ctrl1); 587 if (ret < 0) { 588 dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n"); 589 return ret; 590 } 591 592 if (data->active_high_intr) 593 ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA; 594 else 595 ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA; 596 597 ret = i2c_smbus_write_byte_data(data->client, regs->int_ctrl1, ret); 598 if (ret < 0) { 599 dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n"); 600 return ret; 601 } 602 603 /* On KX023, route all used interrupts to INT1 for now */ 604 if (data->info == &kx0231025_info && data->client->irq > 0) { 605 ret = i2c_smbus_write_byte_data(data->client, KX023_REG_INC4, 606 KX023_REG_INC4_DRDY1 | 607 KX023_REG_INC4_WUFI1); 608 if (ret < 0) { 609 dev_err(&data->client->dev, "Error writing reg_inc4\n"); 610 return ret; 611 } 612 } 613 614 ret = kxcjk1013_set_mode(data, OPERATION); 615 if (ret < 0) 616 return ret; 617 618 data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES; 619 620 return 0; 621 } 622 623 static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data) 624 { 625 const struct kx_odr_start_up_time *times; 626 627 for (times = data->info->times; times->usec; times++) { 628 if (times->odr_bits == data->odr_bits) 629 return times->usec; 630 } 631 632 return KXCJK1013_MAX_STARTUP_TIME_US; 633 } 634 635 static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on) 636 { 637 #ifdef CONFIG_PM 638 int ret; 639 640 if (on) 641 ret = pm_runtime_resume_and_get(&data->client->dev); 642 else { 643 pm_runtime_mark_last_busy(&data->client->dev); 644 ret = pm_runtime_put_autosuspend(&data->client->dev); 645 } 646 if (ret < 0) { 647 dev_err(&data->client->dev, 648 "Failed: %s for %d\n", __func__, on); 649 return ret; 650 } 651 #endif 652 653 return 0; 654 } 655 656 static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data) 657 { 658 const struct kx_chipset_regs *regs = data->info->regs; 659 int ret; 660 661 ret = i2c_smbus_write_byte_data(data->client, regs->wake_timer, data->wake_dur); 662 if (ret < 0) { 663 dev_err(&data->client->dev, 664 "Error writing reg_wake_timer\n"); 665 return ret; 666 } 667 668 ret = i2c_smbus_write_byte_data(data->client, regs->wake_thres, data->wake_thres); 669 if (ret < 0) { 670 dev_err(&data->client->dev, "Error writing reg_wake_thres\n"); 671 return ret; 672 } 673 674 return 0; 675 } 676 677 static int kxcjk1013_setup_interrupt(struct kxcjk1013_data *data, 678 bool status, bool is_new_data) 679 { 680 const struct kx_chipset_regs *regs = data->info->regs; 681 int ret; 682 enum kxcjk1013_mode store_mode; 683 684 ret = kxcjk1013_get_mode(data, &store_mode); 685 if (ret < 0) 686 return ret; 687 688 /* This is requirement by spec to change state to STANDBY */ 689 ret = kxcjk1013_set_mode(data, STANDBY); 690 if (ret < 0) 691 return ret; 692 693 if (is_new_data == true) { 694 ret = kxcjk1013_chip_update_thresholds(data); 695 if (ret < 0) 696 return ret; 697 } 698 699 ret = i2c_smbus_read_byte_data(data->client, regs->int_ctrl1); 700 if (ret < 0) { 701 dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n"); 702 return ret; 703 } 704 705 if (status) 706 ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN; 707 else 708 ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN; 709 710 ret = i2c_smbus_write_byte_data(data->client, regs->int_ctrl1, ret); 711 if (ret < 0) { 712 dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n"); 713 return ret; 714 } 715 716 ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1); 717 if (ret < 0) { 718 dev_err(&data->client->dev, "Error reading reg_ctrl1\n"); 719 return ret; 720 } 721 722 if (is_new_data) { 723 if (status) 724 ret |= KXCJK1013_REG_CTRL1_BIT_DRDY; 725 else 726 ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY; 727 } else { 728 if (status) 729 ret |= KXCJK1013_REG_CTRL1_BIT_WUFE; 730 else 731 ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE; 732 } 733 734 ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret); 735 if (ret < 0) { 736 dev_err(&data->client->dev, "Error writing reg_ctrl1\n"); 737 return ret; 738 } 739 740 if (store_mode == OPERATION) { 741 ret = kxcjk1013_set_mode(data, OPERATION); 742 if (ret < 0) 743 return ret; 744 } 745 746 return 0; 747 } 748 749 static const struct kx_odr_map *kxcjk1013_find_odr_value( 750 const struct kx_odr_map *map, size_t map_size, int val, int val2) 751 { 752 int i; 753 754 for (i = 0; i < map_size; ++i) { 755 if (map[i].val == val && map[i].val2 == val2) 756 return &map[i]; 757 } 758 759 return ERR_PTR(-EINVAL); 760 } 761 762 static int kxcjk1013_convert_odr_value(const struct kx_odr_map *map, 763 size_t map_size, int odr_bits, 764 int *val, int *val2) 765 { 766 int i; 767 768 for (i = 0; i < map_size; ++i) { 769 if (map[i].odr_bits == odr_bits) { 770 *val = map[i].val; 771 *val2 = map[i].val2; 772 return IIO_VAL_INT_PLUS_MICRO; 773 } 774 } 775 776 return -EINVAL; 777 } 778 779 static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2) 780 { 781 const struct kx_chipset_regs *regs = data->info->regs; 782 int ret; 783 enum kxcjk1013_mode store_mode; 784 const struct kx_odr_map *odr_setting; 785 786 ret = kxcjk1013_get_mode(data, &store_mode); 787 if (ret < 0) 788 return ret; 789 790 if (data->info == &kxtf9_info) 791 odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table, 792 ARRAY_SIZE(kxtf9_samp_freq_table), 793 val, val2); 794 else 795 odr_setting = kxcjk1013_find_odr_value(samp_freq_table, 796 ARRAY_SIZE(samp_freq_table), 797 val, val2); 798 799 if (IS_ERR(odr_setting)) 800 return PTR_ERR(odr_setting); 801 802 /* To change ODR, the chip must be set to STANDBY as per spec */ 803 ret = kxcjk1013_set_mode(data, STANDBY); 804 if (ret < 0) 805 return ret; 806 807 ret = i2c_smbus_write_byte_data(data->client, regs->data_ctrl, 808 odr_setting->odr_bits); 809 if (ret < 0) { 810 dev_err(&data->client->dev, "Error writing data_ctrl\n"); 811 return ret; 812 } 813 814 data->odr_bits = odr_setting->odr_bits; 815 816 ret = i2c_smbus_write_byte_data(data->client, regs->wuf_ctrl, 817 odr_setting->wuf_bits); 818 if (ret < 0) { 819 dev_err(&data->client->dev, "Error writing reg_ctrl2\n"); 820 return ret; 821 } 822 823 if (store_mode == OPERATION) { 824 ret = kxcjk1013_set_mode(data, OPERATION); 825 if (ret < 0) 826 return ret; 827 } 828 829 return 0; 830 } 831 832 static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2) 833 { 834 if (data->info == &kxtf9_info) 835 return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table, 836 ARRAY_SIZE(kxtf9_samp_freq_table), 837 data->odr_bits, val, val2); 838 else 839 return kxcjk1013_convert_odr_value(samp_freq_table, 840 ARRAY_SIZE(samp_freq_table), 841 data->odr_bits, val, val2); 842 } 843 844 static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis) 845 { 846 u8 reg = KXCJK1013_REG_XOUT_L + axis * 2; 847 int ret; 848 849 ret = i2c_smbus_read_word_data(data->client, reg); 850 if (ret < 0) { 851 dev_err(&data->client->dev, 852 "failed to read accel_%c registers\n", 'x' + axis); 853 return ret; 854 } 855 856 return ret; 857 } 858 859 static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val) 860 { 861 int ret, i; 862 enum kxcjk1013_mode store_mode; 863 864 for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) { 865 if (KXCJK1013_scale_table[i].scale == val) { 866 ret = kxcjk1013_get_mode(data, &store_mode); 867 if (ret < 0) 868 return ret; 869 870 ret = kxcjk1013_set_mode(data, STANDBY); 871 if (ret < 0) 872 return ret; 873 874 ret = kxcjk1013_set_range(data, i); 875 if (ret < 0) 876 return ret; 877 878 if (store_mode == OPERATION) { 879 ret = kxcjk1013_set_mode(data, OPERATION); 880 if (ret) 881 return ret; 882 } 883 884 return 0; 885 } 886 } 887 888 return -EINVAL; 889 } 890 891 static int kxcjk1013_read_raw(struct iio_dev *indio_dev, 892 struct iio_chan_spec const *chan, int *val, 893 int *val2, long mask) 894 { 895 struct kxcjk1013_data *data = iio_priv(indio_dev); 896 int ret; 897 898 switch (mask) { 899 case IIO_CHAN_INFO_RAW: 900 mutex_lock(&data->mutex); 901 if (iio_buffer_enabled(indio_dev)) 902 ret = -EBUSY; 903 else { 904 ret = kxcjk1013_set_power_state(data, true); 905 if (ret < 0) { 906 mutex_unlock(&data->mutex); 907 return ret; 908 } 909 ret = kxcjk1013_get_acc_reg(data, chan->scan_index); 910 if (ret < 0) { 911 kxcjk1013_set_power_state(data, false); 912 mutex_unlock(&data->mutex); 913 return ret; 914 } 915 *val = sign_extend32(ret >> chan->scan_type.shift, 916 chan->scan_type.realbits - 1); 917 ret = kxcjk1013_set_power_state(data, false); 918 } 919 mutex_unlock(&data->mutex); 920 921 if (ret < 0) 922 return ret; 923 924 return IIO_VAL_INT; 925 926 case IIO_CHAN_INFO_SCALE: 927 *val = 0; 928 *val2 = KXCJK1013_scale_table[data->range].scale; 929 return IIO_VAL_INT_PLUS_MICRO; 930 931 case IIO_CHAN_INFO_SAMP_FREQ: 932 mutex_lock(&data->mutex); 933 ret = kxcjk1013_get_odr(data, val, val2); 934 mutex_unlock(&data->mutex); 935 return ret; 936 937 default: 938 return -EINVAL; 939 } 940 } 941 942 static int kxcjk1013_write_raw(struct iio_dev *indio_dev, 943 struct iio_chan_spec const *chan, int val, 944 int val2, long mask) 945 { 946 struct kxcjk1013_data *data = iio_priv(indio_dev); 947 int ret; 948 949 switch (mask) { 950 case IIO_CHAN_INFO_SAMP_FREQ: 951 mutex_lock(&data->mutex); 952 ret = kxcjk1013_set_odr(data, val, val2); 953 mutex_unlock(&data->mutex); 954 break; 955 case IIO_CHAN_INFO_SCALE: 956 if (val) 957 return -EINVAL; 958 959 mutex_lock(&data->mutex); 960 ret = kxcjk1013_set_scale(data, val2); 961 mutex_unlock(&data->mutex); 962 break; 963 default: 964 ret = -EINVAL; 965 } 966 967 return ret; 968 } 969 970 static int kxcjk1013_read_event(struct iio_dev *indio_dev, 971 const struct iio_chan_spec *chan, 972 enum iio_event_type type, 973 enum iio_event_direction dir, 974 enum iio_event_info info, 975 int *val, int *val2) 976 { 977 struct kxcjk1013_data *data = iio_priv(indio_dev); 978 979 *val2 = 0; 980 switch (info) { 981 case IIO_EV_INFO_VALUE: 982 *val = data->wake_thres; 983 break; 984 case IIO_EV_INFO_PERIOD: 985 *val = data->wake_dur; 986 break; 987 default: 988 return -EINVAL; 989 } 990 991 return IIO_VAL_INT; 992 } 993 994 static int kxcjk1013_write_event(struct iio_dev *indio_dev, 995 const struct iio_chan_spec *chan, 996 enum iio_event_type type, 997 enum iio_event_direction dir, 998 enum iio_event_info info, 999 int val, int val2) 1000 { 1001 struct kxcjk1013_data *data = iio_priv(indio_dev); 1002 1003 if (data->ev_enable_state) 1004 return -EBUSY; 1005 1006 switch (info) { 1007 case IIO_EV_INFO_VALUE: 1008 data->wake_thres = val; 1009 break; 1010 case IIO_EV_INFO_PERIOD: 1011 data->wake_dur = val; 1012 break; 1013 default: 1014 return -EINVAL; 1015 } 1016 1017 return 0; 1018 } 1019 1020 static int kxcjk1013_read_event_config(struct iio_dev *indio_dev, 1021 const struct iio_chan_spec *chan, 1022 enum iio_event_type type, 1023 enum iio_event_direction dir) 1024 { 1025 struct kxcjk1013_data *data = iio_priv(indio_dev); 1026 1027 return data->ev_enable_state; 1028 } 1029 1030 static int kxcjk1013_write_event_config(struct iio_dev *indio_dev, 1031 const struct iio_chan_spec *chan, 1032 enum iio_event_type type, 1033 enum iio_event_direction dir, 1034 bool state) 1035 { 1036 struct kxcjk1013_data *data = iio_priv(indio_dev); 1037 int ret; 1038 1039 if (state && data->ev_enable_state) 1040 return 0; 1041 1042 mutex_lock(&data->mutex); 1043 1044 if (!state && data->motion_trigger_on) { 1045 data->ev_enable_state = 0; 1046 mutex_unlock(&data->mutex); 1047 return 0; 1048 } 1049 1050 /* 1051 * We will expect the enable and disable to do operation in 1052 * reverse order. This will happen here anyway as our 1053 * resume operation uses sync mode runtime pm calls, the 1054 * suspend operation will be delayed by autosuspend delay 1055 * So the disable operation will still happen in reverse of 1056 * enable operation. When runtime pm is disabled the mode 1057 * is always on so sequence doesn't matter 1058 */ 1059 ret = kxcjk1013_set_power_state(data, state); 1060 if (ret < 0) { 1061 mutex_unlock(&data->mutex); 1062 return ret; 1063 } 1064 1065 ret = kxcjk1013_setup_interrupt(data, state, false); 1066 if (ret < 0) { 1067 kxcjk1013_set_power_state(data, false); 1068 data->ev_enable_state = 0; 1069 mutex_unlock(&data->mutex); 1070 return ret; 1071 } 1072 1073 data->ev_enable_state = state; 1074 mutex_unlock(&data->mutex); 1075 1076 return 0; 1077 } 1078 1079 static int kxcjk1013_buffer_preenable(struct iio_dev *indio_dev) 1080 { 1081 struct kxcjk1013_data *data = iio_priv(indio_dev); 1082 1083 return kxcjk1013_set_power_state(data, true); 1084 } 1085 1086 static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev) 1087 { 1088 struct kxcjk1013_data *data = iio_priv(indio_dev); 1089 1090 return kxcjk1013_set_power_state(data, false); 1091 } 1092 1093 static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev, 1094 struct device_attribute *attr, 1095 char *buf) 1096 { 1097 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 1098 struct kxcjk1013_data *data = iio_priv(indio_dev); 1099 const char *str; 1100 1101 if (data->info == &kxtf9_info) 1102 str = kxtf9_samp_freq_avail; 1103 else 1104 str = kxcjk1013_samp_freq_avail; 1105 1106 return sprintf(buf, "%s\n", str); 1107 } 1108 1109 static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO, 1110 kxcjk1013_get_samp_freq_avail, NULL, 0); 1111 1112 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326"); 1113 1114 static struct attribute *kxcjk1013_attributes[] = { 1115 &iio_dev_attr_in_accel_sampling_frequency_available.dev_attr.attr, 1116 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 1117 NULL, 1118 }; 1119 1120 static const struct attribute_group kxcjk1013_attrs_group = { 1121 .attrs = kxcjk1013_attributes, 1122 }; 1123 1124 static const struct iio_event_spec kxcjk1013_event = { 1125 .type = IIO_EV_TYPE_THRESH, 1126 .dir = IIO_EV_DIR_EITHER, 1127 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 1128 BIT(IIO_EV_INFO_ENABLE) | 1129 BIT(IIO_EV_INFO_PERIOD) 1130 }; 1131 1132 static const struct iio_mount_matrix * 1133 kxcjk1013_get_mount_matrix(const struct iio_dev *indio_dev, 1134 const struct iio_chan_spec *chan) 1135 { 1136 struct kxcjk1013_data *data = iio_priv(indio_dev); 1137 1138 return &data->orientation; 1139 } 1140 1141 static const struct iio_chan_spec_ext_info kxcjk1013_ext_info[] = { 1142 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kxcjk1013_get_mount_matrix), 1143 { } 1144 }; 1145 1146 #define KXCJK1013_CHANNEL(_axis) { \ 1147 .type = IIO_ACCEL, \ 1148 .modified = 1, \ 1149 .channel2 = IIO_MOD_##_axis, \ 1150 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 1151 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 1152 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1153 .scan_index = AXIS_##_axis, \ 1154 .scan_type = { \ 1155 .sign = 's', \ 1156 .realbits = 12, \ 1157 .storagebits = 16, \ 1158 .shift = 4, \ 1159 .endianness = IIO_LE, \ 1160 }, \ 1161 .event_spec = &kxcjk1013_event, \ 1162 .ext_info = kxcjk1013_ext_info, \ 1163 .num_event_specs = 1 \ 1164 } 1165 1166 static const struct iio_chan_spec kxcjk1013_channels[] = { 1167 KXCJK1013_CHANNEL(X), 1168 KXCJK1013_CHANNEL(Y), 1169 KXCJK1013_CHANNEL(Z), 1170 IIO_CHAN_SOFT_TIMESTAMP(3), 1171 }; 1172 1173 static const struct iio_buffer_setup_ops kxcjk1013_buffer_setup_ops = { 1174 .preenable = kxcjk1013_buffer_preenable, 1175 .postdisable = kxcjk1013_buffer_postdisable, 1176 }; 1177 1178 static const struct iio_info kxcjk1013_iio_info = { 1179 .attrs = &kxcjk1013_attrs_group, 1180 .read_raw = kxcjk1013_read_raw, 1181 .write_raw = kxcjk1013_write_raw, 1182 .read_event_value = kxcjk1013_read_event, 1183 .write_event_value = kxcjk1013_write_event, 1184 .write_event_config = kxcjk1013_write_event_config, 1185 .read_event_config = kxcjk1013_read_event_config, 1186 }; 1187 1188 static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0}; 1189 1190 static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p) 1191 { 1192 struct iio_poll_func *pf = p; 1193 struct iio_dev *indio_dev = pf->indio_dev; 1194 struct kxcjk1013_data *data = iio_priv(indio_dev); 1195 int ret; 1196 1197 mutex_lock(&data->mutex); 1198 ret = i2c_smbus_read_i2c_block_data_or_emulated(data->client, 1199 KXCJK1013_REG_XOUT_L, 1200 AXIS_MAX * 2, 1201 (u8 *)data->scan.chans); 1202 mutex_unlock(&data->mutex); 1203 if (ret < 0) 1204 goto err; 1205 1206 iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan), 1207 data->timestamp); 1208 err: 1209 iio_trigger_notify_done(indio_dev->trig); 1210 1211 return IRQ_HANDLED; 1212 } 1213 1214 static void kxcjk1013_trig_reen(struct iio_trigger *trig) 1215 { 1216 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1217 struct kxcjk1013_data *data = iio_priv(indio_dev); 1218 const struct kx_chipset_regs *regs = data->info->regs; 1219 int ret; 1220 1221 ret = i2c_smbus_read_byte_data(data->client, regs->int_rel); 1222 if (ret < 0) 1223 dev_err(&data->client->dev, "Error reading reg_int_rel\n"); 1224 } 1225 1226 static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig, 1227 bool state) 1228 { 1229 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1230 struct kxcjk1013_data *data = iio_priv(indio_dev); 1231 int ret; 1232 1233 mutex_lock(&data->mutex); 1234 1235 if (!state && data->ev_enable_state && data->motion_trigger_on) { 1236 data->motion_trigger_on = false; 1237 mutex_unlock(&data->mutex); 1238 return 0; 1239 } 1240 1241 ret = kxcjk1013_set_power_state(data, state); 1242 if (ret < 0) { 1243 mutex_unlock(&data->mutex); 1244 return ret; 1245 } 1246 ret = kxcjk1013_setup_interrupt(data, state, data->motion_trig != trig); 1247 if (ret < 0) { 1248 kxcjk1013_set_power_state(data, false); 1249 mutex_unlock(&data->mutex); 1250 return ret; 1251 } 1252 if (data->motion_trig == trig) 1253 data->motion_trigger_on = state; 1254 else 1255 data->dready_trigger_on = state; 1256 1257 mutex_unlock(&data->mutex); 1258 1259 return 0; 1260 } 1261 1262 static const struct iio_trigger_ops kxcjk1013_trigger_ops = { 1263 .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state, 1264 .reenable = kxcjk1013_trig_reen, 1265 }; 1266 1267 static void kxcjk1013_report_motion_event(struct iio_dev *indio_dev) 1268 { 1269 struct kxcjk1013_data *data = iio_priv(indio_dev); 1270 const struct kx_chipset_regs *regs = data->info->regs; 1271 1272 int ret = i2c_smbus_read_byte_data(data->client, regs->int_src2); 1273 if (ret < 0) { 1274 dev_err(&data->client->dev, "Error reading reg_int_src2\n"); 1275 return; 1276 } 1277 1278 if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN) 1279 iio_push_event(indio_dev, 1280 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1281 0, 1282 IIO_MOD_X, 1283 IIO_EV_TYPE_THRESH, 1284 IIO_EV_DIR_FALLING), 1285 data->timestamp); 1286 1287 if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP) 1288 iio_push_event(indio_dev, 1289 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1290 0, 1291 IIO_MOD_X, 1292 IIO_EV_TYPE_THRESH, 1293 IIO_EV_DIR_RISING), 1294 data->timestamp); 1295 1296 if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN) 1297 iio_push_event(indio_dev, 1298 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1299 0, 1300 IIO_MOD_Y, 1301 IIO_EV_TYPE_THRESH, 1302 IIO_EV_DIR_FALLING), 1303 data->timestamp); 1304 1305 if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP) 1306 iio_push_event(indio_dev, 1307 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1308 0, 1309 IIO_MOD_Y, 1310 IIO_EV_TYPE_THRESH, 1311 IIO_EV_DIR_RISING), 1312 data->timestamp); 1313 1314 if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN) 1315 iio_push_event(indio_dev, 1316 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1317 0, 1318 IIO_MOD_Z, 1319 IIO_EV_TYPE_THRESH, 1320 IIO_EV_DIR_FALLING), 1321 data->timestamp); 1322 1323 if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP) 1324 iio_push_event(indio_dev, 1325 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1326 0, 1327 IIO_MOD_Z, 1328 IIO_EV_TYPE_THRESH, 1329 IIO_EV_DIR_RISING), 1330 data->timestamp); 1331 } 1332 1333 static irqreturn_t kxcjk1013_event_handler(int irq, void *private) 1334 { 1335 struct iio_dev *indio_dev = private; 1336 struct kxcjk1013_data *data = iio_priv(indio_dev); 1337 const struct kx_chipset_regs *regs = data->info->regs; 1338 int ret; 1339 1340 ret = i2c_smbus_read_byte_data(data->client, regs->int_src1); 1341 if (ret < 0) { 1342 dev_err(&data->client->dev, "Error reading reg_int_src1\n"); 1343 goto ack_intr; 1344 } 1345 1346 if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) { 1347 if (data->info == &kxtf9_info) 1348 iio_push_event(indio_dev, 1349 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1350 0, 1351 IIO_MOD_X_AND_Y_AND_Z, 1352 IIO_EV_TYPE_THRESH, 1353 IIO_EV_DIR_RISING), 1354 data->timestamp); 1355 else 1356 kxcjk1013_report_motion_event(indio_dev); 1357 } 1358 1359 ack_intr: 1360 if (data->dready_trigger_on) 1361 return IRQ_HANDLED; 1362 1363 ret = i2c_smbus_read_byte_data(data->client, regs->int_rel); 1364 if (ret < 0) 1365 dev_err(&data->client->dev, "Error reading reg_int_rel\n"); 1366 1367 return IRQ_HANDLED; 1368 } 1369 1370 static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private) 1371 { 1372 struct iio_dev *indio_dev = private; 1373 struct kxcjk1013_data *data = iio_priv(indio_dev); 1374 1375 data->timestamp = iio_get_time_ns(indio_dev); 1376 1377 if (data->dready_trigger_on) 1378 iio_trigger_poll(data->dready_trig); 1379 else if (data->motion_trigger_on) 1380 iio_trigger_poll(data->motion_trig); 1381 1382 if (data->ev_enable_state) 1383 return IRQ_WAKE_THREAD; 1384 else 1385 return IRQ_HANDLED; 1386 } 1387 1388 static int kxcjk1013_probe(struct i2c_client *client) 1389 { 1390 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1391 static const char * const regulator_names[] = { "vdd", "vddio" }; 1392 struct kxcjk1013_data *data; 1393 struct iio_dev *indio_dev; 1394 struct kxcjk_1013_platform_data *pdata; 1395 const void *ddata = NULL; 1396 const char *name; 1397 int ret; 1398 1399 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1400 if (!indio_dev) 1401 return -ENOMEM; 1402 1403 data = iio_priv(indio_dev); 1404 i2c_set_clientdata(client, indio_dev); 1405 data->client = client; 1406 1407 pdata = dev_get_platdata(&client->dev); 1408 if (pdata) { 1409 data->active_high_intr = pdata->active_high_intr; 1410 data->orientation = pdata->orientation; 1411 } else { 1412 data->active_high_intr = true; /* default polarity */ 1413 1414 if (!iio_read_acpi_mount_matrix(&client->dev, &data->orientation, "ROTM")) { 1415 ret = iio_read_mount_matrix(&client->dev, &data->orientation); 1416 if (ret) 1417 return ret; 1418 } 1419 1420 } 1421 1422 ret = devm_regulator_bulk_get_enable(&client->dev, 1423 ARRAY_SIZE(regulator_names), 1424 regulator_names); 1425 if (ret) 1426 return dev_err_probe(&client->dev, ret, "Failed to get regulators\n"); 1427 1428 /* 1429 * A typical delay of 10ms is required for powering up 1430 * according to the data sheets of supported chips. 1431 * Hence double that to play safe. 1432 */ 1433 msleep(20); 1434 1435 if (id) { 1436 name = id->name; 1437 data->info = (const struct kx_chipset_info *)(id->driver_data); 1438 } else { 1439 name = iio_get_acpi_device_name_and_data(&client->dev, &ddata); 1440 data->info = ddata; 1441 if (data->info == &kxcj91008_kiox010a_info) 1442 indio_dev->label = "accel-display"; 1443 else if (data->info == &kxcj91008_kiox020a_info) 1444 indio_dev->label = "accel-base"; 1445 } 1446 if (!name) 1447 return -ENODEV; 1448 1449 ret = kxcjk1013_chip_init(data); 1450 if (ret < 0) 1451 return ret; 1452 1453 mutex_init(&data->mutex); 1454 1455 indio_dev->channels = kxcjk1013_channels; 1456 indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels); 1457 indio_dev->available_scan_masks = kxcjk1013_scan_masks; 1458 indio_dev->name = name; 1459 indio_dev->modes = INDIO_DIRECT_MODE; 1460 indio_dev->info = &kxcjk1013_iio_info; 1461 1462 if (client->irq > 0 && data->info->acpi_type != ACPI_SMO8500) { 1463 ret = devm_request_threaded_irq(&client->dev, client->irq, 1464 kxcjk1013_data_rdy_trig_poll, 1465 kxcjk1013_event_handler, 1466 IRQF_TRIGGER_RISING, 1467 KXCJK1013_IRQ_NAME, 1468 indio_dev); 1469 if (ret) 1470 goto err_poweroff; 1471 1472 data->dready_trig = devm_iio_trigger_alloc(&client->dev, 1473 "%s-dev%d", 1474 indio_dev->name, 1475 iio_device_id(indio_dev)); 1476 if (!data->dready_trig) { 1477 ret = -ENOMEM; 1478 goto err_poweroff; 1479 } 1480 1481 data->motion_trig = devm_iio_trigger_alloc(&client->dev, 1482 "%s-any-motion-dev%d", 1483 indio_dev->name, 1484 iio_device_id(indio_dev)); 1485 if (!data->motion_trig) { 1486 ret = -ENOMEM; 1487 goto err_poweroff; 1488 } 1489 1490 data->dready_trig->ops = &kxcjk1013_trigger_ops; 1491 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 1492 ret = iio_trigger_register(data->dready_trig); 1493 if (ret) 1494 goto err_poweroff; 1495 1496 indio_dev->trig = iio_trigger_get(data->dready_trig); 1497 1498 data->motion_trig->ops = &kxcjk1013_trigger_ops; 1499 iio_trigger_set_drvdata(data->motion_trig, indio_dev); 1500 ret = iio_trigger_register(data->motion_trig); 1501 if (ret) { 1502 data->motion_trig = NULL; 1503 goto err_trigger_unregister; 1504 } 1505 } 1506 1507 ret = iio_triggered_buffer_setup(indio_dev, 1508 &iio_pollfunc_store_time, 1509 kxcjk1013_trigger_handler, 1510 &kxcjk1013_buffer_setup_ops); 1511 if (ret < 0) { 1512 dev_err(&client->dev, "iio triggered buffer setup failed\n"); 1513 goto err_trigger_unregister; 1514 } 1515 1516 ret = pm_runtime_set_active(&client->dev); 1517 if (ret) 1518 goto err_buffer_cleanup; 1519 1520 pm_runtime_enable(&client->dev); 1521 pm_runtime_set_autosuspend_delay(&client->dev, 1522 KXCJK1013_SLEEP_DELAY_MS); 1523 pm_runtime_use_autosuspend(&client->dev); 1524 1525 ret = iio_device_register(indio_dev); 1526 if (ret < 0) { 1527 dev_err(&client->dev, "unable to register iio device\n"); 1528 goto err_pm_cleanup; 1529 } 1530 1531 return 0; 1532 1533 err_pm_cleanup: 1534 pm_runtime_dont_use_autosuspend(&client->dev); 1535 pm_runtime_disable(&client->dev); 1536 err_buffer_cleanup: 1537 iio_triggered_buffer_cleanup(indio_dev); 1538 err_trigger_unregister: 1539 if (data->dready_trig) 1540 iio_trigger_unregister(data->dready_trig); 1541 if (data->motion_trig) 1542 iio_trigger_unregister(data->motion_trig); 1543 err_poweroff: 1544 kxcjk1013_set_mode(data, STANDBY); 1545 1546 return ret; 1547 } 1548 1549 static void kxcjk1013_remove(struct i2c_client *client) 1550 { 1551 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1552 struct kxcjk1013_data *data = iio_priv(indio_dev); 1553 1554 iio_device_unregister(indio_dev); 1555 1556 pm_runtime_disable(&client->dev); 1557 pm_runtime_set_suspended(&client->dev); 1558 1559 iio_triggered_buffer_cleanup(indio_dev); 1560 if (data->dready_trig) { 1561 iio_trigger_unregister(data->dready_trig); 1562 iio_trigger_unregister(data->motion_trig); 1563 } 1564 1565 mutex_lock(&data->mutex); 1566 kxcjk1013_set_mode(data, STANDBY); 1567 mutex_unlock(&data->mutex); 1568 } 1569 1570 static int kxcjk1013_suspend(struct device *dev) 1571 { 1572 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1573 struct kxcjk1013_data *data = iio_priv(indio_dev); 1574 int ret; 1575 1576 mutex_lock(&data->mutex); 1577 ret = kxcjk1013_set_mode(data, STANDBY); 1578 mutex_unlock(&data->mutex); 1579 1580 return ret; 1581 } 1582 1583 static int kxcjk1013_resume(struct device *dev) 1584 { 1585 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1586 struct kxcjk1013_data *data = iio_priv(indio_dev); 1587 int ret = 0; 1588 1589 mutex_lock(&data->mutex); 1590 ret = kxcjk1013_set_mode(data, OPERATION); 1591 if (ret == 0) 1592 ret = kxcjk1013_set_range(data, data->range); 1593 mutex_unlock(&data->mutex); 1594 1595 return ret; 1596 } 1597 1598 static int kxcjk1013_runtime_suspend(struct device *dev) 1599 { 1600 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1601 struct kxcjk1013_data *data = iio_priv(indio_dev); 1602 int ret; 1603 1604 ret = kxcjk1013_set_mode(data, STANDBY); 1605 if (ret < 0) { 1606 dev_err(&data->client->dev, "powering off device failed\n"); 1607 return -EAGAIN; 1608 } 1609 return 0; 1610 } 1611 1612 static int kxcjk1013_runtime_resume(struct device *dev) 1613 { 1614 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1615 struct kxcjk1013_data *data = iio_priv(indio_dev); 1616 int ret; 1617 int sleep_val; 1618 1619 ret = kxcjk1013_set_mode(data, OPERATION); 1620 if (ret < 0) 1621 return ret; 1622 1623 sleep_val = kxcjk1013_get_startup_times(data); 1624 if (sleep_val < 20000) 1625 usleep_range(sleep_val, 20000); 1626 else 1627 msleep_interruptible(sleep_val/1000); 1628 1629 return 0; 1630 } 1631 1632 static const struct dev_pm_ops kxcjk1013_pm_ops = { 1633 SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume) 1634 RUNTIME_PM_OPS(kxcjk1013_runtime_suspend, kxcjk1013_runtime_resume, NULL) 1635 }; 1636 1637 static const struct i2c_device_id kxcjk1013_id[] = { 1638 { "kxcjk1013", (kernel_ulong_t)&kxcjk1013_info }, 1639 { "kxcj91008", (kernel_ulong_t)&kxcj91008_info }, 1640 { "kxtj21009", (kernel_ulong_t)&kxtj21009_info }, 1641 { "kxtf9", (kernel_ulong_t)&kxtf9_info }, 1642 { "kx023-1025", (kernel_ulong_t)&kx0231025_info }, 1643 { } 1644 }; 1645 MODULE_DEVICE_TABLE(i2c, kxcjk1013_id); 1646 1647 static const struct of_device_id kxcjk1013_of_match[] = { 1648 { .compatible = "kionix,kxcjk1013", &kxcjk1013_info }, 1649 { .compatible = "kionix,kxcj91008", &kxcj91008_info }, 1650 { .compatible = "kionix,kxtj21009", &kxtj21009_info }, 1651 { .compatible = "kionix,kxtf9", &kxtf9_info }, 1652 { .compatible = "kionix,kx023-1025", &kx0231025_info }, 1653 { } 1654 }; 1655 MODULE_DEVICE_TABLE(of, kxcjk1013_of_match); 1656 1657 static const struct acpi_device_id kx_acpi_match[] = { 1658 { "KIOX0008", (kernel_ulong_t)&kxcj91008_info }, 1659 { "KIOX0009", (kernel_ulong_t)&kxtj21009_info }, 1660 { "KIOX000A", (kernel_ulong_t)&kxcj91008_info }, 1661 /* KXCJ91008 in the display of a yoga 2-in-1 */ 1662 { "KIOX010A", (kernel_ulong_t)&kxcj91008_kiox010a_info }, 1663 /* KXCJ91008 in the base of a yoga 2-in-1 */ 1664 { "KIOX020A", (kernel_ulong_t)&kxcj91008_kiox020a_info }, 1665 { "KXCJ1008", (kernel_ulong_t)&kxcj91008_info }, 1666 { "KXCJ1013", (kernel_ulong_t)&kxcjk1013_info }, 1667 { "KXCJ9000", (kernel_ulong_t)&kxcj91008_info }, 1668 { "KXJ2109", (kernel_ulong_t)&kxtj21009_info }, 1669 { "KXTJ1009", (kernel_ulong_t)&kxtj21009_info }, 1670 { "SMO8500", (kernel_ulong_t)&kxcj91008_smo8500_info }, 1671 { } 1672 }; 1673 MODULE_DEVICE_TABLE(acpi, kx_acpi_match); 1674 1675 static struct i2c_driver kxcjk1013_driver = { 1676 .driver = { 1677 .name = KXCJK1013_DRV_NAME, 1678 .acpi_match_table = kx_acpi_match, 1679 .of_match_table = kxcjk1013_of_match, 1680 .pm = pm_ptr(&kxcjk1013_pm_ops), 1681 }, 1682 .probe = kxcjk1013_probe, 1683 .remove = kxcjk1013_remove, 1684 .id_table = kxcjk1013_id, 1685 }; 1686 module_i2c_driver(kxcjk1013_driver); 1687 1688 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1689 MODULE_LICENSE("GPL v2"); 1690 MODULE_DESCRIPTION("KXCJK1013 accelerometer driver"); 1691