1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver 4 * 5 * Copyright 2021 Connected Cars A/S 6 * 7 * Datasheet: 8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf 9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf 10 * 11 * Errata: 12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf 13 */ 14 15 #include <linux/bits.h> 16 #include <linux/bitfield.h> 17 #include <linux/i2c.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/regmap.h> 25 #include <linux/types.h> 26 #include <linux/units.h> 27 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/events.h> 30 #include <linux/iio/iio.h> 31 #include <linux/iio/kfifo_buf.h> 32 #include <linux/iio/sysfs.h> 33 34 #include "fxls8962af.h" 35 36 #define FXLS8962AF_INT_STATUS 0x00 37 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0) 38 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4) 39 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5) 40 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7) 41 #define FXLS8962AF_TEMP_OUT 0x01 42 #define FXLS8962AF_VECM_LSB 0x02 43 #define FXLS8962AF_OUT_X_LSB 0x04 44 #define FXLS8962AF_OUT_Y_LSB 0x06 45 #define FXLS8962AF_OUT_Z_LSB 0x08 46 #define FXLS8962AF_BUF_STATUS 0x0b 47 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0) 48 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6) 49 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7) 50 #define FXLS8962AF_BUF_X_LSB 0x0c 51 #define FXLS8962AF_BUF_Y_LSB 0x0e 52 #define FXLS8962AF_BUF_Z_LSB 0x10 53 54 #define FXLS8962AF_PROD_REV 0x12 55 #define FXLS8962AF_WHO_AM_I 0x13 56 57 #define FXLS8962AF_SYS_MODE 0x14 58 #define FXLS8962AF_SENS_CONFIG1 0x15 59 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0) 60 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7) 61 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1) 62 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x)) 63 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x)) 64 65 #define FXLS8962AF_SENS_CONFIG2 0x16 66 #define FXLS8962AF_SENS_CONFIG3 0x17 67 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4) 68 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 69 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 70 #define FXLS8962AF_SENS_CONFIG4 0x18 71 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1) 72 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x)) 73 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0) 74 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x)) 75 #define FXLS8962AF_SENS_CONFIG5 0x19 76 77 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b 78 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c 79 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e 80 81 #define FXLS8962AF_INT_EN 0x20 82 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5) 83 #define FXLS8962AF_INT_EN_BUF_EN BIT(6) 84 #define FXLS8962AF_INT_PIN_SEL 0x21 85 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0) 86 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00 87 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0) 88 89 #define FXLS8962AF_OFF_X 0x22 90 #define FXLS8962AF_OFF_Y 0x23 91 #define FXLS8962AF_OFF_Z 0x24 92 93 #define FXLS8962AF_BUF_CONFIG1 0x26 94 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5) 95 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x)) 96 #define FXLS8962AF_BUF_CONFIG2 0x27 97 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0) 98 99 #define FXLS8962AF_ORIENT_STATUS 0x28 100 #define FXLS8962AF_ORIENT_CONFIG 0x29 101 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a 102 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b 103 #define FXLS8962AF_ORIENT_THS_REG 0x2c 104 105 #define FXLS8962AF_SDCD_INT_SRC1 0x2d 106 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5) 107 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4) 108 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3) 109 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2) 110 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1) 111 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0) 112 #define FXLS8962AF_SDCD_INT_SRC2 0x2e 113 #define FXLS8962AF_SDCD_CONFIG1 0x2f 114 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3) 115 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4) 116 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5) 117 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7) 118 #define FXLS8962AF_SDCD_CONFIG2 0x30 119 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7) 120 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5) 121 #define FXLS8962AF_SDCD_OT_DBCNT 0x31 122 #define FXLS8962AF_SDCD_WT_DBCNT 0x32 123 #define FXLS8962AF_SDCD_LTHS_LSB 0x33 124 #define FXLS8962AF_SDCD_UTHS_LSB 0x35 125 126 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37 127 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38 128 129 #define FXLS8962AF_MAX_REG 0x38 130 131 #define FXLS8962AF_DEVICE_ID 0x62 132 #define FXLS8964AF_DEVICE_ID 0x84 133 #define FXLS8974CF_DEVICE_ID 0x86 134 #define FXLS8967AF_DEVICE_ID 0x87 135 136 /* Raw temp channel offset */ 137 #define FXLS8962AF_TEMP_CENTER_VAL 25 138 139 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000 140 141 #define FXLS8962AF_FIFO_LENGTH 32 142 #define FXLS8962AF_SCALE_TABLE_LEN 4 143 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13 144 145 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = { 146 {0, IIO_G_TO_M_S_2(980000)}, 147 {0, IIO_G_TO_M_S_2(1950000)}, 148 {0, IIO_G_TO_M_S_2(3910000)}, 149 {0, IIO_G_TO_M_S_2(7810000)}, 150 }; 151 152 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = { 153 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0}, 154 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000}, 155 {1, 563000}, {0, 781000}, 156 }; 157 158 struct fxls8962af_chip_info { 159 const char *name; 160 const struct iio_chan_spec *channels; 161 int num_channels; 162 u8 chip_id; 163 }; 164 165 struct fxls8962af_data { 166 struct regmap *regmap; 167 const struct fxls8962af_chip_info *chip_info; 168 struct { 169 __le16 channels[3]; 170 aligned_s64 ts; 171 } scan; 172 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 173 struct iio_mount_matrix orientation; 174 int irq; 175 u8 watermark; 176 u8 enable_event; 177 u16 lower_thres; 178 u16 upper_thres; 179 }; 180 181 const struct regmap_config fxls8962af_i2c_regmap_conf = { 182 .reg_bits = 8, 183 .val_bits = 8, 184 .max_register = FXLS8962AF_MAX_REG, 185 }; 186 EXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, "IIO_FXLS8962AF"); 187 188 const struct regmap_config fxls8962af_spi_regmap_conf = { 189 .reg_bits = 8, 190 .pad_bits = 8, 191 .val_bits = 8, 192 .max_register = FXLS8962AF_MAX_REG, 193 }; 194 EXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, "IIO_FXLS8962AF"); 195 196 enum { 197 fxls8962af_idx_x, 198 fxls8962af_idx_y, 199 fxls8962af_idx_z, 200 fxls8962af_idx_ts, 201 }; 202 203 enum fxls8962af_int_pin { 204 FXLS8962AF_PIN_INT1, 205 FXLS8962AF_PIN_INT2, 206 }; 207 208 static int fxls8962af_power_on(struct fxls8962af_data *data) 209 { 210 struct device *dev = regmap_get_device(data->regmap); 211 int ret; 212 213 ret = pm_runtime_resume_and_get(dev); 214 if (ret) 215 dev_err(dev, "failed to power on\n"); 216 217 return ret; 218 } 219 220 static int fxls8962af_power_off(struct fxls8962af_data *data) 221 { 222 struct device *dev = regmap_get_device(data->regmap); 223 int ret; 224 225 pm_runtime_mark_last_busy(dev); 226 ret = pm_runtime_put_autosuspend(dev); 227 if (ret) 228 dev_err(dev, "failed to power off\n"); 229 230 return ret; 231 } 232 233 static int fxls8962af_standby(struct fxls8962af_data *data) 234 { 235 return regmap_clear_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 236 FXLS8962AF_SENS_CONFIG1_ACTIVE); 237 } 238 239 static int fxls8962af_active(struct fxls8962af_data *data) 240 { 241 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 242 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1); 243 } 244 245 static int fxls8962af_is_active(struct fxls8962af_data *data) 246 { 247 unsigned int reg; 248 int ret; 249 250 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 251 if (ret) 252 return ret; 253 254 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE; 255 } 256 257 static int fxls8962af_get_out(struct fxls8962af_data *data, 258 struct iio_chan_spec const *chan, int *val) 259 { 260 struct device *dev = regmap_get_device(data->regmap); 261 __le16 raw_val; 262 int is_active; 263 int ret; 264 265 is_active = fxls8962af_is_active(data); 266 if (!is_active) { 267 ret = fxls8962af_power_on(data); 268 if (ret) 269 return ret; 270 } 271 272 ret = regmap_bulk_read(data->regmap, chan->address, 273 &raw_val, sizeof(data->lower_thres)); 274 275 if (!is_active) 276 fxls8962af_power_off(data); 277 278 if (ret) { 279 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address); 280 return ret; 281 } 282 283 *val = sign_extend32(le16_to_cpu(raw_val), 284 chan->scan_type.realbits - 1); 285 286 return IIO_VAL_INT; 287 } 288 289 static int fxls8962af_read_avail(struct iio_dev *indio_dev, 290 struct iio_chan_spec const *chan, 291 const int **vals, int *type, int *length, 292 long mask) 293 { 294 switch (mask) { 295 case IIO_CHAN_INFO_SCALE: 296 *type = IIO_VAL_INT_PLUS_NANO; 297 *vals = (int *)fxls8962af_scale_table; 298 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2; 299 return IIO_AVAIL_LIST; 300 case IIO_CHAN_INFO_SAMP_FREQ: 301 *type = IIO_VAL_INT_PLUS_MICRO; 302 *vals = (int *)fxls8962af_samp_freq_table; 303 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2; 304 return IIO_AVAIL_LIST; 305 default: 306 return -EINVAL; 307 } 308 } 309 310 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev, 311 struct iio_chan_spec const *chan, 312 long mask) 313 { 314 switch (mask) { 315 case IIO_CHAN_INFO_SCALE: 316 return IIO_VAL_INT_PLUS_NANO; 317 case IIO_CHAN_INFO_SAMP_FREQ: 318 return IIO_VAL_INT_PLUS_MICRO; 319 default: 320 return IIO_VAL_INT_PLUS_NANO; 321 } 322 } 323 324 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg, 325 u8 mask, u8 val) 326 { 327 int ret; 328 int is_active; 329 330 is_active = fxls8962af_is_active(data); 331 if (is_active) { 332 ret = fxls8962af_standby(data); 333 if (ret) 334 return ret; 335 } 336 337 ret = regmap_update_bits(data->regmap, reg, mask, val); 338 if (ret) 339 return ret; 340 341 if (is_active) { 342 ret = fxls8962af_active(data); 343 if (ret) 344 return ret; 345 } 346 347 return 0; 348 } 349 350 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale) 351 { 352 int i; 353 354 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++) 355 if (scale == fxls8962af_scale_table[i][1]) 356 break; 357 358 if (i == ARRAY_SIZE(fxls8962af_scale_table)) 359 return -EINVAL; 360 361 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1, 362 FXLS8962AF_SC1_FSR_MASK, 363 FXLS8962AF_SC1_FSR_PREP(i)); 364 } 365 366 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data, 367 int *val) 368 { 369 int ret; 370 unsigned int reg; 371 u8 range_idx; 372 373 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 374 if (ret) 375 return ret; 376 377 range_idx = FXLS8962AF_SC1_FSR_GET(reg); 378 379 *val = fxls8962af_scale_table[range_idx][1]; 380 381 return IIO_VAL_INT_PLUS_NANO; 382 } 383 384 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val, 385 u32 val2) 386 { 387 int i; 388 389 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++) 390 if (val == fxls8962af_samp_freq_table[i][0] && 391 val2 == fxls8962af_samp_freq_table[i][1]) 392 break; 393 394 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table)) 395 return -EINVAL; 396 397 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3, 398 FXLS8962AF_SC3_WAKE_ODR_MASK, 399 FXLS8962AF_SC3_WAKE_ODR_PREP(i)); 400 } 401 402 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data, 403 int *val, int *val2) 404 { 405 int ret; 406 unsigned int reg; 407 u8 range_idx; 408 409 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®); 410 if (ret) 411 return ret; 412 413 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg); 414 415 *val = fxls8962af_samp_freq_table[range_idx][0]; 416 *val2 = fxls8962af_samp_freq_table[range_idx][1]; 417 418 return IIO_VAL_INT_PLUS_MICRO; 419 } 420 421 static int fxls8962af_read_raw(struct iio_dev *indio_dev, 422 struct iio_chan_spec const *chan, 423 int *val, int *val2, long mask) 424 { 425 struct fxls8962af_data *data = iio_priv(indio_dev); 426 427 switch (mask) { 428 case IIO_CHAN_INFO_RAW: 429 switch (chan->type) { 430 case IIO_TEMP: 431 case IIO_ACCEL: 432 return fxls8962af_get_out(data, chan, val); 433 default: 434 return -EINVAL; 435 } 436 case IIO_CHAN_INFO_OFFSET: 437 if (chan->type != IIO_TEMP) 438 return -EINVAL; 439 440 *val = FXLS8962AF_TEMP_CENTER_VAL; 441 return IIO_VAL_INT; 442 case IIO_CHAN_INFO_SCALE: 443 switch (chan->type) { 444 case IIO_TEMP: 445 *val = MILLIDEGREE_PER_DEGREE; 446 return IIO_VAL_INT; 447 case IIO_ACCEL: 448 *val = 0; 449 return fxls8962af_read_full_scale(data, val2); 450 default: 451 return -EINVAL; 452 } 453 case IIO_CHAN_INFO_SAMP_FREQ: 454 return fxls8962af_read_samp_freq(data, val, val2); 455 default: 456 return -EINVAL; 457 } 458 } 459 460 static int fxls8962af_write_raw(struct iio_dev *indio_dev, 461 struct iio_chan_spec const *chan, 462 int val, int val2, long mask) 463 { 464 struct fxls8962af_data *data = iio_priv(indio_dev); 465 int ret; 466 467 switch (mask) { 468 case IIO_CHAN_INFO_SCALE: 469 if (val != 0) 470 return -EINVAL; 471 472 if (!iio_device_claim_direct(indio_dev)) 473 return -EBUSY; 474 475 ret = fxls8962af_set_full_scale(data, val2); 476 477 iio_device_release_direct(indio_dev); 478 return ret; 479 case IIO_CHAN_INFO_SAMP_FREQ: 480 if (!iio_device_claim_direct(indio_dev)) 481 return -EBUSY; 482 483 ret = fxls8962af_set_samp_freq(data, val, val2); 484 485 iio_device_release_direct(indio_dev); 486 return ret; 487 default: 488 return -EINVAL; 489 } 490 } 491 492 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state) 493 { 494 /* Enable wakeup interrupt */ 495 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN; 496 int value = state ? mask : 0; 497 498 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value); 499 } 500 501 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val) 502 { 503 struct fxls8962af_data *data = iio_priv(indio_dev); 504 505 if (val > FXLS8962AF_FIFO_LENGTH) 506 val = FXLS8962AF_FIFO_LENGTH; 507 508 data->watermark = val; 509 510 return 0; 511 } 512 513 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data, 514 const struct iio_chan_spec *chan, 515 enum iio_event_direction dir, 516 int val) 517 { 518 switch (dir) { 519 case IIO_EV_DIR_FALLING: 520 data->lower_thres = val; 521 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 522 &data->lower_thres, sizeof(data->lower_thres)); 523 case IIO_EV_DIR_RISING: 524 data->upper_thres = val; 525 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 526 &data->upper_thres, sizeof(data->upper_thres)); 527 default: 528 return -EINVAL; 529 } 530 } 531 532 static int fxls8962af_read_event(struct iio_dev *indio_dev, 533 const struct iio_chan_spec *chan, 534 enum iio_event_type type, 535 enum iio_event_direction dir, 536 enum iio_event_info info, 537 int *val, int *val2) 538 { 539 struct fxls8962af_data *data = iio_priv(indio_dev); 540 int ret; 541 542 if (type != IIO_EV_TYPE_THRESH) 543 return -EINVAL; 544 545 switch (dir) { 546 case IIO_EV_DIR_FALLING: 547 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 548 &data->lower_thres, sizeof(data->lower_thres)); 549 if (ret) 550 return ret; 551 552 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1); 553 return IIO_VAL_INT; 554 case IIO_EV_DIR_RISING: 555 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 556 &data->upper_thres, sizeof(data->upper_thres)); 557 if (ret) 558 return ret; 559 560 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1); 561 return IIO_VAL_INT; 562 default: 563 return -EINVAL; 564 } 565 } 566 567 static int fxls8962af_write_event(struct iio_dev *indio_dev, 568 const struct iio_chan_spec *chan, 569 enum iio_event_type type, 570 enum iio_event_direction dir, 571 enum iio_event_info info, 572 int val, int val2) 573 { 574 struct fxls8962af_data *data = iio_priv(indio_dev); 575 int ret, val_masked; 576 577 if (type != IIO_EV_TYPE_THRESH) 578 return -EINVAL; 579 580 if (val < -2048 || val > 2047) 581 return -EINVAL; 582 583 if (data->enable_event) 584 return -EBUSY; 585 586 val_masked = val & GENMASK(11, 0); 587 if (fxls8962af_is_active(data)) { 588 ret = fxls8962af_standby(data); 589 if (ret) 590 return ret; 591 592 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked); 593 if (ret) 594 return ret; 595 596 return fxls8962af_active(data); 597 } else { 598 return __fxls8962af_set_thresholds(data, chan, dir, val_masked); 599 } 600 } 601 602 static int 603 fxls8962af_read_event_config(struct iio_dev *indio_dev, 604 const struct iio_chan_spec *chan, 605 enum iio_event_type type, 606 enum iio_event_direction dir) 607 { 608 struct fxls8962af_data *data = iio_priv(indio_dev); 609 610 if (type != IIO_EV_TYPE_THRESH) 611 return -EINVAL; 612 613 switch (chan->channel2) { 614 case IIO_MOD_X: 615 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event); 616 case IIO_MOD_Y: 617 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event); 618 case IIO_MOD_Z: 619 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event); 620 default: 621 return -EINVAL; 622 } 623 } 624 625 static int 626 fxls8962af_write_event_config(struct iio_dev *indio_dev, 627 const struct iio_chan_spec *chan, 628 enum iio_event_type type, 629 enum iio_event_direction dir, bool state) 630 { 631 struct fxls8962af_data *data = iio_priv(indio_dev); 632 u8 enable_event, enable_bits; 633 int ret, value; 634 635 if (type != IIO_EV_TYPE_THRESH) 636 return -EINVAL; 637 638 switch (chan->channel2) { 639 case IIO_MOD_X: 640 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN; 641 break; 642 case IIO_MOD_Y: 643 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN; 644 break; 645 case IIO_MOD_Z: 646 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN; 647 break; 648 default: 649 return -EINVAL; 650 } 651 652 if (state) 653 enable_event = data->enable_event | enable_bits; 654 else 655 enable_event = data->enable_event & ~enable_bits; 656 657 if (data->enable_event == enable_event) 658 return 0; 659 660 ret = fxls8962af_standby(data); 661 if (ret) 662 return ret; 663 664 /* Enable events */ 665 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE; 666 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value); 667 if (ret) 668 return ret; 669 670 /* 671 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and 672 * trimmed X/Y/Z acceleration input data. This allows for acceleration 673 * slope detection with Data(n) to Data(n–1) always used as the input 674 * to the window comparator. 675 */ 676 value = enable_event ? 677 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC : 678 0x00; 679 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value); 680 if (ret) 681 return ret; 682 683 ret = fxls8962af_event_setup(data, state); 684 if (ret) 685 return ret; 686 687 data->enable_event = enable_event; 688 689 if (data->enable_event) { 690 fxls8962af_active(data); 691 ret = fxls8962af_power_on(data); 692 } else { 693 if (!iio_device_claim_direct(indio_dev)) 694 return -EBUSY; 695 696 /* Not in buffered mode so disable power */ 697 ret = fxls8962af_power_off(data); 698 699 iio_device_release_direct(indio_dev); 700 } 701 702 return ret; 703 } 704 705 static const struct iio_event_spec fxls8962af_event[] = { 706 { 707 .type = IIO_EV_TYPE_THRESH, 708 .dir = IIO_EV_DIR_EITHER, 709 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 710 }, 711 { 712 .type = IIO_EV_TYPE_THRESH, 713 .dir = IIO_EV_DIR_FALLING, 714 .mask_separate = BIT(IIO_EV_INFO_VALUE), 715 }, 716 { 717 .type = IIO_EV_TYPE_THRESH, 718 .dir = IIO_EV_DIR_RISING, 719 .mask_separate = BIT(IIO_EV_INFO_VALUE), 720 }, 721 }; 722 723 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \ 724 .type = IIO_ACCEL, \ 725 .address = reg, \ 726 .modified = 1, \ 727 .channel2 = IIO_MOD_##axis, \ 728 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 729 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 730 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 731 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 732 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 733 .scan_index = idx, \ 734 .scan_type = { \ 735 .sign = 's', \ 736 .realbits = 12, \ 737 .storagebits = 16, \ 738 .endianness = IIO_LE, \ 739 }, \ 740 .event_spec = fxls8962af_event, \ 741 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \ 742 } 743 744 #define FXLS8962AF_TEMP_CHANNEL { \ 745 .type = IIO_TEMP, \ 746 .address = FXLS8962AF_TEMP_OUT, \ 747 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 748 BIT(IIO_CHAN_INFO_SCALE) | \ 749 BIT(IIO_CHAN_INFO_OFFSET),\ 750 .scan_index = -1, \ 751 .scan_type = { \ 752 .sign = 's', \ 753 .realbits = 8, \ 754 .storagebits = 8, \ 755 }, \ 756 } 757 758 static const struct iio_chan_spec fxls8962af_channels[] = { 759 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x), 760 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y), 761 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z), 762 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts), 763 FXLS8962AF_TEMP_CHANNEL, 764 }; 765 766 static const struct fxls8962af_chip_info fxls_chip_info_table[] = { 767 [fxls8962af] = { 768 .chip_id = FXLS8962AF_DEVICE_ID, 769 .name = "fxls8962af", 770 .channels = fxls8962af_channels, 771 .num_channels = ARRAY_SIZE(fxls8962af_channels), 772 }, 773 [fxls8964af] = { 774 .chip_id = FXLS8964AF_DEVICE_ID, 775 .name = "fxls8964af", 776 .channels = fxls8962af_channels, 777 .num_channels = ARRAY_SIZE(fxls8962af_channels), 778 }, 779 [fxls8967af] = { 780 .chip_id = FXLS8967AF_DEVICE_ID, 781 .name = "fxls8967af", 782 .channels = fxls8962af_channels, 783 .num_channels = ARRAY_SIZE(fxls8962af_channels), 784 }, 785 [fxls8974cf] = { 786 .chip_id = FXLS8974CF_DEVICE_ID, 787 .name = "fxls8974cf", 788 .channels = fxls8962af_channels, 789 .num_channels = ARRAY_SIZE(fxls8962af_channels), 790 }, 791 }; 792 793 static const struct iio_info fxls8962af_info = { 794 .read_raw = &fxls8962af_read_raw, 795 .write_raw = &fxls8962af_write_raw, 796 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt, 797 .read_event_value = fxls8962af_read_event, 798 .write_event_value = fxls8962af_write_event, 799 .read_event_config = fxls8962af_read_event_config, 800 .write_event_config = fxls8962af_write_event_config, 801 .read_avail = fxls8962af_read_avail, 802 .hwfifo_set_watermark = fxls8962af_set_watermark, 803 }; 804 805 static int fxls8962af_reset(struct fxls8962af_data *data) 806 { 807 struct device *dev = regmap_get_device(data->regmap); 808 unsigned int reg; 809 int ret; 810 811 ret = regmap_set_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 812 FXLS8962AF_SENS_CONFIG1_RST); 813 if (ret) 814 return ret; 815 816 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */ 817 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg, 818 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT), 819 1000, 18000); 820 if (ret == -ETIMEDOUT) 821 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg); 822 823 return ret; 824 } 825 826 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff) 827 { 828 int ret; 829 830 /* Enable watermark at max fifo size */ 831 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2, 832 FXLS8962AF_BUF_CONFIG2_BUF_WMRK, 833 data->watermark); 834 if (ret) 835 return ret; 836 837 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1, 838 FXLS8962AF_BC1_BUF_MODE_MASK, 839 FXLS8962AF_BC1_BUF_MODE_PREP(onoff)); 840 } 841 842 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev) 843 { 844 return fxls8962af_power_on(iio_priv(indio_dev)); 845 } 846 847 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev) 848 { 849 struct fxls8962af_data *data = iio_priv(indio_dev); 850 int ret; 851 852 fxls8962af_standby(data); 853 854 /* Enable buffer interrupt */ 855 ret = regmap_set_bits(data->regmap, FXLS8962AF_INT_EN, 856 FXLS8962AF_INT_EN_BUF_EN); 857 if (ret) 858 return ret; 859 860 ret = __fxls8962af_fifo_set_mode(data, true); 861 862 fxls8962af_active(data); 863 864 return ret; 865 } 866 867 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev) 868 { 869 struct fxls8962af_data *data = iio_priv(indio_dev); 870 int ret; 871 872 fxls8962af_standby(data); 873 874 /* Disable buffer interrupt */ 875 ret = regmap_clear_bits(data->regmap, FXLS8962AF_INT_EN, 876 FXLS8962AF_INT_EN_BUF_EN); 877 if (ret) 878 return ret; 879 880 ret = __fxls8962af_fifo_set_mode(data, false); 881 882 if (data->enable_event) 883 fxls8962af_active(data); 884 885 return ret; 886 } 887 888 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev) 889 { 890 struct fxls8962af_data *data = iio_priv(indio_dev); 891 892 if (!data->enable_event) 893 fxls8962af_power_off(data); 894 895 return 0; 896 } 897 898 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = { 899 .preenable = fxls8962af_buffer_preenable, 900 .postenable = fxls8962af_buffer_postenable, 901 .predisable = fxls8962af_buffer_predisable, 902 .postdisable = fxls8962af_buffer_postdisable, 903 }; 904 905 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, 906 u16 *buffer, int samples, 907 int sample_length) 908 { 909 int i, ret; 910 911 for (i = 0; i < samples; i++) { 912 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, 913 &buffer[i * 3], sample_length); 914 if (ret) 915 return ret; 916 } 917 918 return 0; 919 } 920 921 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, 922 u16 *buffer, int samples) 923 { 924 struct device *dev = regmap_get_device(data->regmap); 925 int sample_length = 3 * sizeof(*buffer); 926 int total_length = samples * sample_length; 927 int ret; 928 929 if (i2c_verify_client(dev) && 930 data->chip_info->chip_id == FXLS8962AF_DEVICE_ID) 931 /* 932 * Due to errata bug (only applicable on fxls8962af): 933 * E3: FIFO burst read operation error using I2C interface 934 * We have to avoid burst reads on I2C.. 935 */ 936 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples, 937 sample_length); 938 else 939 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer, 940 total_length); 941 942 if (ret) 943 dev_err(dev, "Error transferring data from fifo: %d\n", ret); 944 945 return ret; 946 } 947 948 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev) 949 { 950 struct fxls8962af_data *data = iio_priv(indio_dev); 951 struct device *dev = regmap_get_device(data->regmap); 952 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3]; 953 uint64_t sample_period; 954 unsigned int reg; 955 int64_t tstamp; 956 int ret, i; 957 u8 count; 958 959 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®); 960 if (ret) 961 return ret; 962 963 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) { 964 dev_err(dev, "Buffer overflow"); 965 return -EOVERFLOW; 966 } 967 968 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT; 969 if (!count) 970 return 0; 971 972 data->old_timestamp = data->timestamp; 973 data->timestamp = iio_get_time_ns(indio_dev); 974 975 /* 976 * Approximate timestamps for each of the sample based on the sampling, 977 * frequency, timestamp for last sample and number of samples. 978 */ 979 sample_period = (data->timestamp - data->old_timestamp); 980 do_div(sample_period, count); 981 tstamp = data->timestamp - (count - 1) * sample_period; 982 983 ret = fxls8962af_fifo_transfer(data, buffer, count); 984 if (ret) 985 return ret; 986 987 /* Demux hw FIFO into kfifo. */ 988 for (i = 0; i < count; i++) { 989 int j, bit; 990 991 j = 0; 992 iio_for_each_active_channel(indio_dev, bit) { 993 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 994 sizeof(data->scan.channels[0])); 995 } 996 997 iio_push_to_buffers_with_ts(indio_dev, &data->scan, 998 sizeof(data->scan), tstamp); 999 1000 tstamp += sample_period; 1001 } 1002 1003 return count; 1004 } 1005 1006 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev) 1007 { 1008 struct fxls8962af_data *data = iio_priv(indio_dev); 1009 s64 ts = iio_get_time_ns(indio_dev); 1010 unsigned int reg; 1011 u64 ev_code; 1012 int ret; 1013 1014 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®); 1015 if (ret) 1016 return ret; 1017 1018 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) { 1019 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ? 1020 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1021 iio_push_event(indio_dev, 1022 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1023 IIO_EV_TYPE_THRESH, ev_code), ts); 1024 } 1025 1026 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) { 1027 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ? 1028 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1029 iio_push_event(indio_dev, 1030 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1031 IIO_EV_TYPE_THRESH, ev_code), ts); 1032 } 1033 1034 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) { 1035 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ? 1036 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1037 iio_push_event(indio_dev, 1038 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1039 IIO_EV_TYPE_THRESH, ev_code), ts); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static irqreturn_t fxls8962af_interrupt(int irq, void *p) 1046 { 1047 struct iio_dev *indio_dev = p; 1048 struct fxls8962af_data *data = iio_priv(indio_dev); 1049 unsigned int reg; 1050 int ret; 1051 1052 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®); 1053 if (ret) 1054 return IRQ_NONE; 1055 1056 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) { 1057 ret = fxls8962af_fifo_flush(indio_dev); 1058 if (ret < 0) 1059 return IRQ_NONE; 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) { 1065 ret = fxls8962af_event_interrupt(indio_dev); 1066 if (ret < 0) 1067 return IRQ_NONE; 1068 1069 return IRQ_HANDLED; 1070 } 1071 1072 return IRQ_NONE; 1073 } 1074 1075 static void fxls8962af_pm_disable(void *dev_ptr) 1076 { 1077 struct device *dev = dev_ptr; 1078 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1079 1080 pm_runtime_disable(dev); 1081 pm_runtime_set_suspended(dev); 1082 pm_runtime_put_noidle(dev); 1083 1084 fxls8962af_standby(iio_priv(indio_dev)); 1085 } 1086 1087 static void fxls8962af_get_irq(struct device *dev, 1088 enum fxls8962af_int_pin *pin) 1089 { 1090 int irq; 1091 1092 irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 1093 if (irq > 0) { 1094 *pin = FXLS8962AF_PIN_INT2; 1095 return; 1096 } 1097 1098 *pin = FXLS8962AF_PIN_INT1; 1099 } 1100 1101 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq) 1102 { 1103 struct fxls8962af_data *data = iio_priv(indio_dev); 1104 struct device *dev = regmap_get_device(data->regmap); 1105 unsigned long irq_type; 1106 bool irq_active_high; 1107 enum fxls8962af_int_pin int_pin; 1108 u8 int_pin_sel; 1109 int ret; 1110 1111 fxls8962af_get_irq(dev, &int_pin); 1112 switch (int_pin) { 1113 case FXLS8962AF_PIN_INT1: 1114 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1; 1115 break; 1116 case FXLS8962AF_PIN_INT2: 1117 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2; 1118 break; 1119 default: 1120 dev_err(dev, "unsupported int pin selected\n"); 1121 return -EINVAL; 1122 } 1123 1124 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL, 1125 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel); 1126 if (ret) 1127 return ret; 1128 1129 irq_type = irq_get_trigger_type(irq); 1130 switch (irq_type) { 1131 case IRQF_TRIGGER_HIGH: 1132 case IRQF_TRIGGER_RISING: 1133 irq_active_high = true; 1134 break; 1135 case IRQF_TRIGGER_LOW: 1136 case IRQF_TRIGGER_FALLING: 1137 irq_active_high = false; 1138 break; 1139 default: 1140 dev_info(dev, "mode %lx unsupported\n", irq_type); 1141 return -EINVAL; 1142 } 1143 1144 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1145 FXLS8962AF_SC4_INT_POL_MASK, 1146 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high)); 1147 if (ret) 1148 return ret; 1149 1150 if (device_property_read_bool(dev, "drive-open-drain")) { 1151 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1152 FXLS8962AF_SC4_INT_PP_OD_MASK, 1153 FXLS8962AF_SC4_INT_PP_OD_PREP(1)); 1154 if (ret) 1155 return ret; 1156 1157 irq_type |= IRQF_SHARED; 1158 } 1159 1160 return devm_request_threaded_irq(dev, 1161 irq, 1162 NULL, fxls8962af_interrupt, 1163 irq_type | IRQF_ONESHOT, 1164 indio_dev->name, indio_dev); 1165 } 1166 1167 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq) 1168 { 1169 struct fxls8962af_data *data; 1170 struct iio_dev *indio_dev; 1171 unsigned int reg; 1172 int ret, i; 1173 1174 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1175 if (!indio_dev) 1176 return -ENOMEM; 1177 1178 data = iio_priv(indio_dev); 1179 dev_set_drvdata(dev, indio_dev); 1180 data->regmap = regmap; 1181 data->irq = irq; 1182 1183 ret = iio_read_mount_matrix(dev, &data->orientation); 1184 if (ret) 1185 return ret; 1186 1187 ret = devm_regulator_get_enable(dev, "vdd"); 1188 if (ret) 1189 return dev_err_probe(dev, ret, 1190 "Failed to get vdd regulator\n"); 1191 1192 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®); 1193 if (ret) 1194 return ret; 1195 1196 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) { 1197 if (fxls_chip_info_table[i].chip_id == reg) { 1198 data->chip_info = &fxls_chip_info_table[i]; 1199 break; 1200 } 1201 } 1202 if (i == ARRAY_SIZE(fxls_chip_info_table)) { 1203 dev_err(dev, "failed to match device in table\n"); 1204 return -ENXIO; 1205 } 1206 1207 indio_dev->channels = data->chip_info->channels; 1208 indio_dev->num_channels = data->chip_info->num_channels; 1209 indio_dev->name = data->chip_info->name; 1210 indio_dev->info = &fxls8962af_info; 1211 indio_dev->modes = INDIO_DIRECT_MODE; 1212 1213 ret = fxls8962af_reset(data); 1214 if (ret) 1215 return ret; 1216 1217 if (irq) { 1218 ret = fxls8962af_irq_setup(indio_dev, irq); 1219 if (ret) 1220 return ret; 1221 1222 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 1223 &fxls8962af_buffer_ops); 1224 if (ret) 1225 return ret; 1226 } 1227 1228 ret = pm_runtime_set_active(dev); 1229 if (ret) 1230 return ret; 1231 1232 pm_runtime_enable(dev); 1233 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS); 1234 pm_runtime_use_autosuspend(dev); 1235 1236 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev); 1237 if (ret) 1238 return ret; 1239 1240 if (device_property_read_bool(dev, "wakeup-source")) { 1241 ret = devm_device_init_wakeup(dev); 1242 if (ret) 1243 return dev_err_probe(dev, ret, "Failed to init wakeup\n"); 1244 } 1245 1246 return devm_iio_device_register(dev, indio_dev); 1247 } 1248 EXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, "IIO_FXLS8962AF"); 1249 1250 static int fxls8962af_runtime_suspend(struct device *dev) 1251 { 1252 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1253 int ret; 1254 1255 ret = fxls8962af_standby(data); 1256 if (ret) { 1257 dev_err(dev, "powering off device failed\n"); 1258 return ret; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static int fxls8962af_runtime_resume(struct device *dev) 1265 { 1266 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1267 1268 return fxls8962af_active(data); 1269 } 1270 1271 static int fxls8962af_suspend(struct device *dev) 1272 { 1273 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1274 struct fxls8962af_data *data = iio_priv(indio_dev); 1275 1276 if (device_may_wakeup(dev) && data->enable_event) { 1277 enable_irq_wake(data->irq); 1278 1279 /* 1280 * Disable buffer, as the buffer is so small the device will wake 1281 * almost immediately. 1282 */ 1283 if (iio_buffer_enabled(indio_dev)) 1284 fxls8962af_buffer_predisable(indio_dev); 1285 } else { 1286 fxls8962af_runtime_suspend(dev); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int fxls8962af_resume(struct device *dev) 1293 { 1294 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1295 struct fxls8962af_data *data = iio_priv(indio_dev); 1296 1297 if (device_may_wakeup(dev) && data->enable_event) { 1298 disable_irq_wake(data->irq); 1299 1300 if (iio_buffer_enabled(indio_dev)) 1301 fxls8962af_buffer_postenable(indio_dev); 1302 } else { 1303 fxls8962af_runtime_resume(dev); 1304 } 1305 1306 return 0; 1307 } 1308 1309 EXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = { 1310 SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume) 1311 RUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL) 1312 }; 1313 1314 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>"); 1315 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver"); 1316 MODULE_LICENSE("GPL v2"); 1317